Selective Area Epitaxy of Defect-Free III-V Layers on Silicon Via Graphene Nanoholes

The integration of III-V semiconductors on silicon is critical for advancing high-performance electronic and optoelectronic devices due to their high electron mobilities and direct bandgaps. However, the large lattice mismatch between III-V materials and silicon typically results in high dislocation densities, which severely degrade device performance. Techniques like graded-buffer layers (GBL), epitaxial lateral overgrowth (ELOG), and aspect ratio trapping (ART) have been proposed to mitigate these issues, but with limited success. While pseudomorphic growth can create dislocation-free III-V layers, it leads to interface roughening and mobility degradation in ultrathin channels. Therefore, it is critical to explore new relaxation mechanisms that avoid the formation of dislocations.<br/><br/>I will describe a graphene-assisted epitaxy technique to achieve strain-relaxed, dislocation-free III-V growth on silicon. Graphene, a two-dimensional material with a sp²-bonded structure, is directly grown on the silicon substrate to act as a buffer layer that mediates strain relaxation through selective area epitaxy (SAE) at engineered nanoholes. These nanoholes expose the silicon substrate which provides nucleation sites where the III-V material can grow, while the surrounding graphene prevents nucleation elsewhere due to its lower sticking coefficient. As the III-V material grows laterally over the graphene, the strain that typically arises from lattice mismatch is relaxed due to the flexible and slippery nature of graphene, which accommodates misfit strain through lateral overgrowth. SiO₂ trenches that confine the laterally grown III-V material further reduce defects by limiting the number of distinct nuclei that form the merged films. The interplay between graphene’s strain-relaxing properties and the controlled nucleation process enables the direct growth of thin III-V layers on silicon without the formation of dislocations.<br/><br/>This graphene-assisted epitaxy method offers a scalable and CMOS-compatible (transfer-free and monolithic) solution for integrating high-quality III-V materials on silicon, paving the way for future high-performance electronic and optoelectronic applications.