Single-Crystal 2D Materials-Based Next-Generation 3D CMOS Transistor

CMOS scaling has provided a cost-effective development route for the electronics industry and enabled an unprecedented level of bit- and performance-density that have met consumers’ demands for several decades. This non-stop scaling in CMOS technology has been driven by the introduction of innovative technologies. In recent CMOS technology, there have been advancements in both structural and material innovations. In terms of structural innovations, three-dimensional (3D) CMOS technology has recently emerged and been explored. 3D CMOS technology is based on the concept of 3D heterogeneous integration of CMOS devices; this approach enables to achieve to aggressive cell scaling to continue Moore’s Law. Meanwhile, in terms of material innovations, two-dimensional (2D) materials have garnered significant attention as promising channel materials that can replace Si in electronic devices. This is because, it has been revealed that high carrier mobility can be maintained when the thickness of 2D materials is scaled even under 5 nm. In particular, the atomistic-level thickness of 2D materials enables extreme gate pitch scaling.<br/>In this presentation, for the first time, we will present the development of single-crystal 2D materials-based high-performance 3D CMOS transistors, wherein CMOS transistors are 3D heterogeneously integrated. Firstly, we demonstrate that single-crystal 2D materials are instrumental in achieving high-performance CMOS transistors. Specifically, we grew single-crystal 2D MoS₂ and WSe₂ semiconductors, which were then employed as channel layers in 2D NMOS and PMOS transistors, respectively. We achieved 69.3 mA/mm and 84.1 mA/mm of on-current density from our NMOS and PMOS transistors, respectively, which are comparable to those obtained from CMOS transistors fabricated using as exfoliated 2D MoS₂ and WSe₂ flakes. Next, we integrate these devices vertically to realize a 3D heterogeneously integrated CMOS transistor. We initially fabricated the 2D PMOS transistor on the substrate, and subsequently, fabricated the 2D NMOS transistor on top of the previously fabricated device. Then, we successfully verified the high-performance operation of the underlaying 2D PMOS layer and the upper 2D NMOS layer in our 3D CMOS transistor, which mainly originated from the single crystallinity of 2D materials. Finally, we explored the applicability of our 3D CMOS transistors toward logic circuits by implementing inverter circuits. We expect that this result will be an important step toward achieving the ultimate performance- and bit-density in microprocessors.