Fully Printed MOSFET Devices Using a Directed Assembly Solution-Based Process

Fully Printed MOSFET Devices Using a Directed Assembly Solution-based Process<br/><br/>G. Cagatay Ozseker, Aditya Kashyap Velide, Priyanshi Rastogi, Ahmed Hafez Abdelaziz, and Ahmed A. Busnaina*<br/>NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing, Northeastern University<br/>Contact: Ahmed Busnaina ([email protected])<br/><br/>With the rising demand for more complex electronics as well as custom electronics (ASICS), the time required for manufacturing has increased exponentially over the past few decades. Today, the overall processing time of a chip is 8-12 months or more. Additive manufacturing of electronic components, although it is still at the development stage, provides a fast, low cost and sustainable alternative to the conventional semiconductor manufacturing approach. This paper introduces a scalable, fully additive, directed-assembly-based process for printing silicon based Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) at high throughput (one layer per minute for a 4-inch substrate regardless of minimum feature size). The assembly process used is fast fluidic directed assembly which utilizes colloidal suspensions of metallic, dielectric and dopant inks to print MOSFETs. This technique utilizes surface energy and fluidic motion to direct the particles the circuit pattern areas on the substrates. Furthermore, the additive nature of the processes results in 1000x reduction in materials use and orders of magnitude less power and water. The printing of silicon MOSFET using a silicon substrate requires P doping (using Boron) and N doping (using Phosphors). In this paper, we introduce a novel approach that allows controlled doping of miniaturized electronic devices using fast fluidic assembly over chemically engineered Si wafers. In this paper, we introduce a novel approach that allows controlled doping of miniaturized electronic devices using fast fluidic assembly over chemically engineered Si wafers. This requires a doping process that requires the printing of the liquid dopants where the source and drain are followed by encapsulation and a precisely-controlled thermal process using Rapid Thermal Process (RTP) up to 900-1000 C to allow the thermal diffusion of the dopant atoms inside the substrate with desired depth. The process takes about 2 minutes and can be controlled to obtain the desired dopant penetration depth into the silicon wafers as well as the correct concentration profile. This is followed by printing of the gate dielectric and gate. The dielectric is also printed using low K dielectric (SiO2). The process allows the fully additive fabrication of the FET devices without the use of high vacuum etching or oxide growth techniques. The MOSFET output curve showed that Vd was swept between 0-1 V, with increasing the gate voltage from 0-24 V with 4 V increments<br/>The output curve resulted from the simulation is similar to the I-V characteristic curve achieved experimentally with negligible drain current at zero gate voltage, confirming that the transistor is operating in enhancement mode as observed experimentally and indicating a working according to the design parameters.