The Influence of Grain Boundaries on Charge Transport in P-Type Polycrystalline Nanoribbon Transistors

Grain boundaries (GB) exert a profound influence on charge transport by introducing localized potential barriers and exhibiting elevated defect state densities, which are critical determinants in the performance of polycrystalline materials. There are a couple of models to estimate the density of states (DoS) of nanostructured materials in field-effect transistors (FETs) which probe interface traps between the semiconductor and dielectric, but not at the grain boundaries.In this study, we introduce an energy band profile that delineates the charge transport mechanisms at grain boundaries, utilizing Levinson’s and Seto’s grain boundary transport models. We then correlate these mechanisms with temperature-dependent hopping transport phenomena observed in copper iodide (CuI) polycrystalline nanoribbon (PNR) field-effect transistors (FETs). Experimentally PNRs are obtained by e-beam lithography and thermal evaporation of CuI. To consider the impact of GB density, the devices are fabricated with different channel aspect ratios by varying widths (80, 260, 570 nm) and lengths (20 to 90 µm). Owing to high hole concentration, PNR FETs operate in depletion mode at 300 K. At various low temperatures (80-300 K), the figures-of-merits of FETs are estimated to understand device performance. We determine GB barrier heights, activation energy, and density of GB trap states and find equivalence between the two models. Further, we calculate temperature-dependent hopping and trap-limited transport parameters to obtain DoS at Fermi energy, trapped and free charge carrier density, localization length, hopping distance, hopping energy, etc. at various channel lengths. Based on this quantitative analysis we propose a channel length-dependent GB barrier height variation due to the in-plane electric field and elucidate CuI energy band levels.