Thickness Scaling Effects on Structural Transformations in Flash Annealed HZO-Based Capacitors via Time-Resolved Synchrotron Grazing Incidence X-Ray Diffraction

In order to extend computational power beyond the era of conventional area scaling of semiconductor circuits, back-end-of-line (BEOL) integration is a promising pathway towards 3D integration of non-volatile memory with logic, to increase integration density and reduce latency and energy consumption associated with data transfer. With improved properties over perovskite-structure ferroelectrics, HfO₂-ZrO₂(HZO) alloys are promising candidates for future nonvolatile memories because of their CMOS compatibility, sub-nanosecond switching speed, and scalability of ferroelectric properties to the nanoscale. However, synthesis of ferroelectric HZO typically requires rapid high temperature heating to stabilize the metastable ferroelectric phase, typically employing a rapid thermal annealing (RTA) procedure to quickly thermalize the entire device stack for processing times of seconds to minutes. In contrast, flash lamp annealing (FLA) quickly thermalizes materials with sub-ms pulses of light that can be potentially localized to the top layers of the device stack and to protect underlying interconnect and front-end-of-line (FEOL) structures while crystallizing higher level materials. Because thermalization depends on the optical and thermal properties of the materials in the device stack, tuning of the film properties (thickness, surface roughness, etc.) can impact the temperature gradient experienced during annealing.<br/>Previous work has demonstrated FLA processing of 10-nm HZO metal-ferroelectric-metal (MFM) capacitors exhibiting similar remnant polarization and coercive field as RTA processed MFM capacitors, but with an imposed thermal budget three orders of magnitude lower than for RTA processing. However, for industrial-scale adoption, the HZO film thickness must decrease to improve ferroelectric memory device performance and energy efficiency. Thus, it is important to determine how thickness scaling of the metallic and ferroelectric layers affect the stabilization of the ferroelectric phase during FLA processing to yield ferroelectric devices with good performance while minimizing the thermal budget imposed for compatibility with BEOL processing.<br/>Our work uses time-resolved synchrotron glancing incidence X-ray diffraction (GIXRD) for in-situ visualization of lattice dynamics to understand phase evolution during FLA processing of metal-ferroelectric-metal (MFM) capacitors with varying HZO and metallic layer film thicknesses. Static GIXRD was subsequently performed to carefully monitor the changes in lattice parameter at discrete elevated temperatures. Electrical measurements were also performed on the MFM capacitors to correlate device performance with phase evolution and optimize processing conditions for integration into memory devices, with the imposed thermal budget of processing calculated using a calibrated computational model. We have found that the optical properties of the metallic electrodes vary significantly with thickness, impacting the thermal budget imposed on the MFM stack during FLA and ultimately affecting the stabilization of the metastable ferroelectric phase. This study has advanced understanding of phase evolution of HZO thin films during FLA processing in efforts for adoption in BEOL device processing.