Ternary Inverter Circuits Based on Carbon Nanotubes and MoS₂ Heterojunctions with Asymmetric Electrodes

Multi-valued logic (MVL) circuits, which can process much more data with fewer devices than conventional binary logic circuits, are considered one of the possible solutions to the challenges of further scaling. A key component for the implementation of MVL circuits is a negative transconductance (NTC) field-effect transistor (FET) whose channel is composed of pn junctions. A monolayer of MoS2 is a representative two-dimensional n-type semiconductor; however, reliable and repeatable formation of pn junctions is challenging due to the relatively small flake size and irregular shape of MoS2. To form reliable pn heterojunctions with n-type monolayer MoS2, a random network of single-walled carbon nanotubes (SWCNTs) can be a good option for a p-type semiconductor channel.<br/> In our devices, SWCNTs are inkjet printed to completely cover the channel area between the source and drain electrodes of the NTC FET, while the underlying MoS2 is connected to the drain electrode only where the MoS2 partially covers the channel. This hybrid channel can be roughly modeled as variable resistors composed of an ambipolar channel and a p-channel connected in series, resulting in the region where the current decreases with increasing voltage (called NTC) after a local current peak. The width of the NTC region plays an important role in the operation of the ternary inverters because the mid-logic state occurs when the currents of two FETs forming ternary inverter circuits overlap in the NTC region.<br/> In this presentation, we will show that the width of the NTC region can be tuned by using asymmetric electrode design. By increasing the width of the source electrode while keeping the width of the drain electrode small, the p-channel I-V characteristic is shifted to the positive voltage direction, resulting in an expanded NTC region. This enables the clear representation of the mid-logic state when the MoS2/SWCNT heterojunction-based NTC FET is connected to another n-type MoS2 FET. The ternary inverter exhibits three distinct logic states at full swing.