Probing Charge Trapping of High k Dielectric Stacks Under Ionizing Radiation

The integration of high k dielectrics in metal-oxide-semiconductor (MOS) devices has been revolutionary for advancing conventional semiconductor devices due to their low leakage and thermal stability at exceedingly low effective oxide thicknesses. Under extreme conditions such as high energy x-ray exposure, electron-hole pairs are generated in the dielectric stack and subsequently trapped, in the form of oxide trapped charge or as interface traps, which will create charge buildup, resulting in a measurable shift in the flatband or threshold voltage of a MOS capacitor or MOS field effect transistor (MOSFET), respectively. Here, we evaluate and report the response of multilayer dielectric stacks to x-ray exposure, with a focus on understanding charge trapping between layers, in an effort to understand the behavior of these materials and their interfaces under extreme conditions.<br/>Dielectric films of HfO₂ and Al₂O₃ are successively grown via atomic layer deposition (ALD) and fabricated into MOS capacitors on a p-type Si substrate with an aluminum top gate. The thicknesses and layering of the dielectric layers were selected to assess how charge is generated, tunnels and recombines. Charge can be trapped via a mismatch in mobility between holes and electrons as well as engineered by the order in stacking of the dielectric layers, which form energy barriers generated by offsets in their respective valence and conduction band edges and/or through band bending at equilibrium. As these charges travel through these layers and recombine to ultimately restore the flatband voltage, we aim to characterize their transport through the following measurements.<br/>Initial characterization includes a multi-frequency capacitance-voltage (CV) measurement to study the interface trap density. Throughout ionizing radiation dosing, single high-frequency CV measurements are performed to evaluate the dependence of flat-band voltage shift on dose. After dosing, a series of CV measurements are performed as a function of time to analyze room-temperature annealing which yields information on the placement and movement of these charges.<br/>This work was supported by the Laboratory Directed Research and Development Program at Sandia National Laboratories and was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525. The views expressed in the article do not necessarily represent the views of the DOE or the U.S. Government.