Demonstration of Self-Aligned Edge Contact for High-Performance WS₂ 2D Field-Effect Transistors

The conventional Si-based semiconductor architectures face scale-down limitations due to the performance degradation caused by short-channel effects. Two-dimensional (2D) transition metal dichalcogenides (TMDs) have become prominent candidates to replace Si owing to their excellent electrical properties at sub-nanometer thickness emanating from their atomically thin layered structures and dangling bond-free surfaces. Tungsten disulfide (WS₂), one of the members of TMDs, exhibits thickness-dependent bandgap (multilayer: 1.3 eV, monolayer: 2.1 eV) and electron mobility of ~234 cm²/Vs, making it a great alternative as an n-type channel material in 2D field-effect transistors (FETs). However, the full potential of the WS₂ is restrained by the charge transport degradation and high contact resistance caused by the formation of a Schottky barrier (SB) in the metal–TMD junctions. Edge contacts have emerged as a promising method to fabricate TMD-based FETs with low contact resistance and controllable polarity without the need for extrinsic chemical doping or additional processing steps during the formation of the contact metal. Contrary to the Fermi-level pinning at specific energy levels of gap states at the metal–TMD interfaces in surface contacts, the absence of a van der Waals gap state in the edge contacts reduces the overall barrier width and enhances charge injection. This work introduces a self-aligned edge contact (SAEC) process for WS₂ FETs. This SAEC process enables the fabrication of edge contact WS₂ FETs without additional lithography which is required to define the channel in conventional edge contact methods. The SAEC process utilizes hexagonal boron nitride (hBN) layers transferred onto the top-gate metal as an etch mask to define the edge contact region where the hBN layers become the gate sidewall spacer after dry-etching. The SAEC process combines the advantages of previous edge contact methods with the self-aligned processes commonly used in the current Si technology, resulting in 2D devices with excellent electrical properties, such as a high on/off current ratio and enhanced field-effect mobility (<i>μ</i>_FE).<br/>In this work, WS₂ and hBN nanolayers were sequentially mechanically exfoliated and dry-transferred onto a Si/SiO₂ substrate to form a WS₂/hBN stack. The top-gate section was patterned using electron beam lithography (EBL), before depositing Ti/Au (20/80 nm) top-gate electrode. In the first reactive ion etching (RIE), the WS₂/hBN stack with the top-gate electrode was etched with an SF₆/Ar gas mixture to partially etch the hBN nanolayer. Then, another exfoliated hBN nanolayer was dry-transferred onto the top-gate electrode to cover the whole gate metal and the adjacent parts of the WS₂ channel. The second RIE was performed using the same gas mixture to form the hBN gate spacers and expose the edges of the WS₂ channel by completely etching away the periphery of the WS₂ and hBN nanolayers. Ti/Au (30/30 nm) source/drain electrodes were defined via EBL and were deposited at the edge contact boundaries.<br/>The formation of steep edges in the WS₂ channel via RIE and the subsequent formation of edge contact after contact metal deposition were confirmed through atomic force microscopy and cross-sectional transmission electron microscopy, respectively. Our SAEC WS₂ FET showed a high on/off current ratio of ~10⁷ and <i>μ</i>_FE of 97.37 cm²/Vs. The self-aligned formation of edge contacts led to the formation of metallized WS₂ layers induced by a strong orbital overlap between WS₂ and the metal atoms, which eliminated the barrier derived from the van der Waals gap and resulted in the lowering of the SB. This unique metal–TMD interface enabled effective layer-by-layer carrier injection into the WS₂ conduction band. The SAEC process can unleash the full potential of 2D TMDs by effectively removing the SB at the metal-semiconductor interface, while preserving their intrinsic properties.