Effects of Gate Dielectric Process on Electrical Characteristics of InGaZnO Vertical TFT

The importance of backplane thin-film transistor (TFT) for ultrahigh-resolution (UHR) displays has grown with the recent advancements in augmented reality (AR) and virtual reality (VR) technology. To minimize screen effects caused by low resolution of displays, AR/VR panels with thousands of pixels per inch are required. As a result, there is an increasing need for TFTs with vertical channels rather than conventional planar structures to reduce the device footprint. [1]<br/> All planar structures used in the current display industry require more area compared to vertical TFTs. In active-matrix organic light-emitting diode (AMOLED) displays, the self-aligned top gate (SATG) TFT is commonly employed as a planar backplane device structure due to its low parasitic capacitance and resistance to illumination degradation from the emitting layer. However, SATG TFTs face inherent limitations for device miniaturization because they require a significant metallization area to reduce contact resistance and have a scaling limit of the channel caused by carrier diffusion, which reduces the effective channel length.<br/> In contrast, Vertical TFT (VTFT), while inherently possessing parasitic capacitance and being susceptible to degradation from backchannel effects, offer the advantage of scaling the channel dimension to below 1 µm by adjusting the thickness of the spacer layer and gate width. Additionally, since the source and drain electrodes are formed on different layers, it is easier to adjust the position of metal line, making it a structure suitable for increasing integration density. Therefore, VTFT are an appropriate structure for transistors in ultrahigh-resolution displays.<br/>However, unlike the extensively studied planar TFTs, VTFTs have not been widely researched concerning the impact of gate dielectric processes, despite its significant sensitivity to backchannel effects. Therefore, we investigated the changes in VTFT characteristics with respect to the temperature and power of the PECVD SiO₂ dielectric process and optimized the process accordingly.<br/><br/>Acknowledgement<br/><br/>This research work was supported by the BK21 FOUR (Fostering Outstanding Universities for Research) funded by the Ministry of Education (MOE) of Korea and National Research Foundation (NRF) of Korea.<br/><br/>Reference<br/>[1] S. Lee <i>et al</i>., "Vertically Extended Channel Architecture for Implementing a Photolithographically Scalable Thin-Film Transistor," in <i>IEEE Electron Device Letters</i>, vol. 44, no. 8, pp. 1296-1299, Aug. 2023, doi: 10.1109/LED.2023.3286100.