December 1 - 6, 2024
Boston, Massachusetts
Symposium Supporters
2024 MRS Fall Meeting & Exhibit
EL05.08.06

Research and Analysis of Flash-Type 2×2 Neuromorphic Transistor Arrays Manufactured by CdSe Quantum Dots

When and Where

Dec 4, 2024
8:00pm - 10:00pm
Hynes, Level 1, Hall A

Presenter(s)

Co-Author(s)

Taehwan Koo1,Jaemin Kim1,Soyeon Jung1,Hyeongjin Chae1,Juyeong Chae1,Moongyu Jang1

Hallym University1

Abstract

Taehwan Koo1,Jaemin Kim1,Soyeon Jung1,Hyeongjin Chae1,Juyeong Chae1,Moongyu Jang1

Hallym University1
This research describes the fabrication and analysis of a flash-type transistor 2×2 array device using quantum dots. Quantum dots are nanocrystals with a size of several nanometers, and research on the application of these quantum dots is being carried out in various semiconductor and semiconductor applications such as displays and solar cells. The cores of the quantum dots used in this study are InP, CdSe, etc. and have been treated with ligands to convert them to hydrophilic, to prevent agglomeration, and for uniform distribution and stability. The flash-type transistor was fabricated in the structure of Pt/Cr/Al<sub>2</sub>O<sub>3</sub>/QDs/Al<sub>2</sub>O<sub>3</sub>/SiO<sub>2</sub>/Si. In this structure, the quantum dots act as floating gates. Quantum dots are spin-coated to form thin films on the order of 100 nm. The spin coating process reduces the process time and cost compared to other thin film processes. In this study, an oxide film(SiO<sub>2</sub>) was formed using a furnace, After then high-k material was deposited using ALD, and Cr, Pt was deposited using a sputter as the top electrode.<br/>In the previous works in our group, The Capacitance - Voltage characteristics were studied in MOS Capacitor structure rather than transistor Current - Voltage characteristics [1]. In this study, We checked the synaptic weights to ensure that we have a ΔVt of more than 1 volt, and we have four connection strengths. I<sub>D</sub>-V<sub>D</sub> and I<sub>D</sub>-V<sub>G</sub> measurements were taken to verify the behavioral characteristics of the transistor. Through this, threshold voltage (V<sub>T</sub>), on-off current ratio (I<sub>on</sub>/I<sub>off</sub>), etc. were checked, and synaptic weights were checked through programming and erasing [2]. Measurements and analyses, we confirmed its potential as a neuromorphic-based transistor and aimed to evaluate the characteristics of multiple transistors in an array. The array process is essential for neuromorphic systems with parallel structures. The device using the array process has the advantage of evaluating multiple of transistor characteristics through a single measurement, and it is expected that the data can be processed efficiently by software as a neuromorphic device.<br/>References<br/>[1] J Choi, <i>et al</i>., New Phys.: Sae Mulli <b>72</b>, 726 (2022)<br/>[2] D. Hu <i>et al</i>., IEEE Transactions on Electron Devices<b> 64</b>, 3816 (2017)

Symposium Organizers

Paschalis Gkoupidenis, Max Planck Institute
Francesca Santoro, Forschungszentrum Jülich/RWTH Aachen University
Ioulia Tzouvadaki, Ghent University
Yoeri van de Burgt, Technische Universiteit Eindhoven

Session Chairs

Paschalis Gkoupidenis
Francesca Santoro

In this Session