Analog Conductive-Metal-Oxide/HfO_x ReRAM Devices—BEOL Integration, Characterization and Modelling

The increase in the number of parameters in modern neural network architectures has led to a significant rise in energy demand for training and inference operations when performed on conventional CMOS technology based on the von Neumann architecture. Recurrent data transfers between memory and processing units are a key source of speed and energy inefficiencies in the calculation of artificial neural networks (ANNs). Specialized hybrid neuromorphic architectures, utilizing crossbar arrays of analog memristors, represent a promising energy efficient alternative for AI workloads [1]. Such architectures enable matrix-vector multiplications (MVMs) operations in the analog domain based on the in-memory computing paradigm.<br/>Analog filamentary conductive-metal-oxide (CMO)/HfO_x redox-based resistive switching memory (ReRAM) technology has shown to exhibit excellent properties for inference and training of deep neural networks. Introducing a properly engineered CMO layer within the conventional Metal/Insulator/Metal ReRAM stack improves devices characteristics such as the number of analog states, stochasticity and endurance. The underlying mechanism could recently be attributed to a modulation of the defect density within the sub-band of the CMO layer [2], where the electric field and temperature confinement in the filamentary CMO/HfO_x structure is playing a major role. For creating a high performing synaptic analog signal processing accelerator, such CMO/HfO_x ReRAM devices must be densely embedded in the Back end of the line (BEOL) of existing CMOS technology.<br/>In this work, we integrated CMO/HfO_x ReRAM devices into the BEOL of TSMC 130nm nMOS transistor technology in a 1Transistor-1ReRAM (1T1R) device configuration. We tailored the CMO/HfO_x ReRAM process flow for compatibility with the copper VIAs of the transistors, realizing a surface-contact bottom electrode ReRAM configuration. The statistical DC and pulsed electrical characterization of these 1T1R cells will be presented. Compared to a CMO/HfO_x 1R configuration, the resistive switching polarity was reversed for precise control of the current during the filament forming and the set processes of the ReRAM devices, by controlling the gate to source voltage of the nMOS transistor. Compared to 1R configuration, this approach allowed for a smaller filament radius, and therefore a lower average conductance switching regime, and a more gradual and controlled set transition, which resulted in a larger number of analog states. An analytical 3D Finite Element Model describing the transport in the optimized 1T1R structures and explaining the underlying physical mechanisms behind the reversed switching polarity compared to the 1R configuration, will be presented. Analog signal processing operations were conducted on 8x1 arrays of the 1T1R cells. The improved switching properties combined with the optimized polarity, make the 1T1R configuration of such CMO/HfO_x technology the fundamental building block for larger crossbar demonstrations of neural network training and inference in hardware.<br/>[1] A. Sebastian, et al. (2017). Temporal correlation detection using computational phase-change memory. Nat Commun 8, 1115. https://doi.org/10.1038/s41467-017-01481-9<br/>[2] D.F. Falcone, et al. (2024). Analytical modelling of the transport in analog filamentary conductive-metal-oxide/HfOx ReRAM devices. Nanoscale Horiz. 10.1039/D4NH00072B.