A Novel Method to Fabricate IGZO FeFET Using Multi-Layered Stressor Capping of HZO for Neuromorphic Computing

Since the first demonstration of the ferroelectricity in doped hafnium oxide (HfO₂) in 2011, the hafnium zirconium oxide (HZO) has risen as a promising candidate of the ferroelectric memory device due to its nature of back-end-of-line (BEOL) compatibility and scalability. Besides, indium gallium zinc oxide (IGZO) which was reported in 2004 for the first time, is also emerging as the channel material for the future memory device in that IGZO has low off-state leakage and low processing temperature of about 300^oC. In this manner, the integration of HZO to the IGZO based field effect transistor (FET) and its application to neuromorphic system using gradual switching characteristic of HZO have been intensively studied. Generally, the fabrication of ferroelectric FET (FeFET) using IGZO channel requires a complicated capping metal etching since the ferroelectricity of HZO is obtained when the tensile stress is induced by the capping metal during the cooling process of the rapid thermal annealing (RTA). However, the etching process may cause the degradation in the back surface of HZO, causing the interface degradation between HZO and IGZO which leads to the critical stability issue for the device. Another approach involves direct capping using IGZO as it can induce tensile stress to the HZO as much as conventional capping metals can, but the semiconducting property of IGZO is severely degradaded due to the oxygen outgassing during the RTA process. In this work, we propose a multi-layered stressor consisting of tungsten (W) and IGZO for the FeFET fabrication to induce sufficient tensile stress to the HZO and at the same time, maintaing the semiconducting property of the IGZO.<br/>We firstly confirmed the ferroelectricity of metal–ferroelectric–metal (MFM) capacitors where the tensile stress was applied by various capping layers such as W, IGZO, and W/IGZO. The 10 nm-thick HZO was deposited using atomic layer deposition (ALD) method. For the IGZO-capped and W/IGZO-capped capacitors, the capping layers were totally removed and W electrode was re-deposited to form the identical MFM structure. A conventional W-capped capacitor exhibited a remanent polarization (2P_r) of 46.05 μC/cm², while the IGZO-capped and W/IGZO-capped capacitors showed 2P_r values of 25.83 μC/cm² and 34.93 μC/cm², respectively. This result indicates that the W/IGZO capping layer can induce larger tensile stress for HZO crystallization compared to the IGZO capping layer. Based on this result, we fabricated FeFET using W/IGZO capping layer where the ferroelectric HZO was used as a gate insulator. Here, the W and IGZO was subsequently patterned and used as a source/drain electrode and channel, respectively. The transfer characteristic showed clear counterclockwise hysteresis, which confirms the ferroelectricity in the gate insulator. Under ± 3 V of gate voltage sweep, our FeFET showed large memory window of 1.76 V, and the on-off ratio of about 10⁶. For comparison, another FeFET was fabricated using IGZO-capping method, and the device did not have semiconducting property without post annealing process in the air due to the outgassing during the RTA process. After the post annealing process, the IGZO-capped FeFET showed the semiconducting property with counterclockwise hysteresis, but the memory window was only 1.12 V. We anticipate that the W layer on IGZO can work as a blocking layer for oxygen outgassing of IGZO during the RTA process. Finally, to confirm the neuromorphic characteristics, synaptic current was measured by applying voltage pusle of ± 2.5 V. As a result, it was confirmed that our FeFET showed proper synaptic characteristics such as potentiaion and depression.