Synaptic Function Emulation with Amorphous SZTO/SIZO Bilayer Transistors and P(VDF-TrFE) for Neuromorphic Applications

Synaptic devices like synaptic memristors and synaptic transistors enable neuromorphic computing, emulating the functions of the human brain. These devices excel in conducting highly efficient parallel computing, effectively addressing the limitations of the von Neumann architecture. Devices based on field-effect transistors (FETs) can be used to emulate synaptic function due to its flexibility in choosing material, controllable parameters, and well-known working mechanisms.<br/><br/>Here we report a simple amorphous SiZnSnO/SiInZnO (SZTO/SIZO) bilayer thin film transistor coupled with a flexible copolymer, poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)), as the gate insulator. Bilayer (SZTO/SIZO) was used for fabrication of synaptic device due to its high field effect mobility of over 30 cm²V^-1s^-1 and exceptional stability under temperature, negative gate bias, and positive gate bias stress. The P(VDF-TrFE) layer was subjected to heating at 140 ^oC, resulting in the formation of the β-phase, which significantly enhances its ferroelectric characteristic. Complete device structure consists of Al/Ti/ P(VDF-TrFE)/ZrO₂/SZTO/SIZO/substrate with channel width and length of 250 and 50 µm, respectively. The synaptic devices exhibit counterclockwise hysteresis, indicating the presence of a ferroelectric layer as the gate insulator. A memory window exceeding 8 V was observed during sweeping between -20 to 30 V, with a saturation current above 1µA at 30 V. The postsynaptic currents (PSCs) were measured using 50 potentiation and 50 depression input pulses ±10 V for 1 s. Maximum conductance of over 90 nS have been calculated using the presynaptic gate voltage and post synaptic drain current. A multilayer perceptron (MLP) neural network was constructed using “MLP NeuroSim+ V3.0” software with 400 input neurons, 100 hidden neurons, and 10 output neurons, interconnected with artificial synapses. The training dataset included a manually written numeral from the Modified National Institute of Standards and Technology (MNIST) database. The neural network simulation demonstrated recognition accuracy exceeding 50% for the handwritten digits. Optimizing the ferroelectric layer and enhancing our understanding of the gate insulator-channel interface could pave the way for developing high-performance synaptic devices in the future.