Dec 5, 2024
4:45pm - 5:00pm
Sheraton, Second Floor, Back Bay C
Ryuichi Nakajima1,Tomonori Nishimura1,Kaito Kanahashi1,Keiji Ueno2,Yasumitsu Miyata3,Kosuke Nagashio1
The University of Tokyo1,Saitama University2,Tokyo Metropolitan University3
Ryuichi Nakajima1,Tomonori Nishimura1,Kaito Kanahashi1,Keiji Ueno2,Yasumitsu Miyata3,Kosuke Nagashio1
The University of Tokyo1,Saitama University2,Tokyo Metropolitan University3
2D materials are promising for future integrated circuit due to the tolerance for short channel effect. However, Fermi level pinning (FLP) represents a critical issue in 2D systems, particularly for <i>p</i>-type FET operation. To suppress FLP, Bi has been addressed because of its low melting point and large vapor pressure, facilitating defect-free deposition that counters defect-induced gap states (DIGS). Moreover, its small density of states helps avoid the formation of metal-induced gap states (MIGS). Indeed, high-performance <i>n</i>-type MoS<sub>2</sub> FET have been achieved using Bi contacts. However, the work function (WF) of Bi is inadequate for the <i>p</i>-type operation.<br/><br/>Here, we propose a novel strategy involving surface segregation in Bi/Pt bilayer electrodes for WSe<sub>2</sub> FETs, where Pt has the highest WF among practical metals and the defect formation during Pt deposition could be suppressed by first Bi layer. By annealing the bilayer electrodes, Bi will be segregated on Pt surface due to large difference of adsorption energy, resulting in the direct Pt contact with WSe<sub>2</sub> [J. Vac. Sci. Technol. A Vacuum, Surfaces, Films <b>19</b>, 1432 (2001)]. In this study, <i>p</i>-type operation of WSe<sub>2</sub> FETs was investigated by controlling the electrode structure.<br/><br/>The segregation of Bi/Pt was first investigated by X-ray photoelectron spectroscopy and X-ray diffraction. It was demonstrated that superior segregation occurs after annealing below 300°C, while reactions started above 400°C. Subsequently, 4L-WSe<sub>2</sub> FET with 10-nm Bi/30-nm Pt electrodes was fabricated and Id-Vg measurement was carried out at RT before/after annealing at 300°C. Strong <i>n</i>-type characteristics were observed initially due to the low WF of Bi, while <i>I</i><sub>d</sub>-<i>V</i><sub>g</sub> transfer curve changed from <i>n</i>-type to <i>p</i>-type after annealing. This method holds promise for facilitating <i>p</i>-type operation in 2D FETs and warrants further discussion on FLP.