December 1 - 6, 2024
Boston, Massachusetts
Symposium Supporters
2024 MRS Fall Meeting & Exhibit
EL02.07.03

A New Paradigm for Ultra-Low Current Phase-Change Memory via a Phase-Changeable Nano-Filament

When and Where

Dec 4, 2024
9:15am - 9:30am
Sheraton, Second Floor, Republic A

Presenter(s)

Co-Author(s)

See-On Park1,Seokman Hong1,Su-Jin Sung1,Seokho Seo1,Hakcheon Jeong1,Taehoon Park1,Jeehwan Kim2,Shinhyun Choi1

Korea Advanced Institute of Science and Technology1,Massachusetts Institute of Technology2

Abstract

See-On Park1,Seokman Hong1,Su-Jin Sung1,Seokho Seo1,Hakcheon Jeong1,Taehoon Park1,Jeehwan Kim2,Shinhyun Choi1

Korea Advanced Institute of Science and Technology1,Massachusetts Institute of Technology2
Phase-change memory (PCM), which switches its electrical resistance via thermal-induced phase transition, is one of the most mature non-volatile memory technologies. Following the development of Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> (GST)-based PCM with non-volatile memory, low latency, and high integration density, PCM has been considered a candidate for enabling emerging computing systems such as compute-in-memory, compute-express-link, and neuromorphic computing. In addition, intrinsic vector-matrix multiplication in PCM crossbar array without the need for external processors makes PCM desirable hardware for artificial intelligence. However, PCM requires a large reset current to melt phase-change materials, significantly reducing energy-efficiency [1].<br/>Several studies have been conducted to address this issue, including scaling device dimensions with confined electrodes [2], utilizing super-lattice-like phase-change materials [3], and using carbon nanotube electrodes [4]. Although these approaches have experimentally demonstrated reduced reset current, some limitations still exist. For example, scaling device dimensions by using ArF-immersion or extreme ultraviolet (EUV) lithography technologies reduce the reset current as the device area decreases. However, reducing device dimensions usually increases fabrication complexity and cost, while the degree of reset current reduction is limited (~100 μA for device diameter of 10 nm). Super-lattice-like phase-change materials have shown lower reset current density compared to GST-based PCM, but the amount of current reduction is small (&lt;5×). Using carbon nanotube electrodes for PCM enables ultra-low reset current under 10 μA, but uniform integration of carbon nanotubes for large-scale fabrication requires further development.<br/>In this study, we propose a new paradigm to reduce the reset current in PCM without increasing fabrication complexity and cost by forming a phase-changeable SiTe<sub>x</sub> nano-filament via an electro-forming method [5]. Thanks to the self-confined filament structure with a diameter of approximately 5 nm, the nano-filament PCM (NFPCM) achieves an ultra-low reset current (~60 μA) regardless of device size. Compared to a GST-based PCM with a 40 nm electrode, the NFPCM with the same device size achieved an approximately 15 times lower reset current, demonstrating its effectiveness in reducing the reset current regardless of device size. In addition to the reset current, the device exhibited favorable memory characteristics, including a large on/off ratio, low variations, and multi-level memory properties. Furthermore, it was confirmed that the reset current can be further reduced (~10 μA) by controlling the stoichiometry of the filament. These findings represent a significant advancement towards novel non-volatile memory technologies applicable in neuromorphic computing systems, edge processors, in-memory computing systems, and traditional memory applications.<br/><br/><b>References</b><br/>[1] Raoux, S. <i>et al. MRS Bulletin</i> <b>39</b>, 703-710, 2014<br/>[2] Im, D.H. <i>et al.</i> <i>2008 IEEE International Electron Devices Meeting (IEDM)</i>, 1-4, 2008<br/>[3] Ding, K. <i>et al. Science</i> <b>366</b>, 210-215, 2019<br/>[4] Xiong, F. <i>et al. Nano Letters</i> <b>13</b>, 464-469, 2012<br/>[5] Park, S.-O. <i>et al. Nature</i> <b>628</b>, 293-298, 2024

Symposium Organizers

Fabrizio Arciprete, University of Rome Tor Vergata
Valeria Bragaglia, IBM Research Europe - Zurich
Juejun Hu, Massachusetts Institute of Technology
Andriy Lotnyk, Leibniz Institute of Surface Engineering

Session Chairs

Elisa Petroni
Andrea Redaelli

In this Session