3D Heterogeneous Integration—Printing of Ultrafine-Resolution Interconnects and Traces

With the rising demand for smaller, mass-produced complex electronic devices, the time required for manufacturing has increased exponentially over the past few decades. Advanced packaging requirements and 3D heterogeneous integration followed a similar rise in demand. Today’s industry can achieve high precision down to 3 nm, but the overall processing time of a chip is more than six months. To accommodate these limitations, additive manufacturing of electronic components provides a significant alternative approach that can be very beneficial to 3D heterogeneous integration. This paper introduces a scalable, fully additive, directed-assembly-based process to print interconnects and electrical components at the micro and nanoscales at high throughput (one layer per minute for a 4-inch substrate regardless of minimum feature size). Fluidic directed-assembly utilizes highly concentrated metallic inks to print 2D and 3D structures – such as flip chip fan-out patterns, traces, interconnects, and touch screen display grids – on rigid and flexible substrates. This technique utilizes external fields that interact with suspended particles in inks and guides them to site-selective patterned areas on the substrates. Furthermore, the additive nature and bottom-up approach of fluidic directed-assembly make this process highly controllable and implementable across many applications. Touch screen display grids, flip chip fan-out patterns, and inorganic dielectric layers for 3D heterogeneous integration are additively printed using silver and dielectric inks on both rigid and flexible substrates with this technique. The current industry trend is moving away from large monolithic chips towards integrating discrete dies on a silicon substrate to increase yield and lower cost. This requires fine resolution and pitch for interconnects and trace to integrate these dies. The EMIB (Embedded Multi-Die Interconnect Bridge) was released by Intel in 2017 to connect multiple heterogeneous dies in a single package. It allows for tighter interconnect density by embedding small bridges into the package substrate. These structures are used to enhance system performance by allowing high-density interconnections with minimal signal loss. With these benefits, they became a supporting scalable solution for modern computing needs. Results show that printed touch screen display grids had 2- and 0.3-micron line widths while EMIB-like structure shows 2-micron line widths with 2-micron spacings while having 50 to 500 length-to-width ratios. AFM and confocal microscope measurements show that both patterns had similar silver thicknesses of 400 nm after sintering. To compare printed silver flip chip fan-out structure to conventional methods, the same pattern is fabricated with copper sputtering at the same thickness of 800 nm. Both chips are electrically characterized with IdVd sweep. Results showed that printed silver had 3.3 ohms resistance compared to that of copper’s 3.75 ohms. Inorganic dielectric layers (Aluminium oxide and Silica) are printed and characterized by XPS and SEM. XPS data show the quality of the printed AlO_x film via densification and chemical composition analysis. XPS results show a strong match between the chemical composition of the printed AlO_x and the ALD deposited counterpart. SEM results show that the printed film’s thickness decreases with the increase in annealing temperature. The printing process utilized has been shown to reduce cost by 10 – 100x and increase throughput by 10 – 100x compared to conventional fabrication in addition to a 1000x reduction in materials use. In addition, it is more than 1000x faster than inkjet or 3D printing.