2D Semiconductor Gate Stack and Implementation of Steep-Switching Impact Ionization Transistor

Two-dimensional (2D) semiconductors are now considered a real possible replacement for Si channels, not only limited to academic society but also to serious efforts at the industry level. One of the serious remaining concerns is the integration of a high-κ dielectric on a 2D semiconductor to overcome the reported challenges of forming high-quality interfaces with suppressed trap density and without degradation of device performance.<br/><br/>In this work, we report a high-quality gate stack (native HfO₂ formed on 2D HfSe₂) fabricated via plasma oxidation (unlike reported deposited or transferred dielectric structures where van der Waals gap exists), realizing an atomically sharp interface with a suppressed interface trap density (D_it ~ 5×10¹⁰cm^-2eV^-1)_. The chemically converted HfO₂ exhibits dielectric constant, κ ~ 23, resulting in low gate leakage current (~10^-3A/cm²) even at scaled EOT ~0.5 nm. Density functional calculations elucidated that the atomistic mechanism for achieving a high-quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe₂ layer without a substitution energy barrier, allowing layer-by-layer oxidation to proceed. The field-effect-transistor-fabricated with HfO₂/HfSe₂ gate stack demonstrated an almost ideal subthreshold slope (SS) of ~ 61 mV/dec (over four orders of I_DS) at room temperature (300 K), along with a high I_on/I_offratio of ~10⁸ and small hysteresis ~ 10 mV.<br/><br/>Furthermore, we report for the first time the successful fabrication of HfO₂/HfSe₂ based impact-ionization FET that exhibits n-type steep-switching characteristics at room temperature. Utilizing the separately controlled channel structure designed to concentrate the sufficient electric field to trigger impact ionization, further scaling of the SS to ~3.43 mV/dec, overcoming the fundamental Boltzmann limit was achieved. We strategically verified the potential for improving the reliability of impact ionization devices, a fundamental limitation, by achieving low gate injection efficiency through effective suppression of gate leakage current from high-quality gate stacks. The TCAD simulation supported the impact-ionization-induced steep switching behavior and scaling of the operating biases in the proposed devices. Our results provide a significant step toward the realization of post-Si semiconducting devices for future energy-efficient data-centric computing electronics.