A Reconfigurable Binary/Ternary Logic Conversion-in-Memory Based on Drain-Aligned Floating-Gate Heterojunction Transistors

Reconfigurable electronics entails designing and implementing circuits that can be dynamically modified to enable more diverse and complex computations within a given footprint. Simultaneously, multi-valued logic extends the binary logic framework by incorporating additional logic states. When combined with reconfigurable electronics, multi-valued logic can significantly enhance data processing efficiency and integration density in conventional digital circuits.<br/>Here, we introduce a novel heterojunction non-volatile memory transistor that allows for dynamic control of the negative transconductance characteristics by integrating non-volatile memory functionality into the heterojunction transistor. Unlike conventional flash memory, the proposed heterojunction non-volatile memory transistor employs a drain-aligned floating gate that partially overlaps with the channel. This design stems from the asymmetric configuration of the heterojunction transistor, where the p-type layer connects the source to the drain electrode, and the n-type layer interacts solely with the drain electrode through the intervening p-type layer. By varying the gate-to-drain electric field, the drain-aligned floating gate in the n-type semiconductor can effectively modulate the electron injection into the channel, thus enabling systematic control of the negative transconductance characteristics during programming operations. Utilizing these dynamic negative transconductance characteristics, we achieved a high-performance binary/ternary reconfigurable inverter with a static noise margin of 85% for binary logic and 59% for ternary logic, as well as stable retention properties and excellent cycle durability. Notably, the static noise margin for ternary logic operation reported here surpasses previously reported values for ternary logic circuits based on different principles. Additionally, the binary/ternary reconfiguration can be achieved without complex circuitry or changes in supply voltage, enabling direct connection between binary and ternary logic systems. For instance, the proposed binary/ternary reconfigurable inverter can be cascaded to form high-level circuits, with each unit being fully reconfigurable. As a proof of concept, we demonstrated binary/ternary logic conversion-in-memory using a two-stage binary/ternary reconfigurable inverter, which produces output signals in three sequences at three logic levels, performing all functions of a standard ternary inverter, positive ternary inverter, and negative ternary inverter based on the memory states of the binary/ternary reconfigurable inverter.