Dec 3, 2024
10:30am - 11:00am
Hynes, Level 2, Room 210
Richard Gottscho1,Keren Kanarik1,Wojciech Osowiecki1,Yu Lu1,Talukder Dipongkar1,Niklas Roschewsky1,Sae Na Park1,Mattan Kamon1,David Fried1
LAM Research Corporation1
Richard Gottscho1,Keren Kanarik1,Wojciech Osowiecki1,Yu Lu1,Talukder Dipongkar1,Niklas Roschewsky1,Sae Na Park1,Mattan Kamon1,David Fried1
LAM Research Corporation1
Although chips have been designed by computers for decades, the processes used to manufacture those chips have eluded design based on physics or data. Virtually all processes used to manufacture chips have been developed, not designed, by trial and error – a costly endeavor using highly trained and experienced process engineers searching for a combination of tool parameters that produce an acceptable result on the device. Because the solution space dimensionality is so large (~10<sup>20</sup>) and because process development is time-consuming and costly, machine learning approaches have been hampered by too little data. Physics based approaches suffer from large numbers of unknown parameters and complex equations that require excessive computational time to solve.<br/><br/>This talk will review results from a study, which showed a “human first, computer last” approach could reach process engineering targets dramatically faster and at substantially lower cost compared to today's empirical approach. A virtual plasma etching environment was created to enable comparison of humans to machines and algorithms to algorithms. The use of synthetic data from a virtual environment, even though it is not precisely predictive, provided a path to leverage the strengths of human experts and their domain knowledge as well as the strengths of machine learning to deal with “little data” and accelerate the pace of innovation in semiconductor process engineering [Kanarik, et al. Nature 616, 707–711 (2023)]. The virtual environment enabled determination of not only the best methodology and algorithm, but also a value assessment of experience relative to education. It also provides a means to quantitatively assess the effectiveness of work force development efforts in semiconductor process engineering.