December 1 - 6, 2024
Boston, Massachusetts
Symposium Supporters
2024 MRS Fall Meeting & Exhibit
EL07.19.02

Ultra-High Speed Photonic Vertical NAND FLASH and Novel Integrated Vertical Cavity Surface Emitting Lasers (VCSELs)

When and Where

Dec 5, 2024
3:45pm - 4:00pm
Sheraton, Second Floor, Back Bay D

Presenter(s)

Co-Author(s)

James Pan1,2

American Enterprise and License Company1,Northrop Grumman2

Abstract

James Pan1,2

American Enterprise and License Company1,Northrop Grumman2
In recent years, Vertical NAND FLASH has replaced NOR FLASH in most of the hand held wireless digital markets, due to advantages of lower cost, higher packing density, and higher speed. However, the speed of NAND FLASH is still behind DRAM and SRAM used in computing tools, caused by the dielectric trapping, and tunneling processes, which result in longer WRITE and ERASE cycles. In this report, we will demonstrate an ultra-high-speed Photonic Vertical NAND FLASH with multiple VCSELs (Vertical Cavity Surface Emitting Laser), that may outperform DRAMs due to lower voltages and much faster nonvolatile memory operations. The new capability of integrated arrays of VCSELs with the high-speed Vertical Photonic NAND FLASH for lasing and nonvolatile data storage can be achieved. <br/><br/><br/>A Photonic Vertical NAND FLASH memory consists of a vertical NAND FLASH transistor (which is a traditional vertical NMOSFET with multiple gates as Word Lines), VCSELs (Vertical Cavity Surface Emitting Lasers) in the top drain region (Bit Line), or in the bottom source region, and photon sensors in the channel and well regions. When gate voltages are applied to the Word Lines, and a drain voltage is applied to the Bit Line, the entire vertical NAND FLASH NMOSFET is turned on (READ operation). When a gate voltage is set to 0V, the vertical NAND FLASH NMOSFET is turned off, so as the lasers and photon sensors. Much faster READ, WRITE and ERASE operations may also be accomplished with the photonic processes.<br/><br/>(1) Device Cross Section and Process Integration of the Vertical Photonic NAND FLASH will be presented.<br/>(2) Process issues, such as polysilicon well and channel regions, and how to deposition crystalline films for VCSELs, will be illustrated.<br/>(3) Equivalent circuits will be presented for READ, WRITE, ERASE operations of Photonic Vertical NAND FLASH.<br/>(4) Fowler Nordheim Tunneling, Frenkel Poole Tunneling, Traps-Enhanced FN Tunneling, and Photon-Enhanced Tunneling for Photonic NAND FLASH will be discussed. Photon-accelerated Hot Carrier Injection will also be analyzed.<br/>(5) Integrated VCSEL arrays with vertical Photonic NAND FLASH - designs for various applications and markets.<br/><br/>Ultra-high-speed operations with much lower voltages and power consumption can be achieved with the Photonic NAND FLASH technology. Process integration is compatible with available NAND FLASH process flows. Potentially Photonic NAND FLASH could outperform DRAMs.

Keywords

nanostructure

Symposium Organizers

Viktoriia Babicheva, University of New Mexico
Ho Wai (Howard) Lee, University of California, Irvine
Melissa Li, California Institute of Technology
Yu-Jung Lu, Academia Sinica

Symposium Support

Bronze
APL Quantum
Enlitech
Walter de Gruyter GmbH

Session Chairs

Yu-Jung Lu
Yang Zhao

In this Session