1998 MRS Spring Meeting & Exhibit

* Invited paper

TUTORIAL 

STB/C: FLAT PANEL DISPLAY MATERIALS AND LARGE AREA PROCESSING 
Monday, April 13, 1:30-5:00 p.m. 
Nob Hill B/C 

This course will provide an overview of the Flat Panel Display (FPD) market and detailed discussion of dominant and emerging FPD technologies. Topics include display-market trends, thin-film transistor technologies for active matrix liquid-crystal displays (AMLCD), reflective LCD technologies, Organic Light-Emitting Devices (OLED) technology, phosphor materials and Field Emission Display (FED) technologies, and plasma display technology. It is intended to serve as an introductory course for entry-level engineers and also to provide a survey of recent developments in FPD technologies for display industry professionals. 
Instructors: 
Tsu-Jae King, University of California-Berkeley 
Bruce Gnade, DARPA 

SESSION B1/A1: JOINT SESSION: 
AMORPHOUS AND POLY-Si TFTs 
Chair: Ruud E.I. Schropp 
Tuesday Morning, April 14, 1998 
Salon 7

8:30 AM *B1.1/A1.1 
HYBRID AMORPHOUS AND POLYCRYSTALLINE SILICON DEVICES FOR LARGE-AREA ELECTRONICS. Ping Mei, James B. Boyce, David K. Fork, Greg Anderson, Xerox Palo Alto Research Center, Palo Alto, CA; Mike Hack, Rene Lujan, Xerox dpiX, Palo Alto, CA. 

A natural extension of active matrix technology is the monolithic integration of peripheral drivers for the improvement of reliability, cost reduction and compactness of large-area electronics. This goal has been approached three ways, namely through large area polysilicon, amorphous silicon peripheral circuit design, and a mix of amorphous silicon pixel switches and polysilicon drivers. For some unique applications, we have developed the third approach to exploit the positive qualities of both amorphous and polysilicon in an intimate monolithic mix analogous to CMOS. Our process is a simple modification of the amorphous silicon transistor process which uses selective area laser crystallization. This approach allows us to share many of the process steps involved in making both the amorphous and polysilicon devices. The first major challenge which has arisen in this work relates to controlling the hydrogen evolution during the selective crystallization. The second major challenge was identifying a common gate insulator for both devices which would provide adequate control of the threshold voltage. Both issues will be addressed in the presentation. 

9:00 AM B1.2/A1.2 
a-Si:H THIN-FILM TRANSISTORS ON ROLLABLE 25-m THICK STEEL FOIL. Eugene Y. Ma and Sigurd Wagner, Princeton University, Department of Electrical Engineering, Princeton, NJ. 

Stainless steel has proven to be a substrate material that is surprisingly compatible with a-Si:H TFTs made from standard processing techniques even though the coefficient of thermal expansion for steel is 5 times that of a-Si:H. After deposition, the thin films comprising the TFT structure are forced to follow the thermal contraction of the much thicker substrate. We have observed, however, that a-Si:H TFTs fabricated on 25 m thick steel foil substrates are highly insensitive to the resulting strain. This evidence is obtained from evaluation of the electrical performance of these devices as a function of mechanical stress introduced by controlled bending. 
The TFTs were made in the inverted-staggered, back-channel etch configuration with 120 nm thick Cr gate electrodes, 320/160/50 nm PECVD SiN gate dielectric, a-Si:H channel, and n⁺ a-Si:H contact layers, respectively, and finally 120 nm Cr source/drain contacts, all on top of spin-on-glass (SOG) planarized steel foil with an additional SiN layer. The maximum process temperature is 350ºC used for the gate nitride. The resulting TFTs-on-steel can be rolled facing-in or facing-out to radii as low as 3 mm with only small drifts in TFT performance. In fact, at smaller radii of curvature the devices fail mechanically, peeling off at the SOG/nitride interface, before failing electrically. We show that under our bending tests, the mechanical stress can be made equal to the stress from differential contraction, and we will describe and analyze the results of electrical and mechanical tests as a function of substrate bending. 
Taking advantage of the flexibility and resiliency of these devices, we have fabricated TFTs using only xerographic toner masks printed directly on to the substrate. We have succeeded for the first time in overlay aligning each of the four mask levels in the laser printer, and will describe this novel process in detail. 

9:15 AM B1.3/A1.3 
SURFACE REACTIONS FOR LOW TEMPERATURE (110ºC) AMORPHOUS SILICON TFT FORMATION ON TRANSPARENT PLASTIC SUBSTRATES. G.N. Parsons, C.S. Yang, C.B. Arthur, T.M. Klein, A.I. Chowdhury, and L.L. Smith, Department of Chemical Engineering, North Carolina State University, Raleigh, NC. 

This paper describes initial results of chemical mechanisms for good quality low temperature amorphous silicon thin film transistor fabrication on transparent plastic substrates. Inverted-staggered TFTís formed in our lab on PET at a maximum process temperature of 110ºC have linear mobility of 0.11 cm²/Vs, on/off ratio > 10⁶, off current <10^-12 Amps, good quality n+ contacts, and minimal gate leakage. Silane/hydrogen mixtures were used for a-Si:H deposition. Mass spectroscopy and infrared transmission show that at temperatures between 250ºC and room temperature, H abstraction and etching reduce H content and control SiH/SiH₂ ratio. Silicon nitride film quality is predominantly sensitive to Si-H/N-H bond density ratio, and materials with optimized bonding can be formed with N₂/SiH₄/He plasmas with H content  20 at. at 110ºC. The process is sensitive to temperature because N-H bond formation proceeds through a thermally activated surface reaction. Using ammonia, the process is less sensitive to temperature, but H contents are about a factor of 2 larger. When smooth glass substrates are used instead of PET to form TFTís at 110ºC, an improved mobility is observed (0.33 cm²/Vs). Scanning force microscopy shows rms roughness of 4 to 5 nm on PET, compared to <1 nm for glass. Progress toward TFT formation on other plastic substrates will be presented. 

9:30 AM B1.4/A1.4 
STEPPED GATE POLYSILICON THIN FILM TRANSISTOR FOR LARGE AREA POWER APPLICATIONS. J. Aschenbeck, Department of Engineering, University of Cambridge, Cambridge, UNITED KINGDOM; Y. Chen, Department of Electrical Engineering & Electronics, University of Liverpool, Liverpool, UNITED KINGDOM; F. Clough, Y.Z. Xu, E.M. Sankara Narayanan, all from Emerging Technologies Research Centre, De Montfort University; W.I. Milne, Department of Engineering, University of Cambridge, Cambridge, UNITED KINGDOM. 

The standard polysilicon (poly-Si) High Voltage Thin Film Transistor (HVTFT) technologies currently available have a range of limitations. The Offset Drain (OD) HVTFT structure has a low on current [1]. Metal Field-Plate (MFP) HVTFT structures have and excellent on/off current ratio of 6 orders but require an additional bias connection to drive the metal field plate. MFP HVTFTs also have a modest blocking capability defined by the electric field peaks which arise at the edges of the MFP due to discontinuities in the bias voltages [1]. The magnitude of this peak field is a function of the field oxide thickness. More recently we demonstrated a HVTFT structure with a Semi-insulating field plate [1]. The SI HVTFT has a blocking capability in excess of 250 V but a switching speed which is limited by the rate at which the SI layer can be charged and discharged. In this paper we propose a new Stepped Gate (SG) HVTFT structure with a much improved switching performance relative to the SI HVTFT. The field oxide in the offset region is stepped to define two field oxide thicknesses. A MFP is connected to the polysilicon gate and covers both levels of the stepped field gate oxide. The result is a 3 terminal TFT structure with a field oxide thickness which becomes progressively thicker from source to drain. 2-D numerical simulation has been used to model both the dc (on/off ratio, blocking voltage) and transient performance of the device. The thicker field oxide near the drain results in a reduced peak field and a good device blocking capability. The Silvaco Atlas Device Simulation tool has been used to model the transient response times. The simulated transient response times are comparable to those of 4 terminal MFP structures. The on/off ratio is as good as in the SI Device. There is still a trade-off between on-current and device blocking capability which has to be considered. This has been optimised by simulations. 

9:45 AM B1.5/A1.5 
TRANSISTORS WITH A PROFILED ACTIVE LAYER MADE BY HOT-WIRE CVD. H. Meiling, A.M. Brockhoff, J.K. Rath, and R.E.I. Schropp, Debye Institute, Section Interface Physics, Utrecht University, Utrecht, THE NETHERLANDS. 

We report on thin-film silicon based transistors, TFTs, in which the channel material is deposited with the hot-wire chemical vapour deposition (hot-wire CVD) technique. Recently, we showed that with hot-wire CVD deposition rates for hydrogenated amorphous silicon, -Si:H, close to 20 Å/s can be achieved while maintaining good material and TFT properties. Also, these TFTs did not show any shift of the threshold voltage upon 1.5 h of gate bias stress, in contrast to conventional, plasma-deposited -Si:H TFTs. In this study we compare the behaviour of hot-wire deposited thin-film silicon transistors, in which the structure of the material changes from purely amorphous to completely polycrystalline silicon (poly-Si:H). We present the transfer characteristics before and after prolonged gate bias stress for up to 65 h. We also show cross-sectional transmission electron microscopy images of the semiconductor/insulator interface, and correlate the observed structures with results on crystallinity from Raman spectroscopy measurements. By diluting silane with hydrogen during hot-wire CVD a wide range of (profiled) materials can be made. With silane only, -Si:H is obtained, whereas when a mixture of silane and hydrogen is used, a 50-nm amorphous incubation layer is present in a furthermore completely poly-Si:H layer. Only at a very high hydrogen dilution of the silane gas we observe a completely poly-Si:H active layer, and the occurrence of the incubation layer at the interface is avoided. The poly-Si:H transistor with the -Si:H incubation layer did not show any threshold voltage shift, even after 65 h of gate bias stress. We suspect that the incubation layer is a heterogeneous layer with nanocrystalline domains. The fully -Si:H TFT showed a minor shift of 1.5 V after 65 h. A reference plasma-CVD -Si:H TFT showed a threshold-voltage shift of 8 V in the same time-frame. 

SESSION B2/A2: JOINT SESSION: 
AMORPHOUS SILICON AND PROCESSING 
FOR DISPLAYS 
Chairs: Ruud E.I. Schropp and Chuang Chuang Tsai 
Tuesday Morning, April 14, 1998 
Salon 7

10:15 AM *B2.1/A2.1 
HIGH CONDUCTIVITY GATE METALLURGY FOR TFT/LCD*s. Peter M. Fryer, IBM Research Division, Yorktown Heights, NY. 

Amorphous silicon based thin film transistor liquid crystal displays (TFT/LCD) have become the dominant technology used for flat panel displays for notebook computers. The need for higher resolution, larger diagonal displays for both notebook and desktop applications will be discussed. Currently used materials and processes are not always extendible as resolution and display size increase, and efforts to replace them can lead to substantial increases in manufacturing cost. Calculations have shown that the use of high conductivity gate metal, together with the implementation of improved groundrules, can significantly extend today's technology. For example, high conductivity gate metal such as aluminum and copper are highly desirable, but they are difficult to implement. Aluminum suffers from problems with hillock formation during PECVD processing, and copper typically has poor adhesion to glass, reaction problems with silicon and other PECVD films, and difficulties in contacting it to other metals. Approaches to solving problems with both materials will be presented, and a typical TFT fabrication process incorporating these materials described. 

10:45 AM B2.2/A2.2 
TFT-LCD FABRICATION TECHNOLOGY FOR DESKTOP MONITORS. C.W. Kim, C.O. Jeong, M.K. Hur, J.H. Souk, AMLCD Division, Samsung Electronics, Kiheung, Kyungkido, KOREA. 

As the notebook PC market is saturated, the TFT-LCD panel makers are looking for the new area and the desktop monitor market is the best candidate. Compared to notebook panels, monitors require large size panel fabrication and driving technology. Longer signal lines for large size panel affect the RC time delay of the signal. Low resistance materials are reviewed for gate line and data line materials. Properties of Al-alloy thin films as well as the fabrication technology of large size TFT panels are discussed. By using the Al-alloy metallization technology, high resolution and large size TFT-LCD monitors are realized. 

11:00 AM B2.3/A2.3 
CONTROLLED CRYSTALLIZATION BY SHORT PULSE LASER INTERFERENCE STRUCTURING OF AMORPHOUS SI FILMS ON GLASS. Silke H. Christiansen, Martin Albrecht, Horst P. Strunk, Uni Erlangen, GERMANY;. Christoph E. Nebel, Berit Dahlheimer, Martin Stutzmann, Walter Schottky Institut, TU Muenchen, GERMANY. 

We analyze by transmission electron microscopy, scanning electron microscopy and laterally resolved Hall measurements the relation between grain boundary distribution (i.e. grain boundary type and distribution) and electronical properties (mobility) of laser crystallized amorphous Si Layers deposited on glass substrates. The amorphous layers are crystallized by a frequency doubled Nd:YAG laser using the following three approaches: (i) short-pulse laser crystallization with two-beam and three-beam interference (interference structuring); (ii) generation of seed arrays based on interference structuring and subsequent thermal annealing for 12 hrs. at 650ºC; (iii) scanning the surface within multiple pulses using interference structuring result in forced growth of grains from the rim of the melted structures where nanocrystals of all orientation reside, to the centre. These grains are single crystalline with preferential orientations (fast growth directions <110> and <112>) and show a low defect density. Evaluation of the grain boundary types from electron backscattering pattern (EBSP) investigations and electron diffraction patterns reveal (i) a high amount of twin related tilt boundaries for the seeded growth experiments; (ii) the typical leaf-like structure for the thermally annealed material; (iii) a drastically increased crystal size for the scanning experiments. 

11:15 AM B2.4/A2.4 
SURFACE PLANARIZATION AND TEXTURE ENGINEERING OF THIN Si FILMS PREPARED VIA SEQUENTIAL LATERAL SOLIDIFICATION. M.A. Crowder, Robert S. Sposili, and James S. Im, Program in Materials Science, School of Engineering and Applied Science, Columbia Univ., New York, NY. 

The sequential lateral solidification (SLS) is a low-temperature excimer-laser crystallization process which can create large, location-controlled single-crystal regions in as-deposited amorphous or polycrystalline silicon films on SiO₂ [Appl. Phys. Lett. 70 (1997) 3434]. 
In this paper, we report on morphological and microstructural characteristics of the resulting SLS processed material, with particular emphasis on (1) improving the surface topology of the crystallized areas and (2) inducing constrained crystallographic textures in the single-crystal regions. The surface of the crystallized areas, examined using profilometry and atomic force microscopy (AFM), is found to be smooth on a microscopic scale, with gentle undulations (e.g., approximately 50 Å amplitude with a spatial period of several microns, for 2000 Å-thick films). 
It is found that these minor undulations can be further reduced by SLS of silicon films with a thick capping oxide layer. Additionally, we show that it is possible to preselect the texture of the single-crystal regions through ``seeding'' by inducing development of restricted crystallographic textures through multiple-pulse-induced-grain-growth of the film -- attained by irradiating at near-complete melting conditions -- prior to SLS. 

11:30 AM *B2.5/A2.5 
RECENT PROGRESS OF LOW TEMPERATURE POLY-SI TFT TECHNOLOGY. Kiyoshi Yoneda, LCD Division, Sanyo Electric Co. Ltd., Osaka, JAPAN. 

Currently, LCD manufactures pay a considerable effort toward the establishment of production technology in low temperature poly-Si TFTs because it promises to produce higher premium TFT LCD management on behalf of a conventional amorphous TFT LCD. In order to achieve a high yield in production, however, low temperature poly-Si technology must overcome a number of significant production challenges. In this article, we will submit the existing subjects of low temperature poly-Si technologies especially, CVD, ELA, and ion doping processes and discuss their recent progresses. 

SESSION B3: POLYSILICON TFTs AND CRYSTALLIZATION 
Chairs: Gregory N. Parsons and Chuang Chuang Tsai 
Tuesday Afternoon, April 14, 1998 
Nob Hill B

1:30 PM *B3.1 
SEQUENTIAL LATERAL SOLIDIFICATION OF Si FILMS: MATERIALS ANALYSIS, PROCESS OPTIMIZATION, AND DEVICE CHARACTERISTIC. James S. Im, M. A. Crowder, P. G. Carey, P. M. Smith, R. S. Sposili, and H. S. Cho, Program in Materials Science, Columbia University, New York, NY. 

The fact that single-crystal Si would make an ideal material for thin-film transistor devices has long been recognized. Despite this awareness, a viable method by which such a material could be realized on a glass substrate has never been formulated. Sequential lateral solidification (SLS) is a recently demonstrated excimer-laser-crystallization process that can produce such a material (i.e., single-crystal microstructure) for TFT and other applications. It utilizes spatially controlled manipulation of melting and ensuing lateral solidification to convert initially amorphous or polycrystalline Si thin film into either a directionally solidified microstructure, or location-controlled, large single-crystal regions on SiO₂-coated substrates, including those that are intolerant to high processing temperatures, such as glass or plastics. In this talk, we will discuss the following aspects of the SLS process: (1) the microstructural characteristics of the resulting material, (2) process-optimization related issues, and (3) device results on single-crystal SLS TFTs ‹ the device characteristics we have obtained from a first set of single-crystal (s-Si) TFTs (that are fabricated on SLS-processed Si films using low-temperature processing methods) were found to exhibit properties and a level of performance that are nearly comparable to similar devices that are fabricated on SOI substrates or bulk Si wafers. 

2:00 PM B3.2 
CO-OPTIMIZATION OF DEPOSITION AND LASER ANNEAL OF MICROCRYSTALLINE SILICON PRECURSOR MATERIAL FOR FABRICATION OF HIGH PERFORMANCE POLYSILICON TFTs. Apostolos T. Voutsas, Sharp Microelectronics Technology, Camas, WA; Aaron Marmorstein, Raj Solanki, Oregon Graduate Institute, Department of Electrical Engineering, Beaverton, OR. 

In this work we investigated the feasibility of microcrystalline silicon as the precursor material for the formation of high crystalline quality p-Si films by application of excimer laser anneal. At equivalent annealing conditions (laser energy density) polysilicon films obtained from c-Si precursor were found to demonstrate improved crystallinity (grain size, defect density) than that of laser annealed amorphous silicon films. We propose that the grain size enhancement, in the case of c-Si precursor, can be attributed to the improved microstructure that develops during the initial, rapid SPC stage preceeding the melting process during laser anneal. Proper engineering of the as-deposited film structure was shown to yield an at least twofold increase in the average grain size. Polysilicon thin film transistors (p-Si TFTs) were fabricated and characterized using this material and compared to our standard process. We found that the performance of c-Si precursor exceeds by 20-30% that of a-Si precursor, with typical values of performance attributes: =180cm²/Vs, Vth=2.5V, S=0.6V/dec. Moreover, use of c-Si was shown to allow for application of lower laser energy density levels to achieve the same level of TFT performance. This latter result may have important implications in reducing substrate damage during ELA process and increasing the width of the ELA process window. 

2:15 PM B3.3 
a-Si:H TFTs ON KAPTON. Helena Gleskova and S. Wagner, Princeton University, Princeton, NJ. 

We have fabricated a-Si:H TFTs on 51 m (2 mil) thick polyimide foil. We chose Kapton E (Dupont) because among the commercially available polyimide grades it has the lowest coefficients of thermal (12  10^-6/ºC) and humidity (9  10^-6/RH) expansion. We are seeking to establish a baseline r.f.-excited PECVD/photolithography process at 200ºC substrate temperature, and to evaluate the standard electrical performance of the inverted-staggered TFTs on Kapton, both in preparation of experiments on using toner etch masks. Therefore, in this paper we will emphasize process issues and TFT/substrate interaction.  Our process begins with the deposition of 500 nm thick SiN passivation layer, which is followed by thermal evaporation and patterning of 100 nm thick Cr gate electrodes. The SiN/a-Si:H/(n)a-Si:H stack is 430/160/50 nm thick. The evaporated Cr source/drain electrodes are patterned and then serve as masks for back-channel etch. At present the TFT performance is below that obtained on glass or steel foil substrates, because of differential thermal and humidity expansion, and of the difficulty of maintaining the integrity of hard films on a soft substrate. To establish a reproducible state of the Kapton we prebake the substrate in the load lock prior to deposition. When the structure is cooled after deposition and then brought to atmosphere, the Kapton first contracts thermally and then expands by uptake of humidity. We are seeking to design the structure and process to make these effects partially compensate each other, and will report results at the symposium. 

2:30 PM B3.4 
ELECTRICAL TEST SITES FOR AMLCD-TFT ARRAY PROCESS CHARACTERIZATION. Evan G. Colgan, Robert J. Polastre, Robert L. Wisnieff, IBM T.J. Watson Research Center, Flat Panel Display Technologies, Yorktown Heights, NY; Masatomo Takeichi, IBM Japan, TFT Array Process Engineering, Yasu, JAPAN. 

Electrical test structures provide a method of rapid and low cost end-of-process metrology for both materials properties and process specific information. We have demonstrated the use of electrical test structures for monitoring key TFT array process parameters such as line width, edge taper width, layer-to-layer alignment, and data metal coverage over topography. These results are compared with those from traditional metrology methods and in all cases, the correlation was very good, R²0.97, demonstrating that electrical test structures have sufficient accuracy for process control applications. For the structures used, the line width, edge taper width, and layer-to-layer alignment electrical measurements have uncertainties of less than 0.1 micron. A novel capacitance method was used for layer-to-layer alignment measurements and a combination of resistive and capacitive line width measurements were used to electrically determine the gate metal taper width. The test structures are all compatible with typical thin film transistor array processing. 

3:15 PM B3.5 
PASSIVATION OF POLY-Si THIN FILM TRANSISTORS WITH ION-IMPLANTED DEUTERIUM, Albert W. Wang and Krishna C. Saraswat, Stanford University, Dept. of Electrical Engineering, Stanford, CA. 

Poly-Si TFTs often require hydrogen passivation for adequate performance, but a passivator with better long-term stability than hydrogen is desirable. Recent work in VLSI CMOS technology indicates a dramatic reduction in hot carrier degradation when deuterium is substituted for hydrogen in passivation anneals for the gate oxide interface. The efficacy of deuterium to passivate states in poly-Si TFTs is compared to hydrogen. Both hydrogen and deuterium were ion-implanted into poly-Si TFTs, and measurements and gate-drain bias stressing were carried out after anneals at 350ºC, 400C, and 45º°C. Deuterated TFTs are more resistant to bias stress than hydrogenated TFTs in terms of PMOS performance and NMOS leakage current, but tend to be less resistant to NMOS threshold degradation. Additionally, the differences in degradation characteristics are much less dramatic than those seen in VLSI CMOS transistors. Deuterium is less effective than hydrogen at initial device passivation at lower annealing temperatures, but more effective at higher annealing temperatures. This is likely due to a combination of factors, including differences in diffusion and activation barriers for passivation/depassivation between hydrogen and deuterium. 

3:30 PM B3.6 
CORRELATION OF PERFORMANCE AND HOT CARRIER STRESS OF POLYCRYSTALLINE SILICON THIN FILM TRANSISTORS WITH SUBSTRATES AND SUBSTRATE COATING. Y.Z. Wang, O.O. Awadelkarim, Electronic Materials and Processing Research Laboratory, The Pennsylvania State University, University Park, PA; C.B. Moore, J.G. Couillard, Corning Incorporated, Corning, NY.

Abstract not available.