Symposium EP07—Next-Generation Interconnects—Materials, Processes and Integration

As semiconductor technology nodes scale towards 3 nm, there are acute difficulties in achieving interconnect scaling due to novel device architectures and dimensionality, design, performance and reliability issues. There are key interconnect scaling and packaging heterogenous integration strategies for future technology nodes. Co-optimizing these strategies determines the overall best definition to enable continued Moore’s law scaling.
For future semiconductor nodes, the ability of optical patterning to support the required interconnect pitches is in doubt. This is the driving factor for the introduction of EUV lithography to continue dimensional scaling. Even with EUV patterning, there are additional design methodology challenges such as the lack of wiring track level reduction due to process related block level scaling issues. From a traditional materials science perspective, BEOL resistance and capacitance is a significant portion of the parasitic degradation of overall technology performance. As physical wire and via sizes decrease, BEOL resistance increases exponentially with decreasing area due to surface and grain boundary scattering and a lack of scaling for Cu diffusion barriers such as TaN. Challenges for BEOL capacitance include integration issues which drive the effective dielectric constant higher than the modeled values. BEOL reliability is challenged by operation voltage requirements and by novel device architectures which strain electromigration and dielectric breakdown performance.
To mitigate these challenges and continue Moore’s law scaling, novel design methodologies decrease the number of wiring tracks in standard cell libraries and increase the wiring levels to improve both performance and density. EUV lithography is replacing optical lithography to enhance design and performance, requiring fewer design rule restrictions, improving patterning tolerances, and enabling bi-directional metal and process simplification. Hardware teams will implement novel processes to enable recovery of resistance and capacitance scaling and to support electromigration and time dependent dielectric breakdown reliability. These patterning and process improvements are needed to support novel device architectures in technologies such as scaled FinFET and Stacked-Si-Nanosheets.
To further mitigate challenges in interconnect scaling, heterogeneous integration of IP has been migrating from SoC (System on a Chip) to SIP (System in Package). This introduces the challenge to use novel packaging techniques with high density interconnects to achieve enhanced functionality and improve bandwidth and latency. There are novel architectural, integration and material related innovations that address the challenges for the continuing enablement of Moore’s law scaling.

Amorphous low-dielectric constant (low-k) and high-dielectric constant (high-k) materials have dominated the nanoelectronic materials research scene over the past decade, but have recently reached a state of maturity and perhaps their scaling limits. Based on this, one may ponder the direction of nanoelectronic dielectric materials research and the future of the field. However, as we will clarify, there is still plenty of room to grow!
In this address, we seek to illustrate that high-k and low-k dielectrics represent just a tiny fraction of the numerous dielectric materials utilized in nanoelectronic products and that numerous new applications for dielectric materials are emerging as the industry transistions to novel patterning schemes and prepares for life post CMOS scaling. We will begin by briefly exploring the entirety of dielectric materials utilized in advanced nanoelectronic products with a particular focus on often ignored etch stopping, diffusion barrier, and passivation dielectrics and their more specialized requirements. We will then transition to examining the various novel pitch division schemes being developed to cope with the delay of EUV lithography and the abundant new dielectric material applications these schemes create. We will specifically focus on the various new spacer and hard mask dielectrics that pitch division requires, their colorful etch selectivity requirements, and suggest future research needed to enable even more exotic patterning schemes.
We will further examine how what was once old can become new again and specifically explore how both high-k and low-k dielectrics are being utilized to fill the needs of future beyond CMOS devices. In particular, the application of high-k and low-k dielectrics in novel resistive switching device applications will be examined. We will conclude by reviewing the unique obstacles that dielectric materials present for the realization of advanced cryogenic quantum computing architectures and the necessary associated research vectors to prevent dielectrics from becoming quantum computing’s Achilles heel.

The successful integration of ULK dielectric films into microelectronic device interconnects has been challenging due to their poor thermal and mechanical properties. We have developed computational tools to investigate the fundamental molecular level parameters controlling the properties of these materials, and also have shown that they exhibit very surprising phenomena ranging from asymmetric elastic behavior to non-affine deformations, and can be engineered to exhibit time dependent inelastic deformation characteristics. In this work, through molecular dynamics simulations we present new design strategies at the molecular level focusing on two unique ways to effectively enhance the mechanical properties: Firstly, we demonstrate how hyperconnected networks with a connectivity exceeding the chemical coordination number of silicon increase elastic modulus. Secondly, we show how hyperstiff precursor molecules themselves with specific geometrical features, which have not been previously considered, can be exploited to further reinforce the rigidity of hyperconnected films. We define a hyperstiff precursor as one with a cyclic planar organic group, an example of which is triethoxysilyl benzene (1,3,5-benzene). The impact of utilizing these two main parameters is such that we are able to design ultrastiff hybrid films with a modulus that goes beyond that of fully dense silica, while still maintaining an ultra low density and dielectric coefficient. One immediate implication of the design of these ultrastiff hybrid networks manifests itself as a new and highly effective method to improve the mechanical robustness of nanoporous hybrid films. Our results show that the nanoporous films designed with an ultrastiff hybrid matrix lead to three to four times increase in the elastic modulus compared to porous films with traditionally bridged networks containing less stiff organic chains, such as ethane-bridged oxycarbosilane (Et-OCS). This substantial increase in the stiffness of nanoporous hybrid films is a crucial step taken to minimize the limitations due to poor mechanical properties, thereby allowing for new opportunities to fully benefit from the ultra low dielectric coefficient of porous thin films.

Three-dimensional integrated circuit (3D IC) integration attracts much attention because it has the potential to enhance IC performance and allows the integration of heterogeneous devices [1]. One approach consists in stacking vertically several chips which are electrically connected with through-Si vias (TSVs). Among the different ways to create TSVs, via-middle integration allows the TSV realization between the front end of line and the back end of line (BEOL) while TSVs are built after the BEOL in via-last integration. One of the key steps in the TSV fabrication is their electrical insulation from the silicon substrate. Usually, SiO₂, deposited by Plasma-Enhanced CVD or by Sub-Atmospheric CVD depending on the integration scheme, is used as the TSV-liner material. However, the use of SiO₂ presents some limitations in order to realize advanced 3D IC, such as a poor step coverage (using PECVD) and higher dielectric constant compared with the low-κ interlayer dielectric material of BEOL. Through-silicon via with polymer liners has attracted attention because these polymers have a low dielectric constant and their expected mechanical compliance can enable higher TSV integration by suppressing the TSV-induced stress [2-3]. However, even though several demonstrations were published in the literature, the TSV insulation using organic polymers is not yet adopted.
In this work, organosilicate thin films were deposited by initiated Chemical Vapor Deposition (iCVD). This deposition technique, which is a low-energy (no plasma) and solvent-free method, allows to deposit organic or hybrid polymers at low substrate temperature, thus compatible with the TSV-last thermal budget requirements. Poly(V3D3) thin films were deposited from trivinyl-trimethyl-cyclo-trisiloxane as the monomer and tert-butyl-peroxide as the initiator. First, the impact of process conditions on the deposition rate, chemical composition and step coverage was investigated. A combination of FTIR, ellipsometry, ellipsometric porosimetry, ToF-SIMS analysis, SEM and electrical characterizations was used to characterize the structure and the properties of the films. It is shown that poly(V3D3) thin films deposited at low temperature (typically lower than 100°C) can present low dielectric constant (down to 2.7) with conformality close to 50% in 10*100 μm TSVs. Moreover, the impact of annealing on the thermal stability of the films was studied. After appropriate curing (thermal-only or UV-assisted), the dielectric film is stable up to 400°C. Finally, a full TSV integration was completed (via-middle integration) using a standard Cu metallization process on 300 mm wafers. This work highlights the advantages and limitations of these low-κ polymer dielectrics for TSV insulation and the demonstration of integration on 300 mm wafers opens the way to the use of iCVD in microelectronics.

[1] J. Gambino et al. “An overview of through-silicon-via technology and manufacturing challenges”, Microelectronic Engineering 135 (2015) 73-106.
[2] H. Kino et al. “Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs”, Proceedings of IITC (2018) 135-137.
[3] S. Lee et al. “TSV Liner Dielectric Technology with Spin-on Low-k Polymer”, Proceedings of ICEP-IAAC (2018) 346-349

Advances in interconnect technologies have played a key role in the rapid pace of semiconductor scaling. Since the introduction of copper interconnects in the late 1990’s, the materials set for back-end wiring has remained remarkably constant through the development of multiple technology nodes. Tantalum-based liners and copper conductors have enjoyed wide use during this ongoing evolution, which has resulted in a greater than ten-fold reduction in feature sizes. Recent advances have driven a newer, more diverse set of interconnect wiring materials among major semiconductor producers. After many years of development, alternative liner and capping materials are now being introduced into volume production to extend gap-fill and reliability. The effects of scaling on interconnect resistance and performance will be covered, with emphasis on more recent technology nodes. As wiring dimensions shrink below the 40nm mean-free path of electrons in copper, the resistance of copper wires rises dramatically due to electron scattering effects. The extrapolation of these scaling trends indicates that a transition is rapidly approaching at which point copper wiring will no longer enjoy a performance advantage, and new conductor materials will be needed. We will summarize screening criteria for alternative conductors at the 7nm technology node and beyond and review recent results for leading material candidates and integration schemes.

In local interconnection of advanced LSI, copper alternative materials have been sought to mitigate the increase of Cu line resistivity with decreasing line width. The required properties for the alternatives are small value of r₀ x l for low resistivity in narrow lines, slow diffusivity for good electro-migration resistance under high current density, low melting temperature for easy grain growth at low process temperature, small Young’s modulus for easy CMP. Proposed materials to date include pure metals, alloys, carbides, nitrides, and silicides. In addition, low and stable material cost is an important factor to be considered.
To provide feasible alternatives which satisfy these properties, we focus intermetallic compounds. For example, NiAl is an ordered bcc compound having a bulk resistivity of 9 mW-cm. It is a well-known heat resistant material having a high melting point of 1638 °C, thus a good electromigration reliability may be expected. Meanwhile, NiAl has a large cohesion energy of -568 kJ/mol, hence the interdiffusion and detrimental reaction of individual Ni or Al ions with Si and SiO₂ may be suppressed. Furthermore, Al oxide has heat of formation of -1678 kJ/mol, much higher than -911 kJ/mol of SiO₂, so there is a tendency for Al atoms to bond with O atoms at the NiAl/SiO₂ interface, possibly leading to good adhesion.
Experimental results showed good adhesion and no interdiffusion between NiAl film and SiO₂/Si substrate. Similar results were obtained in other selected intermetallic compounds. The possibility of intermetallic compounds will be discussed in detail as the Cu alternative.

Electroplated damascene copper has been used for more than 20 years for interconnects in semiconductor and microelectronic industry[1]. As the structures continue to scale, the coarse grains formed during annealing become increasingly difficult to extend into the fine structures, resulting in higher resistance and poorer electro-migration[2]. In addition, as the dimension of structure approaches or falls below the electron mean free path of copper, the resistivity exponentially increases[3], demanding a material change for future technologies. This talk presents fundamental studies on the electrodeposition of cobalt in presence of a class of organic additives, dioxime, to modulate the deposition rate and impurities in cobalt.
Suppression of cobalt deposition was observed upon the addition of dioxime molecules and such suppression effect was found to result from an adsorbed Co-oxime complex structures, which breaks down upon the application of more negative bias. Such break down not only kicks off the deposition of cobalt but also results in the incorporation of impurity elements, such as Carbon, Hydrogen and Oxygen. The nucleation and growth at the beginning of deposition was studied, aiming to understand the limitation on the formation of continuous cobalt films. A two-step nucleation phenomenon was observed for the first time due to the reduction reactions from the chelates and free cobalt ions. A second chemical species was used to purposely introduce different impurity elements into the deposited Co films, aiming to understand the effects of different impurities on the grain structure of cobalt.
REFERENCES
1. P. Andricacos, C. Uzoh, J. Dukovic, J. Horkans, and H. Deligianni, Damascene copper electroplating for chip interconnections,IBM Journal of Research and Development, 1998, 42(5), 567.
2. C.K. Hu, L. Gignac, B. Baker, E. Liniger, R. Yu, and P. Flaitz. Impact of Cu microstructure on electromigration reliability. in IEEE 2007 International Interconnect Technology Conference, 93, 2007, Burlington, CA.
3. W. Steinhögl, G. Schindler, G. Steinlesberger, and M. Engelhardt, Size-dependent resistivity of metallic wires in the mesoscopic range,Physical Review B, 2002, 66(7), 075414.

The electrical reliability of multilayer HDI/BGA-PCBs¹⁾ is mainly affected by the thermo-mechanical stability of stacked micro via interconnections. Here, a critical failure mode is the stress related crack between the electrolytically filled via and the target pad, commonly known as target pad separation. The junction includes two Cu-Cu-interfaces, one between the target Cu pad and the thin electroless Cu layer and the second between electroless Cu and electrolytic Cu.
Large nano-voids (with dimensions of several ten to several hundred nm) and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link to the target pad. These failures are mostly related to insufficient etching and cleaning of the target pad or persistently adsorbed organic residues at the as plated Cu-surfaces and are well observable via standard inspection tools such as cross-sectioning and electro or ion-polishing in combination with SEM²⁾. Recently, closer inspections of such junctions were performed via Transmission Electron Microscopy on thinned lamellas down to 50-60 nm. In a special transmission mode of TEM (HAADF²⁾-mode) a substantial density (up to 30000 µm^-3) of circular shaped “black spots” were found with diameters of lower than 10 nm, i.e. below the spatial resolution of commercial FIB/SEM²⁾-tools. These “black spots” are localized within or closed to the electroless Cu-layer.

In the first part of the paper we will present HR-STEM, XEDS²⁾ and EF-TEM²⁾ measurements, in order to identify the origin of the “black spots” in the TEM-images.
Here STEM/HAADF and Bright-Field TEM point to less material inside of these “black spots”, whereas energy filtering TEM indicates less average lamella thickness within the features. In combination with XEDS-mapping, where no chemical composition difference between the spot region and the Cu-bulk region was found, we conclude that the observed black spots are most likely voids.
To evaluate the impact on the junction reliability and to find probable root causes of this newly discovered void-phenomenon, an extensive field study of more than 400 TEM investigations was performed. TEM in combination with XEDS enables the localization of the electroless Cu layer in the junction by detecting the codeposited Ni (typ.: 0.2-1.5 at%) and a precise assignment of the nano-void affected interfaces or layers.
This nano-void field study comprised the investigation of HDI and BGA-multilayer PCBs with stacked vias produced by several industry partners and single layer reliability test boards produced in industry like on-site facilities (Atotech Techcenters), accompanied by some laboratory plating tests.
Different types of industrially relevant electroless Cu pretreatments, Pd-activator systems, electroless Cu baths and filling Cu-electrolytes were included in the test matrix, as well as the impact of subsequent thermal treatments (one to ten IR-reflow¹⁾ cycles).
Based on this field study, we will present in the second part of the paper a classification of the most relevant nano-void phenomena, determined by the affected interfaces/layers and their appearance after plating or subsequent thermal treatments (IR-reflow). Formation mechanisms and root causes will be discussed as well.

¹⁾HDI-High Denity Interconnections, BGA-Ball Grid Array, PCB-Printed Circuit Board, IR-Infra Red
²⁾FIB-Focused Ion Beam[SK1] , SEM-Scanning Electron Microscopy, HR-STEM- High Resolution Scanning Transmission Electron Microscopy, HAADF-High Angular Annular Dark Field, XEDS-X-Ray Energy Dispersive Spectroscopy, EF-Energy Filtering

The accurate reliability prediction in the development phase is one of the big challenges to achieve the next generation of interconnects. Moreover, for the early adoption of the technologies, the early failure due to process variability defects and a late failure determined by the intrinsic characteristics of materials should be evaluated and improved simultaneously. However, it is difficult to evaluate them accurately for the less-mature technology because of production performance variabilities and small size experiments.
The combining of physical modeling and statistical techniques is one of the approaches to solve the lack of stabilities. Conventional statistical methods to estimate chip-level reliability are described with a competing policy, as the weakest link. Underlying features of the lifetime characteristics are explained by the distribution functions that have definite shape and scale parameters like Weibull and Lognormal distributions. These functions well describe the intrinsic lifetime characteristics but do not express the impacts of the degree of completion. Recently, the distribution families that have two shape parameters is applied to understand and explain the variability impacts. To utilize them effectively, the correlation between the physical mechanism of failure and the shape of distribution must be considered theoretical and experimental.
In this talk, two applications of the statistical distribution are introduced about the lifetime of back-end reliability. The first application is a time-dependent dielectric breakdown(TDDB) under defect clustering condition in back-end-of-line(BEOL) and middle-of-line(MOL) explained by the generalized Burr type XII distribution (GBXII). Because the decrease in spacing has become too excessive, impacts of process variations on product yield and reliability have also become much pronounced. The spacing variation represents the variation of reliability stress and accelerates the breakdown phenomenon around a small space called the "clustering defect." Therefore, understanding the defect impacts on lifetime distribution provides information on not only reliability estimation but also the process variability and TDDB in BEOL and MOL. The GBXII has two shape parameters, and one of them is the clustering parameter that indicates the degree of the defect clustering. A statistical method for the GBXII analysis on TDDB will be introduced.
The second application is a simple prediction method for chip-level electromigration based on segment lifetime. From the distribution of segment lifetime and current density, the chip-level lifetime distribution is approximated by the generalized gamma distribution (GENG). The second shape parameter of the GENG can indicate whether the chip-level distribution is close to the lognormal or Weibull distribution in conjunction with lifetime variation due to process fluctuation and circuit size. Proposed method using GENG can provide the prediction of the chip-level electromigration lifetime for a novel technology without a real circuit design.
These approaches enable to understand impacts of the process variation and the circuit size. It will provide the necessary information for the early adoption of the novel technology to use.

Electric current stressing has been reported to affect the microstructure of metallic materials along with the variations in mechanical properties and other material performance. The electric current stressing can facilitate recrystallization behavior and thus lower the recrystallization temperature of metals. In the present study, the microstructure-properties correlation of pure Sn metals induced by electric current stressing was investigated. The pure Sn strip was quenched in liquid nitrogen after designed periods and cycles of electric current stressing. The mechanical and electrical properties of the pure Sn strips were investigated using Vickers micro-hardness tester and 4-point probe, respectively. The micro-hardness increases with respect to the current density ranging from 5000 to 6500 A/cm² and reaches a maximum value at 6500 A/cm². The maximum enhancement in micro-hardness shows a 35% increment compared with the value of the as-annealed specimen. However, the electric current stressing at higher current densities (7000 and 7500 A/cm²) lowers the micro-hardness, showing a two-stage mechanical property variation between relatively low current density one (5000-6500 A/cm²) and relatively high current density one (7000-7500 A/cm²). In general, all the electric current stressing conditions investigated were found to enhance the micro-hardness of the Sn strips. Dissimilar to the variation trend of micro-hardness, the sheet resistance of the pure Sn strip slightly decreases after cycles of direct current stressing. The average grain size and grain orientation of the Sn metals were investigated using electron back scattered diffraction analysis. The results show that an increasing number fraction of fine grains, corresponding to a general lowering in grain dimension, with the increasing electric current density at the first stage of relatively low ones (5000-6500 A/cm²). However, grain coarsening was observed at relatively high current densities (7000-7500 A/cm²) due to the Joule heating effect. The activation energy for the two-stage micro-hardness variations induced by electric current stressing was estimated, and the mechanisms behind were further disclosed in this research.

Aluminum has been used as global interconnects for semiconductor products due to relatively low resistivity and compatibility with Si process. However, the difference in the thermal expansion coefficient (CTE) between Al and Si is very large, which can cause hillocks due to the stress applied to the Al interconnects during repeated heat treatment. These hillocks can lead to reliability problems, such as electrical circuit shorts between interconnects. Therefore, it is very important to find and control the factors that can suppress the hillocks in order to produce highly reliable products.
In this study, we will discuss the effect of doping other materials on Al thin films. Ti and Ru are selected as doping materials because the differences in the CTE with Si are smaller than Al and the melting point is high. Therefore, it is expected that the hillocks formation will be suppressed by the reduction of diffusion during repeated heat treatment.
Pure Al and Al alloy films were fabricated using DC magnetron sputter on SiO₂/Si substrate. By the wafer curvature method, the abrupt compressive stress relaxation in both the Al-Ti and the Al-Ru alloy film was observed at a certain temperature range. It was found by XRD measurement that the alloy precipitated at this temperature range. By transmission electron microscopy and ASTAR analysis, compared with the Al-Ti alloy film, the amount of alloy precipitation in the Al-Ru alloy film is more than four times that of the Al-Ti alloy film. The surface roughness (RMS) using AFM analysis of the pure Al, the Al-Ti alloy and the Al-Ru alloy were 14.7nm, 19.4nm and 4nm, respectively. It was confirmed that hillock of the Al-Ru alloy was mostly suppressed.
Both the Al-Ti alloy film and the Al-Ru alloy film have smaller grain size than the pure Al film. As the grain size decreased, grain growth during annealing reduce the compressive stress and suppress the hillocks. In addition, more alloy precipitation was found in Al-Ru alloy film than in Al-Ti alloy film, which helps hillocks suppressed mostly due to densification. Hence, Ruthenium is interesting candidates with potential as dopant for Al interconnects.

Cobalt-tungsten alloys have drawn huge attention in many fields owing to their outstanding mechanical, tribological, and magnetic properties.[1] In addition, the studies about electrical and magnetic properties of Co-W alloys are arising for the electrical devices and magnetic applications, which are regarded as suitable next generation candidates for contact plug, recording media and microelectromechanical systems (MEMS) like micromechanical magnetometers, microsensors, and microactuators.[2] However, their promising features have been only focused on thin films so that the researches to Co-W alloy nanowires are still at the early stage.
In this work, Co and Co-W alloy nanowires are synthesized by the electrodeposition from citrate-borate electrolyte with porous anodic aluminum oxide (AAO) templates. Meanwhile, tungsten has relatively negative cathodic deposition potential or very low hydrogen overpotential. Thus, pure tungsten can not be directly deposited alone from aqueous W solution by the electrodeposition.[3] However, when it is co-deposited with Co, Co-W alloys can be easily formed. Shape and composition of Co-W alloy nanowires can be easily controlled by varying the concentration of electrolytes or the applied current density.
Scanning electron microscope (SEM) was used to examine the morphology of alloy nanowires. Every alloy nanowire from different experimental conditions has identically cylindrical shape. The difference among them is the growth rate. W content of nanowires is determined by energy dispersive spectrometer (EDS). The microstructure depending on the amount of tungsten atoms is analyzed by x-ray diffraction (XRD). Pure Co and Co-W alloy nanowires with low W content have hexagonal close packed (HCP) structure. When the W content increases slightly, Co atoms are substituted by W atoms whose size is bigger than that of Co atoms. Therefore, the peak position of XRD shifts to the smaller value. For nanowires containing more than 21 at.% W, amorphous Co₃W phase is deposited significantly. Thus, XRD patterns exhibit broad lines. Also, the change of microstructures according to the amount of W is found by selected area electron diffraction (SAED). Magnetic and electrical properties were measured through vibrating sample magnetometer (VSM) and focused ion beam (FIB).

Reference
[1] N. Tsyntsaru et al., Surface Engineering and Applied Electrochemistry, 48, 491 (2012)
[2] U. Admon et al., Journal of Applied Physics, 59, 2002 (1986)
[3] Z. Galikova et al., Chemical Papers, 60, 353 (2006)

Tantalum triselenide (TaSe₃) is part of the transition metal trichalcogenides (TMTs) family and are of interest due to their high conductivity and low dimensionality. These quasi 1D nanorod structures show promise for future applications as replacement interconnect materials as copper reaches its limits due to surface and grain boundary scattering effects. The main goal of this work is to develop a facile synthesis method and study the properties of these nanorod materials as the cross sections is thinned to the nanometer scale. Here we present a novel chemical vapor deposition (CVD) method which produces TaSe₃ nanorods directly on an SiO₂/Si substrate in under an hour. There nanorods are characterized using Raman spectroscopy and electronic transport measurements revealing their behavior when scaled down to the nanometer scale.

Cu films are widely used for interconnections in microelectronics. In some applications, reliable thin-film connecting elements having high electrical conductivity, mechanical stability and adhesion to the glass substrate are required. In this case the length of the elements amounts to tens of centimeters.
In this paper, Cu was used as the basis for the connecting elements. To ensure high adhesion Cr was used as an underlayer.
The substrate material was glass made of SiO₂ (73%), Na₂O (13%), CaO (8.5%) and other oxides. Cu and Cr films were applied by thermo-vacuum evaporation at residual pressure in the chamber of 10^-6 – 5×10^-7 mmHg. The structure of the films was analyzed on a JEOL-50A scanning microscope. For the study of defect formation, electron and light microscopes were used.
The paper investigates the structure, electrical conductivity, adhesion, defect formation of Cu, Cu-Cr, Cr-Cu-Cr thin-film conductors.
As a result of the conducted research, the regularities of changes of the film structure, electrical conductivity, adhesion, defect formation depending on the technological process parameters were established. Physical and technological mechanisms determining the observed patterns are considered.
The research results are used in the technological regulations for the devices production.

Copper has low leakage and low power consumption due to its lower resistance and faster signal transmission than aluminum. Copper has a high electron migration resistance and is a stable interconnect material. When copper is used as interconnect, it is prepared by damascene process which includes electroplating and chemical mechanical polishing. Since copper has very low reactivity and copper compounds often have high vapor pressure, it is known to be very hard material to etch using a conventional dry etching. As the critical dimension of the devices is diminished under tens of nanometer, the fatal disadvantages of the damascene process are revealed, which demands the development of novel dry etching technique of copper thin films.
In this study, the etch characteristics of copper thin films masked with SiO₂ films were examined under CH₃COOH/Ar gas using inductively coupled plasma reactive ion etching. The etch rate of copper films and SiO₂ hard mask, and the etch selectivity of copper films to SiO₂ mask, and the etch profile were investigated as a function of CH₃COOH in CH₃COOH/Ar gas. Major etch variables including coil rf power, dc-bias voltage to the substrate, and the process pressure were applied to evaluate the etch rate, etch selectivity and etch profile.
The evolution of etch profile of copper films in CH₃COOH/Ar was observed to understand the etch process. The optical emission spectroscopy of the plasmas produced from various CH₃COOH concentration in CH₃COOH/Ar was measured to determine the active species in the plasmas. In addition, the energy dispersive X-ray spectroscopy and X-ray photoelectron spectroscopy for the etched copper surfaces were performed to elucidate the etch mechanism by identifying the copper compounds, if any.
Besides, pulse-modulated plasma has been applied to etch copper films, which has the variables such as the on-off duty ratio and the frequency of the plasma. The effects of pulse-modulated plasma on the etch characteristics of copper were examined. The etching by pulse-modulated plasma is expected to reduce redeposition and etching by-products compared to that by continuous wave plasma.

Acknowldgments This research was supported by the MOTIE(Ministry of Trade, Industry & Energy (10080450) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Advanced packaging solutions, particularly 3D integration technologies, are additional boosters for performance and functionality of microelectronic products. However, at the same time, 3D heterogeneous system integration becomes increasingly challenging for product reliability. This talk will address the nondestructive localization and characterization of defects in interconnects to mitigate reliability-limiting effects in 3D IC stacks. Particularly, the geometry of 3D Through-Silicon-Via (TSV)/micro-bump stacks and defects (voids and micro-cracks) in these metallic structures as well as micro-cracks in Cu/low-k Back-End-of-Line (BEoL) stacks caused by thermomechanical stress (Chip-Package Interaction, CPI) will be discussed. We will demonstrate the applicability of sub-micron and nano X-ray computed tomography (XCT) for nondestructive 3D imaging of advanced packaging and BEoL interconnect structures. The shape of solder interconnects and TSV etch profiles are imaged as well. Defects like filling voids in Cu TSVs and micro-cracks in AgSn solder micro-bumps are clearly visualized too using full-chip region-of interest tomography [1].

Package-induced thermomechanical stress increases the risk of failure caused by delamination along metal/dielectrics interfaces or fracture in dielectrics with low fracture toughness in BEoL stacks. The 3D visualization of crack evolution in Cu/low-k interconnect stacks is demonstrated using an experimental setup which combines X-ray microscopy with in-situ mechanical loading. High-resolution 3D image sequences based on nano XCT are acquired during mechanical loading within the X-ray microscope to visualize crack opening and propagation in fully integrated BEoL structures with about 100 nm resolution [2]. As a result, the weakest layers and interfaces are identified, and the robustness of the BEoL stack against chip-package interaction is evaluated. The obtained results provide valuable information for reliability engineering and design-for-reliability (DFR) in semiconductor industry.

Laboratory micro and nano XCT offer intrinsic advantages in the fields of 3D imaging, physical failure analysis, and metrology of electrical interconnects in semiconductor products for both advanced packaging and on-chip interconnect structures by employing a multi-scalar approach. Perspectives to overcome two major limitations of state-of-the-art nano XCT tools, i.e. the necessity of sample preparation (typically less than 50 mm thickness, depending on the material composition, if 8 keV photons are used) and low imaging throughput, are discussed. A novel tool concept for X-ray microscopy at high photon energies, using advanced X-ray sources with high flux and the option of multi-energy photons [3], and of advanced X-ray optics with high efficiency at photon energies > 10 keV [4], will be presented.

[1] E. Zschech et al., "3D IC Stack Characterization using Multi-Scale X-Ray Tomography”, Proc. 20^th PanPacific Microelectronics Symposium, Kolao/HI (2015)
[2] K. Kutukova et al., "A laboratory X-ray microscopy study of cracks in on-chip interconnect stacks of integrated circuits“, Appl. Phys. Lett. 113, 091901 (2018)
[3] W. Yun et al., “Impact of new high flux laboratory systems”, Synchrotron Radiation Instrumentation Conf. SRI, Brookhaven (2015)
[4] S. Niese et al., “Full-field X-ray Microscopy with Crossed Partial Multilayer Laue Lenses”, Optics Express 22, 20008-20013 (2014)

Superconducting qubits are a prime candidate for constructing a large-scale quantum processor due to their lithographic scalability, speed, and relatively long coherence times. As superconducting quantum processors move beyond the few-qubit scale, it will become increasingly important to develop techniques for addressing large numbers of qubits without degrading their performance. 3D integration can alleviate interconnect crowding and enable the construction of large-scale arrays of coherent superconducting qubits. At Lincoln Laboratory, we are pursuing an approach where high-coherence qubits are isolated from a potentially lossy readout and interconnect chip by an intermediate chip with superconducting through-silicon vias. The three-tier stack is bonded using indium bump bonds, which provide structural support and can be used to galvanically connect metal on different chips. I will present our recent work on developing and characterizing critical components for 3D integration, including indium bumps and superconducting through-silicon vias, and discuss progress towards building 3D integrated coupled qubits.
This research was funded by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA) and by the Assistant Secretary of Defense for Research & Engineering under Air Force Contract No. FA8721-05-C-0002. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of ODNI, IARPA, or the US Government.

3D sequential integration is a promising approach to obtain a vertically stacked FETs (Field Effect Transistors) scheme [1]. This integration offers a very small 3D contact pitch which leads to a wide spectrum of applications like the increase of integration density beyond device scaling [2]. Such an integration requires to limit the thermal budget of top FET processing (T=500°C) [3]. A major challenge is to fabricate high-performance FETs at the top level without electrical characteristic degradation of the bottom active layers.

In order to fulfill the 3D sequential integration requirements, the use of Cu metal lines and ultra low-k dielectrics materials between the two FET levels is mandatory. This intermediate Back End Of Line (iBEOL) is still challenging. Indeed, the thermal budget used to process top transistors is far higher than what is usually requested for CMOS interconnects [4], and it can greatly influence material properties and generate defects into the Cu metal lines and in the low-k dielectric.

In this work, the thermal stability of state-of-the-art BEOL structures with four levels of standard Cu/low-k interconnects was evaluated by applying different post-annealing. For this study, experiments were performed on a damascene BEOL integration of state of the art 28 node FDSOI technology on 300 mm wafers [5]. Inter-Metal-Dielectric was composed of 100 nm of porous SiOCH and 20 nm of SiCNH etch stop layer. A SiCNH layer encapsulated the four metal lines/vias levels. Then, different annealing processes (at variable temperatures from 400°C to 600°C) were applied to simulate the thermal budget that the wafers go through during the realization of the top level FETs. Electrical reliability tests on metal 1&2 and via 1&2 were performed after the removal of the SiCNH encapsulating layer.

The breakdown voltage for line to line and via to line is not significantly modified after a thermal annealing at 500°C for 2h. At higher annealing temperatures, a degradation of the time to breakdown is observed but these modifications cannot be attributed to metal line degradation since no change in the line resistance has been observed. To better understand the mechanisms involved during thermal annealing on the integrated dielectric, the impact of a thermal process on the intrinsic properties of a porous low-k in free surface condition (no capping) was studied. Firstly, constant voltage stress experiments were performed on simple Metal-Insulation-Metal structures with the same low-k as the one used in the four metal levels integration. Secondly, in depth material characterizations (such as FTIR, ellipsometry, Electron Spin Resonance) were performed. By combining these material data with electrical reliability tests on integrated structures, this work shows that Cu/low-k interconnects can be used in the intermediate BEOL for 3D sequential integration. It brings also a better understanding of the stability and the reliably of these interconnects at temperatures above the classical BEOL one.
[1] P. Batude et al., VLSI 2015
[2] P. Batude et al., IEDM 2017
[3] C. Fenouillet-Beranger et al., IEDM 2014
[4] A. Grill, Annual Rev. Mater. Res., 39, 49 (2009)
[5] N. Planes et al., VLSI 2012

Metal-organic frameworks (MOFs) are an intriguing class of porous crystalline materials with record internal surface areas. There is tremendous potential for integrating MOFs into microelectronics, e.g. as active sensor coatings or low-k dielectrics.[1] A key enabling step in leveraging the properties of MOFs in microelectronics will be the development of robust thin film deposition methods. Thus far, typical procedures for the deposition of MOF thin films are incompatible with microelectronic fabrication because of corrosion and contamination issues.
We recently demonstrated chemical vapor deposition (CVD) of MOF thin films.[2] The MOF-CVD process allows conformal growth of thin films and extends MOF processing to one of the most commonly used techniques in thin film research and manufacturing. Two important challenges were tackled to realize this process: vapor phase supply of precursors and crystallization at the vapor-solid interphase. To our knowledge, this is the first vapor phase process for conformal film deposition of a crystalline and microporous network material. Future directions and potential applications of MOF-CVD coatings will be discussed, with special attention to their integration as low-k dielectrics.

References: [1] Stassen, I., Burtch, N., Talin, A. A., Falcaro, P., Allendorf, M. D. & Ameloot, R. (2017) Chem. Soc. Rev. 46, 3185–3241; [2] Stassen, I., Styles, M., Grenci, G., Van Gorp, H., Vanderlinden, W., De Feyter, S., Falcaro, P., De Vos, D. E., Vereecken, P. & Ameloot, R. (2016). Nat. Mater., 15, 304–310.

Transition metal trichalcogenides (TMTs) like that of tantalum triselenide (TaSe₃) are of interest due to there, low dimensional, quasi 1D structure and high conductivity. These materials have generally been synthesized using a chemical vapor transport (CVT) process at high temperatures followed by mechanical and/or chemical exfoliation and transferred onto a substrate. Here we present a novel breakthrough in synthesizing these materials through chemical vapor deposition (CVD). The TaSe₃ nanorods are synthesized directly onto the desired substrate using relatively low temperatures and under one-hour process times. The parameters are optimized to yield the nanorods which are characterized through Raman spectroscopy and device fabrication is conducted to observe the electronic transport characteristics of the material. Using (AFM) the cross section of a multitude of wires were measured to study the effects down scaling would have on the resistivity of the material. The results show that TaSe₃ growth can be successfully optimized through CVD and provides further understanding of the material and its implications for TMTs possible use in future nanometer scale interconnect applications.

As the aggressive scaling in the complementary metal-oxide semiconductor (CMOS) technology continues, there is a growing need to examine new materials that can be used for nm-scale local interconnects. At present, the current density sustained by Cu interconnects in CMOS technology is between 2 MA/cm² to 3 MA/cm². We recently proposed that quasi-one-dimensional (1D) van der Waals materials, such as transition metal trichalcogenides (TMTs), have properties attractive for applications in nm-scale electronics [1-2]. In a way similar to transition metal dichalcogenides (TMDs), which exfoliate into 2D layers, TMTs exfoliate, or can be grown into, quasi-1D atomic thread bundles [1-4]. We found that metallic TaSe₃ nanowires have breakdown current density on the order of ~10 MA/cm² [1]. In principle, such quasi-1D materials could be ultimately downscaled by exfoliation, or grown directly, into nanowires with a cross-section of ~1 nm × 1 nm, which corresponds to an individual atomic thread, i.e. MX₃ chain. In this presentation we show that nanoribbons made of ZrTe₃, another member of the TMT family, reveal exceptionally high current density, on the order of ~100 MA/cm², at the peak of the stressing DC current [3]. We have used low-frequency noise (LFN) spectroscopy to investigate carrier recombination in such materials and verify reliability of the van der Waals interconnects [4]. It was found that LFN in ZrTe₃ reveals conventional 1/f behavior near room temperature (f is frequency). However, at low temperature it is dominated by the Lorentzian bulges of the generation–recombination noise at low temperatures, which is unusual for metals. Unexpectedly, the corner frequency of the observed Lorentzian peaks revealed a strong sensitivity to the applied bias. This dependence on electric field was explained by the Frenkel–Poole effect in the scenario where the voltage drop happens predominantly on the defects, which block the quasi-1D conduction channels. We also have investigated electrical characteristics of a range of other quasi-1D van der Waals materials with the goal of identifying the best material for the interconnects. The local temperature measurements have been conducted using micro-Raman spectroscopy in order determine the breakdown mechanism in the quasi-1D van der Waals metallic interconnects. The obtained results are important for developing the ultimately downscaled local interconnects for future electronic technologies.

This work was supported, in part, by the Semiconductor Research Corporation (SRC) contract 2018-NM-2796: One-Dimensional Single-Crystal van-der-Waals Metals: Ultimately-Downscaled Interconnects with Exceptional Current-Carrying Capacity and Reliability, and by the National Science Foundation (NSF) through the Emerging Frontiers of Research Initiative (EFRI) 2-DARE project: Novel Switching Phenomena in Atomic Heterostructures for Multifunctional Applications (NSF EFRI-1433395).

[1] M. A. Stolyarov, G. Liu, M. A. Bloodgood, E. Aytan, C. Jiang, R. Samnakay, T. T. Salguero, D. L. Nika, S. L. Rumyantsev, M. S. Shur, K. N. Bozhilov, and A. A. Balandin, Breakdown current density in h-BN-capped quasi-1D TaSe₃ metallic nanowires: prospects of interconnect applications, Nanoscale, 8, 34, 15774 (2016).
[2] G. Liu, S. Rumyantsev, M. A. Bloodgood, T. T. Salguero, M. Shur, and A. A. Balandin, Low-frequency electronic noise in quasi-1D TaSe₃ van der Waals nanowires, Nano Letters, 17, 377 (2017).
[3] A. Geremew, M. A. Bloodgood, E. Aytan, B. W. K. Woo, S. R. Corber, G. Liu, K. Bozhilov, T. T. Salguero, S. Rumyantsev, M. P. Rao, A. A. Balandin, Current carrying capacity of quasi-1D ZrTe₃ van der Waals nanoribbons, IEEE Electron Device Letters, 39, 735 (2018).
[4] Adane K. Geremew, Sergey Rumyantsev, Matthew A. Bloodgood, Tina T. Salguero and Alexander A. Balandin, Unique features of the generation–recombination noise in quasi-1D van der Waals nanoribbons, Nanoscale; DOI: 10.1039/c8nr06984k (2018).

Self-healable electrodes can improve the durability and the reliability of electronic devices. In recent years, the need of self-healing ability in materials grows in the field of deformable electronics such as foldable or stretchable devices. However, until now, most of developed self-healable electrodes require additional healing agents or several stimuli such as heat, magnetic field, or UV irradiation to restore the electrical conductivity. Also, some of them takes long time to self-heal after being damaged. And, the healing ability of the electrical conductivity is not maintained through only the low number of breaking and healing cycles. Herein, self-healable electrodes based on silver nanoparticles which make up the disadvantages of other self-healable electrodes have been developed. Because the silver makes the main conductive path of the electrodes, the electrical conductivity of the self-healable electrodes is 2×10⁶ S/m, which is similar level to other metals. The self-healing phenomenon of electrodes is taken by high-speed camera. If the electrodes are cracked by external forces, they reconnect in 10 milliseconds without any external stimuli or healing agents. The electrodes recover 90% of the initial conductivity during cyclic test of 50 times. Unlike the other metal electrodes, these silver-based electrodes have 60% stretchability. Furthermore, these self-healable electrodes are patterned by photolithography, which can be applied to the conventional fabrication process of electronic circuits. The electrodes are applied to foldable organic light-emitting diodes, maintaining the luminescence after folding the devices.

Metal-insulator-Metal (MIM) capacitors have been widely used in various applications including dynamic random access memory (DRAM) technology, analog/logic and radio frequency as well as decoupling capacitance in high power microprocessors.^1-3 With continuous device scaling, on-chip decoupling capacitance is necessary for managing power noise to optimize circuit timing. Integration of MIMCAP in back-end-of-line (BEOL) has been attractive for managing this power noise, particularly for high frequencies due to proximity to transistors.
The integration of gate stack high-k films for the MIMCAP applications has been extensively explored to meet the capacitance targets. However, the range of characteristics for tuning BEOL MIM devices is not well-understood. Additionally, the characteristics of high-k films that are well characterized and understood for gate stack applications may not be applicable due to the low thermal budget requirements in BEOL MIM applications. In this work, we systematically characterized the interface between the high-k and top and bottom metal electrode to reduce leakage. To understand the leakage pathway, density functional theory (DFT) calculations were performed for Al₂O₃-HfO₂ system that explained the role of Al% in the matrix. We further optimized the Al% in HfO₂ dielectric stacks that resulted in 15% capacitance improvement without increased leakage and meeting reliability targets (TDDB, β, EOL). We also developed a low thermal budget annealing process that is compatible with under-layer Cu films for further capacitance improvements. In summary, tuning dielectric composition and deposition, in combination with appropriate thermal treatment, offers a path for high capacitance density MIM for decoupling capacitance.
References:
D. Zhuo et al., Reliability of Al₂O3-doped ZrO₂ high-k dielectrics in three-dimensional stacked metal-insulator-metal capacitors, Journal of Applied Physics, 108, 124104, 2010.
R. Brain et al., A 22nm high performance embedded DRAM SoC technology featuring Tri-gate transistors and MIMCAP COB, VLSI Technology, 2013.
K. Stein et al., High reliability metal insulator capacitors for silicon germanium analog applications, IEEE BCTM, 1997.

Metal-organic frameworks (MOFs) are an intriguing class of porous crystalline materials with record internal surface areas. There is tremendous potential for integrating MOFs into microelectronics, e.g. as active sensor coatings or low-k dielectrics.[1] A key enabling step in leveraging the properties of MOFs in microelectronics will be the development of robust thin film deposition methods. Thus far, typical procedures for the deposition of MOF thin films are incompatible with microelectronic fabrication because of corrosion and contamination issues.
We recently demonstrated chemical vapor deposition (CVD) of MOF thin films.[2] The MOF-CVD process allows conformal growth of thin films and extends MOF processing to one of the most commonly used techniques in thin film research and manufacturing. Two important challenges were tackled to realize this process: vapor phase supply of precursors and crystallization at the vapor-solid interphase. To our knowledge, this is the first vapor phase process for conformal film deposition of a crystalline and microporous network material. Future directions and potential applications of MOF-CVD coatings will be discussed, with special attention to their integration as low-k dielectrics.

References: [1] Stassen, I., Burtch, N., Talin, A. A., Falcaro, P., Allendorf, M. D. & Ameloot, R. (2017) Chem. Soc. Rev. 46, 3185–3241; [2] Stassen, I., Styles, M., Grenci, G., Van Gorp, H., Vanderlinden, W., De Feyter, S., Falcaro, P., De Vos, D. E., Vereecken, P. & Ameloot, R. (2016). Nat. Mater., 15, 304–310.

As the area shrinkage of semiconductor devices with high memory density, the high aspect ratio pattern is needed such as 3D NAND flash. To create a vertical pattern with a mask, mask is needed to be thicker for etching it longer. However, a thick mask distorts the shape of the pattern with a shadowing effect. Therefore, it is necessary to have a hard mask that can be made thinner. The vertical structure is fabricated by plasma based dry etching process with hard masks, which have superior etch resistance. Therefore, it is necessary to study the properties of hard mask materials for deeply patterned devices having higher memory density. The hard mask should have more etch resistant to plasma reactive gas than conventional organic soft mask for deeper pattering. It must also be easily removed after the etching process. These conditions are well satisfied with amorphous carbon, which is the most promising material for hard mask.
Amorphous carbon is known that the kind of bonding is changed according to the process conditions. Carbon has various atomic bonds like sp³ of diamond and sp² of graphite. The difference in carbon bond between the two materials greatly affects the properties such as mechanical and electrical properties. In this study, we have studied how the etch characteristics change with the change of bonding nature of amorphous.
Amorphous Carbon (a-C) was deposited on SiO₂/Si by DC magnetron sputter system using graphite solid target for higher purity and lower roughness than CVD process. The deposition pressure and acceleration voltage was controlled to modify the bonding structure of the carbon film, and the bonding was dramatically modified depending on the conditions of pressure, which was an important parameter for the etching characteristics. In case of the low-pressure deposition process, sp³-bonding rich amorphous carbon film was fabricated and had an excellent etching resistance. On the other hand, at high-pressure deposition process, sp²-bonding rich amorphous carbon film was fabricated and had a poor etching resistance. In order to understand the degradation process of the carbon hardmask induced by the penetration of fluorine ion into the film during dry etching, the phenomenon of fluorine penetration into the film with respect to carbon bonds was proved by density function theory (DFT) calculation. Through the DFT calculation, it is unveiled that the energy barrier for the migration of the fluorine atom through sp3 bonding path is much larger than that of the fluorine atom through sp2 bonding path in the amorphous carbon.
The doping, which is very well-known process to change the characteristics of the material, is also modified the bonding structure of the amorphous carbon film. We fabricate the amorphous carbon film with nitrogen, boron, silicon, and tungsten doping. The effect of the doping elements on the bonding structure of the amorphous carbon film will be discussed.

For damascene metallization, the semiconductor industry uses barrier / liner / seed stacks, such as TaN / Ru / Cu, in which Ru ensures a good adhesion of the Cu seed layer on the TaN barrier, as well as enables ‘reflow’ of the Cu seed to facilitate the Cu filling process by electrochemical deposition (ECD). Next, chemo-mechanical planarization (CMP) is done to achieve metallization which is embedded in a dielectric matrix. Presently, Cu constitutes the largest material fraction as conductor in damascene trenches and is deposited by ECD. In future interconnect technology nodes, Ru is considered a strong candidate to replace Cu, as it shows less electromigration.

Controlled removal of metals is a critical step at many points in a processing flow, such as for bevel cleaning, wafer backside cleaning, and fully aligned vias. For the latter example, a metal recess etch is needed. CMP yields planarized substrates, however, it cannot remove material in a controlled way below the wafer surface. To develop a wet-chemical etchant, oxidizing agents used in CMP slurries, such as bromate (BrO₃^-), periodate (IO₄^-), cerium (IV) (Ce⁴⁺), hypochlorite (OCl^-), or hydrogen peroxide (H₂O₂) can be considered.

In our contribution, we discuss the (electro)chemistry involved in Ru etching and discuss results for selected oxidizing agents. The etch process is characterized in terms of surface roughness, cleanliness, and etch rate. Solution chemistry as well as stability were characterized using UV-vis spectroscopy. Compatibility with low-k dielectric material was investigated and characterized using Fourier transform infrared spectroscopy.

Platinum has been used as an electrode material in transistors, ferroelectric memories, and recently in magnetic tunnel junction (MTJ) devices. Pt is known as a hard-to-dry-etch material due to its nobleness and low volatility of its halides. In past Pt plasma etching, physical sputtering functioned as a dominant etching principle. MTJs have a rather complex thin film stack structure consisting of various metallic layers such as CoFeB, NiFe, MgO, and Co, where MgO is sandwiched with ferromagnetic metals. These ferromagnetic elements (Co, Fe, and Ni) also form low-vapor-pressure chlorides; thus, they should be sputteretched, although sputter etching leads to a deadly sputter residue at the sidewall of a ferromagnetic tunnel junction. Recently atomic layer etching has been gaining a strong attention, whereas the use of plasma chemistry does not abate its potential risks. The application of wet chemistry to the residue removal is more problematic owing to its limitation to nanostructures, electrochemical attacks, and etching selectivity.
In the present work, Pt thin films were etched in supercritical CO2 fluids. Hexfluoroacetlyacetone (Hhfac), a fluorinated compound, was added to a supercritical CO2 fluid together with O2 at elevated temperatures. Experimental set-up, various process parameter dependences, and Pt oxidation status will be presented.

Copper fine lines have been successfully etched with a plasma-based, room-temperature process using the conventional parallel-plate reactor under the RIE condition. This process has been used in preparing IC chips and large area TFT LCDs. Process parameters influencing the copper consumption rate and the sidewall attack on flat and stepped surfaces were studied. The lifetime on the etched lines were also investigated. However, there were few studies on preparing sub micrometer wide lines using this method. The influence of the capping layer on the lifetime was rarely reported.

In this paper, authors will discuss the new result on process and electromigration reliability of the etched copper fine lines. For the etch process, the copper surface condition showed critical influence on the copper-plasma reaction, which determined the reaction rate and etch uniformity. A proper surface treatment step proved effective in achieving the good uniformity. Sub half micrometer copper patterns have been demonstrated using the process. For the copper line electromigration study, the capping layer and the line geometry are important to the lifetime and the breakdown phenomena. The failure mechanism will be explained with the grain structure and the edge roughness.

Authors acknowledge the financial support of this work through NSF CMMI project 1633580.

As BEOL interconnect dimensions continue to shrink, future generation devices will require precise atomic level thickness control for BEOL seed layers. Here, we present the latest developments in interconnect metallization using a new wet process called electrochemical atomic layer deposition (eALD). In this talk, we will discuss innovative modifications to eALD that make this process scalable to full wafers and amenable to the deposition of a variety of metals and alloys. We will review recent success in achieving void-free metallization of sub-20nm interconnect features. We will also explore integration approaches including electroless ALD processing that would enable future interconnect technology nodes.

Selective deposition is likely to become an important process in pattern fabrication for next-generation interconnects. Bottom-up growth strategies such as selective deposition provide advantages in reduced process complexity and improved pattern fidelity. In this presentation, I will describe different approaches to achieve area selective atomic layer deposition (ALD) for materials systems important to back end of line processing. ALD is a good choice for selective deposition because its chemical specificity provides a means to achieve selectivity on a spatially patterned substrate. One successful approach uses inhibitory layers such as self-assembled monolayers (SAMs) to alter the native surface reactivity, allowing ALD selectivity to be achieved. I will show that this process provides good selectivity for thin deposited films, and demonstrate selective deposition on different materials, including low k dielectrics and metals such as Cu, Co, W and Ru. Because area selective ALD processes often break down after more than a few nanometers of material is deposited, strategies to overcome the undesired ALD nucleation on the inhibitory layer and achieve significantly higher selectivity in area selective ALD are also important. Two such strategies that improve the final selectivity will be described, including SAM repair between ALD cycles and a self-correcting process in which selective deposition is combined with selective etching. ALD of low k dielectric thin films as well as selective ALD on low k dielectric/Cu patterns will also be discussed.

Contact metallization in large-scale semiconductor devices such as logic, memory, MEMS, and SoC using 2.5D and 3D interposers requires a high quality and conductivity metal barrier/seed layer for subsequent metal electroplating. Ruthenium metal has a bulk resistivity of 7.1 μΩ cm, a work function of 4.7 eV, and a low solid solubility with strong adhesion to Cu, making Ru an attractive contact metal barrier metal or seed layer for Cu electroplating. There have been numerous reports of Ru ALD using a variety of precursors. However, technical challenges remain including the need for high growth temperature, very long nucleation delay, and the use of plasma that limits Ru conformality in high aspect ratio features. Currently, there is a strong desire and demand for 3D-devices where high quality, uniform, and conformal metal growth on high aspect ratio structures for ultra largescale integration (ULSI) process flow including for 2.5D and 3D interposer substrates creation.

Here we have developed a low temperature (200^oC) Ru atomic layer deposition process using Ru(DMBD)(CO)₃ and O₂ precursors. To enhance the Ru nucleation and growth, especially at low temperature, we performed low temperature Pt ALD using Pt(MeCp)Me₃ and O₂ to deposit a sub-monolayer Pt seed layer that greatly accelerates the subsequent Ru nucleation. High quality Ru films were deposited on a variety of substrates including Si(100), fused silica, Al₂O₃ and TiN. The ALD Ru films were uniform across the 18” deposition zone of our tubular ALD reactor. Thin Ru films were characterized by XPS, SEM, TEM, four point IV measurements, XRD and XRF. We have also performed Cu electroplating on the ALD Ru layers and found that the Ru films deposited using the Pt seed layer exhibited excellent Cu electroplating. Here we will present details of the Ru ALD and Cu electroplating.

It is desired to have selective metal deposition for bottom-up fill for both middle-of-line (MOL or MEOL) and back end-of-line (BEOL) processing. This would induce formation and growth of larger grains, which are expected to decrease via and interconnect resistance by reducing grain boundaries and decreasing surface roughness. In addition, bottom-up growth may remove the need for nucleation layers on low-k dielectrics (SiCOH) since the nucleation will occur only on the bottom surface. The key metals for bottom-up growth include cobalt and ruthenium; cobalt is particularly important since it used as both a capping layer on Cu to protect it from oxidation, and in sub 10 nm vias, where Co is consider to be a better conductor than Cu due to Co having a smaller electron mean free path and problems with Cu electroplating in sub 10 nm vias.

ALD cobalt metal was explored using a metal-organic cobalt precursor, Bis(1,4-di-tert-butyl-1,3-diazadienyl) cobalt (Co(dad)₂), and either a co-reactant of formic acid (HCOOH) or tert-butylamine (TBA) at 180C on Cu, Pt, and SiO₂ substrates. The deposited Co films were studied using in-situ x-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). Cross-sectional scanning electron microscopy (SEM) and 4-point probe measurements were performed to check film thickness and resistivity, respectively.

It was found that there is nearly infinite selective deposition of Co on a conductor and not an SiO₂ for 180C ALD with Co(dad)₂ and HCOOH. XPS was performed after 100 ALD cycles followed by an additional 100 cycles on UHV annealed Pt vs SiO₂. On Pt, a thick (>10 nm) Co⁺⁰ film deposits while virtually no deposition results on SiO₂. AFM images show no change on SiO₂ before and after Co ALD cycles consistent with no nuclei formation, while the Co on Pt surface roughness remains below 1.8 nm. To verify self-limiting precursor exposures consistent with ALD, a saturation study was performed and monitored with XPS; this study highlighted the effect of individual additional half cycle amounts that result in self-limiting Co(dad)₂ and HCOOH exposures consistent with ALD. Additionally, this study revealed a novel mechanism about the reaction. Previously it was thought the HCOOH dissociatively chemisorbed to produce atomic H which removed the ligands from Co(dad)₂. Instead, XPS showed that HCOOH did not remove the ligands but instead induced a ligand-exchange process. The Co 2p peak indicated the HCOOH leaves a higher binding energy component on the surface consistent with a formate on the surface that is then removed upon exposure to Co(dad)₂.

Deposition with HCOOH was attempted on Cu substrates; however, the substrate Cu signal never decreased to zero consistent with etching by HCOOH so an alkyl amine co-reactant (TBA) was also studied. For Co(dad)₂ + TBA ALD at 180C, reduced Co metal films were deposited on Cu and Pt substrates with hyper-selectivity against SiO₂. Films as thick as 30 nm were grown on the conductors without etching the substrates. On SiO₂, only 4% CoO_x was deposited after an initial 50 ALD cycles. After an additional 250 ALD cycles, there was still only 4% CoO_x consistent with saturation and hyper-selectivity. AFM imaging from ALD with TBA confirmed low surface roughness ALD on Pt and Cu, while only small (<5 nm) CoO_x particles were present on SiO₂.

Hyper-selective Co metal deposition was produced from Co(dad)₂ and both co-reactants (HCOOH and TBA). Utilizing HCOOH, no deposition was seen on SiO₂ consistent with infinite deposition, however HCOOH was observed to etch Cu. By switching to TBA, no Cu etching was observed and similar metallic Co films were deposited with only 4% CoO_x on SiO₂ independent of the number of Co ALD cycles. The self-limiting deposition on SiO₂ is a novel mechanism of selectivity through the formation of an oxidic particulate, which results in hyper-selectivity.

As have been widely known, The NAND Flash business is transitioning from the conventional two dimensional, planar structure to three dimensional (3D), vertical structures to meet storage density requirements. Also, in 3D V-NAND Flash memory devices, and device scaling has being achieved by vertical staking of thin film transistors (TFTs) in multiple layer configurations, without heavily relying on advances in lithography. 3D V-NAND Flash memory device fabrication involves many processes that have never before been used in mass production of semiconductor devices, and are extraordinarily challenging. Precise control of every process step is required.
Thickness reduction of 3D Channel layers is a very challenging issue due to the scale-down, vertical etch, and gapfill process limitation of devices. For overcoming these issues, Alternate deposition of ultra-thin films and selective etching are required for successful fabrication of vertically stacked layers used in 3D V-NAND Flash memory devices. In particular, after it has formed a vertical gate channel by the multiple Oxide-Nitride (ON) -stack layers, and the gapfill process for gate isolation is switching from the existing Chemical Vapor Deposition (CVD) Type deposition process to the new Atomic Layer Deposition (ALD) type.
In general, the ALD process has known as the most stable and effective process in the gapfill process up to now by controlling the atomic-layer depositions by the precursor and the source loading time. However, in the gapfill process of 3D NAND flash device with an over 50th floors, as the number of stacked layers increases, the area to gapfill increases proportionally. And ALD process has encountered other new huddles for stable processes. Those are the characteristic deference of gapfill material in the top/bottom area, the void by overhang increasing in top area, and the re-sputtering phenomenon by ion bombardment in bottom area. Finally, these unstable ALD processes has triggered a metal bridge to cause an electronic leakage, and the degradation of device characteristic in Word Line (WL) block fail by channel threshold voltage(Vt) drop.
ALD process has evaluated in process parameter optimization to improve deposition confirmality by the controls in source gas compositions, source/co-gas partial pressure, RF power or RF process time, burst purse flow ratio, and chamber press. However, the evaluations to improve the step coverage of the ALD layer has been improved results by dropping the deposition ratio. In other words, to improve the confirmality of ALD Layer has been unavoidable to lose the production efficiency. The enforcement of source gas plasma density could make the material characteristics of ALD layer stable but the confirmality severe weaken.
In this study, we have evaluated the shape change possibility of as-deposited ALD layer and the strengthening the ALD layer by optimizing the post treatment. We have measured with high resolution cross-sectional transmission electron microscopy (HRXTEM) in real patterned wafer for the ALD layer confirmality transition trace by post treatment ALD Layer Thickness. And then, we have evaluated Wet Etch Rate (WER) in 300:1 HF diluted solution for the ALD layer densification trace. We have demonstrated the possibility of ALD Shape and material characteristics improvement. And we have evaluated the possibility of post treatment of high temperature ALD without loss in production efficiency as like Units Per Hour (UPH).

Integrating bottom-up area-selective building-blocks in microelectronics has a disruptive potential because of the unique capability of engineering new structures and architectures. Atomic layer deposition (ALD) is an enabling technology, yet understanding the surfaces and their modification is crucial to leverage area-selective ALD (AS-ALD) in this field. The understanding of general selectivity mechanisms and the compatibility of plasma surface modifications with existing materials and processes, both at research and production scale, will greatly facilitate AS-ALD integration in microelectronics. The use of self-assembled monolayers to inhibit the nucleation and growth of ALD films is an alternative route to bottom-up area-selective nanofabrication. In our work, we demonstrate i) a straightforward plasma surface modification process capable of inhibiting Ru ALD nucleation on an amorphous carbon surface while still allowing instantaneous nucleation and linear growth on Si-containing materials; ii) metal and/or dielectric surface passivation by molecular organic films which enable AS-ALD of dielectric materials on dielectric surfaces and/or AS-ALD of metallic films on metal surface. Demonstration of ASD on patterned critical dimensions below 50 nm and applications of ASD in back-end-of-line (BEOL) will be illustrated.

Freeform 3D single-crystal silicon micro- and nanostructures offer the opportunity to topologically define the refractive index of a medium. In turn, they enable realization of a myriad of optical devices such as classical elements, metasurface-based elements for silicon photonics, x-ray flat-lenses , optical resonators for biosensing, biomimetic lenses & imagers, and graded-index materials for photovoltaics and space applications. However, existing parallel bulk micromachining processes for silicon do not offer the ability to fabricate freeform structures with specific challenges when it comes to hierarchical micro and nanoscale 3D features, particularly during reactive etching, which in turn limits resolution, aspect-ratio and surface roughness. This paper demonstrates an electrochemical nanoimprinting process for single-crystal semiconductors for directly etching 3D features into silicon wafers. It is shown that stamps made of porous catalysts play a critical role in enabling diffusion of chemical species during imprinting which, in turn, allows for morphology control of imprinted silicon features with sub-20 nm resolution in 3D. This process delivers mirror surface finish (RMS < 5 nm), low-defect density, and large-area patterning (>1 cm²) in a single imprinting operation. Further, it outperforms the resolution and scalability of leading serial (e.g. FIB, electron beam) and parallel (e.g. gray-scale lithography) methods altogether by an order of magnitude, allowing for fast replication of patterns onto hard materials from a soft mold. This technique bypasses the need for dry etching and is potentially compatible with roll-to-roll platforms, amorphous and poly silicon and III-V semiconductors. In turn, it may pave the way for the manufacturing of complex objects for infrared optics.