Meetings & Events

 

2007 MRS Spring Meeting Logo2007 MRS Spring Meeting & Exhibit


April 9-13, 2007
| San Francisco
Meeting Chairs: Timothy J. Bunning, Harold Y. Hwang, Debra Kaiser, Jennifer A. Lewis

Symposium G : Extending Moore’s Law with Advanced Channel Materials

2007-04-10   Show All Abstracts

Symposium Organizers

Srini Chakravarthi Texas Instruments
Reza Arghavani Applied Materials
Gerhard Klimeck Purdue University
G1: Challenges / Directions of Current CMOS
Session Chairs
Reza Arghavani
Srini Chakravarthi
Tuesday AM, April 10, 2007
Room 3005 (Moscone West)

9:00 AM - **G1.1
Future Direction of Strained Si/channel MOSFETs for Advanced 90 to 22nm Logic Technologies

Scott Thompson 1
1 Electrical & Computer Engineering, University of Florida, Gainesville, Florida, United States

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9:30 AM - **G1.2
Mobility Engineering in Si CMOS.

Serge Biesemans 1 , Peter Verheyen 1 , Philippe Absil 1 , Thomas Hoffmann 1
1 CMOSDR, IMEC, Leuven Belgium

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10:00 AM - G1.3
Strain-Transfer Structure Beneath the Transistor Channel for Increasing the Strain Effects of Lattice-Mismatched Source and Drain Stressors.

Yee-Chia Yeo 1 , Kah-Wee Ang 1 , Jianqiang Lin 1 , Chee Lam 1
1 Electrical and Computer Engineering, National University of Singapore, Singapore Singapore

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10:15 AM - G1.4
A Theoretical Investigation of Selected Silicides and Germanides.

Alex Demkov 1 , Manish Niranjan 1 , Leonard Kleinman 1
1 Physics, The University of Texas, Austin, Texas, United States

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10:30 AM - G1.5
Design Guidelines for High Mobility Channel Bulk n-MOSFETs

Lee Smith 1 , Makoto Fujiwara 2 3 , Krishna Saraswat 2 , Yoshio Nishi 2 , Dipu Pramanik 1
1 , Synopsys, Inc., Mountain View, California, United States, 2 , Stanford University, Stanford, California, United States, 3 , Toshiba Corporation, Yokohama, Kanagawa, Japan

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10:45 AM - G1.6
Simplified Surface Preparation for GaAs Passivation Using Atomic-layer-deposited High-k dielectrics.

Peide (Peter) Ye 1 , Yi Xuan 1 , Han-Chung Lin 1
1 School of ECE, Purdue University, West Lafayette, Indiana, United States

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11:00 AM -
BREAK

G2: Prospective Materials for CMOS Channels
Session Chairs
Reza Arghavani
Srini Chakravarthi
Tuesday AM, April 10, 2007
Room 3005 (Moscone West)

11:30 AM - **G2.1
New Channel Materials and the Ultimate MOSFET

Mark Lundstrom 1
1 School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, United States

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12:00 PM - G2.2
Metal-Oxide-Semiconductor Field Effect Transistors with InGaAs and GaAs/InGaAs Channels and High-k Gate Dielectric.

Sergei Koveshnikov 1 2 , Serge Oktyabrsky 2 , Vadim Tokranov 2 , Michael Yakimov 2 , Richard Moore 2 , Feng Zhu 3 , Wilman Tsai 1 , Jack Lee 3
1 , Intel Corporation, Santa Clara, California, United States, 2 College of Nanoscale Science and Engineering, University at Albany-SUNY, Albany, New York, United States, 3 Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas, United States

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12:15 PM - G2.3
Electronic Structure of Si/InAs Composite Channels.

Marta Prada 1 2 , Neerav Kharche 1 , Gerhard Klimeck 1
1 School of Electrical and Computer Engineering, Network for Computational Nanotechnology Purdue University, W Lafayette, Indiana, United States, 2 Physics, University of Wisconsin-Madison, Madison, Wisconsin, United States

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12:30 PM - **G2.4
Building a CMOS technology with Non-Traditional Materials to Satisfy Digital Requirements.

Douglas Barlage 1 , Mark Johnson 2 , David Braddock 3 , Yawei Jin 1 , Lei Ma 1
1 Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 Material Science and Engineering, North Carolina State University, Raleigh, North Carolina, United States, 3 , OSEMI , Cannon Falls, Minnesota, United States

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G3: Advanced Channel Materials I: (110) Si, Ge
Session Chairs
Srini Chakravarthi
Gerhard Klimeck
Tuesday PM, April 10, 2007
Room 3005 (Moscone West)

2:30 PM - **G3.1
Future Channel Materials and Processes for High Performance CMOS

Devendra Sadana 1 , S. Bedell 1 , J. Souza 1 , A. Reznicek 1 , S. Koester 1 , Yanning Sun 1 , E. Kiewra 1 , J. Ott 1 , K. Fogel 1 , D. Webb 2 , J. Fompeyrine 2 , J. Locquet 2 , M. Sousa 2 , R. Germann 2
1 Advanced Substrate Research, IBM, Yorktown Heights, New York, United States, 2 IBM Zurich Research Laboratory, Säumerstrasse 4 / Postfach , Rüschlikon, CH-8803, Switzerland

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3:00 PM - G3.2
Bonded Layer Thickness Optimization for DSB-HOT.

Angelo Pinto 1 , Sachin Joshi 2 , Y. Huang 3 , Rick Wise 1 , Rinn Cleavelin 1 , Mike Seacrist 4 , Mike Ries 4 , Manfred Ramin 2 , Melissa Freeman 5 , Billy Nguyen 5 , Kenneth Matthews 5 , Bruce Wilks 5 , Mike Ma 3 , C. Lin 3 , Sanjay Banerjee 2
1 External Research, SiTD, Texas Instruments Inc., Austin, Texas, United States, 2 Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas, United States, 3 , United Microelectronics Corporation Inc., Hsinchu Taiwan, 4 , MEMC Electronic Materials Inc., St. Peters, Missouri, United States, 5 , Advanced Technology Development Facility Inc., Austin, Texas, United States

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3:15 PM - G3.3
Understanding Facet Formation During Solid Phase Epitaxy of Patterned Amorphized Regions in (001) and (011) Silicon: Observations and Model.

Katherine Saenger 1 , Haizhou Yin 2 , Keith Fogel 1 , John Ott 1 , Joel de Souza 1 , Devendra Sadana 1
1 IBM Semiconductor Research and Development Center, IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 2 IBM Semiconductor Research and Development Center, IBM Microelectronics, Hopewell Junction, New York, United States

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3:30 PM - G3.4
Sub 50nm Strained n-FETs formed on Silicon-Germanium-on-Insulator Substrates and the Integration of Silicon Source/Drain Stressors

Huiqi Grace Wang 1 2 , Eng-Huat Toh 1 2 , Keat Mun Hoe 2 , S. Tripathy 3 , Subramanian Balakumar 2 , Guo-Qiang Lo 2 , Ganesh Samudra 1 , Yee-Chia Yeo 1
1 , National University of Singapore, Singapore Singapore, 2 , Institutue of Microelectronics, Singapore Singapore, 3 , Institutue of Materials Research and Engineering, Singapore Singapore

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3:45 PM - G3.5
Characterization of a Multidirectional Condensation Ge Process for Co-integrated SOI/GeOI Substrate Fabrication.

Benjamin Vincent 1 , Jean-Francois Damlencourt 1 , Denis Rouchon 1 , Pierrette Rivallin 1 , Laurent Clavelier 1
1 , CEA-DRT-LETI-CEA/GRE, Grenoble France

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4:00 PM -
BREAK

G4: Advanced Channel Materials II
Session Chairs
Reza Arghavani
Gerhard Klimeck
Tuesday PM, April 10, 2007
Room 3005 (Moscone West)

4:30 PM - **G4.1
Strained Si-Ge Heterostructure Channel Materials for Bulk and Ultra-thin Body MOSFETs.

Judy Hoyt 1 , Cait Chleirigh 1 , Leonardo Gomez 1 , Ingvar Aberg 1 , Guangrui Xia 1
1 Microsystems Technology Laboratories, MIT, Cambridge, Massachusetts, United States

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5:00 PM - **G4.2
High-κ Material Selection for Realization of High Effective Hole Mobility Ge p-MOSFETs.

Yohiski Kamata 1 , Tsunehiro Ino 1 , Masato Koyama 1 , Akira Nishiyama 1
1 , TOSHIBA CORPORATION, Yokohama Japan

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5:30 PM - G4.3
Interfacial Composition and Electrical Properties of Hf Oxide Dielectric Films Grown on InxGa1-xAs.

Lyudmila Goncharova 1 , Ozgur Celik 1 , Eric Garfunkel 1 , Torgny Gustafsson 1 , Niti Goel 2 , Safak Sayan 2 , Wilman Tsai 2
1 Physics, and Chemistry and Chemical Biology, Rutgers University, Piscataway, New Jersey, United States, 2 , Intel Corp., Santa Clara, California, United States

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5:45 PM - G4.4
Enhancement-Mode (with Channel Inversion) and Depletion-Mode MOSFETs with Ga2O3(Gd2O3)/Si3N4 Dual-Layer Gate Dielectrics on In0.2Ga0.8As

Jun-Fei Zheng 1 , Wilman Tsai 1 , Tsung-Da Lin 2 , Chih-Ping Chen 2 , Minghwei Hong 2 , Raynien Kwo 3 , Sharon Cui 4 , Tso-Ping Ma 4
1 Strategic Technology/External Program, Intel Corporation, Santa Clara, California, United States, 2 Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 3 Department of Physics, National Tsing Hua University, Hsinchu Taiwan, 4 Department of Electrical Engineering, Yale University, New Haven, Connecticut, United States

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G5: Poster Session
Session Chairs
Reza Arghavani
Srini Chakravarthi
Gerhard Klimeck
Tuesday PM, April 10, 2007
Salon Level (Marriott)

9:00 PM - G5.1
Growth and Material Characteristics of Ga2O3(Gd2O3)/Si3N4 Dual-Layer Gate Dielectric for Inversion-Channel and Depletion Mode GaAs-based MOSFET.

T. Lin 1 , C. Chen 1 , M. Hong 1 , J. Kwo 2 , J. Zheng 3 , W. Tsai 3 , S. Cui 4 , T. Ma 4
1 Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan, 2 Department of Physics, National Tsing Hua University, Hsinchu Taiwan, 3 , Intel Corporation, Santa Clara, California, United States, 4 Department of Electrical Engineering, Yale University, New Haven, Connecticut, United States

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9:00 PM - G5.10
Strained Si/Si1-xGex/Relaxed Si1-yGey (x>y) Structures: Identifying Roughness Due to Compressed SiGe and Its Impact on High Mobility MOSFETs.

Enrique Escobedo-Cousin 1 , Sarah Olsen 1 , Anthony O'Neill 1 , Olayiwola Alatise 1 , Rouzet Agaiby 1 , Peter Dobrosz 1 , Glyn Braithwaite 2 , Alan Cuthbertson 2 , Tim Grasby 3 , Evan Parker 3
1 , Newcastle University, Newcastle upon Tyne United Kingdom, 2 , Atmel North Tyneside, Newcastle upon Tyne United Kingdom, 3 , University of Warwick, Coventry United Kingdom

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9:00 PM - G5.11
Embedded SiGe Source/Drains and Buried SiGe channels: A Successful Combination to Increase Drive Current and to Adjust Threshold Voltage in High k pMOS Devices.

Roger Loo 1 , Haruyuki Sorada 2 , Akira Inoue 2 , Masaaki Niwa 2 , Aude Rothschild 1 , Peter Verheyen 1 , Matty Caymax 1
1 , IMEC, Leuven Belgium, 2 assigned to IMEC, Matsushita Electric Industrial Co., Osaka Japan

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9:00 PM - G5.12
Electrical and Physical Characterization of ALD-grown HfO2 Gate Dielectrics on GaAs (100) Substates with Sulfur Passivation.

Eunji Kim 1 , Joseph Chen 1 , Donghun Choi 2 , Niti Goel 3 , Chi On Chui 3 , Wilman Tsai 3 , James Harris 2 , Yoshio Nishi 2 , Krishna Saraswat 2 , Paul McIntyre 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Stanford University, Stanford, California, United States, 3 , Intel Corporation, Santa Clara, California, United States

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9:00 PM - G5.15
Ni-germanide Contacts on Ge: Phase Formation and Electrical Characterization.

Karl Opsomer 1 2 , Eddy Simoen 1 , Christophe Detavernier 3 , Anne Lauwers 1 , Christian Lavoie 4 , Roland Vanmeirhaeghe 3 , Karen Maex 1 2
1 , IMEC, Leuven Belgium, 2 Electrical Engineering Department (ESAT), Katholieke Universiteit Leuven, Leuven Belgium, 3 Solid-State Sciences Department, Universiteit Gent, Gent Belgium, 4 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States

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9:00 PM - G5.16
Gate-all-around (GAA) Fully Depleted (FD) Cantilever Channel MOSFET with high-κ Dielectric and Metal Gate.

Sagnik Dey 1 , Sachin Joshi 2 , Se-Hoon Lee 3 , Prashant Majhi 4 , Sanjay Banerjee 5
1 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States, 2 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States, 3 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States, 4 Intel Assignee, Sematech, Austin, Texas, United States, 5 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States

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9:00 PM - G5.17
Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate for P-FinFETs

Rinus Lee 1 , Kian Ming Tan 1 , Tsung-Yang Liow 1 , Andy Lim 1 , Guo-Qiang Lo 2 , Ganesh Samudra 1 , Dong-Zhi Chi 3 , Yee-Chia Yeo 1
1 Silicon Nano Device Lab, Electrical and Computer Engineering, National University of Singapore, Singapore Singapore, 2 Institute of Microelectronics , Agency of Science Technology and Research , Singapore Singapore, 3 Institute of Materials Research and Engineering, Agency of Science Technology and Research , Singapore Singapore

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9:00 PM - G5.2
Formation and Characterization of Pt-Germanide Thin Films on Ge(001) for Schottky Source/Drain Application in Ge pMOSFETs

Haibiao Yao 1 , Dongzhi Chi 1 , Rui Li 2 1 , Sungjoo Lee 2
1 , Institute of materials research & engineering, Singapore Singapore, 2 SNDL, Dept. of ECE, National University of Singapore, Singapore Singapore

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9:00 PM - G5.21
Fermi Level Position at YbGe/Ge(001) Interface and Schottky Barrier Height Determined by X-ray Photoelectron Spectroscopy

Cheng-Cheh Tan 1 , Haibiao Yao 1 , Jian Wei Chai 1 , Jisheng Pan 1 , Dongzhi Chi 1
1 , Institute of Materials Research & Engineering, Singapore Singapore

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9:00 PM - G5.22
Implications to Work Function Modulation from Metal-Oxide Interface Configurations: Case of Study HfO2 and SiO2.

Blanka Magyari-Kope 1 , Yoshio Nishi 1 , Luigi Colombo 2 , Kyeongjae Cho 3
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 , Texas Instruments Inc., Dallas, Texas, United States, 3 Physics and Electrical Engineering, University of Texas, Dallas, Texas, United States

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9:00 PM - G5.3
Impact of Interfacial Layer Control in high-K Gate Dielectrics on GaAs for Advanced CMOS Devices.

Goutam Dalapati 1 , Yi Tong 1 , Wei Yip Loh 2 , Byung Jin Cho 1
1 Dept. of Electrical & Computer Engineering,, National University of Singapore, Singapore Singapore, 2 , Institute of Microelectronics,, Singapore Singapore

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9:00 PM - G5.4
Current-Voltage Measurements and Photoconductance Spectroscopy of Ultrathin InAs Grown on (211) Si.

Bin Wu 1 , Dane Wheeler 1 , Qin Zhang 1 , Patrick Fay 1 , Alan Seabaugh 1 , Changhyun Yi 2 , Inho Yoon 2 , April Brown 2 , T. Kuech 3
1 Electrical Engineering, University of Notre Dame, Notre Dame, Indiana, United States, 2 Electrical and Computer Engineering, Duke University, Durham, North Carolina, United States, 3 Chemical and Biological Engineering, University of Wisconsin-Madison, Madison, Wisconsin, United States

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9:00 PM - G5.6
High-performance Inversion-mode InGaAs/InP MOSFETs Using ALD Al2O3 as Gate Dielectrics.

Yi Xuan 1 , Han-Chung Lin 1 , Peide (Peter) Ye 1
1 School of ECE, Purdue University, West Lafayette, Indiana, United States

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9:00 PM - G5.7
Material and Electrical Characterization of Nickel Silicide-Carbon as Contact Metal to Silicon-Carbon Source and Drain Stressors

Rinus Lee 1 , Litao Yang 1 , Kah-Wee Ang 1 , Tsung-Yang Liow 1 , Kian-Ming Tan 1 , Andrew Wong 2 , Ganesh Samudra 1 , Dong-Zhi Chi 2 , Yee-Chia Yeo 1
1 Silicon Nano Device Lab, Electrical and Computer Engineering, National University of Singapore, Singapore Singapore, 2 Institute of Materials Research and Engineering, Agency of Science Technology and Research , Singapore Singapore

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9:00 PM - G5.8
A Combinatorial Materials Science Approach to the Ge/HfO2/metal Gate Stack.

Nabil Bassim 1 , Kao-Shuo Chang 1 , Sandrine Rivillon 2 , Min Dai 2 , Peter Schenck 1 , Martin Green 1 , Yves Chabal 2
1 , National Institute of Standards & Technology, Gaithersburg, Maryland, United States, 2 , Rutgers University, Piscataway, New Jersey, United States

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9:00 PM - G5.9
Nanoanalytical Electron Microscope Investigations of Etching Processes for III-V MOSFET Devices.

Paolo Longo 1 , Jamie Scott 1 , Alan Craven 1 , Richard Hill 2 , Iain Thayne 2
1 Department of Physics and Astronomy, University of Glasgow, Glasgow United Kingdom, 2 Department of Electronics & Electrical Engineering, University of Glasgow, Glasgow United Kingdom

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9:00 PM -
G5.19 TRANSFERRED TO G1.5

9:00 PM -
G5.5 TRANSFERRED TO G1.6