Symposium Organizers
Qinghuang Lin IBM T. J. Watson Research Center
Wen-li Wu National Institute of Standards and Technology
E. Todd Ryan Advanced Micro Devices
IBM - Albany NanoTech
Do Yeung Yoon Seoul National University
B1: Dielectric Materials I
Session Chairs
Tuesday PM, April 10, 2007
Room 3002 (Moscone West)
9:30 AM - **B1.1
Vapor Deposition of Pore-Sealing, Barrier, Adhesion and Seed Layers for Interconnects.
Roy Gordon 1 , Huazhi Li 1 , Zhengwen Li 1 , Daewon Hong 1 , Damon Farmer 2 , Youbo Lin 2 , Joost Vlassak 2 , Daniel Josell 3 , Thomas Moffat 3 , Christian Witt 4
1 Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States, 2 Division of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, United States, 3 Metallurgy Division, National Institute of Standards and Technology, Gaithersberg, Maryland, United States, 4 TJ Watson Research Center, IBM, Yorktown Heights, New York, United States
Show AbstractAn integrated process has been developed for vapor deposition of all the layers needed to prepare a damascene structure in porous low-k dielectric for electroplating with copper. As a first step, the open pores were sealed with one atomic layer deposition (ALD) cycle that closes the pores with about 6 nm of smooth silica. At the same time, less than 0.4 nm of silica (less than 2 mono-layers) deposited on the copper at via bottoms that had been protected by a self-assembled monolayer (SAM). This residual silica and SAM can be removed from the copper by ion etching methods normally used to clean the copper at via bottoms. Next a diffusion barrier of amorphous tungsten nitride (WN) ~ 2 nm thick was deposited by ALD or by CVD. An adhesion-promoting layer of ruthenium ~ 2 nm thick was formed by ALD or CVD on the WN. Electron microscopy and chemical etch tests demonstrated complete coverage by the ruthenium film. Finally copper seed layers were made by ALD or CVD with a non-fluorine-containing precursor. Quantitative 4-point bend tests showed very strong adhesion (> 20 J m-2) when the metal layers were deposited without an air break. The resulting completely conformal structure (aspect ratio 4:1) had a sheet resistance less than 50 ohms per square for a copper seed layer thickness of less than 4 nm. Electroplating copper on this structure showed complete trench-filling without voids. The structure also survived chemical-mechanical planarization, forming electrically continuous copper in serpentine trenches.
10:00 AM - **B1.2
Interface with High Adhesive and Cohesive Strength Between SiCOH Dielectrics and SiCHN Caps.
Alfred Grill 1 , Dan Edelstein 1 , Michael Lane 1 , Vishnubhai Patel 1 , Stephen Gates 1 , Darryl Restaino 2 , Steven Molis 2 , Nancy Klymko 2 , Kang Yim 3 , V. Nguyen 3 , Alex Demos 3 , Steven Reiter 3 , Hichem M'Saad 3
1 , IBM - T.J.Watson Res.Ctr., Yorktown Heights, New York, United States, 2 , IBM SRDC, Hopewell Junction, New York, United States, 3 , Applied Materials, Santa Clara, California, United States
Show AbstractThe integration of low and ultralow-k SiCOH dielectrics in the interconnect structures of VLSI chips involves complex stacks with multiple interfaces. Successful fabrication of reliable chips requires, among other, strong adhesion between the different layers of the stacks. A critical interface in the dielectric stack is the interface between the SiCH(N) diffusion cap and the SiCOH intra- and interlevel dielectric (ILD). It was observed that, due to the original deposition conditions, the interface layer was weakened both by a low adhesion strength between SiCHN and SiCOH and by the formation of an initial layer of SiCOH with reduced cohesive strength. The manufacturing process has been modified to engineer this interface and obtain adhesion strength close to the cohesive strength of the bulk ILD. The talk will discuss the reasons for the original low adhesion strength and will present the approach for engineering the interface to the cap for both the dense SiCOH and porous SiCOH ILDs.
10:30 AM - **B1.3
Interfacial Organic Layers: Tailored Surface Chemistry for Nucleation and Growth of Inorganic Barrier Layer Materials.
James Engstrom 1
1 Chemical Engineering, Cornell University, Ithaca, New York, United States
Show AbstractInterfacial organic layers, including self-assembled monolayers, have long been recognized for their potential to modify the chemical and physical properties of surfaces. One particularly exciting concept is to use interfacial organic layers to promote thin film deposition of inorganic materials, particularly in situations where nucleation is problematic. One problem that falls into this class is that of the growth of barrier layer materials on low-κ dielectrics. Nucleation on low-κ dielectrics is difficult due to two basic reasons: the chemical termination of the surface is unreactive, and the void space represented by the pores, of course, is by definition unreactive. In the work we describe here we propose the use of interfacial organic layers to promote nucleation and growth of barrier materials on low-κ dielectrics. In a series of studies we have been investigating a variety of phenomena associated with this concept, from studies of the organic layers themselves, to thin film growth via atomic layer deposition (ALD) on these layers. We have demonstrated controlled growth of organic interfacial layers with reactive terminal organic functional (–OH and –NH2) groups, and both linear (straight chain) and branched microstructures. The structure and reactivity of these layers with precursors for ALD, such as Ti[N(CH3)2]4 and Ta[N(CH3)2]5, has also been evaluated. Nucleation and growth of barrier layer materials (TiNxCy) on these organic interfacial layers via ALD has been investigated via the use of molecular beam techniques. We have found that the interfacial layers with reactive terminations give the most uniform films, and thus they should be best suited for ultrathin barrier layer applications.
11:30 AM - **B1.4
Formation of Porous Organosilicate Glasses Produced by PECVD and UV Curing
Mark O'Neill 1 , Patrick Hurley 1 , Scott Weigel 1 , Mary Haas 1 , Brian Peterson 1 , Raymond Vrtis 1 , Dingjun Wu 1 , Steven Mayorga 1
1 Electronics Technology, Air Products and Chemicals, Inc., Allentown, Pennsylvania, United States
Show AbstractThe need of the semiconductor industry for improved dielectric insulators has resulted in the choice of organosilicate glass materials for the manufacture of devices beyond the 130nm node. The inherent limitations of these materials (e.g. inferior mechanical strength, reduced thermal/chemical stability versus silicate glass) have been overcome through modifications to back-end-of-line (BEOL) integration processes. For 45nm generation IC manufacturing and beyond porous organosilicate glasses (OSGs) produced by plasma enhanced chemical vapor deposition will be employed. The introduction of porosity to OSG materials enables improvements in the insulating property while retaining the basic structure and materials character of the previous generations. These porous materials inherently suffer from further reductions in mechanical properties relative to their non-porous predecessors; post-treatment processes such as UV and e-beam are used to improve the material integrity. The final structure and composition of the porous film will impact the processes used for back-end-of-line integration for integrated circuit manufacturing.Previously we have studied the process involved in the production of dense and porous OSGs produced by PECVD and UV processing [1-3] and its potential impact upon integration [4]. The PDEMS™ ILD process involves the co-deposition of an organosilicate glass network with an organic porogen [5]. The deposition is followed by a post-treatment process to liberate the labile organic material and mechanically fortify the porous structure [6]. The impact of deposition and curing has been the subject of much study, however attention has focused most significantly on final material properties. Analysis of the evolution of the materials produced from of OSGs by a plasma-enhanced CVD process with a UV post-treatment process will aid in the understanding of the critical mechanisms involved in the production of a porous OSG network and provide essential information for the optimization and extendibility of these materials.
12:00 PM - B1.5
Remote Plasma Assisted Atomic Layer Deposition of Ultra-thin Pore-sealing for Self-assembled Porous Low-k Materials
Ying-Bing Jiang 1 , George Xomeritakes 2 , Zhu Chen 2 , Darren Dunphy 1 , Jiebin Pang 2 , Eric Branson 1 , Joseph L. Cecchi 2 , C. Jeffrey Brinker 1 2
1 , Sandia National Labs, Albuquerque, New Mexico, United States, 2 , Univ. of New Mexico, Albuquerque, New Mexico, United States
Show AbstractWith ordered pore structure and mono-dispersed pore sizes as small as 2 nm, mesoporous silica thin films made by evaporation-induced self-assembly (EISA) are of great interest for low-k applications. These spin-on films exhibit excellent mechanical strength and thermal stability, along with an isotropic k and low surface roughness, important for etching or chemical mechanical polishing. To seal the open pores at the surface, atomic layer deposition was employed for its capability of obtaining ultra-thin and conformal coatings. However, on a porous substrate, regular ALD takes place not only on the top of the substrate, but also penetrates into the internal porosity, filling pores and drastically increasing the effective ILD k value. Here we report using remote plasma to prevent this internal deposition and confine ALD only to the very top of a porous low-k material. The ALD process is such designed that ALD deposition will not proceed unless triggered by a plasma. Although ALD precursors will be incident on all exposed surfaces, including the internal pores, they are not reactive to each other unless triggered by active plasma radicals. Since the radicals in the plasma do not penetrate into the nanoporous matrix, no ALD will take place in the internal pores, thus the pores will be sealed without losing the original porosity. TEOS (or the related silanes) and O2 were used as the precursors for SiO2 ALD. The substrate was self-assembled mesoporous silica directed by Brij 56 molecules, patterned by interferometric lithography and etched with a CHF3/Ar plasma to create trenched surface. The samples before and after the remote-plasma ALD (PA-ALD) process have been investigated with gas permeability test, pore surface adsorption measurement by surface acoustic wave, Fourier Transform Infrared Spectroscopy (FT-IR), and transmission electron microscope (TEM) / scanning TEM / elemental TEM mapping by electron energy loss spectrum (EELS). It was found that that the PA-ALD pore-sealing was conformal to the patterned surface, and gas-tight although a few nanometers thick. In addition, no internal deposition and no pronounced impairment to the underlying low-k silica was observed. The k-value changed little after PA-ALD pore-sealing (from 2.42 to 2.49).
12:15 PM - B1.6
Ash-free Porogen for Ultralow Spin-On-Dielectrics
Kun Woo Park 1 , Tae Hoon Lee 1 , Gun Woo An 1 , Sung Kyu Min 2 , Bong Jin Moon 3 , Do Young Yoon 4 , Hee Woo Rhee 1
1 Chemical & Biomolecular Engineering, Sogang University, Seoul Korea (the Republic of), 2 Thin Film Team, Hynix Semiconductor Inc., Icheon, Kyunggido, Korea (the Republic of), 3 Chemistry, Sogang University, Seoul Korea (the Republic of), 4 Chemistry, Seoul National University, Seoul Korea (the Republic of)
Show Abstract According to ITRS 2005 devices with feature size of 50 nm or less would require new interlayer dielectrics whose dielectric constant (k) is less than 2.2. The general method to reduce the dielectric constant is to incorporate nano-scaled air voids in the SOD upon decomposition of thermally labile organic materials called porogen. We prepared the nanoporous ultra-low dielectrics with desirable pore morphologies and remarkably high mechanical strength using β-cyclodextrin (CD)- and glucose (GC)-based porogens, which had reactivity with organosilicate matrices through allylation and hydrosilylation reactions. However, these reactive porogens left a small amount of carbon residue after calcination so that it was needed to develop a new reactive porogen without leaving any carbon residue. Therefore, we used new reactive porogens based on organic noncyclic-polyols and reducing sugars. TGA result indicated that the new porogens completely decomposed without any carbon residue. When the organosilicate matrix (k = 2.9) was combined with the new porogens, we could obtain nanoporous SOD which had much lower dielectric constant (k = 2.12) and higher mechanical properties (E = 9.1 GPa) at the porosity of 60%.
12:30 PM - **B1.7
Robust Ultra-Low K and Directly Patterned Interlayer Dielectrics Prepared by Templating Processes.
James Watkins 1
1 Polymer Science and Engineering, University of Massachusetts, Amherst, Massachusetts, United States
Show AbstractDevice scaling below the 45 nm node will place greater demands on interlayer dielectrics, requiring the development of robust, porous films that can be extended to dielectric constants well below 2.4. Our approach to mesoporous silicates for ULKs involves the infusion and selective condensation of organosilicate precursors within one phase domain of a highly ordered, preformed block copolymer template dilated with supercritical carbon dioxide. The template is then removed to produce the mesoporous oxide. Advantages of this approach include rapid and high degrees of network condensation, low film stress, rapid cycle times, stable templates and precursors and opportunities for direct patterning strategies. The first-generation of templates yielded films dielectric constants as low as 1.8. A film with k = 2.2 was selected for further evaluation and found to survive CMP in a planar test stack. In this talk we describe three recent extensions to the technique that significantly enhance film properties and integration strategies. A second generation of templates yield highly ordered films with pore sizes on the order of 2 nm. The use of selected bridged silsesquioxane precursors, the inclusion of porous silica-based nanoparticles within the template system, and new catalyst systems, yield further enhancement in mechanical properties. We also discuss direct pattering of interlayer dielectric films using optical lithography for selective area exposure of templates containing photoacid generators prior to precursor infusion. Removal of the template then yields a directly patterned mesoporous film, eliminating the need for etching and substantially compressing the number of processing steps. Efforts in this last area are initially targeted towards wide lines, with promising results indicating good potential for scaling.
B2: Dielectric Materials II
Session Chairs
Tuesday PM, April 10, 2007
Room 3002 (Moscone West)
2:30 PM - **B2.1
Requirements and Constraints on Optimizing UV Processing of Low-k Dielectrics.
Ivan Berry 1 , Carlo Waldfried 1 , Kevin Durr 1
1 , Axcelis Technologies, Beverly, Massachusetts, United States
Show AbstractUV curing of low-k dielectrics presents a unique challenge in that the cure process is expected to do the impossible – increase hardness, modulus, cohesive strength, adhesion and reliability, decrease water absorbtion and dielectric constant, remove porogens (for porogen containing films), improve dielectric breakdown and chemical stability, all while minimizing shrinkage and contributions to film stress. Achieving this, in general, requires optimization of all of the cure parameters, such as UV spectral intensity, temperature, time, pressure, background gas, and process sequence, as well as the formulation of the low-k material itself. The spectral dependence of many of these important parameters will be discussed. A good figure of merit for modulus and k-value is the ratio of modulus/k-value. If one plots the spectral response of this ratio, one finds it peaks at a specific wavelength range. In principle it is possible to measure the UV spectral response of all of the critical parameters (not just modulus and k-value) and by overlaying these responses together determine what the proper UV exposure wavelength ranges should be. An example of this will be shown for an idealized porogen containing low-k material, for modulus, k-value, porogen removal and porogen crosslinking. An actual low-k dielectric system has many more wavelength parameters to consider and the problem of bulb spectral intensity optimization is deemed even more complex. It is also found that the relative intensity of the critical wavelength bands also plays a significant role in the curing process and requires a great deal of experimentation to optimize depending on the approach taken.UV cure performance is also dependent on cure temperature, time, background gases and ironically, the deposition or post-deposition bake temperature. Most cure parameters such as modulus, hardness, leakage, adhesion, etc, have a strong and generally exponential dependence on cure temperature. As a result, most UV cures are performed at the highest temperature allowable as defined by thermal budget constraints and copper voiding thresholds. The background ambient can also play a critical role in the UV cure, especially for porous low-k materials and those containing porogens. The ultimate in performance is obtained when the low-k material formulation itself is included as a key parameter in the cure optimization. By optimizing the material, UV spectrum, and cure parameters collectively, significant improvements can be made.In conclusion, UV curing cannot be implemented without serious consideration to the wavelength dependence on many critical process factors. The interdependence of all components that makeup the optical system such as the wavelengths employed, light source technology, chamber design and ironically, the dielectric film itself must be considered. Only with these factors in mind, can the full benefit of UV curing be realized.
3:00 PM - B2.2
Understanding the Role of UV Cure on Enhancing Glass Structure and Mechanical Reliability of Porous Low-k Thin Films.
David Gage 1 , Jonathan Stebbins 2 , Zhenjiang Cui 3 , Amir Al-Bayati 3 , Alex Demos 3 , Kenneth MacWilliams 3 , Reinhold Dauskardt 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Geological and Environmental Sciences, Stanford University, Stanford, California, United States, 3 , Applied Materials, Inc., Santa Clara, California, United States
Show AbstractUV radiation curing has emerged as a promising post-deposition processing strategy for significantly improving the mechanical properties of low and ultra low-k dielectric films while still preserving the films targeted dielectric properties. These include improvements in hardness, elastic modulus and adhesive fracture energy. This study examined the detailed effects of UV curing on the structure and mechanical properties of porous carbon doped oxide thin films (k ~2.5). The effects of UV cure exposure time on glass structure were examined through the use of nuclear magnetic resonance (NMR) spectroscopy and Fourier transform infrared spectroscopy (FTIR). Detailed 29Si and 13C magic angle spinning NMR spectra revealed a significant alteration in the glass structure with UV curing. Most notably, the UV curing process led to a progressive removal of certain terminal, non-bridging bonds (for example, Si-OH and Si-CH3) and a subsequent formation of bridged network Si-O-Si bonds. FTIR data confirmed skeleton network formation and the loss of methyl groups during the initial UV curing and relatively little change of the glass structure with extended curing. Fracture mechanics based testing methods, including the four-point bend (FPB) and double cantilever beam (DCB) testing geometries were used to analyze cohesive and adhesive fracture properties. Interfacial fracture energies increased significantly (~300% increase) between the shortest and longest UV exposure times. However, while the cohesive fracture energy increased with initial UV curing, subsequent increases with additional UV exposure were less pronounced compared to the interfacial fracture energies on either side of the CDO films. Additionally, UV curing was found to have little effect on the films resistance to environmentally assisted cohesive cracking in humid environments. Based on the detailed understanding of UV cure mechanisms gained through the NMR and FTIR data, we are able to explain the significant increases in adhesive fracture energy, as well as the insensitivity of cohesive fracture properties to longer UV curing times. The role of UV curing and implications for reliable integration will be discussed.
3:15 PM - B2.3
The Effect of Ultraviolet Light Curing on the Fracture Properties of a k~2.5 Low-k Dielectric.
Ryan Smith 1 , Ting Tsui 2 , Paul Ho 1
1 Material Science and Engineering, University of Texas at Austin, Austin, Texas, United States, 2 Silicon Technology Development, Texas Instruments, Inc., Dallas, Texas, United States
Show AbstractUltra-violet light curing has been shown to improve the mechanical properties of low-k dielectrics, e.g. modulus and density. Yet, a paucity of literature exists on the effects of UV curing on the fracture properties of ultra low-k films. In this paper, we investigated the role of UV curing on critical and sub-critical fracture of a k~2.5 low-k material. The fracture toughness was correlated with the molecular structure of the material using Fourier Transform IR (FTIR) Spectroscopy. The prinicipal structure elements were network, cage, and sub-oxide. Furthermore, changes in the molecular structure with UV exposure were demonstrated by subtractive FTIR. Density and k-values had a direct correlation with the sub-oxide content. Additionally, UV exposure significantly influenced the critical fracture toughness by increasing the density; yet, sub-critical fracture was insensitive to UV exposure. The surface bond density of the fracture surfaces was roughly independent of UV cure. The threshold and bond rupture energies had a linear dependence on relative humidity.
3:30 PM - B2.4
Structural Transformation During Porogen Removal Under Ultraviolet Assisted Thermal Curing on PECVD Porous Ultra low-k Material.
Aziz Zenasni 1 , Laurent Favennec 2 , Vincent Jousseaume 1 , Olivier Gourhant 2 , Julien Fort 3 , Patrick Maury 2 , Lucile Mage 1 , Samphy Hong 3 , Gerard Passemard 2
1 LETI-D2NT-LBE, CEA, Grenoble France, 2 , STMicroelectronics, Crolles France, 3 , Applied Materials, Meylan France
Show Abstract3:45 PM - B2.5
Self-organized Nanostructures by Atmospheric Microplasma Processing.
Davide Mariotti 1 , Yoshiki Shimizu 1 , Vladimir Svrcek 1 , Dae-Gun Kim 1 , Takeshi Sasaki 1 , Naoto Koshizaki 1
1 NARC, AIST, Tsukuba, Ibaraki, Japan
Show AbstractThe importance of plasmas in the next generation of material processing is evident. At the same time plasma technology needs to progress in order to meet future requirements of nanoscale processing. Our general scope is to achieve an evolutionary and deterministic material synthesis through plasma processing. In this contribution we present the results of our initial attempt to use microplasma processing to promote self-organized growth of nanostructures. Our technique exploits novel microplasma configurations (D. Mariotti et al., J. Appl. Phys. in press, 2006); in this particular case the treated surface is in contact with the plasma and at the same time subjected to strong electromagnetic fields due to the microscale nature of the plasma itself.A description of the microplasma system is provided together with some important plasma parameters measured by optical emission spectroscopy (D. Mariotti et al., Appl. Phys. Lett. 89, in press 2006). The microplasma is ignited by a high voltage pulse and then sustained by power at 450 MHz. The microplasma is formed between a metal wire (or tubing) and a substrate placed on top of the powered copper electrode. Processing occurs in atmospheric pressure argon mixed to other gases such as oxygen or methane.Our original microplasma system shows a high degree of flexibility in the fabrication of nanostructures and more importantly it can induce the formation of self-organized carbon-based interconnects (e.g. nanotubes, nanowires etc.) between nanoparticles. Here we will present results showing evidence of self-organization, in particular we have produced self-aligned molybdenum-oxides nanostructures and we will report on promising self-organized carbon-based structures connecting silicon nanoscrystals, gold nanoparticles or silver nanoparticles onto a silicon substrate. Influence of catalyst and nanoparticle size on interconnections will be discussed in details. In order to characterize such interconnects and nanostructure products SEM, XPS and HRTEM are used.The mechanisms that are responsible for these self-organized nanosctructures are not fully identified nevertheless it is believed that the peculiar microplasma properties and the electromagnetic fields generated in our system are of fundamental importance. Our future work is aimed to achieve complete processing control and contribute to the understanding and a better exploitation of self-organization.
4:30 PM - **B2.6
The Role of Pore Characterization in the Challenge to Integrate Porous low-k Dielectrics
David Gidley 1 , Richard Vallery 1 , Ming Liu 1
1 Physics, University of Michigan, Ann Arbor, Michigan, United States
Show AbstractBeam-based positron annihilation lifetime spectroscopy (PALS) is a powerful porosimetry technique with broad applicability in characterizing nanoporous thin film dielectrics. Pore sizes and distributions in the 0.3 – 30 nm range are non-destructively determined with only the implantation of low energy positrons from a table-top beam. Depth-profiling with PALS has proven to be an ideal way to measure the interconnection length of pores, search for depth-dependent inhomogeneities or damage in the pore structure, and to explore porosity hidden beneath dense layers or diffusion barriers. The capability of PALS is rapidly maturing as new intense positron beams around the globe spawn more accessible positron facilities. After a brief introduction this talk will focus on recent efforts to address the challenge of integrating porous low-k dielectrics. PALS can detect and profile plasma-induced damage especially when pore-collapse is involved. Pore sealing strategies can be tested for sealing efficacy and profiled for pore filling or film densification. Nano-imprinting of trenches in porous dielectrics is being explored and PALS is helping to characterize the effects on pore structure of the imprint process.
5:00 PM - B2.7
Mechanical Impacts of Templating Polystyrene Porogen in Methylsilsesquioxane.
Markus Ong 1 , Geraud Dubois 2 , Willi Volksen 2 , Robert Miller 2 , Reinhold Dauskardt 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Almaden Research Center, IBM, San Jose, California, United States
Show AbstractTemplating porosity in low-k materials such as methylsilsesquioxane (MSSQ) using polymer porogen particles is a way to achieve well-controlled pore size. The pore architecture of these films plays a significant role in the mechanical and fracture properties and ultimately the practical reliability of these ultra-low-k films. The effects of these templating particles on the mechanical and fracture properties of these low-k films were investigated in this study. Polystyrene particles (~10 nm) were used to template porosity in an MSSQ matrix, and the porogen loading was varied from 0 to 50%. Fracture energies were measured using four-point bend tests to quantify the adhesion of the porous MSSQ to adjacent SiC or metal layers. It was found that the porogen was attracted to the MSSQ/SiC interface, leaving behind disproportionately high porosity near this interface during the burnout process. The fracture energies for these films were less than 0.5 J/m2, far below the expected value for films of comparable densities. However, when a dense layer of MSSQ was used to “prime” the substrate before creating the porous film, the porogen had no preference to segregate from the MSSQ matrix toward the dense MSSQ underlayer. Corresponding fracture energies were much higher compared to the films without the priming underlayer and were comparable to measurements made during previous studies of porous MSSQ. Clearly, the chemistry of porogen/matrix systems is a critical factor in the pore structure and mechanical properties of these films.
5:15 PM - B2.8
Atomic-Scale Analysis of Structural and Mechanical Properties of Amorphous Microporous and Mesoporous Silica Thin Films.
M. Rauf Gungor 1 , James Watkins 2 1 , Dimitrios Maroudas 1
1 Department of Chemical Engineering, University of Massachusetts, Amherst, Massachusetts, United States, 2 Department of Polymer Science and Engineering, University of Massachusetts, Amherst, Massachusetts, United States
Show AbstractPorous amorphous silica films have important technological applications in sensor and detection arrays, separation processes, and, more recently, in microelectronic devices as ultra-low-dielectric-constant materials. In microelectronics, the structure of “mesoporous” amorphous silica films (pore diameters of 5-10 nm) creates challenging materials reliability problems due to inferior mechanical strength compared to that of the more traditionally used dense amorphous silica films. Toward fundamental understanding of the nano-scale mechanisms that control the mechanical behavior of microporous and mesoporous structures of dielectric materials and toward predictions of the response of such structures to various mechanical loading conditions, we have performed molecular-dynamics (MD) simulations using a realistic classical potential that includes two-body and three-body interatomic interactions.The normal-density amorphous silica structures are prepared through MD, starting from crystalline beta-cristobalite structures and following a thermal processing protocol. We have generated the microporous amorphous structures by volume expansion of the originally dense amorphous structure and “regular” mesoporous structures through introduction of a regular array of spherical pores by removal of atoms from the amorphous silica matrices. The MD-generated structures are annealed at the temperature of interest to ensure proper structural relaxation. In this presentation, we report results for the mechanical behavior of the microporous and regular mesoporous amorphous silica structures under applied strains within the elastic strain range at temperatures over a range of a few hundred degrees above room temperature obtained through nanosecond-scale MD simulation using large-size computational supercells. The elastic moduli and the hardness of the amorphous microporous and regular mesoporous silica structures are calculated as a function of their density. For the mesoporous structures, the analysis is carried out over a range of pore sizes and pore separation distances. Furthermore, a detailed analysis of the atomistic mechanisms of pore morphological evolution is reported in response to both compressive and tensile strains.
5:30 PM - B2.9
Organic-Functionalized Pure-Silica-Zeolite MFI and MEL Films for Low-Dielectric Constant Applications.
Christopher Lew 1 , Zijian Li 1 , Shuang Li 1 , Sonjong Hwang 2 , Dora Medina 1 , Minwei Sun 1 , Mark Davis 2 , Yushan Yan 1
1 Chemical and Environmental Engineering, University of California, Riverside, Riverside, California, United States, 2 Chemical Engineering, California Institute of Technology, Pasadena, California, United States
Show AbstractAs the feature size of next-generation microprocessors decreases, the need for low-dielectric constant (low-k) materials with high mechanical strength is an increasing concern. Many potential porous materials take advantage of the low-k value of air, which is about 1, but they are often amorphous in nature and thus lack mechanical strength. Porous zeolites, however, are highly crystalline and have a high elastic modulus but still retain the low-k values of amorphous porous silica materials. Since water has a high k value, moisture adsorption is a serious concern for all porous low-k materials. Consequently, along with low-k and high elastic modulus values, hydrophobicity is becoming an increasingly important parameter. To combat this problem, post-spin-on silylation treatments with chlorotrimethylsilane and hexamethyldisilazane have been performed, and pure-silica-zeolite (PSZ) MFI has been functionalized with methyltrimethoxysilane. Here, we report organic-functionalized PSZs with MFI- and MEL-type structures prepared through a direct-synthesis method by adding a fluorinated silane to the synthesis solution, and the added fluorine functionality increased the hydrophobicity of the zeolites. The zeolite was characterized by x-ray diffraction, scanning electron microscopy, 29Si solid-state nuclear magnetic resonance spectroscopy, nitrogen adsorption-desorption measurements, and thermogravimetric analysis. Spin-on films prepared from the nanoparticle suspension exhibited higher water contact angles than non-functionalized PSZ films, and the zeolite powders had low water content. k-values were as low as 1.8 and increases due to moisture adsorption were limited to below 15%. Mechanical strength tests were also performed by nanoindentation.
5:45 PM - B2.10
Damage-free Etching Processes of Low Dielectric (Low-k) Films Using the Neutral Beam
Butsurin Jinnai 1 , Seiji Samukawa 1
1 Institute of Fluid Science, Tohoku University, Sendai, Miyagi, Japan
Show AbstractFor 90 nm and beyond ULSI devices, Al/SiO2 interconnects have been substituted by Cu/low-k film interconnects in order to reduce the RC delay time and the power consumption. Plasma etching processes are extensively used for the etching of low-k films. However, severe damages of low-k films are induced during plasma etching processes. These damages are mainly caused by irradiating UV/VUV photons from the plasma to the low-k surfaces, resulting in the increasing of dielectric constant of low-k films. In order to overcome these problems, we propose novel low-k film etching processes by using our newly developed neutral beam, which enables no UV/VUV irradiation from the plasma. In this paper, we investigated radiation damages of low-k films etched in the conventional inductively coupled plasma (ICP) process and the neutral beam process, and could accomplish damage-free low-k film etching by the neutral beam.Our neutral beam source consists of an ICP and parallel carbon plates. The process chamber is separated from the plasma chamber by a carbon plate fitted at the bottom. Numerous apertures in the bottom carbon plate extract neutral beams from the plasma into the process chamber. The accelerated ions are effectively neutralized by a charge transfer when they pass through the apertures. Additionally, the photons generated in the plasma chamber are almost completely eliminated by passing through the apertures because UV lights are effectively absorbed and/or shaded in the apertures of the carbon plate.SiOC films (film thickness: 200 nm) on silicon substrates were etched to 150 nm depth with SF6 gas chemistries in both the neutral beam process and the conventional ICP process. The in-depth composition of SiOC films after irradiating the plasma and the neutral beam were evaluated by using X-ray photoelectron spectroscopy (XPS). Additionally, thermal desorption spectroscopy (TDS) was used to observe desorption gases (H2O and F) from SiOC films. The change of in-depth composition of SiOC film corresponds to the amount of damages.SiOC films before the processes have the uniform in-depth composition (Si, O, C), and F atom was not observed at all. After irradiating the neutral beam, just at the SiOC film surface, the concentrations of O and C atom were slightly changed. A small amount of F atom was also observed. However, after irradiating the plasma, the structure of the SiOC film was drastically changed even at more than 100 nm in depth. We believe that the change of SiOC film structure is mainly caused by UV/VUV photon irradiation. UV/VUV photons in the conventional ICP process could deeply penetrate into the SiOC film and could break the chemical bonding in the SiOC. On the other hand, in the neutral beam process, because of the elimination of UV/VUV photons, only the slight surface of the SiOC film was influenced. This result suggests that our developed neutral beam process could realize damage-free etching of low-k films.
B3: Poster Session: Dielectric Materials
Session Chairs
Wednesday AM, April 11, 2007
Salon Level (Marriott)
9:00 PM - B3.1
Mechanical Properties and Fracture of Ultra-low-k (ULK) Nanoporous Organosilicate Glass Coatings with Varied Porosities.
Youbo Lin 1 , Han Li 1 , Joost Vlassak 1
1 , Harvard University, Cambridge, Massachusetts, United States
Show AbstractNanoporous organosilicate glass coatings with relative dielectric constant less than 2.5 are widely considered for use as inter-metal dielectric in future generations of advanced integrated circuits. Their ultra low dielectric constant is achieved by incorporating a significant fraction of nanometer-sized pores in a hybrid organic-inorganic matrix, which resembles an amorphous silicon dioxide network with some bridging oxygen atoms replaced by organic groups such as methyl, hydrogen and methylene. While this results in improved dielectric performance, the mechanical response of these coatings is degraded. In order to be successfully integrated in a process flow, it is desired to optimize the mechanical properties while retaining a low dielectric permittivity. This may be done by engineering the pore size and morphology, and tuning the composition and structure of the matrix. Thus, a good understanding of the respective impacts of matrix structure and porosity on the mechanical and fracture properties of these low-k films is critical. In this paper, we will report experimental results on the mechanical properties of nanoporous ULK films, including stiffness, hardness and intrinsic fracture toughness over a range of porosities. The evolution of the mechanical and fracture properties will be rationalized in terms of the structure and porosity changes in the ULK films.
9:00 PM - B3.10
Effect of He, Ar, O2 Plasma Treatments on the Electrical and Chemical Properties low-k SiCOH Film Deposited by PECVD.
Sungwoo Lee 1 , Jaeyoung Yang 1 , Changrok Choi 1 , Sangmin Do 1 , Heeyeop Chae 2 , Donggeun Jung 1 , Jim-hyo Boo 3 , Hyoungsub Kim 4
1 Physics, sungkyunkwan University, Suwon, Gyunggi, Korea (the Republic of), 2 Chemical engnieering, Sungkyunkwan University, Suwon, Gyunggi, Korea (the Republic of), 3 Chemistry, sungkyunkwan University, Suwon, Gyunggi, Korea (the Republic of), 4 Materials Engineering, Ssungkyunkwan University, Suwon, Gyunggi, Korea (the Republic of)
Show AbstractWe investigated the effect of various plasma treatments (helium, argon and oxygen plasma) of the low-k SiCOH films deposited by PECVD. The relative dielectric constants, k, of the SiOCH films may be changed during the interconnect integration process, during which the He and Ar plasma treatment are used for the adhesion enhancement and the surface cleaning, respectively. The O2 plasma treatment is used to remove photoresist. As-deposited and 450oC annealed SiCOH films with k=3.0 and k=2.5, respectively, were used. Ar and O2 plasma treated samples showed increased k-values and decreased breakdown voltages. The plasma treatment is thought to cause modification of the bonding structure of the film, chemical degradation, moisture adsorption and/or O-H bond formation. However, the He plasma treatment of the SiCOH films did not show any notable degradation of SiCOH films. The He plasma treated sample showed decreased k-value from 3.0 to 2.9 for the as-deposited film and from 2.5 to 2.4 for the 450oC annealed film. Suppression of O-H group formation and more decrease of Si-O related groups than C-Hx groups in the SiCOH film were thought to contribute to the reduction of the k values. In terms of the dielectric constant, the largest damage to the film was caused by the O2 plasma treatment, and the lowest damage by the He plasma treatment. The leakage current density of ~10-8A/cm2 at 1MV/cm is obtained for all the SiCOH films.
9:00 PM - B3.11
Optical Absorption and Characteristics of Low-k Films and Barrier Layers in the Ultra-Violet Range
Salvador Eslava 1 2 , Guillaume Eymery 1 , Mikhail Baklanov 1 , Francesca Iacopi 1 , Francesca Clemente 1 , Carlo Carbonaro 3 , Philippe Foubert 1 , Karen Maex 1 2
1 , IMEC, Leuven Belgium, 2 ESAT, Katholieke Univ. Leuven, Leuven Belgium, 3 Dept. of Physics, Cagliari Univ., Monserrato Italy
Show AbstractThe ultraviolet irradiation combined with thermal activation (UV-cure) not only enhances the mechanical properties of low-k materials but also removes more efficiently the porogens. The UV-cure mechanism is assumed to depend on the UV wavelengths used, but so far, no characterization has been reported on the absorption of low-k materials in the ultraviolet range. Moreover, many uncertainties appear when UV-cure is applied to multiple layers, as there is no information of the transmission across a whole stack.Since the absorption characterization might be key for the integration of UV-cure in Microelectronics, we studied the optical characteristics, focusing on the absorption, of low-k materials and barrier layers measured by ellipsometry (UV and visible range) and VacuumUltraViolet absorption (VUV range). In the used ellipsometry setup, the refractive index and the extinction coefficient at every wavelength (150 - 700 nm) are extracted by applying regression analysis of a model that approximates the measured angles Ψ and Δ. In the VUV absorption experiments, measurements have been performed in transmission in the 150 - 300 nm range with synchronous detection.First, the accuracy of the ellipsometry results was assessed. This was done by comparing the results of different incident angles; correlating the regression with direct calculations; and, characterizing thermal oxide, whose absorption can be compared to that of amorphous silica reported in literature. VUV absorption is combined to this study for obtaining direct measurements of the absorption spectra of the thin films. The different organosilica low-k films show a shift in the absorption edge to lower energies as compared to thermal oxide. Moreover, absorption bands appear in the UV range that could be attributed to the C concentration. The absorption bands decrease or shift upon the UV-cure. Finally, the absorption of different barrier layers show marked differences depending on their composition, being TaN the one with the highest absorption. Combining both the extracted refractive indices and the extinction coefficients we simulated the total transmission and absorption for different stacks of low-k and barrier. Due to the multiple internal reflections, the transmission and the absorption strongly oscillate along the spectrum. This simulation provides the intensity spectrum that underneath layers will be exposed to, necessary for the architecture of interconnects.In conclusion, we present the absorption of organosilica low-k films, barrier layers, and combinations of them in multiple layers. This study is of critical importance for a correct implementation of UV-cure processes in Microelectronics manufacturing.
9:00 PM - B3.12
Effects of CH4 Plasma Treatment on Porous Organosilicate Low-k Dielectrics
Hualiang Shi 1 , Junjing Bao 1 , Junjun Liu 2 , Huai Huang 1 , Paul S. Ho 2
1 Physics, The University of Texas at Austin, Austin, Texas, United States, 2 Material Science, The University of Texas at Austin, Austin, Texas, United States
Show AbstractTo investigate plasma induced damage on porous low k dielectrics and possible pre-treatment and post-treatment remedies, effects of direct CH4 plasma and downstream CH4 plasma treatments on porous Organosilicate low-k dielectrics were evaluated. Angle Resolved X-ray Photoelectron Spectroscopy (ARXPS), X-Ray Reflectivity (XRR), Residual Gas Analyzer (RGA), Spectroscopic Ellipsometry (S.E.), Fourier Transform Infrared Spectroscopy (FTIR), and Contact Angle Goniometer were employed to study the damage related to plasma energy, dose, and Ar balance gas, and how CH4 plasma pretreatment and postashing treatment can affect the O2 plasma induced damage. For CH4 plasma pre-treatment of pristine low k films, XRR and XPS depth profiling confirmed the formation of a carbon-rich densified polymer layer (~3 nm) on top of the low-k dielectric. Treatments by mixing Ar to CH4 direct plasma led to negligible additional damages, suggesting that the plasma process was dominated by surface chemical reactions. For post O2-ashing CH4 plasma treatments, the surface carbon concentration and hydrophobicity were partially recovered. A broad absorption peak from 1300cm-1 to 1500cm-1appeared in the FTIR spectra, suggesting the formation of methylene groups. The mechanism of interaction between CH4 plasma and low-k surface will be discussed.
9:00 PM - B3.13
Spin-on Barrier-dielectric/CMP-cap for Cu/low-k Interconnect.
Shin-ya Arase 1 , Nobuhide Maeda 1 , Yoshio Takimoto 1 , Hiroshi Kawakami 1 , Kouji Sumiya 3 , Yoshio Homma 1 , Hidenori Saito 2 , Masahiro Tada 2 , Terukazu Kokubo 3
1 , Consortium for Advanced Semiconductor Materials and Related Technologies (CASMAT), Kokubunji, Tokyo, Japan, 3 , JSR Corporation, Ltd., Tsukuba, Ibaraki, Japan, 2 , Sumitomo Bakelite Co., Ltd., Yokohama, Kanagawa, Japan
Show AbstractIn order to reduce of RC delay in interconnect, various low-k dielectrics have been investigated as ILDs of Cu interconnect. In conventional Cu/low-k interconnect structures, however, p-SiO and p-SiCN films used as CMP-cap and Cu diffusion barrier layer have prevented inter-line capacitance from effective reduction due to their large k-values. Therefore, k-value reduction of CMP cap and Cu diffusion barrier layer is necessary to reduce the effective k-value (k_eff) of interconnect. We have developed Cu/low-k interconnect with spin-on diffusion barrier, and CMP cap. Since k-values of these SODs could be made significantly lower than that of CVD films, incorporation of SODs with lower k-value will result in significant reduction of effective k-value of interconnect. It is estimated that Spin-on-Barrier/Cap (SBC) interconnect shows k_eff reduction of 13% than that of conventional interconnect, in which p-SiO and p-SiCN are used as cap and Cu diffusion barrier layer respectively. In order to evaluate the barrier performance of the new organic barrier SOD (CRC-5200), TDDB measurements are carried out It is seen that CRC-5200 can guarantee 10-year life time against Cu diffusion (0.2 MV/cm @200 degC). In the fabrication process of interconnects, due to spin-on stuck structure, multiple layers could be cured simultaneously. This simultaneous curing enhanced adhesion strength between layers and shortens its process time. In addition, the spin-on type CMP cap (LKD-2055) showed sufficient immunity against SOD dry-etching and subsequent Cu/barrier metal CMP by exhibiting no de-lamination. Since SODs have self planarization property, the Cu diffusion barrier SOD layer shows an excellent planarity regardless of underlying metal line undulations. To suppress chemical interaction between Cu and CRC-5200 varnish components, we also prepared a sample in which Cu lines were covered with CoWP metal cap. I-V characteristics using comb structure of metal-1 layer shows that SBC interconnects with metal cap exhibit similar profile to that of the conventional CVD/SOD structure (CVD cap and barrier). Electrical characteristics of fabricated via chain structures based on SBC indicate good distributions of resistance for 180-nm and 130-nm vias.
9:00 PM - B3.15
Effect of Environment on the Modulus of low-k Porous ILD Films Used in the BEOL.
Eva Simonyi 1 , Christos Dimitrakopoulos 1 , Stephen Gates 1 , Michael Lane 1 , Eric Liniger 1
1 , IBM, Yorktown Heights, New York, United States
Show AbstractReliability is an important requirement for the newly developed porous low-k ILD materials that are being introduced into (BEOL). Dependence of Young’s moduli, as measured by nanoindentation technique, on the environment [such as high relative humidity, water immersion and recovery] is presented along with FT-IR spectra for a number of films with different k values. Effect of the moduli changes on cracking behavior is also discussed.
9:00 PM - B3.16
Dry Etching of SiC with CF4/Ar Inductively Coupled Plasmawith a Photoresist Mask.
Jie Lu 1 , Chris Thomas 1 , Mvs Chandrashekhar 1 , Michael Spencer 1
1 Electrical and Computer Engineering, Cornell University, Ithaca, New York, United States
Show Abstract9:00 PM - B3.17
The Impact of Dielectric Films and Post-Metal Etch Wet Treatment on Charge-Induced Corrosion of Tungsten Vias.
Szetsen Lee 1 , Chi-Jung Ni 2
1 Chemistry, Chung Yuan Christian University, Chungli Taiwan, 2 Module Technology Development, Winbond Electronics, Hsinchu Taiwan
Show AbstractThe prevention of charge-induced corrosion of tungsten vias after metal etch has been studied with several types of commonly used wet chemical solutions and two kinds of dielectric film materials, silicon dioxide and silicon oxynitride. It is found that one of the solutions, leaving essentially no polymer residue on metal lines, can effectively prevent corrosion of tungsten vias. Other solutions either produce minor residues or severe sidewall erosion on metal lines. In our study, it also shows that the combination of wet treatment with oxynitride as the dielectric charge shielding film is as effective as other conventional methods for preventing tungsten vias corrosion. However, significant metal sidewall erosion and surface roughness and residue were observed on metal lines capped with silicon dioxide. Chemical reaction mechanisms are proposed for the preservation of tungsten vias after metal etch.
9:00 PM - B3.18
Synthesis and Characterization of Porogen-bridged Silsesquioxane Monomers and Their Application to Ultralow-k Films
Woojin Lee 1 , Jae Hwan Sim 1 , David Gidley 2 , Do Y. Yoon 1
1 Department of Chemistry, Seoul National University, Seoul Korea (the Republic of), 2 Department of Physics, University of Michigan, Ann Arbor, Michigan, United States
Show AbstractFor advanced microelectronic devices, it is expected that an insulating material should have ultralow-dielectric constant (ultralow-k) lower than 2.2 for feature sizes smaller than 40 nm. This goal can be achieved only through incorporation of nano-sized pores over 30 % porosity in the insulator. However, it is difficult to obtain isolated nanopore structures without pore interconnection by the conventional porogen blending approach at high porosities above 20%. In order to prevent pore interconnectivity, two kinds of porogens can be used simultaneously, such that separate nanopores are obtained in the thin film by repulsion between different porogens. We synthesized porogen-bridged silsesquioxane comonomers and synthesized silsesquioxane polymers containing two different porogens for ultralow-k films. Detailed structure-property relationships of these ultralow-k films will be presented.
9:00 PM - B3.19
Environment-Friendly Plasma Etching of High Aspect Ratio Silicon by a Gas-Chopping Process.
Hyongmoo Rhee 1 , Chang Han Park 1 , Chang-Koo Kim 1
1 Chemical Engineering, Division of Energy Systems Research, Ajou University, Suwon Korea (the Republic of)
Show AbstractPlasma etching is widely used to obtain high aspect ratio patterns of silicon in the fabrication of microelectromechanical systems (MEMS) devices. One of the methods for deep silicon etching is a gas-chopping process, known as the Bosch process or time-multiplexed deep etching. It is a cyclic process, consisting of alternating etching and deposition steps. SF6 and c-C4F8 gases are currently used as discharge gases in the etching and deposition steps, respectively, for the Bosch process. c-C4F8 gas, however, is pefluorocarbon (PFC), and this PFC is considered to be problematic from an environmental point of view because of its long atmospheric lifetime and high global warming potential (GWP). Several classes of environmentally benign chemistries have been examined as alternatives to PFCs, and unsaturated fluorocarbons (UFCs) are one of the attractive candidates due to their shorter atmospheric lifetimes and lower GWP. In this study, we report on a gas-chopping process for etching of high aspect ratio silicon using SF6/c-C4F8 and SF6/C4F6 plasmas. C4F6 was selected since C4F6 (UFC) has a shorter lifetime (0.003 years) and lower GWP (290) compared to c-C4F8 which has a lifetime of 3200 years and GWP of 8700. By varying the source power, bias voltage, pressure, and durations of deposition and etching steps, it was found that deposition of fluorocarbon polymer played a critical role in determining the shape of etch profiles. Patters having an aspect ratio higher than 10 were successfully etched, showing that the feature angle was nearly 90 degrees, in both c-C4F8 and C4F6 plasmas. The etch profiles using the SF6/c-C4F8 plasma was nearly identical those using the SF6/C4F6 plasma. Therefore, it can be said that the use of a C4F6 plasma for a gas-chopping process of deep silicon etching is a good alternative to PFC gases.
9:00 PM - B3.2
Penetration of Tagged Organics into Caulked and Un-caulked Porous Dielectrics Measured by Rutherford Backscattering.
Robert Geil 1 , Jay Senkevich 2 , Bridget Rogers 1
1 , Vanderbilt University, Nashville, Tennessee, United States, 2 , Brewer Science Inc., Rolla, Missouri, United States
Show AbstractThe implementation of low-k porous dielectrics to improve power consumption, cross-talk, and interconnect delay associated with logic device scaling has been met with a number of challenges. During the back-end-of-line (BEOL) process the porous dielectric is exposed to numerous organic solvents and aqueous and alkaline solutions from wet strip and cleans and CMP processes. These chemicals can penetrate into the porous material and have the deleterious effects of increasing the dielectric constant and issues of interface delamination. There has been no clear methodology developed to study the penetration of these chemicals, especially when the porous dielectric is pore-sealed or caulked. In this work we develop such a method that both relates to a real processing environment and is quantitative. By using chlorine-tagged organics, such as 3-chloropropanol and a %5 HCl solution, penetration through the cap layer and into the porous dielectric could be studied with Rutherford Backscattering Spectrometry (RBS). Penetration through two different caulking materials at thickness of ~100 Å was investigated over a range of wet chemical exposure times. The method will be explored and results presented.
9:00 PM - B3.20
Laser Thermo-Reflectance Measurement for Heat Capacity and Heat Resistance Evaluation of Low-k Films
Jiping Ye 1 , Takao Okamura 1 , Yuka Hattori 1 , Sawa Araki 1 , Shigeo Sato 1
1 Research Dept., NISSAN ARC Ltd., Yokosuka Japan
Show AbstractHigh thermal stability and low thermal stress are required for low-k films to prevent thermal deterioration, fracture including debonding of interface and cracking of thin films, or property changes in Cu/low-k interconnect structures during thermal treatment processes. Thermophysical properties such as thermal conductivity, thermal expansion coefficient, glass-transition temperature have been widely estimated for improvement of thermo-mechanical performance of these low-k films. Measurements of these thermophysical properties are well-known and commercially available. Besides these properties, heat capacity and heat resistance are also very important values. Low heat capacity of the low-k films and high heat resistance at the interface are able to elevate film temperature to a high level resulting in high thermal stress and damage to the films. However, it is extremely difficult to determine the heat capacity Cp and heat resistance R for thin films and until recently the measurements of Cp and R has been generally restricted to bulk materials. In this work, an attempt was made to apply a laser thermo-reflectance (LTR) measurement method for evaluating the heat capacity of the low-k films and the heat resistance at the interface between the low-k film and Si substrate. The heat capacity was given by Cp=b2/ρλ, where b is the thermal effusivity obtained by the LTR measurement, ρ is the density obtained from x-ray reflectivity (XRR) measurement, and λ is the thermal conductivity measured by a conventional 3ω method. In the LTR measurement, a reference Mo film with a thickness of 100 nm was pre-deposited on the specimen surface. An intensity modulated laser with a wavelength of 830 nm was used to heat the Mo film surface periodically, whereas a constant intensity laser with a wavelength of 655nm was irradiated onto the surface of the Mo film to get the resulting temperature response by detecting thermo-reflectance light signal under the periodic heating conditions. The phase lags between the surface temperature response and the heating laser were detected for the determination of the thermal effusivity of the specimens. Measurement reliability was examined by using thermal stable SiO2 films. These films had different thicknesses from 200 to 500 nm but the same density of 2.19 g/cm3. It was demonstrated that the SiO2 film had less heat resistance around the interface and had a heat capacity of CP=0.7Jg-1K-1. This method was applied to the low-k materials and was found to be useful for evaluating the heat capacity and heat resistance at the interface of the low-k films.
9:00 PM - B3.21
Synthesis and Characterization of Novel Porogen-Bridged Silsesquioxane Polymers and Preparation of Dual Porogen Based Ultralow-k Films
JaeHwan Sim 1 , Woojin Lee 1 , David W. Gidley 2 , Do Yeung Yoon 1
1 Department of chemistry, Seoul National University, Seoul Korea (the Republic of), 2 Department of Physics, University of Michigan, Ann Arbor, Michigan, United States
Show AbstractGenerally at high porosities above 20%, it is difficult to obtain isolated nanopore structures by the conventional porogen blending approach. Dual porogen method uses two kinds of porogens and induces separate nanopores by repulsion between different porogens, in order to suppress pore-interconnectivity. In order to obtain such a dual porogen system we developed novel porogen-bridged comonomers and synthesized silsesquioxane polymers. A new dual porogen system was prepared by synthesis of modified silsesquioxanes with two kinds of porogen containg comonomers. Subsquently ultralow-k film (k<2.2) were successfully prepared with the polymers containing dual porogens. The detailed structure-property relationship of such ultralow-k film will be presented.
9:00 PM - B3.22
Process Optimization of UV Curing for Ultra Low-k Dielectrics and High-Stress SiN Liners
Masazumi Matsuura 1 , Kinya Goto 1 , Shinobu Hashii 2 , Noriko Miura 1 , Yoshihiro Miyagawa 1 , Tatsunori Murata 1 , Yoshikazu Tsunemine 1 , Koyu Asai 1
1 , Renesas Technology Corp., Itami Japan, 2 , Renesas Semiconductor Engineering Corp., Itami Japan
Show AbstractUV curing technologies have proven to be effective for enhancing device performances in FEOL and BEOL processes at the 45nm technology node and beyond. We have reported that ultra Low-k SiOC (ULK-SiOC, k=2.6), which is required in advanced SoC devices to reduce RC interconnect delay and crosstalk noise, is greatly hardened with the UV modification [1, 2]. High stress silicon nitride (HS-SiN) liner with tensile stress is a promising approach to boost the transistor drive current in nMOS-FET. UV modification enables the tensile stress of the SiN liner to be higher than that of plasma CVD deposited SiN liner without any post-modifications. This paper describes process optimization of UV curing for ULK-SiOC and HS-SiN liner. Two types of UV bulbs (UV-X and UV-Y) were employed for UV curing in this study. The emission of UV-X bulb contains shorter wavelength band (λ<200nm) than that of UV-Y bulb (λ>200nm). We have investigated the impact of UV curing using different UV bulbs on process damages to the ULK-SiOC. Process damages due to the resist strip plasma and wet cleaning were evaluated by using the variation in k-value of ULK-SiOC before and after conducting the processes. The k-value variations of ULK-SiOC modified with UV-X bulb are greater than those of the pristine ULK-SiOC, while the k-value variations of ULK-SiOC modified with UV-Y bulb are as same as those of the pristine ULK-SiOC. These results indicate that UV-X bulb degrades the process survivability of ULK-SiOC, resulting in the great increase in k-value. We have previously reported that the UV-X bulb with high photon energy generates 3-fold Si-O ring defects and Si-H bonds in the ULK-SiOC [2]. These results are consistent with the degraded process survivability of ULK-SiOC when using the UV-X bulb. In order to discuss the pore structure in UV-modified ULK-SiOC, Solvent diffusion of toluene and ethanol in ULK-SiOC were measured. The solvent diffusion of the UV-modified ULK-SiOC with UV-X bulb is faster than that of the UV-modified ULK-SiOC with UV-Y bulb. This result indicates that the pore size of UV-modified ULK-SiOC with UV-X bulb is larger than that of UV- modified ULK-SiOC with UV-Y bulb. The larger pore in UV-modified ULK-SiOC with UV-X bulb may be attributed to the generation of 3-fold Si-O ring defects and Si-H bonds in the ULK-SiOC. The dependence of the stress increase in HS-SiN liner on UV wavelength band has been investigated by using stress measurement and FT-IR. The UV-modified HS-SiN liner with UV-Y achieves higher tensile stress, compared to the UV-X bulb. FT-IR results have revealed that UV-Y bulb is more effective for the dehydrogenation and SiN crosslinking, resulting in the greater increase in the tensile stress. In conclusion, UV-Y bulb with medium photon energy yields the desired UV modifications for ULK-SiOC and HS-SiN applications. References: 1. K. Goto, et al., Proceedings of AMC2005, 277 (2005). 2. M. Matsuura, et al., MRS Proc., vol. 914, F01-06 (2005).
9:00 PM - B3.25
Nanoindentation Measurements on the Instrinsic Strength of Pure-Silica-Zeolite Low-k Materials.
Christopher Lew 1 , Zijian Li 1 , Mark Johnson 2 , Minwei Sun 1 , E. Ryan 3 , David Earl 4 , Wolfgang Maichen 5 , Jeremy Martin 3 , Shuang Li 1 , Junlan Wang 2 , Michael Deem 4 , Mark Davis 6 , Yushan Yan 1
1 Chemical and Environmental Engineering, University of California, Riverside, Riverside, California, United States, 2 Mechanical Engineering, University of California, Riverside, Riverside, California, United States, 3 , Advanced Micro Devices, Inc., Hopewell Junction, New York, United States, 4 Bioengineering, Physics, and Astronomy, Rice University, Houston, Texas, United States, 5 , Teradyne, Inc., Agoura Hills, California, United States, 6 Chemical Engineering, California Institute of Technology, Pasadena, California, United States
Show AbstractPorous silicas are promising candidates to replace dense silica for use as low-dielectric constant (low-k) insulators in microprocessors. With amorphous porous silicas, the mechanical strength deteriorates rapidly with increasing porosity and creates significant concerns over the reliability of these materials under mechanical stresses imposed during the chemical mechanical polishing and packaging processes. Here, we experimentally show that pure-silica-zeolites (PSZs) have a remarkably higher elastic modulus (E) than amorphous porous silicas at any given porosity or k value due to their crystalline structure. Nanoindentation on PSZ MFI-type films grown through a seeded growth method reveal intrinsic data on the E values of zeolite films. Our films have an E and k of 41.8 GPa and 3.10, respectively, while the E of amorphous silica is typically below 20 GPa for similar k values. Further insight into the strength of zeolites was provided by nanoindentation on single zeolite crystals with CHA, MFI, and FER-type structures. The elastic modulus values were 43.3, 50.6, and 62.4 GPa, respectively. A time domain reflectometry technique was used to measure the capacitance of the FER crystals, and a k value of 1.78 was obtained at 1 MHz. Again, compared to amorphous porous silicas, the elastic moduli at comparable k values were significantly higher for the zeolite crystals. The experimental observations are supported by our theoretical calculations of k and E on selected frameworks. The combined experimental and theoretical findings suggest that PSZs have the necessary properties for use as the next generation low-k insulators.
9:00 PM - B3.26
Characterization of Liquid Penetration into Advanced PDEMS® Dielectrics
Madhukar Rao 1 , Dnyanesh Tamboli 1 , Thomas Wieder 1 , Mark O'Neill 1 , Scott Weigel 1
1 , Air Products and Chemicals, Inc., Allentown, Pennsylvania, United States
Show AbstractThe development of robust integration processes for low dielectric constant materials is critical in order to meet the International Technology Roadmap for Semiconductors (ITRS) timeline for next generation materials. Organosilicate glass (OSG) materials with bulk dielectric constant between 2.7 and 3.0 are currently being ramped into production for the 90nm and 65nm semiconductor devices interconnect node. For 45 nm and beyond the ITRS roadmap dictates use of an advanced dielectric material with a bulk dielectric constant below 2.5. The dielectric constant of OSG materials produced by plasma enhanced chemical vapor deposition (PECVD) processes can be reduced to less than 2.01 through the introduction of porosity. During integration processing of porous materials liquids can be absorbed into the pore network (e.g. during the polishing and cleaning process steps) resulting in an increase in the dielectric constant.2 The relationship of the liquid properties (surface tension, contact angle, etc.) and the pore structure and morphology of the dielectric to the penetration of liquids is not well understood. In this paper we evaluate structure-property relationship for liquid penetration into four different porous OSG materials based on PDEMS® technology3. The OSG films are prepared using different porogen precursors, which give rise to a wide range of pore size and total porosity. The kinetics of liquid penetration into these substrates is investigated using ellipsometric techniques. A series of surfactant-containing aqueous solutions, having a range of wetting characteristics, are used as the penetrants. The effect of these chemicals on the materials properties of the porous films can be characterized using dielectric constant measurement, X-ray scattering, surface energy measurement, Scanning Electron Microscopy (SEM), and Fourier Transformed Infrared Spectroscopy (FTIR).1. R. Vrtis, MRS Series Vol. 766, pg. 259 2. D. Tamboli, T. Wieder, M. Rao, S. Weigel, M. O’Neill, G. Banerjee and J. Langan, International Conference on Planarization Technology 2006, Foster City, CA, October 2006. 3. US patent 6,846,515.
9:00 PM - B3.27
Profile Control for Low-k Patterning Using TaN and TiN Metallic Hardmasks.
Herbert Struyf 1 , Dirk Hendrickx 1 , Vasile Paraschiv 1 , Diana Campos Garcia 2 , Geert Mannaert 1 , Werner Boullart 1 , Serge Vanhaelemeersch 1
1 SPDT, Imec , Leuven Belgium, 2 , INSA de Lyon, Villeurbanne France
Show Abstract9:00 PM - B3.3
Evolution of the Porosity and the Structure During the Cleaning Process for a Porous SiOCH ULK Material.
Wilfried Puyrenier 1 , Diane Rébiscoul 2 , Lucile Broussous 1 , Andre Ayral 3 , Vincent Rouessac 3
1 , STmicroelectronics, Crolles France, 2 , CEA-LETI, MINATEC, Grenoble France, 3 , IEM, Montpellier France
Show Abstract9:00 PM - B3.4
Low-k organic Dielectric Film for Barrier-free Interconnect.
Nobuhide Maeda 1 , Yoshio Takimoto 1 , Yoshinori Sakamoto 1 , Masahiro Tada 1 , Hideo Nakajima 2 , Keisuke Funatsu 1
1 R&D Department, Consortium for Advanced Semiconductor Materials and Related Technologies (CASMAT), Kokubunji-shi, Tokyo, Japan, 2 Fundamental Research Laboratory, Sumitomo Bakelite Co., Ltd, Yokohama, Kanagawa, Japan
Show Abstract Barrier metal in Cu/low-k interconnect acts as insulator for conduction, and also behaves as metal for capacitance. Therefore, the Cu/low-k interconnect free from barrier metal is advantageous for RC reduction. For the purpose to eliminate barrier metal, we tried applying a spin-on type organic polymer dielectric, Polybenzoxazole (PBO, k=2.65). According to SIMS measurements, thermal diffusion of Cu into PBO is as low as that of SiCN. We fabricated Cu/PBO damascene interconnects to evaluate electrical characteristics and reliabilities. Flange of the line in barrier-free interconnect is formed roundly. This shape suppresses the concentration of horizontal electric field along the CMP surface. While the square-edge electrode makes much higher field than the average field, the round-edge electrode gives smaller field than the average in the entire interline-space along the CMP interface. The amount of shoulder recession is about 10nm, which reduces inter-line capacitance by 2.6%. Sheet resistance of barrier-free structure is 25% smaller than that of conventional one. This can be explained by the thickness of barrier metal in the conventional structure. Leak current of barrier-free interconnect is one digit smaller up to 2.5MV/cm. The TDDB lifetime of barrier-free structure is longer than that of the conventional one. 90nm- via resistance is reduced by 75%.
9:00 PM - B3.5
Methods for the Determination of Porosity in Organosilicate Low Dielectric Constant Films Produced by PECVD.
Mary Haas 1 , Mark O'Neill 1 , John Zielinski 1 , John Higgins 1 , Brian Peterson 1 , Scott Weigel 1 , Raymond Vrtis 1 , Dingjun Wu 1 , Patrick Hurley 1 , Dino Sinatore 1 , Mark Bitner 1 , Michael Kimak 1
1 Electronics Technology, Air Products and Chemicals, Allentown, Pennsylvania, United States
Show AbstractMaterials with increasingly lower dielectric constant values are needed for future-generation integrated circuits (ICs) in order to continue the enhancement of signal propagation. One commonly used technique to reduce dielectric constant is the generation of nano-sized voids, or porosity. Porous organosilicate glasses (OSG) produced by plasma-enhanced CVD, in particular, have arisen as the leading such candidates for the 45 nm IC node.The dielectric constant of a porous film depends on the total porosity and on the chemistry of the matrix material. Whereas the chemical composition and structure of the matrix can be assessed using methods such as FT-IR and NMR, routine methods for determining total porosity are still emerging.The inclusion of a porous film in an integrated circuit stack presents a number of unknowns. For example, the consequence of subsequent back-end-of-line (BEOL) processing steps on the integrity of the porous ILD is the focus of much study. The total porosity, in addition to pore size, pore interconnectivity, and surface chemistry, is expected to influence the effects of processing on the porous ILD.For these reasons, there is a need to proficiently assess the porosity of OSG dielectrics. Here we discuss several methods for determining porosity, and include experimental data for films produced by the PDEMSTM ILD process.1 This highly relevant material has been shown in previous studies to provide an excellent balance of electrical and mechanical properties for a methyl-doped silicate glass.2NMR and FT-IR data suggest that the network structures of dense DEMSTM and porous DEMSTM films are nearly indistinguishable. For these materials, the major chemical variable under optimized process conditions is the ratio of silicon-methyl to silicon-oxygen species in the film network. Therefore it is possible to create a calibration curve to estimate the porosity of PDEMSTM films using data collected for dense DEMSTM films of appropriate methyl contents. The resulting values for total porosity are compared with those collected by ellipsometric porosimetry and standard sorption techniques.[1] J.L. Vincent, M.L. O’Neill, H.P. Withers, S.E. Beck, and R.N. Vrtis, US Patent 6,583,048 (2003)[2] M.L. O'Neill, R.N. Vrtis, J.L. Vincent, A.S. Lukas, E.J. Karwacki, B.K. Peterson, M.D.Bitner, MRS Symposium Proceedings 766, 321 (2003); M.L. O’Neill, M.K. Haas, B.K. Peterson, R.N. Vrtis, S.J. Weigel, D.J. Wu, M.D. Bitner, and E.J. Karwacki, MRS Symposium Proceedings (2006)
9:00 PM - B3.6
Extendibility of the PECVD Co-deposition Approach for ULK Materials.
Olivier Gourhant 1 , Vincent Jousseaume 2 , Laurent Favennec 1 , Aziz Zenasni 2 , Patrick Maury 1 , Lucile Mage 2 , Julien Fort 3 , Samphy Hong 3 , K. Yim 4 , Vu Nguyen 4 , Patrice Gonon 5 , Gilbert Vincent 5
1 , ST Microelectronics, Crolles Cedex France, 2 LETI, CEA Grenoble, Grenoble cedex 9 France, 3 , Applied materials, Meylan cedex France, 4 , Applied materials, Santa Clara, California, United States, 5 , LTM-CNRS, Grenoble Cedex France
Show Abstract9:00 PM - B3.7
Dynamics of Moisture Uptake and Removal in Porous Low-k Dielectric Films.
Harpreet Juneja 1 , Junpin Yao 1 , Asad Iqbal 1 , Ting Tsui 2 , Farhang Shadman 1
1 NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing, University of Arizona, Tucson, Arizona, United States, 2 Silicon Technology Development, Texas Instruments, Dallas, Texas, United States
Show AbstractIntegration of porous low-k dielectrics in manufacturing environment requires a better understanding of the challenges and issues that are associated with the characteristics of these new materials. Because of its porous structure these films are highly susceptible to Atmospheric Molecular Contamination (AMC), especially moisture and chemicals. This in turn results in retention and incorporation of moisture, which might outgas in further processing steps resulting in delamination and other potential issues. Etching and ashing are typical processing steps, which these films are exposed to during manufacturing environment.The interaction of moisture with porous spin-on dielectric films is investigated using a unique set up for real time and in-situ characterization of moisture uptake and removal, using a combination of analytical methods including mass spectrometers, cavity ring down spectrometer, and IR spectroscopy. A number of low-k materials, including methylsilsesquioxane (MSQ) and black diamond II, were used in this study. This study also compared blanket/cured films with films exposed to etch and ash conditions. A process model is developed that provides information on the dynamics of moisture absorption and interaction with thin MSQ films. The model can predict residual impurity contamination and helps in optimizing process conditions for efficient cleanup of these dielectric films during semiconductor manufacturing. Using this model, the role of physical and geometric properties of the low-k film has been determined and method for optimum design and selection of low-k material is presented.The results show that, compared to traditional SiO2, some of the low-k dielectric films are highly susceptible to moisture contamination and that the removal of moisture from these films is an activated and slow process. Compared to blanket and cure only, N2H2 ash can slightly decrease moisture solubility in MSQ low-k matrix, but significantly raise moisture diffusivity. In addition to changing the film properties, TEM results show that the etching and ashing processes could dramatically decrease the overall film thickness and increase its porosity. Furthermore, by simulation, it was inferred that a 10 nm cap layer with low moisture solubility can effectively block moisture penetration through the low-k film irrespective of the moisture diffusivity. The presentation will also summarize a comparison between a number of commercially available low-k materials.
B4: Poster Session: Novel Concepts and Materials
Session Chairs
Wednesday AM, April 11, 2007
Salon Level (Marriott)
9:00 PM - B4.1
Assembly and Positioning of Carbon Nanotube Bundles for Interconnect Applications
Michael Woodson 1 , Jie Liu 1 , Alexander Tselev 1
1 Chemistry, Duke University, Durham, North Carolina, United States
Show AbstractAs integrated circuit fabrication approaches the 13 nanometer node, assemblies of parallel carbon nanotubes are predicted to demonstrate performance as interconnects superior to that of copper, currently the dominant material. Organizing large numbers of such small particles into the complex architectures required for integrated circuit applications has proved difficult, however. We present a method to fabricate microcircuits including high-density parallel bundles of carbon nanotubes. The bundles are assembled from suspension by control of the dielectrophoretic and surface tension forces, either directly on the substrate or on a sharp tip, to be deposited later. DC and AC measurements are also presented.
9:00 PM - B4.10
Structural, Compositional and Electrochemical Properties of Nanocrystalline Si-Cr Alloy Anodes for Lithium Thin Film Battery.
Arun Patil 1 , Vaishali Patil 1 , Ji-Won Choi 1 , Seok Jin Yoon 1
1 Thin Film Materials Research Centre,, Korea Institute of Science and Technology ,, Seoul, seoul, Korea (the Republic of)
Show AbstractIn recent years, many new materials have been investigated in order to meet the need of high energy density for thin film batteries. Silicon based anode materials are attracting wide attention because of the highest theoretical capacity. Nanocrystalline films of silicon-chromium alloys were deposited on alumina substrate by RF magnetron sputtering technology. High purity chrome and silicon sputtering target were used for the deposition . First aluminium was deposited on substrate acts as a current collector and over that Si-Cr was deposited by Rf sputtering method. Both the layers were analysed by XRD, EDAX, AFM, SEM and TEM. Electrochemical properties of the films were analysed. After Lithium insertion and excertion the effect on the structure and surface on the thin film has been studied. Thickness of Si-Cr and aluminium on alumina substrate is 600 nm and 200 nm respectively. The crystallite size determined by FWHM of XRD peaks. Particle size and microstructure of the film have been studied by SEM and AFM. The thin films have 96% purity of silicon-chromium and aluminium which is confirmed by EDAX. Composition ratio between silicon and chrome obtained by EDAX is 4:1.
9:00 PM - B4.11
Effect of Post-annealing on Thermal Degradation of Indium Tin Oxide Thin Films Deposited by rf Magnetron Sputtering.
Yongnam Kim 1 , Hyungyoo Shin 2 , Junkwang Song 2 , Heesoo Lee 3
1 Failure Analysis Team, Korea Testing Laboratory, Seoul Korea (the Republic of), 2 Material Testing Team, Korea Testing Laboratory, Seoul Korea (the Republic of), 3 National Core Research Center, Pusan National University, Pusan Korea (the Republic of)
Show AbstractIndium tin oxide(ITO) is an advanced ceramic material with many applications in electronics, owing to its high electrical conductivity and transparency to visible light. ITO is an n-type degenerate semiconductor, and both oxygen vacancies and substitutional Sn4+ replaced at In3+ sites contribute to its high carrier concentration. Therefore, ITO films have been used as transparent electrodes for display devices, transparent coatings for solar energy heat mirrors, and transparent contacts in advanced optoelectronic devices such as solar cells, light emitting and photo diodes, photo transistors and lasers.There are several factors that cause decay in the efficiency, and failure of electronic devices. One of the main factors determining the lifetime of electronic devices is degradation of, or damage to, ITO films. In addition, the quality of devices depends largely on the quality of their ITO films. ITO films acquire a thermal history during fabrication, and the normal operating conditions of electronic devices require very high electric fields. Their properties are varied with these conditions. In particular, as high electric fields induce joule heating, thermal degradation in ITO films might be expected. Accordingly, understanding of the thermal degradation behavior of ITO films is essential to overcome the deterioration in performance and improve the lifetime and quality of electronic devices.It is known that thermal degradation of ITO films in air or oxygen results in an increase of resistivity. A decrease of the carrier concentration or the mobility leads to an increase of resistivity, because the conductivity (the reciprocal of resistivity) is a function of the product of the carrier concentration and the mobility. The decrease of the carrier concentration results from the neutralization of ionized Sn donors and the removal of oxygen vacancies. The higher the oxygen concentration in ITO films, the lower the carrier concentration in it becomes, resulting in an increase of resistivity. The mobility is mainly decreased by scattering phenomena. Free electrons in the reduced state (at higher carrier concentration) are scattered by charged donors such as ionized impurities and oxygen vacancies, whereas in the oxidized state (at lower carrier concentration) by neutral impurities. In addition, scattering at grain boundaries is considered to be dominant.The present paper reports the effect of post-annealing on thermal degradation behavior of ITO films deposited on glass substrates by RF magnetron sputtering. The as-deposited specimens were post-annealed under various conditions (atmosphere, temperature and time) to vary the oxygen concentration and the grain size in ITO films. ITO thin films post-annealed were different in the carrier concentration and the mobility and showed different thermal degradation behavior at high temperatures in air. The thermal degradation behavior was investigated, based on XRD and Hall measurement results.
9:00 PM - B4.12
Frequency-dependent Piezoelectric Device for Small-power Harvesting.
Min-Soo Kim 1 , Soon-Jong Jeong 1 , Dae-Su Lee 1 , Jae-Sung Song 1
1 Advanced Materials & Application Research Laboratory, Korea Electrotechnology Research Institute, Changwon, Kyungnam, Korea (the Republic of)
Show AbstractPiezoelectric ceramics and their devices are one of candidates in choosing micro-power harvesting system. In such system, piezoelectric material should exhibit high piezoelectric coefficient and low dielectric constant for achieving high efficiency in transforming from external mechanical vibration energy into electric energy. One of promising application of piezoelectric harvesting system is self powered sensor systems and their wireless communication which require power over 10 mW. To achieve such high power from environmental vibration, two major considerations should be pointed out in material and vibration mode. Such system consisting of piezoelectric device can achieve higher power when it is in resonant mode. However, the resonant condition for the system varies with environmental condition. In order to maintain easily the best resonant mode, this paper presents a simple method to tune a resonant frequency of the system. In this study, a system consisting of multilayer piezoelectric device and moonie type strain amplifier was presented. The system was designed to operate in resonant mode at 120 Hz. When a vibrating force of 2 N is given to the system, power of over 20 mW was generated. When a resistor is connected serially to the system, the resonant frequency changed in range of 10%. The relationship between the material of piezoelectric system and external resistor was considered.
9:00 PM - B4.2
Direct Synthesis and Modification of Singlewalled Carbon Nanotubes-Silica Nanoparticles Functional Systems.
Yung Joon Jung 1 , Myung Gwan Hahm 1 , Ahmed Busnaina 1 , Lije Ci 1 , Pulickel Ajayan 1
1 Mechanical and Industrial Engineering, Northeastern University, Boston, Massachusetts, United States
Show Abstract9:00 PM - B4.3
Synthesis of Fe-catalyst through Spray Pyrolysis for MWNTs
Jun Ho Choi 1 , Joon He Jeong 1 , Jin Ho Lee 1
1 R&D Center, Samsung Corning, Gyeonggi-do Korea (the Republic of)
Show Abstract9:00 PM - B4.4
Improvement of the Performances in Vertical GaN Blue Laser Diode by Backside Contact Process Optimization.
Taehoon Jang 1 , YounJoon Sung 1 , Kyusang Kim 1 , Suhee Chae 1 , Okhyun Nam 1 , Yongjo Park 1
1 Photonics, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of)
Show Abstract9:00 PM - B4.5
Synthesis and Characterization of Electronic Ink Particles for Electronic Paper
Hwa Jin Cha 1 , Hyo Sim Kang 1 , Young Soo Kang 1 , Ju Chang Kim 1 , Sun Hwa Oh 2
1 Chemistry, Pukyong National Univ., Pusan Korea (the Republic of), 2 Basic Science Research Institute, Pukyong National University, 599-1 Daeyon-3-Dong, Nam-Gu, Pusan Korea (the Republic of)
Show Abstract9:00 PM - B4.8
A Low Temperature Photonic Crystal Technology for Integration with Modern CMOS Technologies.
Khadijeh Bayat 1 , Mahdi Farrokh Baroughi 1 , Sujeet Chaudhuri 1 , Safieddin Safavi-Naeini 1
1 ECE, University of Waterloo, Waterloo, Ontario, Canada
Show AbstractSilicon photonic crystal (PC) technology is a new approach to integrate optical interconnects and compact optical devices in CMOS ICs. Currently, silicon-based photonic crystals rely on silicon on insulator (SOI) PCs. Although SOI-PCs can be integrated easily in SOI CMOS ICs with minor modifications in the fabrication process, it is not possible to engineer the thickness and the refractive index of the film and cladding layers in this technology. Further, the technology is solely limited to SOI based integrated circuits. In this work, we introduce a low temperature (LT) PC technology based on hydrogenated amorphous silicon oxy-nitride (a-SixOyNz:H) thin films for integration with conventional CMOS technologies. This provides significant freedom in engineering of the thickness and the refractive index of the film. Further, the LT-PC technology can be implemented on any kind of CMOS technology.The a-SixOyNz:H thin films are deposited by PECVD technique on top of the inter layer dielectric layers of the CMOS chips. The process temperature is kept less than 300οC, typically 260οC, to prohibit side effects of high temperature post processing. The films are patterned by conventional lithography and an anisotropic reactive ion etching process to form PC-based photonic devices and waveguides. Then another layer of a-SixOyNz:H film with a different composition and refractive index is used as the cladding layer for further control of refractive index contrast in the PC structure. The a-SixOyNz:H films of 1um thickness were deposited on glass and CZ c-Si substrates for optical and compositional characterizations, respectively. Films of different refractive indices were deposited by different gas flows of SiH4, N2O, NH3, and H2. The RF power density, process pressure, and the hydrogen flow were fixed at 90 mW/cm2, 400 mTorr, and 200 sccm, respectively. Gas flows of SiH4, N2O, and NH3, were varied in the range of 0.5-10 sccm, 0 – 80 sccm, and 0 – 80 sccm, respectively. The refractive index and the composition of the films were characterized by spectroscopic ellipsometry and Rutherford back scattering techniques. By changing the film composition refractive indices in a wide range of 1.6 – 3.1 has been obtained for the films at 1.53 μm. A three dimensional finite difference time domain (3D-FDTD) analysis was employed to design single mode optical waveguides and polarization converters using the developed material library. The 3D-FDTD analysis shows that the thickness of the film layer plays an important role in guiding mechanism and polarization dependence of the PC based optical waveguides. The results of our analysis, which were fed by our measured material parameters, show that the LT-PC technology is superior to the existing SOI-PC technology because of extra degrees of freedom in thickness and refractive index of the film.
9:00 PM - B4.9
A Modeling and Simulation Study for Control of Diameter of Si Single Crystal Ingot in Cz Furnace
Jae Hak Jung 1 , Jin Soo Park 1 , Won Shoup So 1 , Min kyo Seo 1 , Mi Jung Park 1
1 School of Display and Chemical Engineering, Yeungnam University, Gyongsan, Gyeongsangbuuk-do Korea (the Republic of)
Show Abstract
Symposium Organizers
Qinghuang Lin IBM T. J. Watson Research Center
Wen-li Wu National Institute of Standards and Technology
E. Todd Ryan Advanced Micro Devices
IBM - Albany NanoTech
Do Yeung Yoon Seoul National University
B5: Emerging Interconnect Concepts and Materials
Session Chairs
Wednesday AM, April 11, 2007
Room 3002 (Moscone West)
9:30 AM - **B5.2
A Novel Method to Prepare Superhydrophobic, Self-cleaning and Transparent Coatings for Biomedical Electronic Devices.
ChingPing Wong 1
1 Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractNatural superhydrophobicity has recently gained much attention and inspired mimetic attempts. In many plants, notably the lotus flower, leaves utilize superhydrophobicity as the basis of a self-cleaning mechanism. Two criteria define superhydrophobicity: one is the surface has a very high water contact angle and the other is that the surface need to be micro/nano structured. The surface roughness can enhance the hydrophobic surface to superhydrophobicity. The Wenzel’s equation was to account for roughness through the ratio of the actual to projected area. If the contact angle (CA) is large and the surface sufficiently rough, the liquid may trap air so as to give a composite surface effect and an apparent contact angle specified by the Cassie’s equation. Under this regime, the superhydrophobic surface can be achieved.Due to the excellent water repellency of superhydrophobic surfaces, it is desirable to develop a robust superhydrophobic coating for the self-cleaning, transparent and antifouling applications in biomedical devices. With this coating, the device can be more reliable under complicated conditions such as corrosive body fluid. And in some cases where sun light is required, the transparency is also a prerequisite for the successful application of the superhydrophobic coatings. The superhydrophobicity depends on both the surface energy and the surface morphology. Even a material with the lowest surface energy provides water CA of only 120 degrees if the surface is smooth. For superhydrophobicity (water CA considerably larger than 150 degrees), an appropriate surface roughness is required. A major problem in developing transparent superhydrophobic surfaces arises from the light scatter that is naturally induced by surface roughness. There are several reports on rough coated or etched surfaces revealing superhydrophobicity, however, no solution has been presented that achieves superhydrophobic surfaces with a desirable low scatter losses. In this presentation, we will report for the first time a novel method of preparing ultra-thin films with nanostructures to make transparent superhydrophobic coatings. A sol-gel process was employed with a novel solvent, eutectic liquid solvents, which acts as both low vapor pressure, low melting point liquid and a templating agent in the sol-gel process, together with a nonionic surfactant for the mesoporous structure templating for the film. From the results of UV-Visible spectrum we found that the coating on a microscope glass slide can show better light transmittance than a bare glass slide. This suggests the improved light transmittance with this superhydrophobic coating. This superhydrophobic surface is biocompatible because of the extremely low surface energy due to the combination of fluoroalkyl chain on the surface and the surface nanostructures. And the superhydrophobic coating can also effectively prevent the penetration of body fluid to the device to improve the system reliability.
10:00 AM - B5.3
Angular Orientation-Specific Directed Self-assembly Enabling the Integration of Ultra Small Dies.
Robert Knuesel 1 , Shameek Bose 1 , Wei Zheng 1 , Heiko Jacobs 1
1 Electrical and Computer Engineering, University of Minnesota, Minneapolis, Minnesota, United States
Show AbstractWe report on recent progress in the directed self-assembly of discrete high performance semiconductor device components. Different from prior research, the goal is to enable the integration of ultra small dies (10-100 micrometer in size) while supporting unique angular orientation and contact pad registration. The process is based on the reduction of surface free energy between liquid solder coated areas on the substrate and metal-coated binding sites on the semiconductor dies. This paper will discuss the design of a fluidic platform to inspect the assembly process as it proceeds. Angular orientation control and discrimination between differently sized objects is accomplished using three dimensional docking sites that make use of raised pedestals and sequential batch transfer of differently sized components. Surface chemistry to prevent aggregation and agitation schemes will be presented that are key to the successful assembly of ultra small dies. The reported method aims at enabling integration and formation of interconnects to 10-100 micrometer sized chiplets closing the gap between nanoscopic and macroscopic systems, which is not possible using current robotic assembly and wire bonding concepts.
10:15 AM - B5.4
Stretchable Interconnects for Microelectronics.
Joyelle Jones 1 , Stephanie Lacour 2 , Prashant Mandlik 1 , Sigurd Wagner 1
1 Electrical Engineering, Princeton University, Princeton, New Jersey, United States, 2 , University of Cambridge, London United Kingdom
Show AbstractWe have created stretchable thin-film interconnects for several types of applications. For microelectronic systems, stretchable interconnects have a high initial conduction, can be patterned in 10µm wide lines in any directions, and are encapsulated with a stretchable dielectric allowing for multilayered circuits . For some biomedical applications such as biochemical sensing, the interconnect topography must be controlled on the micrometer and nanometer scales. Therefore, we fabricated stretchable metallic interconnects on nanopatterned substrates. The fabrication sequence starts with the patterning by photolithography of 75 nm thick gold (Au) lines on polydimethylsiloxane (PDMS) substrates. The substrate surface may be flat or nanostructured with arrays of 250nm tall hillocks spaced 500nm apart. Two different patterns of lines were fabricated by photolithography on the PDMS containing hillocks. One set of lines was patterned so that the stretching direction was parallel to the hillocks. The other set of lines were patterned so that the direction of stretching was at an angle to the hillocks. Lines with similar geometry were patterned by photolithography on flat PDMS surfaces. Lines patterned on flat PDMS were encapsulated with a second layer of PDMS. All lines were stretched, and the electrical resistance was measured under tensile strain. For up to 20% strain, the resistances of encapsulated lines and lines patterned parallel to the hillocks were comparable to lines patterned by photolithography on PDMS containing a flat surface. The resistance of lines patterned at an angle to the hillocks was several orders of magnitude higher when compared to the other samples. We will discuss the fabrication, morphology, and electro-mechanical behavior of each type of interconnects.
10:30 AM - B5.5
Nano-scale Conductive Films for High Performance Fine Pitch Interconnect
Yi Li 1 , ChingPing Wong 1
1 Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractRecently anisotropic conductive films (ACFs) and nonconductive films (NCFs) are becoming popular as promising candidates for lead-free interconnection solutions in microelectronic packaging application due to their technical advantages such as fine pitch capability (<40 μm pitch), low temperature processing ability, low cost and environmentally friendly materials and process, etc. However, there are several issues for ACF/NCF as lead-free interconnection application. Still they need high bonding pressure for the assembly and interconnection. Another limitation of ACF/NCF is the lower electrical properties compared to solder joints. To ensure low contact resistance and high current density, interface between conductive fillers and electrode should be improved. In order to solve the issues (high bonding pressure and lower electrical performance) of NCF while maintaining the advantages of ultra fine pitch and low cost, a novel conductive film incorporated with very low loading of nano-scale conductive fillers are studied for next generation high performance fine-pitch packaging applications. This novel interconnect film combines the electrical conduction along the z-direction (ACF-like) and the ultra fine pitch (< 100 nm) capability (NCF-like). Unlike typical ACF which requires 1-5 vol% of conductive fillers, the novel NCF only needs less than 0.1 vol% conductive fillers to achieve good electrical conductance in the z direction. Therefore, the x-y plane remains a good insulation/dielectric property and the pitch size of the interconnect is not limited. The nano-sized conductive fillers exhibited obvious sintering behavior at the curing temperature of the film. Therefore, the novel nano-scale conductive films with nano-Ag sintering form the metallurgical joints between the IC chip bumps or pads and the substrate metal pads, which result in the significantly reduced joint resistance and the enhanced current carrying capability of the interconnect. By using this novel material, much lower bonding pressure was required to achieve the low joint resistance compared to a typical NCF process, and the joint formation also enhanced the electrical performance and reliability of the interconnect. While the typical NCF/ACF showed obvious delamination after reliability test, the nano-scale NCF/ACF remained intact after reliability test due to the metallurgical joints and thus stronger bonding of the joints. Therefore, the novel nano-scale NCF/ACF which combined the advantages of NCF (low cost, ultra fine pitch) and ACF (low bonding pressure) and exhibited better performance (lower joint resistance, higher current carrying capability, better reliability and high frequency stability) than both NCF and ACF, could be potentially used as high performance interconnect in next generation fine-pitch packaging applications.
11:15 AM - **B5.6
Design of Chemical Vapor Deposition Processes for Low k Dielectrics and Air Gap Formation.
Karen Gleason 1
1 , MIT, Cambridge, Massachusetts, United States
Show AbstractStructural rules for the chemical makeup of mechanically robust low k organosilicate glass (OSG) dielectrics will be presented and validated against nanoindentation experiments performed on series of plasma enhanced chemical vapor deposition (PECVD) films. Predictions for precursor chemistries capable of selectively building the desired film structures are made by density functional calculations (DFT). The results of the DFT calculations will be compared to the observed chemical structures of OSG PECVD films. Additionally, alternate methods of introducing porogens into PECVD films and the effect of porogen decomposition on the structure of the OSG matrix will be explored. Finally, extension of porogen materials to full sacrificial layers for air gap formation will be discussed. The design of the sacrificial layers with the desired properties is achieved by initiated chemical vapor deposition (iCVD).
11:45 AM - B5.7
Measuring Pattern Quality and Porosity of Dielectric Insulator Films Directly Patterned by Nanoimprint Lithography
Hyun Wook Ro 1 , Jones Ronald 1 , Peng Huagen 2 , Hines Daniel 3 , Hae-Jeong Lee 1 , Eric Lin 1 , Alamgir Karim 1 , Do Yoon 4 , Gidley David 2 , Soles Chris 1
1 Polymers Division, NIST, Gaithersburg, Maryland, United States, 2 Department of Physics, University of Michigan, Ann Arbor, Michigan, United States, 3 Laboratory for Physical Sciences, University of Maryland, College Park, Maryland, United States, 4 School of Chemistry, Seoul National University, Seoul Korea (the Republic of)
Show AbstractDirectly patterning low-dielectric constant materials via nanoimprint lithography has significant potential for integrating nanoporous inter-layer dielectric (ILD) into the technology node below 32 nm. In this study 100 nm line-space patterns are imprinted into a poly(methylsilsesquioxane) (PMSQ)-based resin, both with and without porogen, while the pattern shape is precisely quantified with specular X-ray reflectivity (SXR) and critical dimension small angle X-ray scattering (CD-SAXS). These measurements show that the patterns transferred into the organosilicate material with excellent reproducibility and high fidelity. Positron annihilation lifetime spectroscopy (PALS) measurements indicate imprinting of the PMSQ resin increases the native microporosity and leads to decrease of dielectric constant from 2.84 to 2.68 for the material without porogen. An additional reduction of dielectric constant is realized by adding a commercial PEO-b-PPO surfactant (Tetronics 150R1, BASF) as a porogen. PALS data on the porogen-loaded patterns indicates that the imprinting process decreases the fraction of mesoscale pores associated with the porogen while retaining the increased fraction of microporosity. The combined effect of increased microporosity and decreased mesoporosity should reduce pore interconnection and will be attractive from an application point of view.
12:15 PM - B5.9
NanoCT: Visualizing of internal 3D-Structures with Submicrometer Resolution.
Dirk Neuber 1 , David Lehmann 2 , Oliver Brunke 1
1 , phoenix|x-ray Systems + Services GmbH, Wunstorf Germany, 2 , phoenix|x-ray Systems + Services Inc., St. Petersburg, Florida, United States
Show Abstract12:30 PM - B5.10
Monolithic Tunnel Junctions for Molecular Electronics using Atomic Layer Deposition.
Rahul Gupta 1 , Brian Willis 1
1 Chemical Engineering, University of Delaware, Newark, Delaware, United States
Show AbstractAccording to the 2005 International Technology Roadmap for Semiconductors the gate length of transistor is expected to reach below 20 nm by 2015. These small dimensions are expected to face physical as well as technical limitations. Thus, there is great interest in new concepts for future computing technologies. One of the areas of exploration is molecular electronics. Due to the vast possibilities of molecular synthesis and the atomic precision of molecule design, there is an interest in understanding the electrical properties of molecules for future nanoelectronic devices. Molecular devices may function as wires, switches, transistors, or sensors, for example.
In this work, we present a novel device to measure the electrical properties of single or very few numbers of molecules trapped in a nanojunction. The design uses advanced reaction engineering principles including atomic layer deposition(ALD) and selective area growth to fabricate molecular junctions with tunable spacing. The excellent growth control(~0.05nm) in ALD allows fabrication of electrodes spaced in the critical range of 1nm to 10nm. Copper is selected for the ALD process as it can be grown selectively on metal seed layers and not on insulating surfaces which is important for minimizing current leakages. In comparison to previous approaches the main advantage of the device design is the cleanliness of the electrode surfaces which is maintained at all times in vacuum. Moreover, the atom migration between the electrodes is prevented by the use of non-coplanar structure which maintains a vacuum space between the electrodes. In addition, the monolithic design alleviates the concerns about the vibrations and thermal expansion of electrodes which is difficult with many approaches. For example, the electrode spacing reduces by less than 0.1nm when the electrodes cool from 200C to 29C.
Successful nanofabrication of monolithic metal-vacuum-metal tunnel junctions has been achieved with demonstrated nanojunctions of 1-2nm. Field emission and metal-vacuum-metal tunneling electrical measurements are used to characterize the electrode properties and electrode spacing in-situ during the ALD growth. The in-situ electrical measurement shows two growth regimes. Initially, the field emission data show a linear drop in voltage as a function of growth cycles for a fixed current. After many cycles, a saturation regime is encountered where the voltage saturates for a fixed precursor cycle time. The self saturation reflects the precursor (~1.5nm in size) transport limited regimes in nanojunctions. The data is modeled using Teague’s code[1] for tunnel junctions which gives a good fit to the experiment with barrier height of 4.5eV, spacing of 1nm and tip radius from 1-100nm. The tunnel junctions are found to be stable in vacuum as well as in air for at least one week.
References:
[1]E.C Teague, Journal of Research of the National Bureau of Standards 1986,91(4),171.
12:45 PM - B5.11
Adhesion of Interfaces in Ultra Thin-Film Transistor Gate Structures.
Ryan Birringer 1 , Ching-Huang Lu 2 , Yoshio Nishi 2 , Steven Hung 3 , Gary Miner 3 , Reinhold Dauskardt 1
1 Department of Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Department of Electrical Engineering, Stanford University, Stanford, California, United States, 3 , Applied Materials Corporation, Sunnyvale, California, United States
Show AbstractThe integration of new materials in front-end device structures of CMOS technologies has introduced a range of ultra-thin films and interfaces with largely unknown adhesive and cohesive properties. Materials include advanced high-k dielectrics required to attain sub-nm equivalent oxide thicknesses and metal inserted poly-silicon gate electrodes that have been proposed to address such issues as poly-silicon gate depletion. In addition, the application of metal bilayer gate electrodes has been shown to exhibit work function tunability. While these innovations are clearly driven by electrical and device performance needs, the mechanical strength, adhesion and cohesive properties of these new materials and interfaces have not been characterized. The film thicknesses in transistor gate applications are also extremely thin, typically ranging from 5 – 40 Å, making quantitative mechanical property measurements more challenging. In the present study we present methods to quantitatively assess interface adhesion between ultra-thin high-k dielectric and gate electrode layers as a function of both layer thickness and annealing conditions. Specific materials include Pt/W and Al/W bilayer gate electrodes on SiO2 dielectric, Ti/Pt bilayer gate electrodes on HfO2-based dielectric, and poly/TiN on HfSiON. We disclose a novel “T-beam” variation of the well know 4-point bend adhesion specimen geometry that allows for greater yield during adhesion testing of these thin-film structures. Adhesion values in the range of ~ 2 – 10 J/m2 are reported and shown to be sensitive to interface chemistry and annealing conditions. Mechanical separation of these interfaces is also shown to allow for improved surface characterization of the gate electrode and high-k layers using angle resolved x-ray photoelectron spectroscopy. In the case of the Ti/Pt/HfO2 structures, a correlation between interface work function and fracture energy is proposed based on mass transport of Ti.
B6: Interconnect Reliability
Session Chairs
Wednesday PM, April 11, 2007
Room 3002 (Moscone West)
2:30 PM - **B6.1
Low-K Dielectrics — Nanostructure and Process Effects on Reliability.
Reinhold Dauskardt 1
1 , Stanford University, Stanford, California, United States
Show AbstractThe successful application of low-k materials has been significantly delayed due to major challenges associated with reliable integration in advanced interconnect structures. Inferior mechanical properties together with debonding and cracking of fragile dielectric films and interfaces has resulted in reduced yield at all levels of device processing including survival through chemical mechanical planarization and subsequent device packaging. Other weak interfaces in interconnect structures have lead to similar challenges particularly for atomically smooth interfaces and ALD processed barrier/Cu interfaces. We review progress in understanding the effect of dielectric materials structure and composition, together with other weak interfaces, on resulting mechanical properties that are important for robust integration. We consider the effects of selected curing processes to optimize the structure and properties of the dielectric, together with the effects of processing environments on defect evolution. Implications for BEOL reliability, integration of new materials, and process yield are discussed.
3:00 PM - **B6.2
Cu Migration-induced Dielectric Breakdown Mechanism During Time Dependent Dielectric Breakdown (TDDB) Test.
Young-Chang Joo 1 , Sang-Soo Hwang 1 , Sung-Yup Jung 1
1 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Show AbstractCu and low-k dielectrics are widely used for interconnects for advanced integrated circuits to reduce RC delays. Unlike the Al/SiO2 system, the Cu ions can migrate into dielectrics under a bias-temperature stress condition and cause dielectric failure. Dielectric breakdown occurs by formation of a conductive path between the anode and the cathode. The conductive path can be composed of metal ions that have migrated from the electrode (extrinsic failure mechanism) or the broken-bonds that are induced by an applied electric field (intrinsic failure mechanism). In order to understand the mechanism for the Cu-migration-induced dielectric breakdown and the relative contribution between extrinsic and intrinsic failure mechanisms, we have conducted experiments and simulations in a model system of a metal-insulator-semiconductor (MIS) structure with various metal electrodes and dielectrics. The Cu electrode was used for the extrinsic failure system and the Al (for SiO2) and Ta (for low-k dielectrics) electrodes were used for the intrinsic failure systems. For the dielectrics, SiO2, spin-on dielectrics, and CVD low-k dielectrics were examined and compared. First, the time dependent dielectric breakdown (TDDB) tests were conducted for Cu/SiO2 and Cu/low-k systems to determine the lifetime, activation energy, and jumping distance of Cu migration into the dielectric. Then these results were compared with a 1-D finite difference method (FDM) simulation which accounts for the space charge effect of the migrated Cu ions. The lifetime behaviors at various stress conditions were simulated and discussed. Secondly, the change in mechanisms of the electron conduction in the intrinsic and the extrinsic systems were evaluated through voltage ramping dielectric breakdown (VRDB) tests. In order to study the effect of the migrated metal ions into dielectric on the leakage current conduction mechanisms, some of the samples were subjected to the BTS prior to the VRDB tests. For SiO2 samples with no Cu in the dielectrics, the leakage current is passed only by the Fowler-Nordheim (F-N) tunneling mechanisms. However, as Cu migrated into SiO2, the electric current by Poole-Frenkel (PF) mechanism was observed. Because the migrated Cu ions play the role of PF trap site, the PF currents increase with time. Through FDM simulations, the change in leakage currents during TDDB tests were simulated by considering the increase in Cu ions that act as PF trap sites. For the Cu/low-k system, PF conduction mechanism has been observed prior to Cu ion migration. For the intrinsic system (Al/SiO2 or Ta/low-k), no significant change in conduction mechanisms was observed. By comparing the experimental results and simulations of the extrinsic and the intrinsic systems, the dielectric failure mechanisms of the Cu/low-k damascene interconnects under bias-temperature stress conditions are discussed
3:30 PM - B6.3
Charging and Aging Effects in Porous ULK Dielectrics.
Cyril Guedj 1 , Eugenie Martinez 1 , Gregory Imbert 2
1 , LETI, Grenoble France, 2 , STMicroelectronics, Crolles France
Show AbstractFuture generations of integrated circuits require ultra-low-k (ULK) materials to increase device speed, reduce power and heat dissipation, and reduce interline cross talk. In terms of reliability, the evolution from SiO2 to porous SiCOH insulators with lower dielectric constant (k<2.6) brings new challenges. Porous ULK materials usually have a complex nanostructure, for instance involving siloxane or silicon oxycarbide -(SiOxCy)- network with dangling bonds passivated by hydrogen atoms. The reduction of k can be achieved by producing nanovoids around methyl (CH3) groups to reduce the material density. This nanoporous material is usually sensitive to moisture, especially in case of open porosity, but little is known about the detailed intrinsic material evolution during bias and thermal stress. Recent studies have demonstrated that pores could act as quantum “antidots”, inherently leading to charge trapping [1], but this effect has not been thoroughly investigated yet in back-end dielectrics. This presentation is focused on charging and aging effects in porous ULK dielectrics designed for CMOS 65 nm node.In this study, the as-deposited SiOCH has 26 % microporosity consisting of pores with a diameter of 1.2 nm resulting in a k value about 2.5. This dielectric is integrated into copper single damascene comb-comb test structures with a dielectric spacing of about 65 nm. The thermal evolution of leakage electrical field versus injected current displays several regimes, depending on the maximum bias reached. When the stress is increased, the progressive contribution of relaxation effects and charging effects is observed up to irreversible aging degradation. The total electrical energy needed to reach the irreversible threshold critically depends on temperature. The modelling of the conduction mechanism is satisfactorily explained by variable-range hopping at low fields, and Poole-Frenkel (PF) conduction at higher fields, in agreement with previous studies on different dielectric material. [2] The conduction mechanism gradually evolves during bias-thermal stress, and the charging regime is associated with an apparent decrease in PF defect density but little change in PF dynamic permittivity. When the material can no longer withstand any additional charging, the irreversible degradation start to occur, and the PF defectivity and permittivity start to gradually increase. Novel bias-temperature stress diagrams for charging and aging regimes are henceforward obtained. Auger and XPS measurements are used to interpret these results in term of current-induced nanostructural changes. The impact of these dynamic effects on dielectric lifetime predictions will be outlined. [1] J. Planelles* and J. L. Movilla, Phys. Rev. B 73, 235350 (2006)[2] C. Guedj et al., Proc. MAM conference (2005)AcknowledgementsThis work has been carried out in the frame of the Alliance and LETI collaboration, and is partially supported by the IST 026828 Pullnano program.
3:45 PM - B6.4
Influence of Interfacial Delamination on Channel Cracking of Brittle Thin Films.
Rui Huang 1 , Yaoyu Pang 1
1 Department of Aerospace Engineering and Engineering Mechanics, University of Texas at Austin, Austin, Texas, United States
Show AbstractChanneling cracks in low-k dielectrics have been observed to be a key reliability issue for advanced interconnects. Previous studies have shown that the driving force for channel cracks (i.e., energy release rate) depends on the constraint effect of surrounding layers. For a brittle thin film on an elastic substrate, the driving force increases for increasingly compliant substrates. Furthermore, the effect of constraint can be partly lost as the substrate deforms plastically or creeps. More recent studies have focused on effects of stacked buffer layers. However, in most studies, the interfaces between the film and the substrate or buffer layers are assumed to remain bonded during channel cracking. This contradicts with many experimental observations, which showed concomitant interfacial delamination as channeling cracks grow in the film. The stress concentration at the root of a channel crack drives interfacial delamination. In turn, the constraint on the channeling crack is partly lost due to delamination. In this paper, we study the coupled process of channel cracking and interfacial delamination by using a cohesive interface model together with a finite element analysis of channel cracking. We show that the total energy release rate for channel cracking increases when the interfacial delamination occurs. Furthermore, the resistance to channel cracking now includes contributions from both the cohesive toughness of the film and the adhesive toughness of the interface. Together, a nontrivial influence of the interfacial properties on channel cracking is revealed. The implication of this result on cracking of low-k dielectrics in integrated interconnects will be discussed.
4:30 PM - **B6.5
Distribution of Plasma Damage in Low-k Film and Fine Trench Structure.
Shinichi Ogawa 1 , Yuji Otsuka 2 , Miyoko Shimada 1 , Hirofumi Seki 2 , Hideki Hashimoto 2
1 , Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan, 2 , Toray Research Center, Inc., Ohtsu, Shiga, Japan
Show AbstractPorous low-k films have been eagerly developed, however plasma process induced “damages” have been one of severe problems in Cu / Low-k interconnects fabrication. “Damage” here means deterioration of film properties affected by changes of film structures. Damages induced by plasma processes such as dry etch and ash which decompose Si-CH3 and C-H bonds in low-k films have been widely known to cause moisture absorption, and consequently dielectric constant increases. A low damage ash technique (1) has been proposed and damages in the low-k films were characterized using several methods such as FTIR and wet etch.In this paper, structural changes in low-k films and trench structures of 200 nm line and space after ash have been investigated by a STEM / valence electron EELS (V-EELS) technique of nm space resolution (2), (3) correlated with a micro-beam IR method with a novel gradient shaving preparation (GSP) for characterization of damages in depth direction (4). Ash processes were performed using O2, NH3, and He/H2 plasma. The GSP micro-beam (10 um diameter) IR method of 20 nm resolution in depth direction results showed that Si-CH3 bond decreased gradually from a depth of 100 nm up to the surface area after the NH3 ash, whereas, after the O2 ash, it showed an extremely low level of concentration over the entire depth of 250nm, on the other hand, after the He/H2 ash, no change in the concentration was observed. A 2-D distribution of dielectric properties such as complex dielectric functions in the 200 nm line and space low-k trench structures have been characterized by V-EELS / STEM. Kramers-Kronig analysis was carried out to estimate complex dielectric functions from the V-EELS spectra. The results derived from the V-EELS spectra of several points of 1 nm diameter showed that the dielectric constants in a 100 nm space low-k trench pattern increased gradually from a center area to a side wall area, especially in the vicinity of the side wall. Even in the sample with He/H2 ash in which the micro-beam IR method did not show any change, the V-EELS showed the change in dielectric properties.The GSP micro-beam IR and V-EELS are a unique technique to characterize distributions of damages in the films and fine line structures, and it clearly showed the change or distribution of structures and dielectric properties in there.(1) A.Matsushita et al., in Proc. 2003IITC, p.147 (2) M.Shimada et al, in Proc. 2005IITC, p.88 (3) Y.Otsuka et al, in Proc. SSDM 2006, p.156 (4) H.Seki et al., in Proc. AMC2004, p.34
5:00 PM - B6.6
Improved Electromigration Lifetime for Copper Interconnects using Tantalum Implant.
Jeff Gambino 1 , Tim Sullivan 1 , Jason Gill 2 , Fen Chen 1 , Steve Mongeon 1 , Ed Adams 1 , Jay Burnham 1 , Phil Pokrinchak 1 , Ken Rodbell 3
1 , IBM Microelectronics, Essex Junction, Vermont, United States, 2 , IBM Microelectronics, Hopewell Junction, New York, United States, 3 , IBM Thomas J. Watson Reseach Center, Yorktown Heights, New York, United States
Show Abstract Copper interconnects have gained wide acceptance in the microelectronics industry due to improved resistivity and reliability compared to Al interconnects. However, as devices become smaller, the current density through the interconnects increases, requiring a longer electromigration lifetime. Refractory metal capping processes can significantly improve the electromigration lifetime of Cu interconnects. However, these processes are difficult to implement, due to additional cost, increased resistivity of the Cu wires, or reduced reliability of the dielectric. In this study, a novel method is explored for improving the electromigration lifetime of Cu wires, using Ta implantation into Cu. Samples were fabricated using a 0.13 um CMOS process with via-first dual damascene Cu in an FTEOS dielectric. After M2 CMP, the wafers were capped with a thin SiN layer. Tantalum was then implanted into some of the wafers. After the Ta implant, all wafers were capped with an additional SiN layer, then standard processing was used to make V2 vias and M3 metal. For the highest Ta implant dose, the electromigration lifetime is improved by over 3X, with a minimal increase in wire resistance. An increase in lifetime is achieved, even for an average surface concentration of Ta on the order of 0.1 atm%. SIMS analysis shows that the Ta is located at the surface of the Cu, within 10 to 20 nm of the SiN capping layer. Unfortunately, the line-to-line leakage at high voltages (> 5V) also increases with the Ta implant, with higher leakage at higher Ta concentrations. The increase in leakage may limit the application of this method.
5:15 PM - B6.7
Plasticity-inducing Texture in Cu Interconnects: Correlations and Implications for Electromigration Lifetime Assessment.
Arief Budiman 1 , Christine Hau-Riege 2 , Amit Marathe 2 , Paul Besser 3 , Young-Chang Joo 4 , Nobumichi Tamura 5 , Jamshed Patel 1 5 , William Nix 1
1 Materials Science & Engineering, Stanford University, Stanford, California, United States, 2 Technology & Reliability Development (TRD), Advanced Micro Devices, Inc., Sunnyvale, CA, California, United States, 3 Technology Research Group (TRG), Advanced Micro Devices, Inc., Sunnyvale, CA, California, United States, 4 Materials Science & Engineering, Seoul National University (SNU), Seoul Korea (the Republic of), 5 Advanced Light Source (ALS), Ernest Orlando Lawrence Berkeley National Laboratory (LBNL), Berkeley, California, United States
Show AbstractPlastic deformation has been observed in damascene Cu interconnect test structures during an in-situ electromigration experiment and before the onset of visible microstructural damage (ie. voiding). We show here, using a synchrotron technique of white beam X-ray microdiffraction, that the extent of this electromigration-induced plasticity is dependent on the texture of the Cu grains in the line. In lines with strong <111> textures, the extent of plastic deformation is found to be relatively large compared to our previous plasticity results for another set of Cu lines with weak textures (Budiman et al., APL 88, 233515, 2006). This is consistent with our earlier observation that the occurrence of plastic deformation in a given grain can be strongly correlated with the availability of a <112> direction of the crystal in the proximity of the direction of the electron flow in the line (within an angle of 10 degrees). In <111> out-of-plane oriented grains in a damascene interconnect scheme, the crystal plane facing the sidewall tends to be a {110} plane, so as to minimize surface energy (Besser et al., J. Elec. Matls. 30, No. 4, p. 320, 2001; Paik et al., J. Elec. Matls. 33, No. 1, p. 48, 2004). Therefore, there is a high probability for having <111> grains with <112> directions nearly parallel to the direction of electron flow. However, as we establish this texture-plasticity correlation, the effect of plasticity on the Cu EM degradation process remains ambiguous. We have models and preliminary observations suggesting that the effect of plasticity can be both beneficial as well as damaging to EM, perhaps even at the same time. In this manuscript, we describe how these considerations may affect EM lifetime assessment methodologies.
5:30 PM - B6.8
Non-uniform Interconnect Geometries for Improved Electrical Conductance.
Daniel Josell 1
1 Metallurgy Division, NIST, Gaithersburg, Maryland, United States
Show AbstractWhen designing electrical conduction paths it is almost instinctive to say that a line of uniform width set to the maximum permissible value is the best option given a fixed height and length: thinner regions would contribute higher associated resistance as resistance scales inverse to the area of the wire cross-section. Nonetheless, when other factors are considered, uniform line width need not be the optimal solution. Specifically, I will discuss the case of a wire with a bamboo grain structure that, because of electron scattering from the grain boundaries across the wire, exhibits increased electrical resistance. I will describe how systematic variations of the wire width along the length of the wire (defined by a splay angle between the wire direction and the local sidewall tangent and a repeat length for the pattern) might be used to drive the grain boundary spacing up, and to thus decrease the grain boundary scattering. I will present an analysis that accounts for both the decreased grain boundary scattering term (analyzed using the model of Shatzkes-Miyada) and the impact of the varying width itself using the standard inverse-area formulation. To permit both relevance and meaningful comparison I evaluate average wire dimensions below 100 nm and compare the results to values for straight-edged wires arranged with equivalent pitch and with equivalent minimum thickness of dielectric normal to the wires. Results are presented for a wire geometry that resembles an overlapping series of diamonds (i.e., the sidewalls zig-zagging in and out, with the spacing of the opposite sides of the wire from the midplane being equivalent along the wire length) under the assumption that minimization of the grain boundary free energy drives grain boundaries toward the positions along the wire that have minimum width. Predictions are made for different splay angles and pattern repeat lengths, including an analysis of the impact of periodic roughness that would create local minima that could trap the migrating grain boundaries; substantial improvement over typical stagnated bamboo structures with grain boundary spacing similar to wire width is found to be possible. Values for grain boundary reflectivity are placed in context of the literature on size effects in sub-100 nm wide copper and silver interconnects and values of sidewall roughness are referenced to the International Technology Roadmap for Semiconductors.
5:45 PM - B6.9
The Influence Of Microstructure On Electromigration And Stress Induced Void Nucleation And Evolution In Interconnect Structures.
Allan Bower 1 , Paul Ho 3 , Sadasivan Shankar 2
1 Division of Engineering, Brown University, Providence, Rhode Island, United States, 3 Laboratory for Interconnect and Packaging, University of Texas at Austin, Austin, Texas, United States, 2 Design and Technology Solutions, Intel Corporation, Santa Clara, California, United States
Show AbstractWe describe a fundamental analysis of electromigration-induced void nucleation, growth, and evolution in copper interconnects. Our analysis includes both computational and experimental studies to describe the effect of microstructures on interconnect reliability. The computations include a detailed description of the microstructure of polycrystalline interconnects, and account in detail for the effects of grain boundaries and interfaces in the line, as well elastic deformation and electric current flow within the grains themselves. In addition, the simulations are used to predict the influence of line geometry, microstructure, properties, and loading conditions on electromigration induced void nucleation and growth in representative interconnect structures. Nucleation sites for voids are identified, and the subsequent evolution and growth of the voids are simulated. Grain boundaries are found to play an important role in trapping voids at critical locations in the structure. The predicted failure sites and void morphologies are shown to be in good agreement with experimental observations.
B7: Poster Session: Interconnect Reliability and Packaging
Session Chairs
Thursday AM, April 12, 2007
Salon Level (Marriott)
9:00 PM - B7.10
Interfacial Behavior between Au Deposits and Electronic Substrates by Utilizing Au Nanoparicle Suspension
Tzu Hsuan Kao 1 , Jenn Ming Song 2 , In Gann Chen 1 , Teng Yuan Dong Dong 3
1 Department of Materials Science and Engineering, National Cheng Kung University, Tainan Taiwan, 2 Department of Materials Science and Engineering, National Dong Hwa University, Hualien Taiwan, 3 Department of Chemistry, National Sun Yat-Sen University, Kaohsiung Taiwan
Show AbstractMetallic nanoparticle suspensions could be applied to the manufacturing of desired conducting patterns by using a proper deposition technique, e.g., drop-on-demand ink jet printing. In this study, suspensions with thiol-stablibized gold nanoparticles were prepared and spin-coated onto several metallic substrates (Cu, Ni, Ag, Al, Zn and Sn), which are extensively adopted in electronic industry, and then thermally processed at a low curing temperature (300oC). Experimental results show that the morphology and the degree of continuity of the films on the Cu, Ag and Ni substrates were much better than those on the Zn, Al and Sn substrates. Among the substrates jointed well with Au films, the adhesion strength between the Au/Ni was stronger than the Au/Cu, in turn greater than that between the Au/Ag. Specific manifestation of interdiffusion and alloying behavior were evidenced via XPS depth profiling. Stoichiometric intermetallic phases were detected at both the Au/Cu and Au/Ni interfaces, while a nonstoichiometric reaction layer, a miscible solid solution, was found to emerge at the interface between Au/Ag. This may explain the difference in adhesion strength. Further discussion on chemical shift upon alloying reaction between Au nanoparticles and the substrates will also be presented. This research is supported by National Science Council under the contract of No. NSC95-2120-M-006-003
9:00 PM - B7.11
Effects of Bonding Force and Nanometer-Scale Surface Roughness on Cu-Cu Thermocompression Bonds
Hoi Liong Leong 1 4 , Chee Lip Gan 1 4 , Carl Thompson 3 4 , Kin Leong Pey 2 4 , Hongyu Li 5
1 School of Material Science and Engineering, Nanyang Technological University, Singapore Singapore, 4 , Singapore-MIT Alliance, Singapore Singapore, 3 Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 2 School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore Singapore, 5 , Institute of Microelectronics, Singapore Singapore
Show AbstractWafers with blanket or Damascene-patterned Cu bonding layers were thermo-compression bonded and dice-sawed. The dicing yield is taken as an indicator of the bonding quality of the bonded wafers. It was found that the dicing yield did not scale simply with the apparent applied pressure, but was also significantly affected by the pre-bonding nano-scale surface roughness of the bond layers, as characterized using atomic force microscopy. The nano-scale surface roughness is characterized in terms of asperity curvature radius, standard deviation of asperity heights and density of asperities. These parameters, together with the applied load and apparent contact area, are being applied to contact theory for estimating the true contact area, which was found to be proportional to the dicing yield. The true contact area during bonding, and therefore the dice yield and bond strength, depends on the nano-scale elastic or elasto-plastic deformation that occurs during bonding which in turn, depends on the nano-scale surface roughness. Results showed that the applied load as well as the nano-scale surface roughness, are equally critical factors in determining the strength of metal-to-metal thermocompression bonds.
9:00 PM - B7.12
Effects of Ti Content in Mo-Ti Glue Layer on the Interfacial Property of Cu-Mo Alloy and Cu-Si3N4 in Si3-N4/Cu/Mo-Ti Alloy/SiO2 Structure.
Taeki Hong 1 , Chang-Oh Jeong 2 , JeHun Lee 2 , Yang Ho Bae 2 , Jaegab Lee 1
1 School of Advanced Materials Engineering, Kookmin University, Seoul Korea (the Republic of), 2 Active Matrix Liquid Crystal Display Division, R&D Team, Samsung Electronics Co., Ltd, Yongin Korea (the Republic of)
Show Abstract9:00 PM - B7.13
Reliability Evaluation of a Biocompatible Flip Chip Under Bump Metallization Stack for Electrode Arrays used for Neuroprothetics.
Rajmohan Bhandari 1 , Sandeep Negi 1 , Michael Toepper 2 , Matthias Klein 3 , Hermann Opermann 3 , Richard Normann 4 , Florian Solzbacher 1 4 5
1 ECE, University of Utah, Salt Lake City, Utah, United States, 2 High Density interconnect & Wafer Level Packaging, Fraunhofer Institute for Reliability and Micro Integration IZM, Berlin Germany, 3 Module Integration & Board Interconnection Technologies, Fraunhofer Institute for Reliability and Micro Integration IZM, Berlin Germany, 4 Bioengineering, University of Utah, Salt Lake City, Utah, United States, 5 Material Science, University of Utah, Salt Lake City, Utah, United States
Show Abstract9:00 PM - B7.14
Wafer Level Chip Size Packaging Technology for Bulk Acoustic Wave Filters.
Hajime Yamada 1 , Naoko Aizawa 1 , Hiroyuki Fujino 1 , Yoshihiro Koshido 1 , Yukio Yoshino 1 , Takahiro Makino 1
1 , Murata Manufacturing Co.,Ltd., Yasu-shi Japan
Show AbstractWafer level chip size packages (WL-CSP) have been successfully fabricated for bulk acoustic wave (BAW) filters. WL-CSP was completed at the wafer level prior to dicing. Two silicon wafers were used as a die and a lid for chip size packaging. Both device and lid wafers had the same expansion coefficient and the package was strong enough to withstand the thermal stress. The BAW filter was hermetically packaged at the wafer level and sealed with copper-tin intermetallic bonding. Via holes were formed by reactive ion etching (RIE) and filled by copper electroplating. The package was then thinned by grinding after bonding.Copper-tin bonding was performed as a hermetically sealed cavity. The lid wafer contained metal seal made from tin/copper multiplayer films. The device wafer contained copper seal same as the lid wafer. The metal seal rings were formed by electron beam evaporation and lift-off processes. The lid wafer was aligned to the device wafer, so the lid and device wafers were brought into contact with pressure at about 8 MPa, and heated to 300 degrees C in a nitrogen atmosphere. No void was observed around the bonding interface between the copper and copper-tin compounds by using a cross-sectional scanning electron microscope (SEM). The composition analysis using a auger electron spectroscopy (AES) indicated that the intermetallic compound at the bonding interface was in the Cu3Sn phase. However tin melts at 230 degrees C, the melting point of Cu3Sn was raised to 600 degrees C. The bonding was strong enough to withstand the thermal stress in the fabrication processes. A cavity was formed by the tin-copper intermetallic bonding. The leakage rate was about 10-9 Pa*m3/sec.The wafer thinning process was performed by grinding after bonding the lid and device wafer. A wafer with a thickness less than 200 micrometers can be broken easily in the handling and bonding processes. The lid and device wafers with a thickness of 300 micrometers were bonded and the bonded wafers were reduced from 600 micrometers to 180 micrometers by grinding the top and bottom sides. There were no cracks in the wafer thinned by grinding after bonding the lid and device wafers. We have applied WL-CSP to a 2 GHz BAW filter. The 2 GHz CSP-BAW filter has a 75 MHz bandwidth at 2.4 dB insertion loss without degradation in WL-CSP processes. We succeeded to produce a CSP-BAW filter with a hermetically sealed cavity, which was 840 micrometers squared and 180 micrometers in height.
9:00 PM - B7.15
Chip-on-glass Process Using Cu-Sn Mushroom Bumps Fabricated by Electrodeposition
Sun-Hee Park 1 , Kwang-Yong Lee 1 , Young-Ho Kim 2 , Tae-Sung Oh 1
1 Materials Science and Engineering, Hongik University, Seoul Korea (the Republic of), 2 Materials Science and Engineering, Hanyang University, Seoul Korea (the Republic of)
Show AbstractChip-on-glass (COG) technologies using flip chip bonding have been extensively investigated to attach IC chip directly on the glass substrate of the liquid crystal display (LCD) panel. COG technologies can accommodate high density and fine pitch interconnection between LCD panel and driver IC, reduce the interconnection distance, and make the LCD devices thinner, lighter, and smaller. Recently, COG bonding using non-conductive adhesive (NCA) has been proposed to overcome disadvantages of the COG process using anisotropic conducting film (ACF) for fine pitch applications. In COG process using NCA, prevention of NCA entrapment at the bonded chip/pad interface is of great importance to ensure the low contact resistance of the joints. Adoption of mushroom-type bumps instead of planar bumps may be a good solution to prevent the NCA entrapment. Surface smoothness and hardness of the mushroom bump may affect the plastic deformation behavior at the bonded interface and as a result the contact resistance of the joint. In this study, Cu-Sn mushroom bumps of 25um pitch were fabricated by electrodepositing Cu mushroom bump and then capping a thin layer of Sn on the top surface of a Cu mushroom bump successively. Cu-Sn mushroom bumps were held at 250C for 30∼120 sec to reflow the Sn cap for surface smoothness. Cu-Sn intermetallic compound formation behavior was characterized as a function of the Sn cap thickness and the reflow time. NCA entrapment percentage and the contact resistance were measured and correlated with the Sn cap thickness and the reflow time.
9:00 PM - B7.16
Improvement of LDI BUMP Stripping Process by Development of Room Temperature PR Stripper.
Dong-Min Kang 1 , Young- Sam Lim 1 , Hyun-Joon Kim 1 , Dong Chan Bae 2 , Young- Nam Kim 1 , Young Ho Kim 2 , Tae Sung Kim 1
1 Manufacturing Technology Team 1, Samsung Electronics, Yongin-City, Gyeonggi-Do, Korea (the Republic of), 2 Bump Section , Samsung Electronics, Yongin-City, Gyeonggi-Do, Korea (the Republic of)
Show Abstract9:00 PM - B7.17
Fatigue of Damascene Copper Lines under AC Loading.
Stephane Moreau 1 , Sylvain Maitrejean 1 , Gerard Passemard 2
1 D2NT/LBE, CEA-LETI, Grenoble France, 2 , STMicroelectronics, Crolles France
Show Abstract9:00 PM - B7.18
Mechanical Stability of Cu/low-k Interconnect Stacks: Measurement of Local Modulus and Adhesion.
Anand Vairagar 1 , H. Geisler 1 , D. Chumakov 1 , C. Zhai 2 , E. Zschech 1
1 , AMD Saxony LLC & Co. KG., Dresden Germany, 2 , Advanced Micro Devices, Sunnyvale, California, United States
Show Abstract9:00 PM - B7.2
Surface Modification of Polycrystalline 3C-SiC Thin Films for Low Contact Resistivity Ohmic Contacts of Harsh Environment M/NEMS Applications
Gwiy Chung 1 , Chang-Min Ohn 1 , Ki-Bong Han 1
1 School of Electrical Enginnering, University of Ulsan, Ulsan Korea (the Republic of)
Show Abstract9:00 PM - B7.3
Stress Induced Grain Structure Evolution in Copper Interconnects
Daniel Bentz 1 , Max Bloomfield 1 , Timothy Cale 1
1 Focus Center – New York, Rensselaer: Interconnections for Hyperintegration, Rensselaer Polytechnic Institute, Troy, New York, United States
Show Abstract We discuss mechanical reliability issues with Cu interconnects and 3DICs [1]. We have shown that inter-wafer via structures may be susceptible to failure due to CTE mismatches between Cu and surrounding materials, particularly the BCB used as a wafer bonding agent [2,3]. By comparing the computed stresses in the Cu to the Hall-Petch correlation of yield stress to grain size [4], we concluded that inter-wafer vias may fail depending on the BCB thickness, via pitch, and via diameter.
The high stresses computed in the Cu at the BCB layer motivates further examination of the failure mechanisms of the via structure. In materials such as Cu, grain structure can have a large impact on the mechanical characteristics of films [5]. Young’s modulus for single crystal Cu is 2.9 times as large in <111> directions as it is in <100> directions [6]. As the dimensions of the interconnects and vias are of the same order as the grain sizes [7], grain structure is particularly important.
We study the evolution of 3D grain structures using energy based modeling. We use PLENTE [8,9] to represent and track the motion and topology changes of grain boundaries, and a commercial finite element package (Comsol Multiphysics or CM [10]) to computes stress distributions caused by CTE mismatches during temperature changes. We then compute grain boundary speeds from differences in strain energy between grains [5,11].
As one example application of this 3D modeling approach, we consider thermally induced grain boundary evolution in a segment of a polycrystalline Cu line encapsulated in an oxide layer on a Si wafer. A grain-boundary-fitted, finite element mesh is generated by PLENTE and exported to CM. Thermally induced stresses and strain energies are computed by CM. Grain boundary speeds are then sent back to PLENTE where the grain structure is updated. At room temperature, grain boundary displacements of ~100 nm are observed on the time frame of hours. Other examples include vias in 3DICs of different design. We compare our results with available experimental evidence.
[1] J.-Q. Lu, et al., in Proc. of 2002 IITC, 2002 (IEEE), p. 78.
[2] J. Zhang, et al., Microelec. Eng. 82, 534 (2005).
[3] D. N. Bentz, et al., in Proc. 22nd VMIC, IMIC, 2005, p. 89.
[4] Y. Xiang, et al., in Thin Films - Stresses and Mechanical Properties X, 2004, MRS, p. 417.
[5] C. V. Thompson, Ann. Rev. Mat. Sci. 30, 159 (2000).
[6] G. Simmons and H. Wang, Single crystal elastic constants and calculated aggregate properties: a handbook, M.I.T. Press, 1971.
[7] M. Nygards, Mech. Mat. 35, 1049 (2003).
[8] M. O. Bloomfield, et al., Phil. Mag. 83, 3549 (2003).
[9] M. O. Bloomfield and T. S. Cale, Microelec. Eng. 76, 195 (2004).
[10] Comsol Multiphysics 3.2, Comsol, Inc. http://www.comsol.com, 2005.
[11] R. Carel, et al., Acta Mat. 44, 2479 (1996).
9:00 PM - B7.4
Electromigration Study on Sn Capped Air-gap Cu Damascenes Structure
Chih-Kai Hsu 1 , Ming-Chang Lin 1 , Chih-Chieh Hsu 1 , Fon-Shan Huang 1
1 Electronics engineering, National Tsing Hua University, Hsinchu Taiwan
Show Abstract The lifetime of interconnect Cu/SiLK is affected by the Cu surface diffusion. Recent research reveals that the metal cap can highly improve the electromigration (EM) characteristics. M. Y. Yan et al [1] fabricated Sn capped dual-damascene interconnects by immersion Sn process. EM tests of Sn capped and SiNx capped samples were performed at 300 °C with a current density 3.6 MA/cm2. For Sn capped sample, lifetime was found to be increased by close to one order of magnitude. X-ray analysis and high resolution TEM image showed existence of the entire ε-Cu3Sn intermetallic compound overlayer. A stronger chemical bond in the form of intermetallic compounds on Cu surface may be effective in retarding Cu surface diffusion. In order to investigate EM mechanism at temperature below 200 °C to avoid the annealing effect on Cu line, the Sn capped and SiNx capped Cu/Ta/SiO2 air-gap damascene structure was developed in this work. Electroless plating Sn was deposited on Cu interconnects. First, air-gap damascence structure was fabricated. Thermal oxide with thickness 550 nm was grown on Si substrate. Diluted HSQ was spin coated (thickness ~350 nm) on SiO2 surface and prebaked at temperature 350 °C for 3 min. Its partially network-like structure could not only endure CMP pressure but also serve an adequate sacrificial layer for air gap formation. The partially network-like HSQ can be easily removed by BOE solution treatment from the HSQ/SiO2 interface. Trench with width/space = 0.6μm/0.6μm and height 380 nm was formed by RIE. Cu/Ta was deposited by PVD and electroplating. The samples were then annealed in N2 ambient at temperature 200 °C for 10 minutes. After chemical mechanical polish (CMP) process was carried out, sacrificial HSQ layer was peeled from the HSQ/SiO2 interface by BOE treatment. Finally, Sn and SiNx capping layers were deposited by immersion plating and PECVD, respectively. Sequently, EM tests were performed on Sn capped sample at various temperatures 150, 175 and 200 °C with a current density 4 MA/cm2. The electromigration lifetime of Sn capped air-gap Cu interconnects with 175 °C stressed was observed about 4.5 times larger than that of SiNx capped sample. Furthermore, the activation energy of EM for Sn capped sample determined by above measurement was found to be 1.07 eV. It is larger than 0.84eV obtained from SiNx capped sample. After EM tests, SEM shows that the voids were observed underneath the capping layer for Sn capped sample. For SiNx capped sample, SEM image revealed voids formed in Cu lines. Meanwhile, the composition of Sn capping layer was analyzed by AES depth profile and GIAXRD for samples of various stressed temperature. The above composition results are correlated with electrical measurement at temperature below 200 °C.[1] M. Y. Yan, J. O. Suh, F. Ren, K. N. Tu, A. V. Vairagar, S. G. Mhaisalkar, Ahila Krishnamoorthy, Appl. Phys. Lett. 87, 211103 (2005)
9:00 PM - B7.5
Solid –State Impedance Spectroscopy for Studying Copper Ionization in Porous low-k Interconnects in Integrated Circuits.
Ravi Achanta 1
1 , Rensselaer Polytechnic Institute, Troy, New York, United States
Show Abstract9:00 PM - B7.6
Polysilicon And Metallization Local Stress Measurement In Industrial Processes
Moustafa Kasbari 1 2 , Sylvain Blayac 1 , Christian Rivero 2 , Florian Cacho 3 , Ola Bostrom 2 , Roland Fortunier 1
1 PS2, CMP-GC, Gardanne France, 2 , STMicroelectronics, Rousset France, 3 , STMicroelectronics, Crolles France
Show AbstractDuring semiconductors processing mechanical stress appeared in thin films and in the substrate. The growing integration of the modern circuits induced high number of interconnects levels and complex designs. This, leads yield and reliability issues associated with mechanical stress phenomena.The measurement of the local mechanical stress induced in the materials used for the fabrication of semiconductor devices becomes essential as the industry migrates to 300 mm wafers. However, it is difficult to measure local stresses developed in thin films, especially in an industrial environment. For instance, the mechanical stress induced in the gate can not be easily measured because polysilicon is naturally deposited on the both sides of the wafer (LP-CVD) which excluded curvature methods or imposed a supplementary “back etch” step. In this study, we propose a solution to monitor stress in polysilicon thin films deposed during standard industrial processes.We developed, on the basis of a previous work, a sensor based on a rotating beam. The structure consists in patterning a polysilison cross which is deposited over a sacrificial oxide. The MEMS is composed of two expansion arms anchoring a pointer. When the polysilicon cross is released from the underlying oxide, the stress in the arms is relaxed. This, manifested itself by the rotation of the pointer. The measure of the rotation angle gives the residual stress level in the polysilicon before etching.The sensor was designed and calibrated to be used in a standard industrial 130nm CMOS technology. It permitted to monitor the effect of process parameters change on stress generation in polysilicon thin films. A Finite Elements Model was built in order to perform the accuracy of the sensor and to explore plasticity phenomenon at the anchor points. Then, the sensor was integrated in two different technologies and results were compared. In addition, the MEMS were integrated in interconnects levels which gives a direct value of the stress in the copper lines. The polysilicon presented a compressive stress state whereas the copper lines show a tensile stress state. Finally, the results were compared to values obtained by curvature methods (full wafer deposition plus “back etch” step) and Finite Elements Analysis.We have shown that the test structures we developed are adapted to a standard industrial process. They are able to discriminate compressive and tensile stress in materials. They also allow a correlation between the stress levels and the process parameters which will ensure a data collecting for process control.
9:00 PM - B7.7
The Effect of Capping Layer and Post CMP Surface Treatments on Adhesion Between Cu and Capping Layer.
Seol-Min Yi 1 , Cheonman Shim 2 , Han-Choon Lee 2 , Jae-Won Han 2 , Kee-Ho Kim 2 , Young-Chang Joo 1
1 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 , Dongbu electronics, Eumsung, Chungbuk, Korea (the Republic of)
Show AbstractWith progressive miniaturization of advanced integrated circuits fabricated using the Cu damascene process, aggressive current density is applied to the interconnects therein. The increasing current density makes the electromigration to be one of great reliability problems. The electromigration reliability of Cu interconnects is likely to depend heavily on the fabrication processes, since the dominant path of mass transport is along either surface or interface, e.g. between Cu and capping layer. Therefore, mechanical as well as electromigration reliability can be estimated in terms of adhesion between Cu and capping layer. We have studied the adhesion between Cu and capping layer by using the sandwiched structure four-point bending (SS4PB) method. Different types of capping layer materials and various surface treatment methods after chemical-mechanical polishing (CMP) process were investigated. For capping layer materials, SiC and SiN were compared. For the post-CMP surface treatment methods, NH3 plasma, He plasma, N2 plasma, H2 plasma, dilute HF, chemical stripper named NE14 (mixture of dimethylacetamide and NH4F), and annealing at 350oC in H2 ambient were studied. The adhesion strength between SiN and Cu was about twice of that between SiC and Cu. The adhesion strength increases when the surface was cleaned by NE14 while He plasma cleaning makes adhesion decrease in comparison with no treatment. To study the role of each cleaning or treatment method, the interfaces were analyzed by AES and XPS. It was found that the amount of residual oxygen on the interface plays an important role in adhesion strength.
9:00 PM - B7.8
Mean Stress Effect on Fatigue Behavior of Thin Copper Foil for Electronic Components
Seungwoo Han 1 , Gi-Jeong Seo 1 , Wandoo Kim 1 , Hyunwoo Lee 2
1 Nano-Mechanical Systems Reseach Center, KIMM, Daejeon Korea (the Republic of), 2 Mechanical Engineering, Pusan National University, Pusan Korea (the Republic of)
Show AbstractMechanical property of materials is the very important information for electronic parts that are integrated more intensively. This information becomes the raw data in identifying performance of the product at the design phase, and the input data to analyze the product, and the indispensable data to secure product reliability that becomes the foundation of competitive product. Since the thin foil has the different manufacturing process from bulk materials and has similar thickness to the grain size, mechanical property of it is significantly different from that of bulk material. FPCB (Flexible Printed Circuit Board) that connects LCD (Liquid Crystal Display) to the main board of folding type or sliding type mobile phone receives mechanical loading repetitively while it is being used, which leads to a crack and electrical short circuit on the board. To resolve this problem and secure reliability, characterization of mechanical properties regarding FCCL (Flexible Copper Clad Layer) material of the FPCB, becomes important. This paper studies fatigue test that can characterize mechanical properties of thin copper foil that is the material for FCCL used for the mobile phone. The fatigue test of the FCCL was performed, by supplementing the alignment device and the gripping device to the commercial fatigue tester. To identify the effect of the initial stress that occurs when assembling the FPCB, the fatigue test was carried out, considering the mean stress. The result has shown that the thin copper foil had the same mean stress effect with the bulk material. We suggested stress – fatigue life relationship considering mean stress effect.
9:00 PM - B7.9
Hermetically Sealed Chip Size Cavity Package by a Wafer to Wafer Bonding Technique with Fitting Convex and Concave Shaped Solder Frames.
Yoshihiro Koshido 1 , Naoko Aizawa 1 , Hajime Yamada 1 , Yukio Yoshino 1 , Hiroyuki Fujino 1 , Takahiro Makino 1
1 , Murata manufacturing Co., Ltd., Nagaokakyo-shi, Kyoto Japan
Show AbstractWafer to wafer bonding techniques have been investigated to develop cavity packaging techniques for Micro Electro Mechanical Systems (MEMS), Surface Acoustic Wave (SAW), and Bulk Acoustic Wave (BAW) devices, etc. It is difficult to bond wafers with different thermal expansion coefficients, because the residual stress caused by the difference of thermal expansion coefficients between the wafers. Our bonding technique would be practical, because it makes no residual stress and wafer cracking, and is less sensitive to contamination.A Si wafer and a glass wafer(both are 100mm in diameter), of which the thermal expansion coefficients are both about 3ppm/degree C, were bonded with our technique. Convex frames on the glass wafer are formed by single frames consisting of CuSn solder, and concave frames on the Si wafer are formed by double frames consisting of the same material. Each frame has a height of 17μm and a width of 13μm-25μm. The chip sizes are 1mm×0.9mm and 2mm×1.8mm. We aligned the two wafers and temporarily fixed them by inserting the convex frames to the concave frames with a force of 20N at room temperature. A moderate taper of the frames makes an alignment shift of several um allowed. The accuracy of the alignment machine of about ±5μm makes the wafer level fitting possible .The wafers were never separated by hand. After the alignment and fixing process, the frames are melted and bonded by heat treatment at 300 degrees C for 10 minutes. The cavities are hermetically sealed with a CuSn alloy whose melting point is up to 600 degrees C. The bond is strong enough against the reflow process and shear strength. After dicing to chips, these frames showed a seal level of 10-9Pa m3/s.For wafers having different thermal expansion coefficients, temporarily fixing them with convex and concave frames and one by one chip sealing by Yttrium Alminum Garnet (YAG) laser welding through glass wafer is available. YAG laser goes through the glass wafer, and only the sealing frames are melted and bonded. Local elevation of temperature on the wafer can avoid wafer cracking due to the stress caused by the difference of thermal expansion coefficients. We showed the effect of YAG laser welding using 4mm×3.6mm Si and glass substrates and plane AuSn solder frames. YAG laser welding had a 10-9Pa m3/s leak rate. We are going to investigate the combination of convex and concave frames and YAG laser welding for low temperature bonding, in order to bond wafers having different thermal expansion coefficients without wafer cracking.
B8: Poster Session: Metallization
Session Chairs
Thursday AM, April 12, 2007
Salon Level (Marriott)
9:00 PM - B8.1
Electrical and Structural Properties of Ruthenium Film Grown by Atomic Layer Deposition Using Liquid-phase Ru(CO)3(C6H8) Precursor.
Sung-Hoon Chung 1 , Yong-Won Song 1 , Hyuk-Kyoo Jang 3
1 Nano-Optics Engineering, Korea Polytechnic University, Siheung Korea (the Republic of), 3 R&D Center, Mecharonics co., Ltd., Pyoungtaek Korea (the Republic of)
Show AbstractRuthenium (Ru) film has been known as one of the promising capacitor electrode materials for ultra-large scale integration dynamic random access memory (ULSI DRAM) device because of high conductivity of Ru oxides as well as its own low resistivity and high thermal stability [1,2]. Ru(EtCp)2 and Ru(OD)3 have been widely used as Ru precursor so far despite a long nucleation time, the additional cost for a liquid delivery system and film degradation giving arise to film lift-off and increase of surface roughness [3]. Here, we present fabrication possibility of Ru films on the 8 inch Si and Al2O3/Si substrates using a volatile liquid-phase Ru precursor, tricarbonyl-1,3-cyclohexadienyl ruthenium (Ru(CO)3(C6H8)) and investigate the fabricated films in structural and electrical methods: the scanning electron microscopy, atomic force microscopy, energy dispersive X-ray analysis, and four-probe measurement. For the purpose an atomic layer deposition (ALD) technique, in which self-limiting surface reaction character leads to highly-conformal film formation indispensable for the DRAM involving holes and trenches with high aspect ratios, was employed. Dependence of surface morphology on Ru precursor vapor pressure explicitly provides the stoichiometric amount of precursor material for making a complete fill over the entire substrate surface. The film deposition rate l tended to saturate at l = 1.5 Å/cycle beyond the Ru precursor dose nRu = 20 μmol, which exceeds over a monoatomic radii of the Ru element, i.e., > 1.34 Å. The deposition rate above a monolayer per cycle could be explained with one of the standard ALD process models [4] including promoted saturation density at ALD window due to undecomposed molecules inside films. The undecomposed molecules are supposed to be linked to carbon density inside films; sharp drop in resistivity after thermal annealing may indicate emission of decomposed carbon molecules from the films by thermal energy. References[1] T. Aaltonen, P. Alén, M. Ritala, and M. Leskelä, Chem. Vap. Deposition, 9, 46 (2003).[2] M. Ritala, and M. Leskelä, Nanotechnology, 10, 19 (1999).[3] Y. Matsui, M. Hiratani, T. Nabatame, Y. Shimamoto, and S. Kimura, Electrochem. Solid-State Lett., 5, C18 (2002).[4] T. Suntola, Materials Science Reports, 4, 261 (1989).
9:00 PM - B8.10
Diffusion Behavior of Tungsten-titanium Barrier Layers in Silver Metallization.
S. Bhagat 1 , N. Theodore 1 2 , T. Alford 1
1 School of Materials, Arizona State University, Tempe, Arizona, United States, 2 , Freescale Semiconductor Inc., Tempe, Arizona, United States
Show AbstractCurrently, Cu is the most common interconnect material used in the electronic industry. Copper has advantages over aluminum in terms of better electromigration behavior, lower RC delay, and low bulk resistivity. However, deficiencies of copper interconnects in conjunction with the continued miniaturization of feature sizes has led the way to study other metallic interconnects as well. Silver is one such potential interconnect metal, which enjoys the lowest bulk resistivity and higher resistance to electromigration than copper. However, silver thin films have the problem of rapid diffusion into Si at elevated temperatures. Also, silver does not adhere well to Si. In order to overcome these drawbacks, a barrier layer between silver thin films and Si substrate is needed. W-Ti has been extensively researched for aluminum and copper metallization. In the present investigation we have studied W-Ti barrier layers for silver metallization. We see that at elevated temperatures of around 600 °C, W and Ti start moving into the Ag layer. Furthermore, Si starts moving into W-Ti layer indicating the formation of silicide at the Si/W-Ti interface. These interfacial reactions and movements enhance adhesion of the layers. At 700 °C, silver agglomerates. These studies are performed using X-ray diffraction analysis, secondary ion mass spectrometry, transmission electron microscopy, Rutherford backscattering spectrometry and four point probe resistance measurements. This study shows the diffusion behavior of the various species in the Ag/W-Ti/Si stack. This structure shows promise for use as an efficient barrier layer for silver metallization.
9:00 PM - B8.13
Electrical and Chemical Characteristics of CoWP Capping Layers Deposited on Cu by Electroless Plating.
Hyeong Jin Yun 1 , Tae Ho Kim 1 , Chang-Koo Kim 1
1 Chemical Engineering, Division of Energy Systems Research, Ajou University, Suwon Korea (the Republic of)
Show AbstractAs the feature size of Si-based devices keeps shrinking, copper interconnection is expected to be a very important process for the fabrication of nano-scale devices because the electrical properties such as conductivity and electromigration resistance of copper are much better than those of aluminum. The use of copper, however, also has some drawbacks, and one of the demerits in the use of copper is corrosion and degradation of copper surfaces by oxidation. Therefore, the deposition of cladding or capping layers to protect copper surfaces from oxidation draws much attention. This capping layer must have low resistance, and be able to prevent copper from being oxidized and diffusing to upper low-k dielectric layers. CoWP alloy is suitable for being used as capping layers due to its excellent electrical and mechanical properties. In this study, CoWP capping layers were deposited on copper by electroless plating. Electroless plating is a simple method using chemical potential difference without external current, and it can produce thinner and more uniform films than conventional electrodeposition methods. Other studies on electroless plating of CoWP layers have used sodium-containing precursors. Sodium ions, however, are known to be harmful to the electrical performance of devices. Therefore, ammonium-containing precursors were used in this study. By varying process conditions such as pH of electrolytes, concentrations of each precursor, plating time, post baking time, and temperature, electrical and chemical characteristics of the CoWP layers were analyzed with sheet resistance and XPS measurements. It was found that the sheet resistance went through a minimum as pH of the electrolytes was changed. The sheet resistance was also found to have a maximum with varying the concentration of Co ions. This behavior could be explained in terms of the fractional amounts of phosphorous and tungsten in the CoWP layers.
9:00 PM - B8.14
Thermal Treatments Influence on the Microstructure of Electrochemically Deposed Cu in Damascene Trenches.
Vincent Carreau 1 2 , Sylvain Maitrejean 1 , Marc Verdier 2 , Yves Brechet 2 , Anne Roule 1 , Alain Toffoli 1 , Vincent Delaye 1 , Gerard Passemard 3
1 D2NT/LBE, CEA-LETI, Grenoble France, 2 , LTPCM (INPG-CNRS-UJF), St Martin d'Hères France, 3 , STMicroelectronics, Crolles France
Show AbstractTo improve microelectronic circuit performances in term of data processing and power consumption, feature’s dimensions are reduced. Concerning interconnects, when conductor line dimensions are reaching the electron mean free path in the material, 40nm in the Cu case, the electric resistivity is increasing. That will imply a rise in power losses in interconnects, in RC delay, and heating in chips. It has been shown that the resistivity increase is mainly due to electron scattering at line surfaces and grain boundaries. Therefore, there’s a need to control copper microstructure to reduce the material resistivity increase at nano scale.This work presents relations between grain size, Damascene line widths and thermal treatments and their consequences on Cu resistivity. Different annealing conditions (time and temperature) were applied on Damascene Cu feature with line width between 3µm and 50nm. On these lines, resistivity measurements have been performed using Thermal Coefficient Resistance measurement technique. Grain size is extracted using ionic microscopy and TEM techniques.As expected, we first demonstrate a correlation between Cu resistivity and grain size. Secondly, we show that resistivity decreases with increasing annealing temperature and time.The major results concern the identification of different grain growth regimes. These regimes depend on line width and annealing temperature. For larger lines, a bamboo structure with large grains is obtained. On the contrary, for very narrow Cu lines (line width below 150nm), grain morphology is equiaxial and grain size close to the line width. For these line widths, at temperatures below 250°C, if annealing time is long enough, resistivity saturates at value independent of temperature. In contrast, for 400°C anneal, resistivity decreases below the low temperature saturation value.These results are discussed with respect to grain growth mode: for larger lines, grain morphology comes from growing grain in the Cu overburden that invades the pattern. For narrow lines, overburden grains can no more grow inside the patterned structure. The microstructure is then controlled by growth mechanisms inside the pattern. These grain growths occur with two different regimes, a low temperature one and a high temperature one.These results imply that, in order to control the Cu microstructure for sub 45nm node, studies might be performed with line dimension below 150nm for which the same grain growth mechanism occurs. High temperature anneal might be required for further resistivity reduction.
9:00 PM - B8.15
Porosity and its Effect on Barrier Performance of Thin Electroless Cobalt Alloy Capping layers on Cu Interconnects.
Qingyun Chen 1 , Jun Liu 2 , Elizabeth Walker 2 , Richard Hurtubise 1
1 R & D, Enthone, Inc., West Haven, Connecticut, United States, 2 R & D, ATMI, Danbury, Connecticut, United States
Show AbstractElectroless cobalt deposition has been under intensive study for ULSI applications in recent years. Electroless cobalt alloys are proven to be superior candidate as the capping layer because of higher electromigration resistance, good barrier property and thermal stability, and possible reduction of effective k value of the dielectric stack1-3. However, deposit defectivity is still a challenge to meet the reliability specifications for future ULSI fabrication lines of 45/32 nm technology node and beyond. Typical morphological defects include nodulation or particle formation, grain decoration or lateral roughness, porosity, and thickness non-uniformity. Those defects can decrease diffusion barrier effectiveness, lower the capability of the capping layer to suppress electromigration, increase current leakage, and thus are the major limitation for this technology to be adopted. Porosity is one of the most characteristic defects of an electroless cobalt deposition process, recognizing that the co-evolution of hydrogen during cobalt deposition can lead to entrapment of the hydrogen gas in the film. It is also observed that cobalt nucleates differently at copper facets and grain boundaries, causing higher porosity at the interfaces due to liquid entrapment during the process. Those pores can connect to each other and form a “through hole” in the film, performing as a diffusion channel for copper to travel though, thus decreasing the barrier effectiveness. The through holes can be enlarged during the following integration process steps such as dielectric deposition and resist strips, and eventually affect the barrier performance at greater level on devices. Pores which originate from the base metal and traverse through the deposit are generally considered as pits or pinholes in the deposit. In general, the density of pits and pinholes decreases as the film thickness builds up. However, for future ULSI applications, the acceptable thickness for electroless CoWP caps is limited (<10 nm). Therefore, pits or pinhole formation must be suppressed in order to maximize the barrier performance of the thin cobalt alloy caps. In this study, pinhole densities of electroless cobalt alloy films with different thickness on copper substrate are characterized using optical instruments, x-ray techniques and electrochemical methods. The impact of pits and pinholes on deposit film barrier property and thermal stability are investigated on films with different thickness and various cobalt alloy compositions. Effects of process conditions such as pre-clean, bath formulation and plating condition as well as post-clean on pit and pinhole densities were investigated. References:1.A.Kohn, M. Eizenberg, Y. Shacham-Diamand et al., Materials Sci. and Eng. A302, P.18 (2001).2.P. Singer, Semiconductor International, Oct. 1, 2005.3.A.Kohn, M. Eizenberg, Y. Shacham-Diamand et al., J. of Applied Physics, Vol.2, No. 9, P.5508 (2002).
9:00 PM - B8.17
Electroless Deposition of Gold Nanoparticles Over Silicon-based Substrates.
Hassan Borteh 1 , Nicke Ferrell 2 , Derek Hansford 2 , Randall Butler 3
1 Biophysics, Ohio State University, Columbus, Ohio, United States, 2 Biomedical Engineering, Ohio State University, Columbus, Ohio, United States, 3 Materials Scisnce and Engineering, Ohio State University, Columbus, Ohio, United States
Show AbstractIn this work we demonstrated the deposition of gold nano-particles from aqueous solution of HAuCl4 on peptide patterns. Gold templates have been used widely in biosensors and microelectrodes. This approach tries to obtain dense and uniform patterned deposition of gold on the substrates. First, silicon substrates with thermally grown oxide layer, coated Ni, and native oxide were patterned with a polymer in the clean room. For non-clean room patterning, stamping of PDMS molds on the substrates was used. Then the protein solution was physically or covalently adsorbed on the substrates. For covalent binding of the protein to the substrates a bifunctional linker, which is 4-(maleimidomethyl)cyclohexanecarboxylic acid (SMCC) was used. The polymer layer was removed with an organic solvent (lift-off process) afterwards. Finally, an aqueous solution of HAuCl4 was reacted with the protein template. The protein reduced the gold, and gold particles were deposited on top of the protein template. 3X FLAG peptide from Sigma-Aldrich and bovine serum albumin (BSA) were used as proteins in this experiment. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) were used to confirm the results.
9:00 PM - B8.18
Ultra-smooth Ag Film Fabricated Using e-beam Evaporated Ge as an Intermediate Wetting Layer for Applications in Nanoscale Devices and Superlens.
Logeeswaran Vj 1 2 , Nobuhiko Kobayashi 2 , Wei Wu 2 , M.Saif Islam 1 2 , Nicholas Xuanlai Fang 3 , Shih Yuan Wang 2 , R. Stanley Williams 2
1 Electrical & Computer Engineering, Univ. of California Davis, Davis, California, United States, 2 Quantum Science Research Advanced Studies, Hewlett Packard Laboratories, Palo Alto, California, United States, 3 Mechanical Science & Engineering, University of Illinois, Urbana-Champaign, Urbana-Champaign, Illinois, United States
Show AbstractWe demonstrate a new method to obtain ultra-smooth Ag film with an RMS roughness of ~0.8nm and average grain size of less than ~20nm by depositing Ag on a Ge intermediate layer. Our method does not require any post-deposition processing such as annealing at high temperatures or special substrate preparation. An analysis of the surfaces of freshly deposited Ag surfaces using characterization techniques such as atomic force microscopy reveal a very rough surface topology with RMS roughness of ~5-10nm and average grain size of ~150nm. This often causes high degree of scattering losses in optical applications and device shorts in nano-electronics contributing to plummeting yields as well as decreased device reliability. In this work, we deposited thin film of Ag on double-polished borosilicate glass substrates with 1nm and 2nm Ge intermediate layers. Both materials were deposited using e-beam evaporation. AFM image analysis shows that having the evaporated Ge intermediate layer drastically changes the Ag surface morphology, namely, the surface roughness to ~0.8nm and grain size distribution to ~20nm. Importantly, increasing the Ag:Ge thickness ratio reduces the RMS roughness and the grain size distribution significantly. We believe that Ge acts as a wetting layer for the evaporated Ag film thus directly minimizing the island cluster formation of Ag. Electrical characteristics of the Ag-Ge bilayer will also be discussed. The results are very promising for applications in molecular scale electronics and several other areas of nano-scale devices. The application of this ultra-smooth Ag surface will also help overcome the issue of high transmission loss in the superlens and other plasmonic devices.
9:00 PM - B8.19
Grain Orientation Analysis by TEM of 180 nm Cu Interconnects Using an Automated Crystallography Software.
Jin Ho An 1 , Paulo Ferreira 1
1 , University of Texas at Austin, Austin, Texas, United States
Show AbstractGrain orientation is an important factor in the reliability of Cu interconnects, as it affects thermal and electrical properties. Past research has studied the overall texture of Cu interconnects through X-Ray Diffraction, while local grain orientation has been investigated by Electron Back Scattered Diffraction (EBSD). However, as the width of Cu interconnects continues to decrease, the use of EBSD is becoming increasingly difficult to perform and is often inaccurate. In this context, Transmission Electron Microscopy is currently the most reliable method for determining grain orientation in Cu Interconnects with linewidths below 100 nm. With the use of a small TEM probe, Convergent Beam Electron Diffraction and Nano Beam Diffraction techniques can be used in the TEM to obtain accurate grain orientation. However, the use of these techniques is very time consuming as the orientation of each grain needs to be resolved individually. In this work, we have studied the grain orientation in 180 nm Cu Interconnects by TEM, equipped with an Automated Crystallography Software. This method greatly expedites grain orientation measurements by automatically determining the orientation of each grain on the basis of spot diffraction patterns. In addition, the Automated Crystallography Software was used to analyze the local grain orientation adjacent to voids that formed under thermal stress conditions.
9:00 PM - B8.2
Chemical Vapor Deposition of Amorphous Ruthenium-phosphorus Alloy Films for Cu Interconnect Applications.
Jinhong Shin 1 , Hyunwoo Kim 2 , Kyriacos Agapiou 3 , Richard Jones 3 , Gyeong Hwang 2 , John Ekerdt 2
1 Material Science and Engineering, University of Texas at Austin, Austin, Texas, United States, 2 Chemical Engineering, University of Texas at Austin, Austin, Texas, United States, 3 Chemistry and Biochemistry, University of Texas at Austin, Austin, Texas, United States
Show AbstractContinuous improvement in functionality, operating speed, and density of VLSI devices drove the transition from an Al to a Cu based interconnect technology. Copper provides lower electrical resistivity and higher intrinsic electromigration resistance than Al, however it requires liner materials that function as a diffusion barrier, a seed layer for electroplating, and an adhesion promoting layer. Ruthenium has been considered as a promising liner material as a directly plateable diffusion barrier because of its low electrical resistivity, high melting point, chemical inertness, and immiscibility with Cu. However, it has been reported that Ru itself is not an effective Cu diffusion barrier due to its microstructure, which is polycrystalline and features a columnar structure. Therefore, controlling the microstructure of ultra thin Ru films is crucial in obtaining the required liner properties. Here we report amorphous Ru films grown by chemical vapor deposition (CVD) using cis-dihydridotetrakis(trimethylphosphine)Ru (cis-RuH2(PMe3)4 (Me=CH3)). The films were grown on a thermal oxide substrate using a cold wall CVD system having base pressure of 5 × 10-8 Torr with an inert purge gas (Ar). The growth temperatures examined were 150 – 300 °C, and the film thicknesses were less than 50 nm. The microstructures of the films were analyzed using X-ray diffraction (XRD) and transmission electron microscopy (TEM), and compared to the Ru films grown with physical vapor deposition (PVD) and CVD using Ru3(CO)12 and (2,4-dimethylpentadienyl)(ethylcyclopentadienyl)Ru (Ru(C7H11)(C7H9)) precursors. Clear differences in XRD and TEM results were observed, indicating the amorphous microstructure of the Ru films with the cis-RuH2(PMe3)4 precursor. Composition analysis using X-ray photoelectron spectroscopy (XPS) showed that the films were Ru-P alloys with 15 – 20 % P in the bulk and low C incorporated (<1 %). The chemical states of Ru and P by XPS were zero valent for both elements, suggesting that the formation of amorphous structure can be explained by a hard sphere model. Charge density distributions obtained by computational analysis also supports the minimal electronic interaction between Ru and P. The films are metastable like other metallic glasses, and the apparent recrystallization starts at ~ 500 °C, which is lower than reported binary metallic glasses like NiPx and CoPx, possibly due to the lack of chemical interaction between alloying elements. The electrical resistivity of the films is 300 – 800 μΩ.cm, and is strongly dependent on the P content and microstructure. The adhesion properties with Cu and barrier capability of the Ru-P films will also be presented in this work.
9:00 PM - B8.20
Cu Filling Behavior and Contact Resistance of the Three-Dimensional Interconnection Structures Using Cu Vias for Chip Stack Package
Kwang-Yong Lee 1 , Teck-Su Oh 1 , Tae-Sung Oh 1
1 Materials Science and Engineering, Hongik University, Seoul Korea (the Republic of)
Show AbstractChip stack packages where Si chips are stacked in a single package have drawn much attention as a new electronic packaging technology for smaller, lighter and thinner electronic products with more functionality. Chip stack packages have been processed by assembling Si chips in stack and wire-bonding the I/O pads of each Si chip to substrate pads. However, wire-bonding in such packages may deteriorate high frequency characteristics and hinder further size reduction. To overcome such limitations caused by wire-bonding in chip stack packages, three-dimensional interconnection between stacked Si chips has been proposed with Cu filling of via holes using electrodeposition. In this study, three-dimensional interconnection structure for chip stack package was processed with Cu via filling and bump formation by electrodeposition. Cu filling behavior and average resistance of a three-dimensional interconnection joint composed of a Cu via and Cu/Sn bump bonding were investigated. Trench channel formation of various size(75~10um) were analyzed filling behavior with current source, current mode, current density and RDE speed. Cu/Sn bumps were fabricated under Cu vias and bonded to Cu/Sn bumps of the substrate for chip stack process. Microstructure and electrical properties of the 3D interconnection joint were characterized. When flip-chip bonded at 270C for 2 minutes, the resistance of a 3D interconnection joint composed of a Cu via and Cu/Sn bump bonding was evaluated as 13.1 mΩ.
9:00 PM - B8.22
Surface Deformation of Metal Films Under Controlled Pressure for Generating Ultra-flat Metal Surfaces.
Logeeswaran Vj 1 3 , Mei-Lin Chan 2 , M.Saif Islam 1 3 , David Horsley 2 , Wei Wu 3 , Shih Yuan Wang 3 , R. Stanley Williams 3
1 Electrical & Computer Engineering, Univ. of California Davis, Davis, California, United States, 3 Quantum Science Research Advanced Studies, Hewlett-Packard Laboratories, Palo Alto, California, United States, 2 Mechanical and Aeronautical Engineering, Univ of California Davis, Davis, California, United States
Show AbstractA mechanical pressing technique for generating ultra-smooth surfaces on thin metal films by flattening the bumps, asperities, rough grains and spikes of a freshly vacuum deposited metal film is presented. We implemented the method by varying the applied pressure from 100MPa to 600MPa on e-beam evaporated silver film of thickness 100nm deposited on double polished (100)-oriented silicon surfaces, resulting in a varying degree of film smoothness. The surface morphology of the thin film was studied using atomic force microscopy. Notably, at a pressure of ~600MPa an initial Ag surface with 13 nm RMS roughness was plastically deformed and transformed to an ultra-flat plane with better than 0.1 nm RMS roughness. The pressing mechanism also paves the way for direct patterning of soft metals e.g. Au & Ag. The demonstration with an e-beam evaporated Ag thin film exhibits the potential for applications in decreasing the scattering induced losses in optical metamaterials, plasmonic nanodevices and electrical shorts in molecular-scale electronic devices.
9:00 PM - B8.23
Texture Evolution in Cu Films and Lines.
Chia-Jeng Chung 1 , David Field 1 , No-Jin Park 2 , Christy Woo 3
1 , Washington State University, Pullman, Washington, United States, 2 , Kumoh Institute of Technology, Gumi City Korea (the Republic of), 3 , Advanced Micro Devices, Sunnyvale, California, United States
Show AbstractGrain growth in polycrystalline films is controlled by the energetics of the surface, interface and grain boundaries as well as strain energy. The unique character of damascene lines fabricated from electroplated Cu films introduces the additional considerations of bath chemistry and geometric constraints. The moderate stacking fault energy of Cu allows for the development of a substantial twin fraction for certain growth conditions. This paper discusses in-situ observation of grain growth in Cu films and lines under various processing conditions. It is shown that for thicker films and for structures constrained within damascene trenches the energetics of twin boundary formation play a large role in texture development of these structures.
9:00 PM - B8.24
Potential of Ag Interconnect and Contact Metallization for Various Applications via Cu Additions.
Hauk Han 1 , Yeongseok Zoo 1 , James Mayer 1 , Terry Alford 1 2
1 School of Materials, Arizona State University, Tempe, Arizona, United States, 2 Flexible Display Center, Arizona State University, Tempe, Arizona, United States
Show AbstractThe thermal stability of Ag(Cu) alloy thin films on indium tin oxide (ITO) has been investigated and compared to pure Ag thin films on ITO. After thermal annealing atomic force microscopy (AFM) and X-ray diffraction results of annealed films show discrepancy of surface morphology changes and texture with annealing temperature. In this study Cu atoms in the silver affect the grain growth. The surface morphology of Ag(Cu) and Ag films on ITO layers evolve in very different ways and show enhanced (111) texture in the Ag(Cu) during thermal annealing. The normalized (111) texture intensity (I111/I111+I200) of Ag (Cu) enhanced by 5% compared to that of pure Ag films. The resistivity of both samples annealed at high temperatures (~up to 600°C for 1 h in vacuum) remained constant due to no occurrence of agglomeration. AFM, RBS, and electrical resistivity data show that no agglomeration occurs during the annealing process. The stable ability and enhanced texture of Ag(Cu) alloys on ITO layer up to 600 °C indicates that it is useful for conventional IC application, flip-chip light-emitting diodes, as well as many high temperature applications for constitute potential contact materials.
9:00 PM - B8.25
Evaluation of Copper Oxide to Copper Selectivity of Chemical Systems for BEOL Cleaning Through Electrochemical Investigations
Nandini Venkataraman 1 , Ashok Muthukumaran 1 , Srini Raghavan 1
1 Materials Science & Engineering, The University of Arizona, Tucson, Arizona, United States
Show AbstractBack End of Line Cleaning of copper based structures requires chemical formulations that can remove copper oxide selectively without corroding copper and etching the dielectric. Many commercially available semi-aqueous and all aqueous formulations claim to meet these criteria. These include semi-aqueous fluoride strippers (SAF) and all- aqueous ammonium phosphate based chemical systems. This paper will report the results from a fundamental study undertaken to evaluate the performance of a semi-aqueous fluoride formulation in removing copper oxide films of controlled thickness grown on copper. The thickness and composition of the oxide films were determined electrochemically using cathodic reduction technique. Electrochemical Impedance spectra of samples immersed in the formulation have been measured as a function of time to follow copper oxide dissolution and the data has been analyzed to detect the transition of copper oxide to copper.
9:00 PM - B8.26
Electrochemical Corrosion Inhibition System for Photoresist Stripper for New Copper FPD Manufacturing.
Seiji Inaoka 1 , Sang In Kim 2
1 , Mallinckrodt Baker Inc., Phillipsburg, New Jersey, United States, 2 , Mallinckrodt Baker Int. Korea Inc., Pyeongtaek-City, Gyeonggi-Do, Korea (the Republic of)
Show AbstractFPD devices with new Cu, Cu-alloy or bimetal stack technology are being developed to take advantage of lower electrical resistance of Cu compared to conventional Al. The lower resistance of metal is particularly beneficial when the display device becomes larger in size and/or higher in resolution. Conventional bulk photoresist strippers were developed to be compatible with conventional metals (Al based) and are not fully compatible with Cu based systems.Copper corrosion is described as an electrochemical oxidation of Cu, and the corrosion rate of Cu is affected by both electron transfer rates the solubility of Cu oxide that forms on the metal surface. Conventional photoresist strippers are based on alkaline compounds (such as organic amines) that attack Novolac resin to dissolve the photoresist film. In order to lower the Cu corrosion rate while keeping the alkaline properties, it is necessary to reduce formation of Cu oxide. While benzotriazole is widely used as a corrosion inhibitor for Cu, its corrosion inhibition performance is not optimal in non-aqueous basic systems. New chemistries that effectively reduce Cu corrosion are necessary.A model alkaline photoresist stripper composition was used throughout the study. This non-aqueous composition has polar organic solvents and an alkanolamine. The type of alkanolamine, as well as its amount in the composition was comparable to that of conventional (not Cu compatible) photoresist strippers. The experimental solutions were prepared by adding small amounts of electron donating additives to the base stripper composition StandardTriazole and Phenolic additives were used as references materials to assess effectiveness of the electron donating materials. Blanket Cu wafers were used to determine etch rates by processing them in each experimental composition. AlthoughTriazole and phenolic additives reduce the corrosion rates, they still showed significant Cu corrosion even with a high amount added.Even a small amount of the electron donating materials component significantly reduces the Cu corrosion. This strongly suggests an active corrosion inhibition mechanism (such as electron transfer between metal surface and additives), rather than a simpler mechanism (such as surface coverage by the additives). It is suggested that electrochemical corrosion inhibition mechanisms play a major role in these solutions.
9:00 PM - B8.27
Copper Chemical Vapor Deposition using a Novel Cu(II) Precursor for Contact Via Filling Process
Hideaki Zama 1 , Yuuji Nishimura 1 , Michiyo Yago 1 , Mikio Watanabe 1
1 Institute for Semiconductor Technologies, ULVAC, Inc., Susono, Shizuoka, Japan
Show AbstractChemical vapor deposition (CVD) of copper is a promising method for ULSI interconnect technology. The CVD precursors are metallorganic Cu compounds, the most favored being ligand-stabilized Cu(I) and Cu(II) β-diketonates. In particular, Cu(I) β-diketonates, Cu(hfac)TMVS[1], have been frequently used, being liquid at room temperature and showing high vapor pressure and low decomposition temperature. On the otherhand, the disproportionation reaction from Cu(I) β-diketonate to Cu have a few problems as follows; (i) It is difficult to occur the reaction on the metal surface except Cu. (ii) The reaction synthesizes Cu(hfac)2 as a by-product, which is the bigger molecule than Cu(hfac)TMVS.In this paper, we report on the development of CVD using Cu(II) β-diketonate, Cu(sopd)2 (=C24H46CuO6Si2), as a novel precursor and hydrogen as a reducing agent, and realize the filling process for fine contact vias in 32nm and more advanced generation chips.Our experimental setup is a typical system of thermal CVD for 8-inch wafer equipped with a liquid delivery system, a gas shower plate, a ceramic substrate heater and a dry-sealed vacuum pump. The Cu(sopd)2 is solid at room temperature and the gaseous source is supplied by a vaporizer in the liquid delivery system using a n-octane solution. The Cu film is grown on a vanadium nitride (VN) glue layer grown from a vanadium-amido source by CVD. We prepare a 40nm-diameter hole, as the target-size via of this process, by using a 130nm-diameter SiO2 hole pattern wafer and the SiN refilling process.Pure Cu films could be prepared under the condition with the product of hydrogen partial pressure (Ph[Pa]) and molar ratio of H2/Cu(sopd)2 (Rm) being over 1,000,000. It shows that the Cu films are generated by hydrogen reduction reaction. We examined an Arrhenius plot with substrate temperatures between 210C and 310C under the Ph of about 2300Pa and the Rm of about 600. The behavior of surface reaction limitation appeared below 270C. By optimizing the growth conditions of VN layer, the Cu film with high nucleation density and fine stepcoverage was obtained. At the optimized conditions, Cu was conformally deposited on both the side wall and the bottom of hole at the initial stage and then the hole was completely filled.In conclusions, we demonstrate that the 40nm-diameter contact via is filled by Cu-CVD using the new Cu(II) β-diketonate, Cu(sopd)2, and the hydrogen reduction process.[1] J.A.T.Norman et al.: Proc. of VLSI Multilevel Interconnection Conf. (1991) p.123.
9:00 PM - B8.28
The Effect of the O2 Addition on the ZrO2 Thin Film’s Characteristics
Bong-Ju Lee 1 , Young-Tae Cho 2 , Honglae Sohn 3
1 Division of Physics and Chemistry, Chosun University, Gwangju Korea (the Republic of), 2 Dept. of Manufacturing and Design Engineering, Jeonju University, Jeonju Korea (the Republic of), 3 Division of Physics and Chemistry, Chosun University, Gwangju Korea (the Republic of)
Show Abstract9:00 PM - B8.29
In-situ Annealing Effects on the Improved Selectivity of Co Patterns Selectively Deposited on OTS Patterned Glass Surface.
Heejung Park 1 , Jeonggil Lee 1 , Jaegab Lee 1
1 , Kookmin university, Seoul Korea (the Republic of)
Show Abstract9:00 PM - B8.30
Increased Electron Confinement Effect on High Electron Mobility in Dopant-free AlGaN/GaN Multi-quantum-well MIS-FET by MOCVD.
Jae-Min Jang 1 , Seung-Hee Go 1 , Jae-Gab Lee 1 , Woo-Gwang Jung 1
1 School of Advanced Materials Engineering, Kookmin university, Seoul Korea (the Republic of)
Show Abstract9:00 PM - B8.4
Ultra-thin Cubic B1-TaN Diffusion Barrier for Cu Interconnects Using a TiN Seed Layer.
Roy Araujo 1 , Jongsik Yoon 1 , Haiyan Wang 1 , Xinghang Zhang 2
1 Electrical and Computer Engineering, Texas A&M University, College Station, Texas, United States, 2 Mechanical Engineering, Texas A&M University, College Station, Texas, United States
Show AbstractTaN has been demonstrated as a very promising diffusion barrier material for Cu interconnects, because its high thermal stability, relatively dense interstitial structure and thickness advantages fulfill the requirements for next generation Ultra-large scale integration (ULSI) devices. Recently we have demonstrated that epitaxial cubic TaN (B1-NaCl structure) can be stabilized on Si substrates using a TiN buffer layer and this configuration has much better Cu diffusion-barrier properties than other polycrystalline TaN barriers. However the total thickness of the TaN/TiN stacks was in the range of 100 nm or more which is far beyond the thickness requirement for the state-of-the-art Cu-metallization technology. In this paper, we proposed to apply an ultra-thin TiN as a seed layer to provide nucleation sites for growing the metastable cubic-TaN on Si substrates. All the TaN/TiN bilayer structures were deposited using a pulsed laser deposition technique (PLD) and characterized by X-ray diffraction (XRD), transmission electron microscopy (TEM), high resolution TEM and scanning transmission electron microscopy (STEM). Total thickness of the ultra-thin cubic-TaN/TiN bilayers was maintained around 30 nm, while the thickness of TiN seed layer was varied from 1nm to 5 nm for thickness optimization. Nucleation mechanisms of cubic TaN as a function of the seed-layer thickness will be discussed. Diffusion barrier properties for all the bilayer stacks were then studied by depositing a Cu layer (~10-15nm), annealing and characterized using etching experiments, resistivity measurement, secondary ion mass spectroscopy (SIMS) depth profiling and high resolution STEM. Potentially this approach can be easily adapted in other growth techniques including MOCVD and sputtering which are more popular in semiconductor industry.
9:00 PM - B8.5
Time Evolution of Nanoscale Surface Topography of Tungsten Carbide Coatings on “Hot” Silicon Carbide Electronics Devices.
Lance Wilkinson 1 , Daryush Ila 1 , Claudiu Muntele 1
1 Physics, Alabama A&M University, Normal, Alabama, United States
Show AbstractWe are reporting here on the status of our investigations on the time evolution of the nanoscale surface morphology of thermally evaporated tungsten carbide coatings on silicon carbide substrates. The purpose of the study is to develop a recipe for creating thermally and chemically stable electrical contacts on silicon carbide electronic devices able to work at elevated temperatures (up to 800 °C) in oxidizing environments. Silicon carbide is one of the few materials targeted for developing “hot” electronics, due to its mechanical, chemical, and electrical properties. While at room temperature, its 3 eV bandgap makes it a semi-insulating material, at 800 °C becomes a good semiconductor while still stable mechanically and chemically. Tungsten carbide was chosen for an electrical contact on silicon carbide because it gives an ohmic contact at those temperature levels, while is chemically and thermally stable (does not interact with the silicon carbide substrate). The deposits were investigated using atomic force microscopy (AFM) and Rutherford Backscattering Spectrometry (RBS) before and after each 1-hour interval of thermal treatment of our samples. Preliminary results show that deposits are uniform (therefore electrically continuous), with a rms roughness in the order of 5 –10 nm, and a stoichiometry approaching single digits after only few heat treatment steps. Detailed results will be given during the meeting.Acknowledgement: Research sponsored by the Center for Irradiation of Materials, Alabama A&M University and by the AAMURI Center for Advanced Propulsion Materials under the contract number NNM06AA12A from NASA, and by National Science Foundation under Grant No. EPS-0447675.
9:00 PM - B8.6
Enhanced (111) Preferred Orientation of Ag Thin Film on Amorphous SiO2 by Cu Addition.
Yeongseok Zoo 1 , Hauk Han 1 , Terry Alford 1
1 School of Materials, Arizona State University, Tempe, Arizona, United States
Show AbstractSilver has been recognized as one of promising candidates in ultra-large scale integrated (ULSI) applications in that it has the lowest bulk electrical resistivity of all pure metals and higher electromigration resistance than other interconnect materials. However, the agglomeration during the thermal processing limits the stability of Ag thin films and compromises the film’s reliability. To address these drawbacks of Ag, small amounts of Cu were added to enhance the adhesion and minimize agglomeration of Ag thin films on SiO2 substrates. The texture evolutions of Ag and Ag(Cu) thin films after annealing were investigated using θ-2θ XRD scan and pole figure analysis. These two XRD analyses revealed that the (111) textures of Ag and Ag(Cu) thin films were enhanced with increasing temperature. Comparison of texture profiles between Ag and Ag(Cu) thin films showed that Cu additions enhanced (111) texture in Ag thin films. The improved (111) texture in Ag(Cu) thin films is due to the enhanced adatom diffusion by Cu addition. The comparison of surface morphologies between Ag and Ag(Cu) films is indicative of copper’s influence (i.e., increasing surface diffusion) to form distinctive grain boundaries of Ag thin film and reconstruct disordered regions around grain boundaries.
9:00 PM - B8.7
Texture Evolution and Stress in Silver Thin Films on Different Substrates Using X-ray Diffraction.
Yeongseok Zoo 1 , Terry Alford 1
1 School or Materials, Arizona state university, Tempe, Arizona, United States
Show AbstractSubstrate surface roughness effects on Ag film texture was investigated using Bragg-Brentano scan (θ-2θ geometry) and pole figure analysis. Relative (200) intensities normalized to the intensities of the (111) peak from Bragg-Brentano scans were obtained for Ag on SiO2 (I200/I111 = 4.7) and PEN (I200/I111 = 13.2), which implies that Ag thin films on smooth SiO2 substrates had strong (111) texture when compared with Ag films on PEN. This texture comparison was confirmed by spatial distributions of (111) and (200) textures using pole figure analysis. Comparing the calculated surface energy difference (ΔEs,i) and strain energy difference (ΔEε) between (111) and (200) grains, it appears that the difference in surface energy is higher than that in strain energy for both Ag films on SiO2 and PEN. However, it is noted that the value of ΔEε in Ag film on PEN (0.039 MPa) is almost 5 times greater than that on SiO2 (0.0084 MPa). The comparison between surface and strain energies shows that (111) texture of Ag thin film on SiO2 is explained by minimization of the surface energy. Comparatively higher (200) texture in Ag thin film on PEN is due to reduction in strain energy. Weaker (111) texture of Ag on PEN is a result of the decreased supersaturation rate of nuclei and reduced diffusion length of Ag adatoms on the rough PEN surface. Therefore, the (200) texture of Ag on PEN evolved to minimize the strain energy arising from the intrinsic stress. This study regarding texture evolution of metal films is useful to understand the relation between highly preferred oriented crystal structures (i.e., bamboo structure) and the electromigration in metal interconnects.
9:00 PM - B8.8
Comparing AuNi5 Thin Films Obtained by Pulsed Laser Deposition and by Sputtering for Micro-Switch Contact Application
Noha Farghal 1 , Moustafa Ghannam 2 , Amr Shaarawi 1 , Philippe Soussan 3 , Kris Baert 3
1 Yousef Jameel Science and Technology Research Center, American University in Cairo, Egypt, Cairo Egypt, 2 EE, Kuwait University, Kuwait Kuwait, 3 MCP, IMEC, Leuven Belgium
Show Abstract9:00 PM - B8.9
High-Density, Low-Resistivity TaN Films Synthesized by Plasma-assisted ALD.
E. Langereis 1 , H. Knoops 1 , J. Klootwijk 2 , F. Roozeboom 3 , M. van de Sanden 1 , W. Kessels 1
1 Applied Physics, Eindhoven University of Technology, Eindhoven Netherlands, 2 , Philips Research, Eindhoven Netherlands, 3 , NXP Semiconductors, Eindhoven Netherlands
Show Abstract
Symposium Organizers
Qinghuang Lin IBM T. J. Watson Research Center
Wen-li Wu National Institute of Standards and Technology
E. Todd Ryan Advanced Micro Devices
IBM - Albany NanoTech
Do Yeung Yoon Seoul National University
B9: Atomic Layer Deposition and Metallization
Session Chairs
Kelly Malone
Christian Witt
Thursday AM, April 12, 2007
Room 3002 (Moscone West)
9:15 AM - **B9.1
Chemical Routes to Ultra Thin Films for Copper Barriers and Liners
John Ekerdt 1 , Jinhong Shin 2 , Wyatt Winkenwerder 1 , Hyun-Woo Kim 1 , Kelly Thom 1 , Gyeong Hwang 1 , Kyriacos Agapiou 3 , Richard Jones 3
1 Chemical Engineering, University of Texas at Austin, Austin, Texas, United States, 2 Materials Science and Engineering, University of Texas at Austin, Austin, Texas, United States, 3 Chemistry and Biochemistry, University of Texas at Austin, Austin, Texas, United States
Show AbstractRuthenium shows considerable potential as a seed layer and adhesion layer in advanced metallization schemes and may also function, alone or in concert with an under layer, as a copper diffusion barrier. Microstructure and thickness uniformity are key film parameters. This talk describes the use of alloying constituents to force the growth of amorphous ruthenium films and to stabilize the amorphous films that are grown, and describes the surface chemistry that controls film growth on amorphous and polycrystalline substrates. In general, Ru films are polycrystalline because of Ru’s high surface energy, which results in a 3D, Vollmer-Weber growth mode. Extending insight into amorphous structure gained from the bulk metallic glass literature one can anticipate that Ru will form various coordination polyhedra with metalloids, such as boron and phosphorus. Provided these polyhedra form during atomic layer deposition or chemical vapor deposition, an amorphous thin film should grow. This talk presents the growth and stability of amorphous Ru-P alloy films through the use of single source precursors, such as cis-ruthenium(II)dihydridotetrakis-(trimethylphosphine), cis-RuH2(PMe3)4, and dual sources such as Ru3(CO)12 and P(C6H5)3 or PMe3. The films contain zero-valent Ru and P. The P content is related to the growth temperature, with more P found at higher temperatures, and the amount of alklyphosphorus in the chamber background. When using cis-RuH2(PMe3)4 at 575 K, the films contain approximately 15 % P in the bulk of 30 nm thick films and these films are amorphous upon annealing for up to 3 hr at 635 K. The films are metastable and begin to form small crystalline regions upon annealing at 775 K for 30 min. Ab initio molecular dynamics calculations show that Ru-P alloys with moderate P content can result in a glassy structure exhibiting topological and strong chemical short-range order. In the Ru80P20 structure, the P-centered polyhedra prefer the tri-capped trigonal prism packing phase with Veronoi index <0,3,6,0>. In addition, the Ru-P system shows the medium-range order arising from packing the “quasi-equivalent” P-centered Ru clusters in three-dimensional space. The structural model based on melt-quenching simulations support the experimental results. Film properties, such as resistivity, are related to P content and resistivity increases with P content. Surface studies suggest the trimethylphosphine ligands undergo demethylation and desorb at the growth conditions and readsorb, and subsequently incorporate the P into the Ru film. The film growth rate with cis-RuH2(PMe3)4 appears limited by the demethylation reaction. Calculations suggest less boron than phosphorus would be required to form a stable amorphous alloy with ruthenium. The talk will address the specifics of growth with cis-RuH2(PMe3)4 and the broader implications of the surface and modeling studies on managing the properties and microstructure of ultra thin metal films.
9:45 AM - **B9.2
Beam Activation for Barrier Formation by ALD on Low k Dielectric Surfaces.
Junjun Liu 2 , Hualiang Shi 1 , Junjing Bao 1 , Paul Ho 1
2 , Tokyo Electron of America, Inc., Austin, Texas, United States, 1 Microelectronics Research Center, The University of Texas at Austin, Austin, Texas, United States
Show Abstract10:15 AM - B9.3
Characterization of Atomic Layer Deposited Ultrathin HfO2 Film as a Diffusion Barrier in Cu Metallization.
Prodyut Majumder 1 , Rajesh Katamreddy 1 , Christos Takoudis 2
1 Chemical Engineering, University of Illinois at Chicago, Chicago, Illinois, United States, 2 Departments of Chemical Engineering and Bioengineering, University of Illinois at Chicago, Chicago, Illinois, United States
Show Abstract10:30 AM - B9.4
One Step Nitride Mediated Epitaxy of CoSi2 from Plasma Enhanced Atomic Layer Deposition Cobalt Films
Han-Bo-Ram Lee 1 , Hyungjun Kim 1
1 , POSTECH, Pohang, Gyung Sang Bukdo, Korea (the Republic of)
Show AbstractThe epitaxial CoSi2 has been considered as an attractive alternate to polycrystalline CoSi2. One of the epitaxial silicide growth methods is interlayer mediated epitaxy (IME) in which a nitride or oxide is used as an interlayer. In this study, we propose a novel approach using plasma enhanced atomic layer deposition (PE-ALD) Co film to form epitaxial CoSi2 without a separate interlayer formation step. By PE-ALD of Co using metal organic precursor and NH3 plasma, a thin SiNx interlayer was formed between Co and Si. The thickness of the interlayer was successfully controlled by varying process parameters. After rapid thermal annealing, the microstructure of annealed film was analyzed by synchrotron radiation X-ray diffraction and transmission electron microscope. The results have shown that the epitaxial CoSi2 formation was achieved through IME mechanism. The effects of interlayer on silicidation were investigated as a function of key process parameters and the results were comparably discussed with physical vapor deposition (PVD) Co.
11:15 AM - **B9.5
Interface Stability of Metal Barrier and low K Dielectrics.
Toh-Ming Lu 1
1 Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractRefractory metal has been successfully used as the diffusion barrier in modern integrated circuits. A good metal barrier should prevent Cu penetration into the barrier and then into the dielectric. At the same time, the barrier material itself should not penetrate into the dielectrics. It is well known that the interface between refractory metal such as the Ta family and SiO2 is very stable against thermal and electrical stresses. An important reason for the choice of refractory metal as the diffusion barrier is because of its high melting temperature. However, recently it was found that the interface between refractory metal and many low K systems may not be stable against a bias temperature stress. Even under a moderate bias temperature stress condition, refractory metal ions are found to penetrate deep into the dielectric systems. In this talk, I will discuss the origins of this ionic penetration and recent experimental works in this area of research. It is believed that the interface chemistry such as the oxidation tendency (heat of oxide formation) can play an important role in the observed phenomenon. I will also discuss some possible strategies to overcome this issue and ways to create a stable metal/low K interfaces.
11:45 AM - B9.6
Low Temperature CVD of Ru from C6H8Ru(CO)3
Sophia Lazarz 1 , Yu Yang 1 , Navneet Kumar 1 , Do Young Kim 2 , Wontae Noh 2 , Gregory Girolami 2 , John Abelson 1
1 Materials Science and Engineering, U. Illinois at Urbana-Champaign, Urbana, Illinois, United States, 2 Department of Chemistry, U. Illinois at Urbana-Champaign, Urbana, Illinois, United States
Show Abstract Ruthenium is being investigated for multiple uses in microelectronics, including DRAM capacitors, dual damascene metallizations, and as diffusion barriers for copper. Previous studies have generally prepared Ru films by evaporation or by CVD from ruthenocene or its ring-substituted analogues. Other ruthenium compounds bearing ligands such as β-diketonates, arenes, dienes and carbonyls have also been investigated as CVD precursors. In all cases, however, the growth rates been unsatisfactory (< 2 nm/min) or the films have been contaminated by heteroatoms due to ligand incorporation. We have used the single-source liquid precursor (1,3-cyclohexadiene)tricarbonylruthenium(0), C6H8Ru(CO)3, to deposit metallic ruthenium films by CVD at substrate temperatures ranging between 150 and 450 °C. Ligand removal is expected to be relatively facile from this Ru(0) compound, and provided that the C6H8 ring does not fragment on the growth surface, this precursor has the potential to afford high quality films for microelectronics applications. The preparation of C6H8Ru(CO)3 is relatively simple and easy to scale up; the molecule is stable at room temperature and is relatively stable in air; and its room temperature vapor pressure is sufficiently high that precursor can be injected into the CVD system without the aid of a carrier gas. The Ru growth rate is relatively fast, 11 nm/min at 300 °C on Si. In situ spectroscopic ellipsometry indicates negligibly short delays before film nucleation on Si, SiO2, or sapphire substrates. The resistivity ranges between 230 and 440 μΩ-cm. The films have a grain size ~ 40 nm, as determined by X-ray Scherrer analysis. The texture of the films depends on deposition temperature: on silicon, low-temperature growth is characterized by a strong (002) preferred orientation, whereas high-temperature growth produces randomly oriented grains. The oxygen content is below AES detection limits (< 1 at. %), and the carbon content is estimated to be low. We will report the degree of conformal growth on trench substrates and the performance of these films as copper diffusion barriers. The combination of ease of synthesis and good growth rate at low temperature make C6H8Ru(CO)3 a very attractive precursor for Ru CVD in microelectronic metallization.
12:00 PM - B9.7
Laser-Induced Microstructural Modification of Polycrystalline Cu Films Encapsulated in SiO2.
Rong Zhong 1 , Jorg Wiezorek 1 , John Leonard 1
1 Materials Science and Engineering, University of Pittsburgh, Pittsburgh, Pennsylvania, United States
Show AbstractPost deposition microstructural modification by excimer laser melting has become an economical large-area thin film process due to its successful development for crystallization of silicon on glass in TFT applications. Recently, this technique has been extended to copper thin films encapsulated in silica, yielding ultra-large single crystal grains over 20 um in length. Development of this process for producing single-crystal Cu-based interconnects is a promising technology that may address resistivity and electromigration issues in future interconnect designs.We will discuss new findings in the excimer-laser-induced rapid lateral solidification of copper films encapsulated above and below with SiO2. This includes the identification of a strong <001> texture in the growth direction along the major axis of the grains as well as texture parallel to the film surface. Various dislocation and faulted defect structures are identified and examined in the context of the fundamentals of rapid solidification kinetics. Additionally, interfacial morphological evolution and extension of the process to Cu alloys with dilute additives such as Mg and Al will be discussed.
12:15 PM - B9.8
Height Dependent Resistivity of Copper Interconnects in the Size Effect.
Hideki Kitada 1 , Takashi Suzuki 2 , Takahiro Kimura 2 , Tomoji Nakamura 2
1 , Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa, Japan, 2 , Fujitsu Laboratories Ltd., Akiruno Technology Center, 50 Fuchigami, Akiruno, Tokyo, Japan
Show Abstract To study of an electrical resistance increase caused by the size effect is very important for the Cu wiring technology, because the increase of a resistance brings about the RC delay and it may result in a loss the merits of scaling down of LSI devices. There are a lot of reports concerning about the resistance increase size effect caused by the surface and the grain boundary scattering. However, it has not been clarified how the different interfaces such as barrier metal/Cu or dielectric/Cu have effects upon the electron scattering behavior. In addition, an effect of the grain size distribution in the depth direction has not been investigated enough, although there are a lot of reports discussing about the size effect concerning about the width dependences of grain size in Cu wiring.Throughout this study, we used various thickness Cu films by thinning a film using chemical mechanical polishing (CMP), in order to exclude the influence of the grain size depending on the deposited Cu film thickness. Firstly, we investigated the different interface effect using a Ta and SiC films deposited on various thickness Cu films. It was found that the electron scattering at the interfaces of both of Ta/Cu and SiC/Cu is almost an inelastic scattering. Secondly, we measured the grain size distribution in the depth direction. For the evaluation of the grain size, we used the Electron Back Scattering Diffraction Patterns (EBSP) method.The results show that there are the grain size distributions in both the depth and width directions. Lastly, measured wiring width and height dependence of the resistivity were fitted to the Fuchs and Sondheimer and the Mayadas and Shatzkes model. By using the adequately derived surface and grain boundary scattering parameter from our experiments, the fitting was very well. Especially, taking the wiring height dependence of the grain size into consideration is found to be important for the accurate estimate of the wiring resistance. Since the grain size becomes small with the decrease of the vertical and horizontal size, it is found that the effect of grain boundary scattering plays an important role in the resistance of narrower wirings. We will discuss about the resistance of Cu wiring with the same or smaller size to the electron mean free length in the future LSI generation.
12:30 PM - B9.9
AC Fatigue Tests of Damascene Interconnect Structures
David Read 1 , Roy Geiss 1
1 Materials Reliability Division, National Institute of Standards and Technology, Boulder, Colorado, United States
Show AbstractThe AC fatigue test technique uses cyclic Joule heating to apply thermal cycles to metal lines and vias in damascene dielectric structures on silicon substrates. Cyclic stresses from differential thermal expansion produce elastic and plastic deformation and possibly other mechanical damage in the metal line and its surrounding dielectric. Here we focus on the functional relationship between the number of temperature cycles to failure and the cyclic temperature change in damascene copper lines and vias.Previous studies have shown: that the AC fatigue technique produces data that are similar to S-N curves in metals; that these data can be fit by the Basquin law for fatigue in the appropriate range of cyclic temperature; and, that the values of the exponent in the fit are typically within the same range as those for mechanical fatigue of bulk metals. The stress prefactor in the Basquin law is an estimator of the ultimate tensile strength in metals, and this same relationship has been proposed for the AC fatigue test. However, previous AC fatigue experiments have not clarified the role of constraint. The dielectric in the damascene structure clearly constrains the metal lines. The range of dielectric mechanical properties in advanced interconnect structures creates the need for a good quantitative understanding of the effect of the constraint on the AC S-N curve.AC (100 Hz) S-N curves for commercial damascene copper lines and vias in two-metal damascene structures with different dielectrics will be reported. The lines used are approximately 500 nm deep by 300 nm wide. Vias with diameters from about 250 to 500 nm were tested. Cyclic lifetimes from a few thousand to over 10 million were recorded as a function of cyclic temperature ranges from a little over 100 C, for the longest-lived vias, to around 900 C, for the shortest-lived lines. The temperatures during the tests were measured through the variable electrical resistance of the structures. Vias with a variety of diameters were tested; the S-N data plotted against cyclic temperature followed the same general trend for all via diameters. The S-N curve for the vias falls well below that for the lines. However, the vias are roughly as deep as they are wide, and are constrained only by copper at the top, whereas the lines are fully constrained by dielectric. The S-N curves for the damascene lines fall above similar curves for e-beam deposited copper lines with no surrounding dielectric, while the S-N curves for the damascene vias fall below that of the unconstrained copper lines. The results will be interpreted using SEM examination of the microstructure of the metal conductors and of the condition of the dielectric near the failure sites before and after testing.These early data indicate that the AC fatigue test is sensitive to differences in material, structural geometry, and constraint conditions; as such, it may be useful in assessing the reliability of advanced interconnect structures.
12:45 PM - B9.10
Electroluminescence from Single Colloidal Quantum Dots at Room Temperature.
Hao Huang 1 , August Dorn 1 , Moungi Bawendi 1 , Vladimir Bulovic 2
1 Chemistry, M.I.T., Cambridge, Massachusetts, United States, 2 Electrical Engineering & Computer Science, M.I.T., Cambridge, Massachusetts, United States
Show AbstractPhotoluminescence studies at low laser excitation power have shown that quantum dots behave as non-classical light sources. Electroluminescence from single quantum dots, which is more appealing for practical applications, has only been demonstrated recently at low temperature using self-assembled quantum dots grown by molecular beam epitaxy. To date, however, there are no reports of electroluminescence from single colloidal quantum dots, which can be synthesized by wet chemical methods enabling processing and integration versatility. In the present study, we report the demonstration of electroluminescence from single colloidal CdSe/ZnS (core/shell) nanocrystals embedded in organic light emitting device structures at room temperature. Spectral diffusion and blinking from individual quantum dots, key features of single quantum dots, were observed both in electro- and photoluminescence. We propose a model in which the nanocrystals act as seeds for the formation of current channels that lead to enhanced exciton recombination in the vicinity of the quantum dots. Atomic force microscopy (AFM) studies on different layers of the device also support the model.
B10: Novel Interconnects and Packaging
Session Chairs
Atsushi Shiota
Albert Yee
Thursday PM, April 12, 2007
Room 3002 (Moscone West)
2:30 PM - **B10.1
Assembling Carbon Nanotube Films as Thermal Interface Materials.
ChingPing Wong 1
1 Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractAs the feature size of integrated circuits (ICs) decreases and the IC clock frequency and transistor density per chip increase, the power density increases exponentially. Heat generation has become a critical issue in advanced high performance ICs in recent years. The current thermal solutions will soon be inadequate for heat dissipation. New thermal management strategies and high thermal conductivity materials are urgently needed for electronic thermal management within the chip and surrounding packaging. Carbon nanotubes (CNTs), which are reported to be the most thermally conductive material (>3000 W/K.m), are a promising candidate for thermal management. However, several existing technical barriers have restrained the application of CNTs in microelectronic devices. One of the main challenges is that the high temperature required to grow high quality CNTs (>600°C) is too high to be compatible with back-end microelectronic fabrication processes. Another major obstacle is the poor adhesion between CNTs and substrates, which results in high interface thermal resistance and poor long term reliability.To address these challenges, we proposes to use a novel CNT transfer process, which features separated steps of in-situ open-ended CNT synthesis and low-temperature CNT assembly to engineer well-aligned open-ended CNT architectures for microelectronic thermal management. In-situ growth of high density open-ended CNTs with vertical alignment was first developed. To successfully achieve CNT assembly with good thermal performance, the following issues should be addressed. (1) Appropriate metals/solders should be selected to form good thermal and electrical coupling with CNTs. (2) The wetting of solder metals in CNT channels and on the CNT outer walls by capillary force should be further clarified. (3) An appropriate solder reflow process should be developed to guarantee good wetting on CNTs. Preliminary results show that the transferred open-ended CNT structures can have very strong adhesion to the substrate, which promise to improve the CNT-metal interface properties. The thermal characteristics of this interface will be described. The thermal conductivity of the CNT assembly will be measured using laser metrology.
3:00 PM - B10.2
Impact of Fabrication Process, Layout Variation, and Packaging Process on Cu/Low-k Interconnect Reliability.
Aditya Karmarkar 1 , Xiaopeng Xu 2 , Dipu Pramanik 2 , Greg Rollins 2 , Xiao Lin 2
1 TCAD DFM Solutions, Synopsys (India) Pvt. Ltd., Hyderabad, Andhra Pradesh, India, 2 TCAD DFM Solutions, Synopsys, Inc., Mountain View, California, United States
Show AbstractThe industry trend towards smaller feature size and higher integration density leads to multi-level Cu/low-k interconnect schemes with reduced line width and spacing. Mechanical stress is generated during interconnect fabrication. The spatial distribution of the stress is strongly affected by the layout variation. The packaging process generates a global chip level stress that permeates to the local interconnect level. Stress related failures and yield loss are major areas of concern for Cu/low k because of the lower mechanical strength of the low-k dielectrics. Therefore, it is imperative to understand the effect of fabrication process, layout variation, and packaging process on stress distributions in interconnects.The thermal mismatch between various materials and the material formation process are the two main sources of the fabrication process induced stress. A sequential process simulation capability has been developed to simulate the fabrication process stress using process conditions and mask layout information. To analyze the effects of layout variation, stress analysis is carried out using a geometric engine linked directly to the layout design database. An entire cell pattern with multiple metal lines, via connections and other features can be simulated using special algorithms to process GDSII design data and to generate 3D structures. To assess the effects of packaging on the metallization structure, a multilevel submodeling technique is used. The entire packaging process is simulated with a global package model, and the solution fields are extracted along the submodel boundaries to be simulated at a lower level. The solution fields extracted from the global model are then applied to the submodels to simulate the detailed stress distributions within the submodel. The simulated stress fields in the metallization structure represent the packaging induced stress. The simulated packaging induced local stress fields in the metallization structure are then imposed on the interconnect structure with the fabrication process induced stress. This method combines fabrication process induced and packaging process induced stress with the full consideration of layout variation. The full paper examines the effect of fabrication process, layout variation, and packaging process on the final stress distributions in Cu/low-k interconnects, and explores the reliability impact of mechanical stress. Stress sources from each fabrication step, proximity overlapping effects within a layout, and global to local interactions during packaging are assessed following process step history. Correlations of peak stress, stress gradient and other stress derivatives with various measured damage patterns are examined. Strategies to mitigate stress related reliability failures in back end of the line structures and to improve overall yield are proposed.
3:15 PM - B10.3
Low Temperature Direct Metal Bonding by Self Assembled Monolayers.
Xiaofang Ang 1 , Li Cheong Chin 1 , Jun Wei 2 , Zhong Chen 1 , Chee Cheong Wong 1
1 School of Materials Science & Engineering, Nanyang Technological University, Singapore Singapore, 2 , Singapore Institute of Manufacturing Technology, Singapore Singapore
Show AbstractElevated bonding temperature for interconnection deteriorates the reliability of both the device and the interconnect; hence the imperative for developing low temperature bonding methods. This study investigates the feasibility of using self-assembled monolayers (SAMs) to assist direct gold-gold bonding. This involves a simple molecular self-assembly process whereby a monolayer of alkyl chains with a sulfur end group is attached to the gold surface prior to thermocompression bonding. Using this method, we have achieved gold to gold bonding at a bonding temperature below 100°C, a significant reduction compared to the conventional bonding temperatures of above 150°C. We attribute this temperature reduction to two properties of SAMs - (1) surface passivation of the Au surface that precludes adsorption of surface contaminants, and (2) The easy displacement of SAMs through thermal desorption just before bonding occurs. This SAMs-assisted bonding mechanism is supported by X-ray photoelectron spectroscopy (XPS) and surface plasmon resonance (SPR) results.
3:30 PM - B10.4
A Trial for Micro-Scale Evaluation of Adhesion Strength around Cu Metallization Systems.
Shoji Kamiya 1 , Hitoshi Arakawa 1 , Hiroshi Shimomura 1 , Masaki Omiya 2
1 , Nagoya Institute of Technology, Nagoya, Aichi, Japan, 2 , Tokyo Institute of Technology, Tokyo Japan
Show AbstractAlong with further miniaturization of integrated circuits, reliability issues has become more important and complicated. The multilayered Cu metallization systems introduced recently for faster operation of circuits has emerged severe mechanical problems, including the integrity of their interfaces. Therefore quantitative evaluation of adhesion has become one of the major concerns in IC technologies. A de facto standard of adhesion measurement in IC industries is the four point bending technique[1], which evaluates the adhesion in terms of energy required to extend a unit area of interface crack, i.e., toughness. However, this technique uses fairly large specimens in millimeter size in contrast to the recent miniaturization of systems, and yet requires quite a thin metal layer thickness to avoid influence of plastic deformation on the evaluated amount of toughness. Taking account of these backgrounds, we recently tried a new technique to more locally evaluate toughness of interface and applied the technique to Cu metallization systems.In the new technique, micron-scale specimens were fabricated on the wafer by using focused ion beam. Sharp diamond stylus with submicron tip radius was used to load these specimens to extend interface cracks. Because of the point loading applied by the stylus tip to the specimens, interface crack extension was two dimensional. Three dimensional finite element model was developed to adequately simulate the crack extension behavior and thus accurately determine the toughness of interface by comparing the simulated crack extension behavior to that experimentally obtained. Separation of dissipated energy due to plastic deformation of metal layer, and thus independent evaluation of energy consumed purely for the separation of the interface, was also realized by microscopically simulating the elastic-plastic deformation process at the crack tip during interface crack extension.In-plane size of down to 5 micron square is currently achieved, which is already roughly 1000 times smaller than the specimens for four point bending technique. Variety in specimen fabrication also allows selective access to a specific interface in multilayered systems. Favorable advantages are discussed in detail in the presentation.[1] M. Lane, R. H. Dauskardt, A. Vainchtein, H. Gao, J. Mater. Res., 15 (2000), 2758-2769.
3:45 PM - B10.5
Modified Creep Experiments of Polydimethylsiloxane (PDMS) Films on Si Substrate Using Nanoindenter and Flat-ended Cylindrical Tip.
Seung Tae Choi 1 , Su Jeong Jeong 2 , Seung Ryun Lee 3 , Youn Young Earmme 3 , Changyoul Moon 1
1 Micro Device and Systems Lab, Samsung Advanced Institute of Technology, Suwon, Gyeonggi-do, Korea (the Republic of), 2 Vehicle CAE team, Advanced Technology Center, Hyundai & Kia Corporate Research & Development Division, Hwaseong-si, Gyeonggi-do, Korea (the Republic of), 3 Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology, Daejeon Korea (the Republic of)
Show AbstractPolymeric thin films are ubiquitous in contemporary microelectronic devices and micro-electro-mechanical systems. Specially, polydimethylsiloxane (PDMS) is widely used in biomedical applications, in membrane technology, in micro-lithography as high voltage insulator, or in a cross-linked form as a nearly ideal elastomer. Compared to other polymers, PDMS has a relatively low glass transition temperature, excellent flexibility (the shear modulus may vary between 100 kPa and 3 MPa), very low loss tangent, and high Poisson’s ratio. The mechanical behavior of polymers is usually described by viscoelastic and/or viscoplastic characteristics, depending on time (or frequency) as well as temperature, which make the mechanical response of the polymer systems complicated. A uniaxial tension test, a dynamic mechanical analyzer, and a dynamic mechanical thermal analyzer are commonly used to measure the thermomechanical properties of bulk polymers. In accordance with the extensive applications of thin polymer films, experimental measurements using a nanoindenter and a scanning probe microscope have been widely performed. The indentation method is preferred to the conventional methods due to its easy specimen preparation and experimental procedure, and it makes possible the study of the size effect on the material properties in the micro- and nano-scales. However, indentation experiments can require complicated analysis, depending on the shape of the indenter tips.In this study, a quantitative approach to instrumented nanoindentation to measure the viscoelastic properties of polymer films is developed. The indentation problem of using a circular rigid punch on an elastic film perfectly bonded to a rigid substrate was solved in the authors’ previous work, which provides the relation between the applied force and the penetration depth. With the aid of the elastic-viscoelastic correspondence principle, the force-depth relation for elastic films can be converted into that for viscoelastic films, which enables to obtain the Poisson’s ratio and relaxation modulus of viscoelastic films from indentation experiments. By using the Nano Indenter® XP 'basic creep method' with a flat-ended cylindrical tip made of diamond, 'raw load'-controlled experiments on PDMS (Sylgard 184 Silicone Elastomer from Dow Corning Co.) films were performed. When the specimen shows creep behavior, even though the 'raw load' is held constant, not only the 'displacement into surface' but also the 'load on sample' can gradually change due to the support springs of the Nano Indenter XP® head, which is therefore named as the modified creep experiment. This special head mechanism of the Nano Indenter XP® was taken into account in analyzing the measured experimental data with the force-depth relation, which yields the relaxation modulus of the PDMS film. Residual deformation in the PDMS films after unloading is also measured by scanning the indented PDMS surface with an atomic force microscope.
4:30 PM - **B10.6
Active and Passive Photonic Components on a Silicon Chip.
Michal Lipson 1
1 , Cornell University, Ithaca, New York, United States
Show AbstractPhotonic structures that bend, split, couple and filter light have their flow of light predetermined by the structure design and cannot be modified once fabricated. In order to control the flow of light, modulators and switches need to be developed in silicon where a change in refractive index induces a change in the transmission properties of the device. Here I review our recent results on ultra-fast active devices on silicon, identify the factors determining the speed of the device and discuss schemes for ultra high speed operation.The most effective mechanism for changing the refractive index in Si at a fast rate is the free carrier plasma dispersion effect [1], which also has the advantage of being polarization independent. The induced real refractive index and optical absorption coefficient variations (Δn and Δα, respectively) produced by free-carrier dispersion at a wavelength of 1.55 μm are given by [1] where an electro-refractive changes of Δn~2x10-3 at a wavelength of 1.55 μm can be produced with a depletion or injection of 1018 carriers/cm3. The free-carrier concentration can be varied in Si by injecting or generating carriers. In an electro-optic device we can inject carriers by applying an electric field to the device in order to control the flow of light. In an all-optical device, we can generate carriers within the device using an optical pump source where one optical beam controls the flow of another. In electro-optical devices, the carrier concentration can be varied by injection, accumulation, depletion or inversion of carriers. P-i-n diodes [2] and metal-oxide-semiconductor field-effect-transistors (MOSFET) [3] may be employed for this purpose.In [4] we use a ring resonator as a modulator for achieving high modulation in micron-size structures. For a ring resonator we show that an index change as small as 10-3 is sufficient to tune the resonance by 1 nm and modulate the output intensity of the device by nearly 100%. This index change is achieved by carrier injection. Figure 1 (inset) shows a schematic cross-section of a ridge waveguide with an integrated lateral p-i-n diode for electro-optic modulation. It consists of a ridge waveguide with a p+ region and an n+ region defined in the slab at each side of the ridge. The waveguide is fabricated on a silicon on insulator (SOI) wafer comprising of three layers, one single-crystal layer of silicon, a base silicon substrate and a thin insulator (BOX) that act as bottom cladding and therefore prevents light leakage to the substrate. The silicon layer (device layer) has an n-type background doping concentration of 1015 cm-3, whereas a uniform doping concentration of ~1019 cm-3 for both p+ and n+ regions is considered. A top SiO2 cladding layer covers the whole structure.
5:00 PM - B10.7
Waveguide Couplers Induced Optically over Junction Between Organic Substances.
Andrzej Walczak 1 , Edward Nowinowski-Kruszelnicki 1
1 Institute of Computer Science, Military University of Technology, Warsaw Poland
Show Abstract5:15 PM - B10.8
Sonochemical and Microwave Synthesis and Characterization of ZnS Nanoparticles.
Vijaya Rangari 1
1 center for advanced materials, tuskegee university, Tuskegee, Alabama, United States
Show Abstract