Symposium Organizers
Raj Jammy SEMATECH
Ajit Shanware Texas Instruments, Inc.
Veena Misra North Carolina State University
Yoshitaka Tsunashima Toshiba Corporation
Stefan De Gendt IMEC
E1: Alternate Substrates
Session Chairs
Tuesday PM, April 18, 2006
Room 3008 (Moscone West)
9:30 AM - E1.1
Thermal Stability and Band Alignments for Ge3 N4 Dielectrics on Ge by Direct Atomic Source Nitridation.
S. J. Wang 1 , J. W. Chai 1 , J. S. Pan 1 , A. C. H. Huan 1
1 , Institute of Materials Research & Engineering, Singapore Singapore
Show AbstractBecause of higher low-field intrinsic carrier mobility than that of silicon, Ge and its alloy are attractive for high-frequency applications. The integration of high-k gate dielectrics with high performance substrate or channel materials of Ge and its alloy not only allow the continued scaling of semiconductor devices, but also have the higher mobility to improve device speed. However, Ge oxide is not thermodynamically stable and incorporates too much defect in the film, which hamper the development of high-quality FETs. Recently, high-k gate dielectrics have been fabricated on Ge showing promising results in terms of low equivalent oxide thickness, low leakage current and enhanced hole mobility. But it was also report that Ge would be oxidized to form GeOx to degrade the device performance during high-k gate dielectrics deposition or post annealing process, which hinders the integration of high-k gate dielectrics with Ge. Ge surface Nitridation has been reported to improve the interface stability and electrical properties. In order to apply this Ge-nitride as interface passivation layer to integrate high-k gate dielectrics with Ge and its alloy, some issues related to high temperature thermal stability and band alignment for Ge3N4 on Ge should be well understood. In this report, we present the in-situ Ge3N4 growth through direct atomic source Ge surface nitridation and in-situ photoelectron spectroscopy (XPS) studies of high temperature thermal stability and band alignments at the Ge3N4/Ge interface. The high-k gate dielectric HfO2 has been integrated with Ge by using Ge-nitride buffer layer to improve interface stability and physical performance.
9:45 AM - E1.2
Effects of Nitrogen Reactive Species on Germanium Plasma Nitridation Processes.
Takuya Sugawara 1 2 , Raghavasimhan Sreenivasan 2 , Paul McIntyre 2
1 , Tokyo Electron America Inc., Santa Clara, California, United States, 2 Dept. of Materials Science and Engineering, Stanford University, Stanford, California, United States
Show Abstract10:00 AM - E1.3
Atomic Layer Deposition (ALD) of WN/GdScO3 Stacks for Silicon and Germanium MOS Applications.
Kyoung Kim 1 2 , Philippe de Rouffignac 2 , Roy Gordon 2
1 Division of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, United States, 2 Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States
Show AbstractAtomic layer deposition (ALD) was used to deposit gadolinium scandate, GdxScyO3, a high electric permittivity (high-k) dielectric material, on Si and Ge substrates for possible MOS applications. The new metalorganic precursors Gd tris(N,N’-diisopropylacetamidinate) and Sc tris(N,N’-diisopropylacetamidinate) were used for alternate deposition of Gd2O3 and Sc2O3 mono-layers to form GdxScyO3. We adjusted the atomic ratio of Gd:Sc to be approximately 1:1 and the growth rate was approximately 1.5 Å/cycle at a deposition temperature of 340 °C. To study its feasibility as a dielectric layer for gate stacks and DRAM capacitors, we fabricated Pt/GdxScyO3/Si and Pt/ GdxScyO3/Ge MOS capacitors and measured C-V and leakage current characteristics. An 8 nm thick film had the equivalent oxide thickness (EOT) of 2 nm (k~16) and the leakage current density as low as 1x10-6 A/cm2 at 1 MV/cm. The capacitor showed less than 50 mV hysteresis in C-V curves. ALD WN was also used for gate electrodes and the electrical properties of the complete ALD stack, WN/GdxScyO3/Si(Ge), are compared to those of Pt/GdxScyO3/Si(Ge).
10:15 AM - E1.4
Surface Termination and Roughness of Ge(100) Cleaned by HF and HCl Solutions.
Shiyu Sun 1 2 , Yun Sun 2 , Zhi Liu 2 , Dong-Ick Lee 2 , Samuel Peterson 2 , Piero Pianetta 2
1 Physics Department, Stanford University, Stanford, California, United States, 2 , Stanford Synchrotron Radiation Laboratory, Menlo Park, California, United States
Show Abstract To maintain the rapid scaling of Si CMOS devices, new semiconductor materials are required. Because of its high intrinsic carrier mobility, Germanium (Ge) is a good candidate. In order to incorporate Ge into Si devices, it is essential to understand the Ge surface chemistry and find effective methods to clean and passivate its surface, which has not yet been systematically studied at an atomic level. In this study, Ge(100) surfaces treated by aqueous HCl (10%) and HF solutions with three different concentrations (1:3, 1:5, and 1:25) are systematically studied by synchrotron radiation photoelectron spectroscopy (SR-PES) and atomic force microscopy (AFM) at the Stanford Synchrotron Radiation Laboratory (SSRL). SR-PES results show that clean surfaces without any oxide can be obtained after wet chemical cleaning followed by vacuum annealing with a residual carbon contamination of less than 0.02 monolayer. HF etching leads to a hydrogen terminated Ge surface whose hydrogen coverage is a function of the HF concentration, i.e. solutions with higher HF concentrations leave the Ge surface with higher hydrogen coverage. In contrast, HCl etching yields a chlorine terminated surface, and both Ge monochloride (with a chemical shift of 0.6eV and coverage of 0.29 ± 0.06 ML) and dichloride (with a chemical shift of 1.15eV and coverage of 0.50 ± 0.1 ML) are formed. Possible etching mechanisms will be discussed. We want to point out that neither aqueous HF nor HCl etching alone can lead to an oxygen free or low carbon coverage surface; therefore, final vacuum annealing is needed. The residual carbon and oxygen contaminants come from the solutions, and the HCl treated surface has more contaminants due to its hydrophilic nature. The surface roughness after HF and HCl treatment was also investigated by AFM. AFM results show that the average Root Mean Square (RMS) value of the HCl treated surface is 0.29 ± 0.02 nm, close to that of the sample as received (0.23 ± 0.02 nm), implying the original morphology is preserved. On the other hand, the HF treated surface is rougher with a roughly doubled RMS value (0.6±0.1nm) for all three HF concentrations, which is consistent with Ge back bond breaking during HF etching.
10:30 AM - **E1.5
Wet Chemical Cleaning of Germanium Surfaces for Growth of High-κ Dielectrics.
Yves Chabal 1 , Sandrine Rivillon 1
1 Chemistry and Biomedical Engineering, Rutgers University, Piscataway, New Jersey, United States
Show AbstractOne of the major difficulties preventing the wide use of germanium (epi or bulk) as a gate material is the poor stability of its oxide, leading to reproducibility and reliability issues. In contrast to silicon, the nature and thickness of Ge ``native" oxides are history dependent, and most phases of germanium oxide are water-soluble. As a result, the procedures for passivating Ge surfaces with hydrogen (HF last) are more complex and less forgiving. The H-passivated Ge surfaces are also much less stable in air than H-terminated Si surfaces. We have used infrared absorption spectroscopy and x-ray photoelectron spectroscopy to investigate the nature of oxidized, nitrided and H-terminated Ge surfaces, prior to high-κ dielectrics growth. The GeO2, GeO and nitride phases have been identified and quantified as a function of processing conditions, including ozone oxidation and ammonia nitridation. Various methods to passivate germanium surfaces with hydrogen, chlorine or alkyl molecules have been evaluated and the stability of the H-terminated surfaces has been examined in air and in controlled environments. The initial growth of HfO2 on Ge surfaces has been studied for different starting surfaces using in-situ IR spectroscopy.
E2: Non Hf Based High-k Dielectrics
Session Chairs
Tuesday PM, April 18, 2006
Room 3008 (Moscone West)
11:30 AM - E2.1
Impact of the Composition on the Electrical Properties of MOCVD Crystalline SrTiO3 Thin Films Deposited on Silicon.
Yoann Rozier 1 , Frederique Ducroquet 2 , Sandrine Lhostis 3 , Olivier Salicio 3 , Catherine Dubourdieu 3
1 LPM, INSA de Lyon , Villeurbanne France, 2 IMEP, ENSERG, Grenoble France, 3 LMGP, ENSPG, St Martin d'Heres France
Show Abstract11:45 AM - E2.2
Effect of Nitrogen Incorporation on the Thermal Stability of La, Hf-Aluminate High-k Gate Dielectrics on Si (100).
Prasanna Sivasubramani 1 , Jiyoung Kim 1 , Moon Kim 1 , Bruce Gnade 1 , Robert Wallace 1
1 Electrical Engineering and Physics, University of Texas at Dallas, Richardson, Texas, United States
Show AbstractThe International Technology Roadmap for Semiconductors (ITRS) 2003 predicts the need for the introduction of high dielectric constant (k) gate dielectrics by 2006 to meet continued scaling requirements in metal-oxide silicon field-effect transistor (MOSFET) digital logic technology. Hf, Zr, group III or rare earth oxides with N, Al and/or Si additions have been identified as possible high-k gate dielectric candidates for near term MOSFET scaling. The thermal stability of a high-k dielectric film in direct contact with the underlying Si substrate is essential because out-diffusion of metal impurity atoms into the channel region during processing can cause carrier mobility degradation and affect the electrical performance of an integrated circuit. Evaluation of the thermal stability of molecular beam deposited LaAlO3 thin films shows crystallization and out-diffusion of La and Al into a Si (100) substrate when subjected to rigorous rapid thermal anneals (RTA) at or above 950 oC, 20 sec. in N2 ambient. In this study, nitrogen is incorporated into the La- and Hf-aluminate thin films and at the Si (100) interface using reactive sputter deposition in Ar + N2 from suitable ceramic sputter targets. The effect of nitrogen incorporation on the crystallization and metal out-diffusion into Si (100) are evaluated using high resolution transmission electron microscopy, x-ray photoelectron spectroscopy, x-ray diffraction, electrical measurements and/or secondary ion mass spectroscopy. Thermal stability studies after a 1000 oC, 10s N2 RTA indicate suppression of crystallization for LaAlON thin films with a relative nitrogen concentration of ~3%. This work is supported by the Semiconductor Research Corporation (SRC) FEP Transition Center.
12:00 PM - E2.3
Alumina-Aluminum titanate-Titania Nanocomposites as Mid-Range High-k Dielectrics
Vikas Somani 1 , Samar Kalita 1
1 MMAE, University of Central Florida, Orlando, Florida, United States
Show AbstractIn this research, we have synthesized alumina-aluminum titanate-titania nanocomposites via a sol-gel process using aluminum propoxide and titanium propoxide as precursors and characterized it for applications as high-k dielectrics. Propanol and 2-methoxy ethanol were used as solvent and stabilizer, respectively. The aged gel obtained was heat-treated at 400oC to obtain amorphous powder, which was subsequently calcined at 600-900oC to produce crystalline powder. Phase evolution and crystal structure of the powder were determined using XRD. HR-TEM and SEM studies were performed to obtain information on powder morphology. XRD analysis showed sharp peaks of Al2O3 and TiO2 with small amount of Al2TiO5 in samples calcined at 900oC. HR-TEM results of the calcined powder showed agglomerates of powder particles with particle size in 15-20 nm range. Uniaxially pressed pellets were sintered at elevated temperatures (900-1500oC) to understand densification behavior and phase composition/transformation. Increase in the sintering temperature above 900oC resulted in the decomposition of Al2TiO5 into Al2O3 and TiO2. Dielectric constant and dissipation factor of the sintered pellets were measured using HP 4284A impedance-capacitance-resistance (LCR) meter and 16451 B dielectric test fixture at frequencies in the range 1 KHz to 1 MHz. The effects of sintering time, temperature and phases present on the electrical properties were studied. Increase in sintering temperature resulted in better electrical properties. This oral talk will present our recent findings on alumina-aluminum titanate-titania nanocomposite as an alternate mid-range high-k (10 ≤ k ≤ 100) material for microelectronic applications.
12:15 PM - E2.4
Field Effect Transistors with Epitaxial SrHfO3 as Gate Oxide.
Christophe Rossel 1 , B. Mereu 1 , C. Marchiori 1 , D. Caimi 1 , M. Sousa 1 , A. Guiller 1 , H. Siegwart 1 , R. Germann 1 , J.-P. Locquet 1 , J. Fompeyrine 1 , D. J. Webb 1
1 Science and Technology, IBM Research GmbH, Zurich Research Laboratory, CH-8803 Rueschlikon Switzerland
Show AbstractWe demonstrate that the compound SrHfO3 grown epitaxially on Si(100) by molecular beam epitaxy (MBE) is a good gate dielectric to fabricate n- and p-metal oxide semiconductor field effect transistors (MOSFET) with equivalent oxide thickness EOT below 1 nm. Despite a larger lattice mismatch with Si (~6%), SrHfO3 has the advantage to have a larger band gap (> 5 eV) and higher conduction band offset (~1 eV) than SrTiO3. The typical stack investigated is made of 4 nm of SrHfO3 deposited on a template layer of 0.5 nm SrO on Si. A multi-step deposition process is used to achieve high quality epitaxial films with minimal interfacial oxidation of the Si. The film quality and the nature of the interface were analyzed by XRD and XPS. On average a rms film roughness of 2.5 Å over 4 μm2 was found by AFM imaging. In capacitors fabricated with Pt electrodes, we found leakage currents below 10-6 A/cm2 at VFB ± 1V and an EOT~ 0.7 nm from capacitance data C(V) in accumulation. Non-self-aligned long-channel FETs were fabricated with channel lengths and widths in the range 2 to 100 μm. We found in nFETs effective peak electron mobilities up to μe~ 30 cm2/Vs and in pFET hole mobilities up to μh~ 60 cm2/Vs. These still low mobility values are explained mainly by the excessive interface charge trapping density Dit, in the range 1013 eV-1cm-2, as measured by charge pumping as well as conductance techniques. Comparison is made with the literature data that display a clear reduction of mobility with decreasing EOT, explained mainly by the remote Coulomb and phonon scattering mechanisms.
12:30 PM - E2.5
Plasma-Assisted Atomic Layer Deposition of Al2O3 Films for System-in-Package Applications.
W. M. M. Kessels 1 , S.B.S. Heil 1 , E. Langereis 1 , J. Klootwijk 2 , F. Roozeboom 2 , M.C.M. van de Sanden 1
1 Dept. of Applied Physics, Eindhoven Univ. of Technology, Eindhoven Netherlands, 2 , Philips Research Laboratories, Eindhoven Netherlands
Show AbstractA plasma-assisted atomic layer deposition (PA-ALD) process of Al2O3 has been developed using trimethylaluminum dosing and O2 plasma exposure. The method of ALD, with its thickness control, uniformity and conformality in high-aspect ratio structures, is very valuable for heterogeneous and passive integration of high-density MOS decoupling capacitors in RF System-in-Package (SiP) applications [1]. Here, the Al2O3 ALD can be used as dielectrics in the MOS trench capacitor, to increase the capacitance per unit of area with respect to conventional silicon-oxide/nitride/oxide dielectric stacks. At the same time, the Al2O3 can electrically insulate through-wafer vias used for interconnect applications in multiple-die stacks. The advantages of the plasma-assisted ALD process are improved material properties, the possibility to deposit the material at low temperatures (down to room temperature) without the need for extremely long purge times, and the absence of poor water transport with regard to thermal ALD in very high-aspect ratio (>20) features as used for the high-density MOS capacitors [2]. For PA-ALD of Al2O3 growth rates of around 1 Å/cycle were obtained with a slightly increasing growth rate when going to lower substrate temperatures. These growth rates are similar to those obtained by thermal ALD indicating that the adsorption of trimethylaluminum and in particular the steric hindrance of the surface CH3-groups controls the maximum growth rate of the ALD process. Results on the film composition, determined by nuclear analysis techniques, and the electrical performance of Al2O3 stacks, investigated by J-V and C-V measurements, will be discussed paying particular attention to the Si-Al2O3 interface properties. Furthermore, fundamental insight into the PA-ALD process of Al2O3 will be presented as obtained by plasma studies such as Langmuir probe measurements and (time-resolved) optical emission spectroscopy as well as by in situ film studies using spectroscopic ellipsometry and quartz-crystal microbalance measurements. The surface reactions with respect to CH3 removal by the plasma after trimethylaluminum dosing will be discussed on the basis of the mass increase and the emission by hydrocarbon fragments immediately after striking the plasma.[1] F. Roozeboom, A. Kemmeren, J. Verhoeven, E. van den Heuvel, H. Kretschman and T. Frič, Mat. Res. Soc. Symp. Proc. 783, 157 (2003). [2] J. Klootwijk, A. Kemmeren, R. Wolters, F. Roozeboom, J. Verhoeven and E. van den Heuvel, "Defects in Advanced High-κ Dielectric Nano-Electronic Semiconductor Devices", (E. Gusev, Ed.), Springer, Dordrecht, 2006, pp. 17-28.
12:45 PM - E2.6
SrTiO3–based Epitaxial Oxides on Si: Impact of Oxygen Stoichiometry on Interface Stability and Electrical Behavior.
Gerd Norga 1 2 , Christophe Rossel 2 , Chiara Marchiori 2 , Jean-Pierre Locquet 2 , Jean Fompeyrine 2 , Alexandre Guiller 2 , J. W. Seo 3 , Ch. Dieker 3
1 L-NESS, Politecnico di Milano, Como Italy, 2 Science and Technology, IBM Research GmbH, Rueschlikon Switzerland, 3 IPMC, EPFL, Lausanne Switzerland
Show AbstractE3: Gate Stack Reliability
Session Chairs
Tuesday PM, April 18, 2006
Room 3008 (Moscone West)
2:30 PM - **E3.1
Reliability Issues Associated with Metal Gates and High-k Gate Dielectrics
Joe McPherson 1
1 SiTD, Texas Instruments, Dallas, Texas, United States
Show AbstractCMOS scaling success has depended largely upon the reliability robustness of the Poly/SiO2 gate stack. However, the nitrided SiO2 gate dielectrics (used today) have been thinned to the point (~1.2nm) where the gate dielectric is very leaky, difficult control, can suffer from gate-edge and boron penetration issues. Also, transistor performance can suffer from the fact that a significant percentage of the gate voltage is now being dropped in the Poly rather than in the gate oxide and substrate. Several important gate-dielectric reliability issues such as stress-induced leakage current (SILC), soft breakdown and negative-bias temperature instability (NBTI) are starting to become very important. To eliminate/mitigate these issues, significant materials research is being conducted on metal gates and high-k gate dielectrics. High-k gate dielectrics permit a much thicker film to be used for the same gate-oxide equivalent thickness. Thicker films generally provide for: more process margin, reduced gate leakage, and less boron penetration issues. Metal gate electrodes potentially have lower voltage drop in the gate material and the wide range of metal work functions available permits separate device matching to n-type and p-type silicon. However, there are several reliability concerns associated with the metal gate electrodes (adhesion, film stresses, implant damage, work function stability, etc.) and high-k gate dielectrics (TDDB, NBTI, PBTI, CHC, plasma charging, etc.). During this presentation, the major reliability issues associated with metal gates and high-k will be discussed.
3:00 PM - E3.2
Investigation of NBTI Recovery During Measurement.
Robert Entner 1 , Tibor Grasser 1
1 Christian Doppler Laboratory for TCAD in Microelectronics, TU Wien, Wien Austria
Show AbstractNegative bias temperature instability (NBTI) has come to the forefront of not only academic but also industrial interest. It is well known that themeasurement technique used for evaluating NBTI degradation can have aconsiderable impact on the life-time extrapolation results [1,2]. In this workwe present, for the first time, a rigorous investigation of the NBTI recoveryprocess during measurement intervals in comparison to the numerical solution ofan extended reaction-diffusion (RD) model. In contrast to previous work, theRD model has been implemented in a multi-dimensional device simulator and issolved self-consistently together with the semiconductor device equations.This allows us to directly use many commonly approximated quantities such asthe interface hole concentration and the oxide electric field. In addition,the influence of the trapped charges can be more accurately considered by usinga distributed Shockley-Read-Hall interface trap-charge model [3,4] which hasbeen coupled to the RD model. Thus, due to the self-consistent solutionprocedure, also the feedback of these charged interface-states on the Poissonequation is considered which we show has a significant influence on theobserved threshold voltage shift.This novel approach allows us to directly simulate a measurement cycle byalternating stressing and measuring intervals. Hereby, the complete dynamicsof the process are considered. In particular, the method allows us to studythe influence of the measurement method on the degradation. The importantadvantage is that the threshold voltage can now be extracted from thesimulation results in the same way as is done in real measurements rather thanthrough simplistic estimations via the generated interface states.It is confirmed that the use of complete Id/Vg sweeps introduces undesiredadditional stress and relaxation periods which interfere with the measurementresults [5], in particular for long measurement times (larger 1s). Instead,the drain-current at a gate-voltage close to Vth is measured and the realthreshold-voltage is approximated by using the initial Id/Vg characteristic[2]. This method drastically decreases the necessary measurement time and,thus, increases the accuracy of life-time extrapolation. We explain themethods in detail and compare the results with the "ideal" measurement withzero recovery.[1] B. Kaczer et al., in Proc. IRPS (San Jose, 2005), pp. 381-387.[2] M. Ershov et al., Appl.Phys.Lett. 83, 1647 (2003).[3] W. Shockley and W. T. Read, Phys.Rev. 87, 835 (1952).[4] R. N. Hall, Phys.Rev. 87, 387 (1952).[5] M. A. Alam, IEDM Tech. Digest, p. 345 (2003).
3:15 PM - E3.3
Interfacial Reaction-Related Intrinsic PBTI and NBTI in HfN/HfO2 Gate Stacks Caused by High Temperature Process.
Kang Jinfeng 1 , Ning Sa 1 , Hong Yang 1 , Xiaoyan Liu 1 , Xing Zhang 1 , Ruqi Han 1 , Chi Ren 2 , Hongyu Yu 3 , D.-L. Kwong 4
1 Institute of Microelectronics, Peking University, Beijing China, 2 Silicon Nano Device Lab, Dept. of ECE, National University of Singapore, Singapore Singapore, 3 , IMEC, Leuven Belgium, 4 , The University of Texas at Austin, Austin, Texas, United States
Show Abstract3:30 PM - E3.4
Electron Trapping in N Incorporated Hf-based Gate Stacks
Gennadi Bersuker 1 , Chadwig Young 1 , Patrick Lysaght 1 , Rino Choi 1 , Manuel Quevedo-Lopez 1 , Paul Kirsch 1 , Byoung Hun Lee 1
1 , SEMATECH, Ausitn, Texas, United States
Show AbstractHigh-k gate stacks are usually represented by the multilayer structures, which include, besides a transition metal oxide dielectric, interfacial layers between the dielectric and the electrode and substrate. Such a multilayer structure, properties of each of its components being strongly process dependent, significantly complicates evaluation of the intrinsic electrical characteristics of the gate stack. In particular, an important consequence of weak covalent bonding in transition metal oxides is the potentially high density of as-grown structural defects in high-k dielectrics. Some defects may represent electron traps capable of capturing injected electrons, which would lead to instability of the transistor electrical properties (e.g., threshold voltage). This instability demonstrates peculiar dependences on the dielectric composition (% of SiO2 component in Hf-silicates, N content, etc.), morphology, thickness, etc., all of which still lack comprehensive understanding. These affects should be studied in the context of the metal oxide’s tendency to phase separate and crystallize. Since defect energy levels, and their electrical activity, seems to be primarily determined by the defect’s nearest environment rather than by long-range crystal order, charge trapping characteristics can be expected to be modulated by adding defect passivating agents, like N. On the other hand, N, when introduced in the film under certain conditions, has been reported to suppress dielectric crystallization, which is suspected to affect electron trapping. In this study, in order to understand the role of N in reducing electron trapping, we evaluate electron trapping versus N content in the high-k dielectrics fabricated by different N incorporation methods. The employed fast pulsed I-V technique allows profiling of the high-k dielectric film while avoiding contribution from the interfacial layers.
3:45 PM - E3.5
Incorporation of Fluorine in high-k (HfO2/SiO2) and its Impact on Electrical Properties.
Kang-ill Seo 1 , Raghavasimhan Sreenivasan 1 , Paul McIntyre 1 , Krishna Saraswat 2
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Stanford Univeristy, Stanford, California, United States
Show AbstractEven though many promising results on HfO2-based high-k dielectrics have been reported, many critical obstacles still remain in implementing them in Si CMOS technology. The potential reliability issues for these new dielectrics include negative bias temperature instability (NBTI), which is known to result from generation of interface traps and positive oxide charges in metal-oxide-silicon (MOS) structures under negative bias, especially at elevated temperature. In the SiO2/Si system, extensive studies have been performed to understand and reduce NBTI. It has been shown that the introduction of fluorine at the SiO2/Si interface improves NBTI by forming Si-F bonds which are more stable against hot carrier stressing than are Si-H bonds. In this work, we report the result of incorporating fluorine and engineering its profile in HfO2/SiO2 gate stacks and the impact on electrical properties such as capacitance-voltage (C-V), gate leakage current density-voltage (J-V), and NBTI.HfO2 was deposited by atomic-layer-deposition (ALD) using Hf[(C2H5)2N]4 and water precursors at 150oC on Si substrate with 1.5nm chemical-SiO2 passivation of Si (100) wafers. For fluorine incorporation, the samples were annealed in the dilute F2 gas ambient (3.5% F2 / 96.5% He) at the temperature range of R.T. ~ 400oC with ultraviolet (UV) light. Angle resolved XPS spectra show that F tends to diffuse from the surface to the bulk of HfO2 and formation of surface F species such as CFx is suppressed as the anneal temperature increases. C-V and J-V results indicate negative oxide charges and leakage current density increase proportional to the amount of F in HfO2/SiO2. However, we demonstrate that if F concentration profile is properly engineered to be localized at the HfO2 and SiO2 interface, NBTI behavior is remarkably improved without degrading flat band voltage and leakage current. We report significantly less C-V hysteresis, positive charge trapping and interface states generation in the sample with F compared to the control sample without F under the same negative bias stressing conditions. The mechanism for NBTI improvement with F will be discussed.
E4: Gate Electrode I
Session Chairs
Tuesday PM, April 18, 2006
Room 3008 (Moscone West)
4:30 PM - **E4.1
Impact of Electrode-side Chemical Structure on Electron Mobility in Metal/HfO2 MISFETs.
Yasushi Akasaka 1 , Kazuhiro Miyagawa 1 2 , Takaoki Sasaki 1 3 , Kenji Shiraishi 4 5 , Satoshi Kamiyama 1 , Osamu Ogawa 1 , Fumio Ootsuka 1 , Yasuo Nara 1
1 Reaearch Dept. 1, Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan, 2 , Present Affiliation: Sanyo Semiconductor Manufacturing Co.,Ltd., Anpachi, Gifu, Japan, 3 , Present Affiliation: Seiko Epson Corporation, Sakata, Yamagata, Japan, 4 Institute of Physics, University of Tsukuba, Tsukuba, Ibaraki, Japan, 5 Nanomaterials Lab., National Institute for Materials Science, Tsukuba, Ibaraki, Japan
Show AbstractMobility degradation of nMISFETs is one of the main concerns regarding metal/high-k gate MISFETs. The electron mobility is degraded with EOT scaling, whereas hole mobility remains constant even in sub-1nm EOT region. Scattering mechanisms of carriers in metal/high-k MISFETs have been extensively studied. However, the change in the chemical structure of HfO2 after gate stack formation has not been fully investigated. We found that TaSiX gate electrode has excellent properties for n-metal from the viewpoints of both electron mobility and effective work function. In this study, by comparing the electron mobility of TiN MISFETs, TiN being one of the most popular metal gate materials, and TaSiX MISFETs, the impacts of gate material and deposition process were studied.MISFETs were fabricated by the replacement gate process. After HF-last cleaning, 2.5-3nm-thick HfO2 films were deposited directly on Si by ALD at 275°C, followed by plasma oxidation at 400°C. TaSiX(15nm)/TiN(10nm)/W(100nm) and TiN(10nm)/W(100nm) were deposited as gate electrodes. To avoid complexity due to EOT thickening caused by high-temperature process, all the process steps after HfO2 formation were performed at temperatures lower than 450°C. Effective mobility was measured for these MISFETs. Chemical structure of the metal/HfO2 stacks after gate formation was analyzed by x-ray photoelectron spectroscopy (XPS) from channel-side (backside XPS). Si substrate was selectively etched off to the interfacial SiO2 layer (IL).Electron mobility of the TaSiX/HfO2 MISFET is much larger than that of TiN/HfO2 MISFET in the low carrier density region. Temperature dependence of the electron mobility was also examined. At high temperatures, the mobility of the TaSiX MISFET approaches that of TiN MISFET. The temperature dependence of the additional scattering factor of the TiN MISFETs, by 1/μadditional =1/μTiN-1/μTaSix, is calculated. The additional factor shows very weak temperature dependence at around room temperature. It strongly suggests that the principal cause of the low mobility in TiN/HfO2 MISFETs is Coulomb scattering.The main difference between the backside XPS Hf4f spectra taken from TiN/HfO2 and TaSiX/HfO2 is the component corresponding to HfOX (X<2: HfO2 with oxygen vacancies) or Hf-N observed in the electrode-side of the TiN/HfO2 stack. The integral intensity of the component is about 14% of total Hf4f signal.To separate the effect of Hf-N bond, effects of additional nitridation after HfO2 formation are examined. TiN MISFET shows larger mobility degradation than TaSiX MISFET. Nitridation itself doesn’t cause mobility degradation. The fixed charge due to oxygen vacancy formation is thought to be a cause of Coulomb scattering. This assumption coincides with the results of electrical measurement of MISFETs with and without additional nitridation. Deoxidation during TiN-CVD deposition is one of the possible causes of the formation of the oxygen vacancy.
5:00 PM - E4.2
High Temperature Post Si-Deposition Annealing for FUSI/High-k MOSFET with 1nm-EOT.
Masashi Takahashi 1 , Hideki Satake 1 , Masaru Kadoshima 1 , Arito Ogawa 1 , Hiroyuki Ota 2 , Kunihiko Iwamoto 1 , Toshihide Nabatame 1 , Akira Toriumi 2 3
1 , MIRAI-ASET, Tsukuba Japan, 2 MIRAI-ASRC, AIST, Tsukuba Japan, 3 , The University of Tokyo, Tokyo Japan
Show AbstractWe have achieved excellent MOSFET characteristics with an electron mobility of 200 cm2/Vs @0.8MV/cm in FUSI NiSi/HfAlON MOSFETs with 1nm EOT. The high temperature annealing process after amorphous Si deposition on high-k is very effective for improving the electron mobility as well as suppressing additional interface layer (IL) formation. We fabricated 1.0nm EOT HfAlON dielectrics by the LL-D&A process [1] in combination with the HiTOA process [2], followed by amorphous Si deposition. After Ni deposition on the amorphous Si layer, FUSI NiSi gate electrode was formed at 400°C [3]. Two kinds of high temperature annealing processes before the silicidation process were employed; one was post deposition annealing (PDA) from 1000 to 1050°C in N2 ambient for 0.1 sec after fabricating HfAlON, while the other was post silicon deposition annealing (PSA) from 950 to 1050°C in N2 for 20 sec just after growing amorphous Si. We found that the PDA treatment above 1000°C improved the mobility, while it increased EOT by 0.5nm due to additional IL growth caused by unavoidable residual oxygen in a chamber. Thus, high temperature PDA is not suitable for realizing a sub-1nm EOT. On the other hand, in the case of the PSA, EOT increase was negligibly small. Moreover, the high temperature PSA significantly improved the electron mobility from 120 cm2/Vs (without PSA) to 200 cm2/Vs (with 1050°C PSA) in addition to densification of the film. In the PSA process, it is inferred that the unavoidable residual oxygen in the chamber was blocked by the Si capping layer, so additional IL growth was suppressed. This implies that the film quality was drastically improved by high temperature annealing possibly due to the structural relaxation and the reduction of defects sites in high-k and IL.It is shown that the high temperature annealing with a Si capping layer is quite effective for achieving the high mobility FUSI gate MOSFETs for a sub-1nm EOT region.This work was supported by NEDO. [1] T. Nabatame et al., Symp. VLSI Tech., 2003, p. 25. [2] K. Iwamoto et al., IWDTF, 2004, p. 15. [3] M. Kadoshima et al., Symp. VLSI Tech., 2005, p. 70
5:15 PM - E4.3
The Thermal Stability Studies of FUSI NiSi with Dopants on Silicon on Insulator (SOI) for 45 nm CMOS and Beyond.
Penghui Zhao 1 , Moon Kim 1 , Bruce Gnade 1 , Robert Wallace 1
1 Electrical Engineering , University of Texas at Dallas, Richardson , Texas, United States
Show AbstractFully silicided (FUSI) NiSi as a dual metal gate has received significant attention due to low resistivity, scalability, and work function tunability by doping Poly-Si with proper dopants [1-3]. However, there remain many challenges for the integration of FUSI NiSi metal gates, such as phase stability, incomplete silicidation and possible impurity diffusion. The interdiffusion of Ni from FUSI NiSi through dielectrics into the underlying Si substrate (channel) has been recently reported [4]. In this presentation, the thermal stability studies of FUSI NiSi with Arsenic or Boron dopants on Silicon on Insulator (SOI) were investigated. After the stack is subjected to a typical back-end of line (BEOL) annealing (400oC, 30-240 min), the abnormal oxidation of FUSI NiSi with As-doped was observed by XPS and confirmed by HRTEM. Arsenic out-diffusion is also observed by XPS. XRD results show Ni rich phases like Ni3Si were formed during abnormal oxidation of FUSI NiSi. In contrast to As-doped stacks, no phase transformation and abnormal oxidation are observed for Boron-doped stacks. However, backside SIMS results suggest Boron penetration through a 3 nm SiON layer into the Si channel after 400oC 4 hrs N2 annealing. In addition, sheet resistance of FUSI NiSi, Ni and As diffusion results will also be presented, and the possible diffusion mechanism will be discussed. This work is supported in part by IBM and the Semiconductor Research Corporation Front End Transition Center.1. Z. Krivokapic, W. Maszara, F. Arsnia, E. Patron, Y. Kim, L. Washington, et al., IEEE VLSI 2003, p. 131-132 (2003)2. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, et al., IEEE IEDM 2002, p.247-250 (2002)3. C. Cabral, Jr., J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozlowski, R. Carruthers, and R. Jammy. 2004 Symposium on VLSI Technology Digest of Technical Papers, p.184-1854. P. Zhao, I. Trachtenberg, M. J. Kim, B. E. Gnade, and R. M. Wallace, submitted to Electrochem. Sol. State Letters (2005)
5:30 PM - E4.4
Impact of TiN/HfO2 Integration on Carrier Mobility.
Mikael Casse 1 , L. Thevenod 1 , B. Guillaumot 2 , L. Tosti 1 , F. Martin 1 , J. Mitard 2 , O. Weber 3 , F. Andrieu 1 , T. Ernst 1 , G. Reimbold 1 , T. Billon 1 , M. Mouis 4 , F. Boulanger 1
1 , CEA-DRT/LETI, Grenoble France, 2 , STMicroelectronics, Crolles France, 3 , LPM-INSA Lyon, Lyon France, 4 , IMEP (CNRS/INPG/UJF JRU), Grenoble France
Show Abstract5:45 PM - E4.5
A Systematic Approach of Understanding and Retaining PMOS Compatible Work Function of Metal Gate Electrodes on HfO2 Gate Dielectrics
Rashmi Jha 1 , Jiyoung Choung 2 , Robert Nemanich 2 , Veena Misra 1
1 Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 Department of Physics, North Carolina State University, Raleigh, North Carolina, United States
Show AbstractIn this work we performed Ultraviolet Photoelectron Spectroscopy (UPS) and X-Ray Photoelectron Spectroscopy (XPS) on: (i) 40Å of Ru deposited on 20Å of ALD-HfO2/p-silicon (40Å-Ru/ 20Å-HfO2/p-Si), and (ii) 40Å of W deposited on 20Å of ALD-HfO2/p-silicon (40Å-W/ 20Å-HfO2/p-Si) in as deposited as well as after 600οC anneal in the UPS chamber. The samples were exposed to atmosphere before UPS and XPS resulting in an adsorbed layer of oxygen atoms on the surface. For 40Å-Ru/ 20Å-HfO2/p-Si, UPS showed decrease in the surface work function of Ru and the corresponding XPS showed significant reduction in the oxygen content on the surface of Ru, and shift in Hf peak towards higher binding energy after anneal as compared to the as-deposited state. The reduction in the oxygen content can be attributed to the transport of oxygen atoms from the surface of Ru to HfO2/Si interface after anneal. The shift in the binding energy of Hf after anneal can also be related to the oxygen transport. The higher surface work function of Ru, as obtained from UPS analysis in as-deposited state, can be due to the charge transfer from Ru to the adsorbed oxygen atoms on the surface of Ru leading to the formation of dipole causing high effective work function of Ru or due to the formation of RuOx on the surface having higher work function than Ru. After anneal, Ru-O charge transfer on the surface can be inhibited due to the transport of oxygen atoms from the surface of Ru to the HfO2/Si interface causing reduction in the surface work function of Ru. However, UPS analysis of 40Å-W/ 20Å-HfO2/p-Si sample showed significant increase in the surface work function of W after anneal as compared to the as-deposited state. The corresponding XPS showed no significant change in the oxygen content on the surface of W and small shift in Hf peak towards higher binding energy after anneal as compared to the as deposited state. The XPS showed clear peaks of WOx in as deposited state which broadened after anneal indicating the existence of multiple oxides of W after anneal. From these important observations, we conclude that:(i) Ru-O charge transfer is necessary at Ru/HfO2 interface to achieve high effective work function compatible for PMOS applications, (ii) Any thermal treatment can cause transport of oxygen atoms from the surface of HfO2 to HfO2/Si interface which in turn can cause Ru to exchange charge with oxygen vacancies or Hf, and (iii) mono-layers of W between Ru and HfO2 can retain oxygen and allow Ru-O bonding having high effective work function.
E5: Poster Session
Session Chairs
Raj Jammy
Shriram Ramanathan
Wednesday AM, April 19, 2006
Salons 8-15 (Marriott)
9:00 PM - E5.1
Systematic Characterization of Ni Full Silicide in Sub-100 nm Gate Regions.
Daisuke Ito 1 , Akira Sakai 1 , Osamu Nakatsuka 2 , Hiroki Kondo 1 , Yasushi Akasaka 3 , Masaki Ogawa 4 , Shigeaki Zaima 1
1 Graduate School of Engineering, Nagoya University, Nagoya Japan, 2 EcoTopia Science Institute, Nagoya University, Nagoya Japan, 3 , Semiconductor Leading Edge Technologies, Inc., Tsukuba Japan, 4 Center for Cooperative Research in Advanced Science and Technology, Nagoya University, Nagoya Japan
Show AbstractNi full silicide (FUSI) is one of promising candidates for a metal gate in nano-scale metal-oxide-semiconductor (MOS) field effect transistors to eliminate ploy-Si gate electrode depletion. Introduction of NiSi using the salicide process to the metal gate requires a precise control of silicidation locally occurring in sub-100 nm scaled gate electrode regions. However, the mechanism of solid-phase reaction between Ni and Si in such a microscopically localized space has not been clear yet and the elucidation of it is an important issue for reducing fluctuation of the gate electrode work function. In this work, we investigated systematically crystallographic structures of Ni silicides in the local region of actual sub-100 nm MOS structures.Poly-Si (100 nm) / SiO2 (5 nm) gate stacks with a gate length (Lg) ranging from 70 to 150 nm were formed on a Si(001) substrate. The top surface of the gate stacks was subjected to chemical mechanical polishing after pre-metal dielectrics deposition. A TiN (10 nm)/ Ni (65 nm) film was then formed by physical vapor deposition on the surface for the silicidation of gate electrodes. The samples were annealed in a conventional quartz furnace or a rapid thermal annealing system in N2 ambient. Transmission electron microscopy (TEM) and diffraction (TED), energy dispersive X-ray spectroscopy, and X-ray diffraction (XRD) were performed for analysis.TEM observation showed the formation of NiSi and Ni2Si as well as non-reacted poly-Si at the bottom of the gate region after annealing at 350°C for 30 min. 500°C-annealing resulted in full reaction between Ni and Si and resultant FUSI layers consisted of a two-layered structure; there were smaller grains at the bottom and larger ones at the top. On the other hand, higher temperature annealing, for example at 700°C, led to FUSI grains which were more homogeneous textures and sizes as large as Lg. Microscopic analysis using TED revealed silicide phases which were different from those observed by XRD for macroscopic areas of Test Elementary Group chips. For example, silicide phases of NiSi, Ni2Si and Ni5Si2 were mainly observed in the XRD spectra of the sample annealed at 700°C, but Ni3Si was actually detected by TED for the gate region of Lg=70 nm. The volume expansion ratio (VER) of the non-silicided poly-Si region to the resultant silicided region was also estimated for various samples. VER strongly depends on the formed phase of Ni silicide and was found to increase with decreasing Lg and the annealing temperature. The lateral diffusion of excess Ni atoms into the finite gate region should cause the unexpected formation of the Ni-rich silicide. The authors acknowledge ASUKA Line Groups for preparation of TEM samples.
9:00 PM - E5.10
Preparation and Characterization of Rare Earth Scandate Thin Films as an Alternative Gate Dielectric.
Martin Wagner 1 , Tassilo Heeg 1 , Juergen Schubert 1 , Matty Caymax 2 , Chao Zhao 2 , Steffi Lenk 1 , Siegfried Mantl 1
1 Institute of Thin Films and Interfaces (ISG), Research Center Juelich, Juelich Germany, 2 , IMEC, Leuven Belgium
Show Abstract9:00 PM - E5.11
Dielectric Properties of Rare-Earth Metal Oxides
Chao Zhao 1 , An Hardy 2 , Sheron Shamuilia 3 , Valery Afanas'ev 3 , Marlies Van Bael 2 4 , Jules Mullens 2 , Stefan De Gendt 1 5 , Matty Caymax 1
1 SPDT, IMEC, Leuven Belgium, 2 , Hasselt University, Diepenbeek Belgium, 3 Dept. Physics, University of Leuven, Leuven Belgium, 4 , IMEC vzw Division IMOMEC, Diepenbeek Belgium, 5 Dept. Chemistry, University of Leuven, Leuven Belgium
Show AbstractPromising properties for high-k applications have been demonstrated with rare-earth metal (RE) scandate DyScO3 and GdScO3 [1-2]. In this work, a series of RE-oxides, including Sm2O3, Eu2O3, Pr2O3, Nd2O3, and La2O3, have been prepared using sol-gel technique on Si wafers, to study the dielectric properties of these materials. The phase compositions of the layers were studied using grazing incidence XRD. The band gap of the RE-oxides was defined by measuring the photoconductivity spectra of the layers. The K-value of the RE oxides was extracted from C-V measurement. It is found that all the layers after annealing in O2 at 750°C for 1 hour are crystalline. The crystalline phase for the five different oxides is monoclinic Sm2O3, cubic Eu2O3, cubic Pr6O11, hexagonal Nd2O3 and cubic La2O3, respectively. The layer of Pr6O11 is too leaky to measure the bandgap and C-V curves. The other RE-oxides show similar band structures and dielectric constants. References: 1.V. V. Afanas’ev et. al. APL 85, (2004)59172.C. Zhao et. al. APL 86 (2005) 132903
9:00 PM - E5.12
Synthesis of Highly Thermal Stable ultra-thin HfO2 by Combination of High Concentration Ozone Oxidation and Nitrogen Incorporation.
Lei Wang 1 , Kun Xue 1 , Jianbin Xu 1 , Anping Huang 2 , Paul Chu 2
1 Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong Hong Kong, 2 Department of Physics and Materials Science, City University of Hong Kong, Hong Kong Hong Kong
Show Abstract9:00 PM - E5.13
Chemical Vapor Deposition of ZrxTi1-xO and HfxTi1-xO Thin Films Using the Composite Anhydrous Nitrate Precursors.
Qi-Yue Shao 1 2 , Ai-Dong Li 1 2 , Di Wu 1 2 , Zhi-Guo Liu 2 3 , Nai-Ben Ming 2 3
1 Materials Science and Engineering Department, Nanjing University, Nanjing, Jiangsu, China, 2 National Laboratory of Solid State Microstructures , Nanjing University, Nanjing, Jiangsu, China, 3 Physics Department, Nanjing University, Nanjing, Jiangsu, China
Show Abstract9:00 PM - E5.14
Nitridation of HfO2 Grown on Ge (100) Substrates by Atomic-Layer Deposition.
Kwun Bum Chung 1 2 , Chung Nam Whang 1 , Mann-Ho Cho 2 , Dae-Won Moon 2 , Dae-Hong Ko 3
1 Institute of Physics and Applied Physics, Yonsei University, Seoul Korea (the Republic of), 2 Nano Surface Group, Korea Research Institute of Standards and Science, Daejeon Korea (the Republic of), 3 Ceramic Engineering, Yonsei University, Seoul Korea (the Republic of)
Show Abstract9:00 PM - E5.15
Suppression of Phase Separation for Hf-silicate Films Using NH3 Annealing Treatment.
Kwun Bum Chung 1 2 , Chung Nam Whang 1 , Mann-Ho Cho 2 , Dae Won Moon 2 , Chan-Jung Yim 3 , Dong Chan Seo 3 , Dae-Hong Ko 3
1 Institute of Physics and Applied Physics, YONSEI UNIVERSITY, Seoul Korea (the Republic of), 2 Nano Surface Group, Korea Research Institute of Standards and Science, Daejeon Korea (the Republic of), 3 Ceramic Engineering, YONSEI UNIVERSITY, Seoul Korea (the Republic of)
Show Abstract9:00 PM - E5.17
Metal Transport and Loss in Hafnium and Lanthanum Aluminate Films on Si Hampered by Thermal Nitridation.
Leonardo Miotti 1 , Carlos Driemeier 1 , Felipe Tatsch 1 , Claudio Radtke 2 , Krug Cristiano 3 , Israel Baumvol 4 , Vincent Edon 5 , Marie Hugon 5 , Bernard Agius 5 , Robert Wallace 6
1 Instituto de Fisica, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil, 2 Pos-Graduacao em Microeletronica, Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil, 3 Department of Physics, North Carolina State University, Raleigh, North Carolina, United States, 4 , Universidade de Caxias do Sul, CCET and Universidade Federal do Rio Grande do Sul, Instituto de Fisica, Porto Alegre, RS, Brazil, 5 Laboratoire de Physique des Gaz et des Plasmas, Universite Paris Sud, Orsay France, 6 Department of Electrical Engineering and Physics, University of Texas at Dallas, Richardson, Texas, United States
Show Abstract9:00 PM - E5.18
The Development of Zero-temperature-gradient Zero-bias Thermally Stimulated Ccurrent (ZTGZBTSC) Spectroscopy Technique for the Detection of Defect States in Ultra-thin High-k Dielectric Films.
Wai Shing Lau 1
1 School of EEE, Nanyang Technological University, Singapore Singapore
Show AbstractThermally stimulated current (TSC) spectroscopy is a well known technique to detect defect states in semiconductors or insulators. For semiconductors, TSC is largely replaced by transient capacitance or current spectroscopy techniques like the DLTS technique. However, TSC is still practised for insulators. Defect states are filled with electrons or holes either by optical or electrical excitation at low temperature, the sample current under a bias voltage is measured as a function of temperature when the sample is heated up to a high temperature; defect states will show up as peaks in the TSC spectrum. TSC has been demonstrated for tantalum oxide, zirconium oxide and aluminum oxide thin films, etc. However, for microelectronics, ultra-thin high-k dielectric films are used for DRAM or gate dielectric applications; the bias voltage used during TSC measurement will create a big parasitic current which usually increases exponentially with temperature rise and can bury TSC peaks. Previously, we have demonstrated that if the bias voltage is decreased to 0 V, this parasitic current is significantly reduced such that defect states in ultra-thin tantalum oxide films can be detected by zero-bias thermally stimulated current (ZBTSC) [1]-[2].However, experimentally we observed that the parasitic current is still significant when we performed ZBTSC on an ultra-thin high-k dielectric film. This is because of the existence of a small parasitic voltage even for ZBTSC. Previously, we showed that one mechanism of the existence of a small parasitic voltage is due to the non-zero input offset voltage of the operational amplifier connected as a current-to-voltage converter in the current meter used to measure TSC (Mechanism 1). This can be solved by improving the electronics used to measure TSC.In this paper, we will show that another mechanism of the existence of a small parasitic voltage is a parasitic thermoelectric voltage arising from the existence of a small temperature gradient in the sample (Mechanism 2). This can be solved by improving the thermal design of the TSC system and then the new version of TSC is named "zero-temperature-gradient zero-bias thermally stimulated current (ZTGZBTSC)" [3]. In this paper, we will demonstrate our new ZTGZBTSC technique on ultra-thin tantalum oxide films. With Mechanism 1 and Mechanism 2 of parasitic current suppressed, ZTGZBTSC will be able to extend the range of ZBTSC such that deeper defect states can be detected in ultra-thin high-k dielectric films.Reference:[1] W.S. Lau, L. Zhong, A. Lee, C.H. See, T. Han, N.P. Sandler and T.C. Chong, Appl. Phys. Lett., 71, 500 (1997).[2] W.S. Lau, L.L. Leong, T. Han and N.P. Sandler, Appl. Phys. Lett., 83, 2835 (2003).[3] W.S. Lau, US Patent 6,909,273 (2005).
9:00 PM - E5.19
Aluminum Oxide and Silicon Nitride as Barrier Layers between Atomic Layer deposited HfO2 and Silicon Substrates.
Ramarajesh Katamreddy 1 2 , Ronald Inman 2 , Axel Soulet 2 , Gregory Jursich 2 , Christos Takoudis 1
1 Chemical Engineering, University of Illinois at Chicago, Chicago, Illinois, United States, 2 , American Air Liquide, Countryside, Illinois, United States
Show Abstract9:00 PM - E5.2
Thermal Stability of Ru Gate Electrode on High-κ Dielectrics.
Karol Frohlich 1 , Milan Tapajna 1 4 , Kristina Husekova 1 , Andrej Vincze 2 , Juan Pedro Espinos 3
1 , Institute of Electrical Engineering, SAS, Bratislava Slovakia, 4 , Faculty of Electrical Engineering and Information Technology, STU, Bratislava Slovakia, 2 , International Laser Centrum, Bratislava Slovakia, 3 , Instituto de Ciencia de Materiales de Sevilla, Sevilla Spain
Show Abstract9:00 PM - E5.21
Electron Spin Resonance and Spin Dependant Recombination Studies of Silicon Dangling Bond Centers in Hafnium Oxide MOS Structures
Jason Ryan 1 , Patrick Lenahan 1 , Thomas Pribicko 1 , Jason Campbell 1 , Gennadi Bersuker 2 , Pat Lysaght 2 , S Song 2 , Wilman Tsai 3
1 Engr Sci and Mech, Penn State, University Park, Pennsylvania, United States, 2 , SEMATECH, Austin, Texas, United States, 3 , Intel, Santa Clara, California, United States
Show AbstractWe have utilized both conventional electron spin resonance (ESR) and a very sensitive electrically detected ESR technique called spin dependent recombination (SDR) to examine performance limiting defects in the interface and near interface regions of Si/HfO2 MOS structures. Our results strongly indicate the presences of oxygen deficient silicon in the near interface region. This result supports the idea that the near interface region is an oxygen deficient, silicon rich, dielectric.1 Conventional ESR measurements were performed on simply processed HfO2 films which had been deposited via atomic layer deposition (ALD) on very thin (1-2nm) layers of SiO2 on silicon. SDR measurements were made on fully processed metal gate HfO2 transistors. Both ESR and SDR measurements detect relatively narrow spectra with zero crossing g values of g = 2.0020 to g = 2.0005. The g is a second rank tensor defined as g = hν/βH, where h is Planck’s constant, ν is microwave frequency, β is the Bohr magneton, and H is the magnetic field at resonance. Narrow lines at g = 2.0005 and g = 2.0020 have previously been associated with E’ like defects, defects involving oxygen deficient silicon dangling bonds in which the center silicons are back bonded to three oxygens.2 These centers are very widely observed in conventional Si/SiO2 systems, but generally observed only after the oxides are subjected to some sort of stressing. These centers are observed in fully processed metal gate HfO2 MOSFETs if the devices are subjected to high temperature post deposition anneals. In conventional ESR the intensity of the E’ like spectra increases dramatically when the ALD reaction is deprived of oxygen. Both of these observations strongly suggest that the HfO2 removes oxygen from the thin Si/dielectric transition layer, creating a silicon rich, oxygen deficient transition region. This result supports the conclusions of Bersuker et. al.1 who proposed that deposition of HfO2 films on thin layers of SiO2 may lead to the formation of a highly oxygen deficient interfacial layer which contributes to mobility degradation in HfO2 based transistors.1.G. Bersuker, J. Barnett, N. Moumen, B. Foran, C.D. Young, P. Lysaght, J. Peterson, B.H. Lee, P.M. Zeitzoff, and H.R. Huff, J. J. Appl. Phys., 43, No.11B, 7899 (2004).2.P.M. Lenahan and J.F. Conley Jr., J. Vac. Sci., B16 (4), 2134 (1998).Work at Penn State was supported by SEMATECH and Intel Corporation custom funding through the Semiconductor Research Corporation.
9:00 PM - E5.23
Diffusion of Hafnium in Single Crystal Silicon
Ravinder Sachdeva 1 , Andrei Istratov 1 , Prakash Deenapanray 2 , Eicke Weber 1
1 Material Science and Engineering, U.C. Berkeley, Berkeley, California, United States, 2 Center for Sustainable Energy Systems, The Australian National University, Canberra, Australian Capital Territory, Australia
Show AbstractThere is great current interest in replacing silicon gate oxide in Si microelectronics with alternative, high-k dielectric films. Most promising in terms of meeting the requirements and improving the performance of Si devices appear to be HfO2, due to its high dielectric constants. During processing such structures, Hf might enter the Si substrate. However, there is a lack of systematic data on the the diffusion of this metal in silicon that is addressed in this study. Diffusivity of Hf was studied using two methods for Hf incorporation in Si - ion implantation and sputtering. Diffusion of Hf was observed only after anneals at temperatures above 1200°C for the time period of 24 hrs, which confirms that Hf is a slow diffuser. Analysis of broadening of Hf profile in implanted samples, which were annealed for 168 hrs, allowed us only to estimate the diffusivity of Hf as 1x10-15 cm2/s at 1250°C: the spreading of implanted profiles at lower temperatures was too small. Analyses of sputtered samples, which were annealed for a longer time, upto 168 hrs, revealed that Hf appears to have a fast and slow component to its diffusivity whose migration energy was determined to be 3.5±0.3 eV and 4.1±0.3 eV respectively. Kick-out and Frank-Turnbull mechanisms can be ruled out for Hf. The slow and fast component could point to substitutional and interstitial Hf. The mechanism for fast component seems to indicate direct interstitial diffusion mechanism whereas the substitutional Hf seems most consistent with the concerted exchange diffusion mechanism.
9:00 PM - E5.24
Electrical Properties of Hafnium in Single Crystal Silicon
Ravinder Sachdeva 1 , Andrei Istratov 1 , Prakash Deenapanray 2 , Eicke Weber 1
1 Material Science and Engineering, U.C. Berkeley, Berkeley, California, United States, 2 Center for Sustainable Energy Systems, The Australian National University, Canberra, Australian Capital Territory, Australia
Show AbstractThere is great current interest in replacing silicon gate oxide in Si microelectronics with alternative, high-k dielectric films. Most promising in terms of meeting the requirements and improving the performance of Si devices appear to be HfO2, due to its high dielectric constants. During processing such structures, Hf might enter the Si substrate. However, there is a lack of systematic data on the electrical properties of this metal in silicon that is addressed in this study. Several deep level defects were found for Hf in both the upper and lower half of the silicon band gap, and their parameters were tabulated. Energy levels, concentrations, and capture cross sections were determined for all Hf defects. For defects that appeared in the highest concentration, trap filling experiments were conducted to determine their capture cross sections directly. Electric field enhanced emission due to the Poole-Frenkel effect was experimentally confirmed for defect N146 found in the upper half of the bandgap. C-V, DLTS and TSCAP results confirm the donor nature of this dominant defect in the deep level spectra. In the lower half of the bandgap, defect P143 was found to have a temperature dependent capture cross section whose capture barrier was found to be 0.04 eV.
9:00 PM - E5.25
Enhanced Phonon-Energy Coupling: Dramatic Reduction of Leakage Current of Silicon Oxide.
Zhi Chen 1 , Jun Guo 1 , Chandan Samantaray 1
1 Dept. of Electrical Engineering, University of Kentucky, Lexington, Kentucky, United States
Show Abstract One of the fundamental limitations for scaling MOS transistors is the exponential increase in gate leakage current as oxide is scaled down to below 3 nm. High-k gate oxides have been considered as candidates to replace silicon dioxide or oxynitride. However, there are numerous challenging issues facing high-k gate oxides, e.g. threshold and flat-band voltage shifts, low mobility, and Fermi-level pining at the metal-gate/oxide interface. If the leakage current of the oxide or oxynitride can be reduced by several orders of magnitude through the structure modification, the oxide/oxynitride may be further scaled down to the ultimate limit. In this abstract, we report a surprising discovery that the Si-O bonds have been strengthened due to energy coupling from Si-O rocking mode to the Si-Si TO mode and the Si-D mode using rapid thermal process (RTP) directly on oxides plus deuterium anneal. The gate leakage current has been reduced by five orders of magnitude for oxides of 2 nm, equivalent to that for HfO2. Using the Fourier transform infrared (FTIR) spectroscopy, we studied the effect of hydrogen/deuterium isotope effect on vibration modes of the SiO2/Si samples. It is found that the absorbance of the Si-Si TO phonon mode and the Si-O TO rocking mode are all enhanced significantly (>25%) after deuterium anneal. It is surprising that the enhancement has been further increased when RTP anneal is directly applied on the oxide (Fig. 1). The enhancement for the Si-Si TO mode is about 50%, which is much larger than that for the deuterium anneal only (~25%). After further deuterium anneal, the Si-Si TO mode is enhanced by about 73% which is about three times larger than that for deuterium anneal only (~25%). Therefore, there is enhanced energy coupling among Si-Si TO mode, Si-Si LO mode, Si-O TO rocking mode, and Si-D mode. However, if the oxide is too thick, e.g. 80 nm, there is no enhancement (See Fig. 2). This suggests that the energy coupling enhancement may not be available for the polysilicon/oxide stack. Although there is some energy coupling for thick oxides (10 nm) after deuterium anneal (~25%), Si-O bonds are not strengthened. Fig. 3 shows that there is no difference for gate leakage currents of oxides annealed in both hydrogen and deuterium. However, after RTP processing, there is one-order-of-magnitude reduction of leakage current and 10% improvement for the breakdown voltage (See Fig. 4). After further deuterium anneal, the gate leakage current has been reduced by two orders of magnitude and the breakdown voltage improved by 30% (See Fig. 5). This suggests that Si-O bonds in thick oxide (10 nm) are strengthened due to energy coupling. It is even more surprising that for ultrathin oxide (2 nm), the gate leakage current has been reduced by five orders of magnitude due to RTP processing (See Fig. 6). This reduction of direct tunneling current is equivalent to that of HfO2.
9:00 PM - E5.28
Influence of Intrinsic Defects and Strain on Electronic Reliability of Gate Oxide films
Ken Suzuki 1 , Yuta Ito 1 , Hideo Miura 1
1 , Tohoku University, Sendai Japan
Show AbstractElectronic products such as mobile phones and PCs have been miniaturized continuously and their functions have been improved drastically. With miniaturization of semiconductor devices, the structure of devices has become very complicated. Since multi-layered structures of thin films are used for electronic devices, the constituent materials have large mechanical stress, strain and intrinsic defects caused by the lattice mismatch between the adjacent layers. Mechanical stress or strain in a gate oxide film of a MOS transistor decreases its band gap and thus, increases the leakage current through the gate oxide film. In order to make clear the effect of the strain and intrinsic defects on both electronic and structural characteristic of gate oxide films, we performed a quantum chemical molecular dynamics analysis for SiO2-x and HfO2-x structure under strain by using colors code [1]. The formalization of this program is based on the extended Hückel approximation, resulting in much faster simulations than those based on regular first principle calculations. Three dimensional periodic unit cell of α-cristobalite with oxygen vacancies was used for SiO2-x model and cubic fluorite structure of HfO2 with oxygen vacancies was used for HfO2-x. The simulation enabled us to present a clear view of the change in the structure of SiO2 and HfO2 with oxygen vacancies on the atomic level. The crystallographic structure of the SiO2-x deformed drastically because the Si-O bonds neighboring an oxygen vacancy were broken and a free silicon monoxide molecule was generated in the SiO2-x structure. The magnitude of the band gap of the SiO2-x decreased from 8.9 eV to 6.3 eV due to the change in the atomic configuration accompanying the diffusion of the free monoxide. The calculated band gap of HfO2 was 5.6 eV on average during the simulation. This value agrees well with the reported experimental results. For HfO2-x, we found a peak in the band gap due to the oxygen vacancy state. This state was at about 4 eV above the valence band of HfO2.The electron of defect state localized in the oxygen vacancy site. Both SiO2-x and HfO2-x had large fluctuation of the magnitude of the band gap during the simulation. The large fluctuation of the band gap was caused by the change in the atomic configuration due to the oxygen vacancy, leading to the serious degradation of the electronic reliability of the gate oxide film in semiconductor devices.[1] K. Suzuki, Y. Kuroiwa, S. Takami, M. Kubo, A. Miyamoto and A. Imamura, Solid State Ionics, 152-153 (2002) 273-277.
9:00 PM - E5.3
Comparison of C-V and Scanning Kelvin Probe (SKPM) Methods for Determining Work Functions of Nb-W-Pt/HfO2 Combinatorial Composition Spreads
Kao-shuo Chang 1 2 , Martin Green 1 , John Suehle 1 , Eric Vogel 1 , Hao Xiong 1 , Joseph Kopanski 1 , Jason Hattric-Simpers 2 , Ichiro Takeuchi 2 , Parhat Ahmet 3 , Toyohiro Chikyo 3 , Prashant Majhi 4 , Huang-chun Wen 4 , Byoung-Hun Lee 4 , Mark Gardner 4
1 Materials Science and Engineering, NIST, Gaithersburg, Maryland, United States, 2 Materials Science and Engineering, U. of Maryland, College Park, Maryland, United States, 3 , NIMS, Tsukuba Japan, 4 , Sematech, Austin, Texas, United States
Show AbstractThe use of poly-Si as the gate electrode for CMOS (Complement Metal Oxide Semiconductor) devices has encountered some severe limits, among them poly-Si depletion and Boron dopant diffusion. Metal gates offer a solution because of their intrinsically high conductivity; however, the determination of the effective work functions of metals, the most critical property for optimum transistor performance, is not trivial since they are affected by the underlying dielectrics, and are very dependent on processing conditions. In this work, we use combinatorial methodology to systematically study work functions of Nb-W-Pt ternary composition spreads deposited by ion beam evaporation on ALD HfO2. The capacitance (C) - voltage (V) characteristics of hundreds of devices across the entire ternary system were measured at 1 kHz on an autoprobe station. We used the Hauser CVC program to automatically fit the measured C-V curves to extract work functions. We found distinct variations across the ternary system, with higher work function values close to the Nb- and Pt-rich corners than at the W-rich corner, consistent with the literature. In addition, SKPM was also used to extract the nominal work functions, for comparison. A good correlation between the two measurements was found.
9:00 PM - E5.4
Comparison of the Work Function of Pt-Ru Binary Metal Alloys Extracted from Metal-Oxide-Semiconductor Capacitors and Schottky Barrier Diodes
Ravi Todi 1 , Kalpathy Sundaram 1 , Katayun Barmak 2 , Kevin Coffey 3
1 School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, Florida, United States, 2 Department of Materials Science and Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States, 3 Department of Mechanical Materials and Aerospace Engineering, University of Central Florida, Orlando, Florida, United States
Show AbstractAs the equivalent oxide thickness (EOT) for gate dielectrics in complementary metal-oxide-semiconductor (CMOS) technology is reduced below 1 nm, limitations associated with the use of poly-silicon gate electrodes become increasingly important. These limitations include the poly-depletion effect, high gate resistance, boron penetration, and compatibility issues with high permittivity gate dielectric films. Metal gates that can potentially address these limitations are attracting research interest. A key parameter for the choice of the metal gate material is its work function. Ideally, metal gate electrodes will have work functions that are within 0.2 eV of the silicon conduction and valance band edges, namely work functions of 5.0-5.2 eV for PMOS and 4.1-4.3 eV, for NMOS. The high work function of Pt, Ru and their binary alloys make them potentially suitable choices for the gate metal in PMOS. In this work, we present work function studies for Pt-Ru alloys prepared by sputter deposition in an ultrahigh vacuum (UHV) system. The alloy is formed by co-sputtering of Ru and Pt at different DC powers. Rutherford backscattering spectroscopy (RBS) is used to determine the composition of the alloy. The silicon dioxide gate dielectric is thermally grown in dry oxygen ambient in the range of 20 to 150 Å, followed by a passivation anneal in hydrogen-containing ambient. For both MOS and Schottky devices, Al is thermally evaporated and annealed at 500 oC in an Ar ambient to achieve good back-side ohmic contact. Capacitance-voltage C-V measurements are used to extract the work functions from the MOS capacitors. The alloy work functions are found to be in the range of 4.8 to 5.3 eV for alloy compositions of 10-90 at% Ru. Alloy work functions are also extracted by using Schottky diodes with co-sputtered Ru-Pt electrodes. The work functions from the two methods are compared.
9:00 PM - E5.5
Phase and Morphological Study of Nickel Metal Gate for CMOS Devices
Weiwei Kuang 1 , Dongzhi Chi 2
1 , North Carolina State University, Raleigh, North Carolina, United States, 2 , Institute of Materials Research and Engineering, Singapore Singapore
Show Abstract9:00 PM - E5.7
Defect Engineering of Hafnium Oxide by Aluminum Addition.
Quan Li 1 , Jiyan Dai 2 , Xingao Gong 3
1 Physics, The Chinese University of Hong Kong, Hong Kong Hong Kong, 2 Department of Applied Physics, The Hong Kong Polytechnic University, Hong Kong Hong Kong, 3 Physics, Fudan University, ShangHai China
Show AbstractBeing one of the most promising high-dielectric constant (high-K) materials to replace SiO2 in nanoelectrical devices, the application of the HfO2 is hindered by the formation of various native defects that not only deteriorate its electronic structures, but also act as charge traps. Through a combined experimental and theoretical effort, we have identified two occupied native defect bands in the as-deposited pure HfO2 thin film, as related to charged oxygen vacancies and oxygen interstitials. Furthermore, we show that adding Al to the HfO2 system can effectively passivate mid-gap levels induced by the oxygen vacancy and improve its electrical properties. In addition, we have investigated the electronic/defect structure change of the as-deposited films (including the pure HfO2 film and those with Al addition at different concentrations) when annealed in different ambient gas environments. The results and the corresponding physical understanding provide an alternative approach to design high-K materials, i.e., via defect engineering, for the next generation of nanoelectric device integration.
9:00 PM - E5.8
The Microstructure and Electronic Structure Evolution of Hafnium Aluminate with Increasing Al Concentrations.
Quan Li 1 , Xiaofeng Wang 1
1 Physics, The Chinese University of Hong Kong, Hong Kong Hong Kong
Show AbstractHafnium aluminate is one of the most promising pseudo-binary Hf-based materials to serve as a potential candidate to replace SiO2 in the future nanoelectrical industry. The addition of Al to the HfO2 is expected to increase, relative to the properties of pure HfO2, the Si/dielectric interfacial stability, crystallization temperature, and the band gap, etc. Despite quite a few literature reports on satisfactory electrical behavior and various desirable properties demonstrated by the hafnium aluminate films, the basic microstructure and electronic structure of these amorphous materials remain unclear. In this study, we have carried out a systematic study on the structure evolution of a series of hafnium aluminate films, which are grown by pulsed laser deposition, as a function of the Al concentration. The short range orders and the information on the atomic coordinates of the amorphous hafnium alumiate films are disclosed by both the radial distribution functions extracted from the transmission electron diffraction patterns and the energy loss near edge structures of the O K edges. The electronic structures of the films are examined by the valance electron energy loss spectroscopy and x-ray photoelectron spectroscopy. An interesting correlation in-between the microstructure and the electronic structure of the corresponding hafnium aluminate film is observed. The evolution of the films’ microstructure and electronic structure is discussed as a function of the Al concentration. The possible consequence of such evolution on the materials’ electrical behavior is also elaborated.
Symposium Organizers
Raj Jammy SEMATECH
Ajit Shanware Texas Instruments, Inc.
Veena Misra North Carolina State University
Yoshitaka Tsunashima Toshiba Corporation
Stefan De Gendt IMEC
E6: Interface I
Session Chairs
Wednesday AM, April 19, 2006
Room 3008 (Moscone West)
9:30 AM - E6.1
Investigation of the Mechanism of the Flatband Voltage Shift for poly-Si/HfSiON/Si Structures by Means of Barrier Layer Insertion into the Interfaces.
Yuuichi Kamimuta 1 , Masato Koyama 1 , Tsunehiro Ino 1 , Masumi Saitoh 1 , Katsuyuki Sekine 2 , Motoyuki Sato 2 , Takuya Kobayashi 2 , Kazuhiro Eguchi 2 , Mariko Takayanagi 3 , Mitsuhiro Tomita 1 , Akira Nishiyama 1
1 Advanced LSI Tech. Lab., Corporate R&D Center, Toshiba Corporation, Yokohama Japan, 2 Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company, Yokohama Japan, 3 SoC Research & Development Center, Toshiba Corporation Semiconductor Company, Yokohama Japan
Show Abstract9:45 AM - E6.2
Band Alignments at Metal gate-high-κ gate Dielectric Interfaces.
S. J. Wang 1 , Q Li 2 , Y. F. Dong 2 , YY Mi 2 , Y. P. Feng 2 , A. C. H. Huan 1 , CK Ong 2
1 , Institute of Materials Research & Engineering, Singapore Singapore, 2 Department of Physics, National Unviersity of Singapore, Singapore Singapore
Show AbstractWith the alternative high-k gate dielectrics are expected to replace current SiO2 gate oxide for the continued scaling of metal-oxide-semiconductor field-effect transistors (MOSFET), there is an immense interest in replacing conventional poly-Si gate with metal gates because of the serious problems related to poly-Si gate depletion and high gate resistance. However, in general, the work function of metal in contact with high-κ dielectric (termed as effective work function) differs from its value in vacuum. The difference of work function may be caused by the intrinsic and extrinsic contributions of interface states at metal-dielectric interfaces. Widely interesting attempts have been provided to insight the physical origin of Schottky barrier formation, such as the metallization induced band bending and band alignments of the metal/dielectric stack. Furthermore, the possible atomic bonds of metal-metal or metal-oxygen at metal gate/oxide gate dielectric interface are different from conventional silicon-oxygen bond at poly-Si-SiO2 interface. How these bonds affect the band alignment at the metal/high-k oxide interface is a important issue for the implementation of this gate stack. In this presentation, we present in situ photoemission studies for the band alignments at the interfaces of Ni/HfO2, Ni/ZrO2, Ni/MgO and Ni/SiO2. The band bending induced by metal deposition has been observed. And the impact of interface atomic structure on the schottky-barrier heights (SBH) for metal-gate/high-k gate dielectric interfaces has been revealed from photoemission study and first-principle calculation.
10:00 AM - E6.3
First Principles Study of HfO2/SiO2 Interfaces: Intrinsic and Extrinsic Defect Properties.
Jeong-Hee Ha 1 , Paul McIntyre 1 , Kyeongjae (KJ) Cho 2
1 Department of Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Department of Mechanical Engineering, Stanford University, Stanford, California, United States
Show AbstractContinued scaling of semiconductor circuits requires sub-0.1 µm MOSFET channel lengths, for which the gate oxide also needs to scale to less than 1.5 nm in equivalent oxide thickness (EOT) to maintain electrostatic control of the device. High-k dielectrics which give high gate capacitances for physically thicker films are thus desirable. The great majority of recent work on alternative gate dielectric materials has focused on hafnium oxide-based dielectrics because HfO2 has shown good thermal stability against solid state reaction with Si, has adequate band offsets to Si, and a dielectric constant of ~ 20. However, fabrication of optimized HfO2/Si gate stacks remains a challenge, because an interfacial SiO2 layer almost always grows during film deposition or after post-deposition-annealing, due to residual oxygen in post-anneal ambient or to oxidizing species incorporated in the films during their deposition. This uncontrolled SiO2 layer generally has poor electrical properties and increases the EOT of the gate stack. Therefore, HfO2 is almost always deposited onto controlled ultra thin SiO2-based passivation layers which have the advantage of an excellent Si/SiO2 interface for better device performances. Defects from the internal dielectric interface between HfO2 and SiO2, however, may contribute to problems such as fixed charge and threshold voltage instability under bias. In this presentation, we report a careful ab initio density-functional theory (DFT) analysis based on a reasonable atomistic HfO2/SiO2 interface model and make suggestions for future experimental remedies for fixed charge and reliability problems in high-k gate stacks. To elucidate fundamental properties, we chose to model ideally abrupt interfaces between HfO2 and SiO2. The simulation shows that even an abrupt interface without any extrinsic defect introduces occupied midgap states within the band gap. This is a result of undercoordinated Hf atoms at the interface, and the mid gap states provide a source of positive fixed charge when non-bonding electrons on the interface Hf atoms are depleted by Fermi level change. Therefore, even for an atomically abrupt HfO2/SiO2 interface, passivation of unfulfilled bonds at the HfO2/SiO2 interface is a problem. We have also investigated possible roles of residual impurities. Oxygen interstitials, chlorine impurities (present in some atomic layer deposited HfO2 films), and OH groups at the HfO2/SiO2 interface may affect the fixed charge. The simulation results suggest that they can introduce empty midgap states, or act as partially-compensating negatively charged defects by accepting non-bonding electrons from undercoordinated Hf atoms.
10:15 AM - E6.4
Influence of Vacancies on the Dielectric Properties of HfO2.
Eric Cockayne 1
1 Ceramics Division, NIST, Gaithersburg, Maryland, United States
Show AbstractFirst-principles calculations were used to study the effectsof neutral and 2+ charged oxygen vacancies on the dielectric properties of crystalline HfO2. In agreement with previous results, the neutral vacancy is more stable on the 4-fold coordinated site, while the charged vacancy is more stable on a 3-fold coordinated site. For both vacancypositions, HfO2 remains insulating whether the vacancy is neutral or in the 2+ charge state. Phonon frequencies were calculated for each defect structure studied. Localized phonons are observed at various frequencies, especially around 750 cm-1. The full ionic effective charges tensors of each structure were determined. From the phonons and the effective charges, the dielectric constant of each defect structure was found,as well as that of defect-free HfO2. The effective charges ionic charges are generally reduced for ions near the defect center, thus leading to suppression of the dielectric constant.
10:30 AM - E6.5
Effect of Impurities on the Fixed Charge of Nanoscale HfO2 Films Grown by Atomic Layer Deposition
Raghavasimhan Sreenivasan 1 , Hyoungsub Kim 2 , Krishna Saraswat 3 , Paul McIntyre 1
1 Dept. of Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Dept. of Advanced Materials, Sungkyunkwan University, Seoul Korea (the Republic of), 3 Dept. of Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractHf-based oxides are being extensively researched to replace SiO2 as the gate dielectric for low power applications. Their implementation has been limited by the presence of a large amount of fixed charge and a high density of interface states. Atomic layer deposition (ALD) is a layer-by-layer deposition technique where alternating surface reactions saturate the substrate in each cycle. The ability to grow stoichiometric, highly uniform films with precise thickness control makes ALD a very promising method for gate stack applications. Unlike thermally grown SiO2, oxides deposited using CVD or ALD can have impurities in them that can act as defect centers. The choice of precursors plays an important role in deciding the nature and type of impurities incorporated in the dielectric film. Conventionally, HfO2 has been deposited using HfCl4 as the metal source and H2O as a hydrolyzing reactant. HfCl4 being a solid precursor, this process suffers from particle contamination, precursor gas-line clogging and chlorine incorporation in the film. The metalorganic precursors are liquid at room temperature, have high volatility and produce pure films with very low residual impurities.HfO2 films were grown by ALD using two different precursor chemistries – HfCl4 and tetrakis(diethylamido)hafnium (TDEAH) with H2O as the oxidant. A substrate temperature of 300°C was used for the chloride-HfO2 whereas the TDEAH-HfO2 was grown at 150°C. Electrical measurements on MOSCAP structures fabricated using the films showed a 0.4V positive shift in the flatband voltage for the chloride-HfO2 with respect to the amide-derived HfO2 indicating a considerable negative fixed charge in the dielectric. SIMS depth profile of the gate stack showed Cl piled up preferentially at the HfO2/SiO2 interface for the chloride-derived HfO2. In-situ vacuum anneals at 500°C did not affect the profile indicating that Cl segregates stably to this interface. A similar analysis of the TDEAH derived HfO2 showed very low concentrations of C, N and H impurities. The magnitude, sign and location of the fixed charge in the gate stacks was estimated by systematically varying the thickness of HfO2 on a given thickness of interfacial SiO2. From the VFB vs EOT plots, a positive fixed charge of +4.5E11/cm2 was extracted for the amide-HfO2 whereas a negative fixed charge of –1.86E12/cm2 was estimated for the chloride-HfO2. Thus, Cl incorporation in the HfO2 film can significantly alter the fixed charge in the dielectric. A systematic comparison of HfO2 grown using HfCl4 and TDEAH will be presented. Key differences in the electrical behavior of the films like hysteresis, Dit and fixed charge and their correlation to the impurities in the dielectric will be highlighted.
10:45 AM - E6.6
Defect Energy Levels in HfO2 and other High K Oxides.
Ka Xiong 1 , John Robertson 1
1 Engineering, Cambridge University, Cambridge United Kingdom
Show AbstractHigh dielectric constant (K) oxides such as HfO2 are needed to replace SiO2 as the gate oxide in future CMOS devices. However, these oxides possess a much higher bulk density of charge traps than SiO2. It was recently calculated that the O vacancy in HfO2 gives rise to a number of energy levels of different charge state in the upper oxide gap [1]. V- gives a half-filled state at 0.8 eV and a filled state 2.1 eV below the oxide CB. This is equivalent to states at midgap and 1.5 eV above midgap of the Si channel. These levels correspond closely to the bulk level needed to account for rapid electron trapping [2,3] especially in terms of its energy [4]. It also corresponds to optical absorption and PL data [5,6]. This implies that the O vacancy is the dominant defect in processed gate oxides, after gate deposition, and is responsible for charge trapping, and transient Vt instability. We argue that it is also responsible for much of the mobility degradation. It also accounts for why trapping varies with gate metal [6], due to reduction of the oxide.The calculations are extended to Hf silicate, La oxide and LaAlO3. The results are broadly similar; levels are deeper in HfSiO4 and La2O3 and shallower in LaAlO3. The energy levels can be correlated to subgap features seen in photoconductivity / internal photoemission spectra [5]. Thus a general model of active defects in high K oxides is possible.1.K Xiong, J Robertson, M C Gibson, S J Clark, App Phys Lett 87 183505 (2005) 2.A Kerber, et al, IEEE ED Lett 24 87 (2003)3.L Pantisano et al, Tech Digest VLSI (2003) 4.G Reimbold, et al, in proc NATO workshop (Springer, Berlin, 2005)5.H Takeuchi, D Ha, T J King, J Vac Sci Technol A 22 1337 (2004)6.L J Brillson, G Lucovsky, et al, MRS Spring (2005) paper G8.37.E P Gusev, et al, Tech Digest IEDM (2004) p7298.V V Afanasev et al, App Phys Lett 85 5917 (2004)
E7: High-k-Hf Based I
Session Chairs
Wednesday PM, April 19, 2006
Room 3008 (Moscone West)
11:30 AM - **E7.1
High-k/Metal Gate Stacks Scaling for High Performance MOS Devices
Manuel Quevedo 1 , P kirsch 3 , S Krishnan 2 , H Li 4 , J Peterson 5
1 , SEMATECH/Texas Instruments, Austin, TX, Texas, United States, 3 , SEMATECH/IBM, Austin, Texas, United States, 2 , SEMATECH, Austin, Texas, United States, 4 , SEMATECH/Infineon, Austin, Texas, United States, 5 , SEMATECH/Intel, Austin, Texas, United States
Show AbstractMoore’s law scaling of planar metal-oxide-semiconductor (MOS) technology has maintained its dizzying pace in recent years. Throughout the history of integrated circuits, shrinking the dimensions of the transistor has required that many difficult challenges be overcome. Not surprisingly, the current push towards sub-0.045 um technology generations requires numerous innovations aimed at overcoming substantial challenges. In particular, it is clear that today’s gate dielectric material, SiON, will soon reach the predicted limits of scaling, thus presenting a fundamental challenge to continued CMOS scaling [1]. Therefore, the introduction of high-k materials to continue scaling of CMOS devices is imminent. Before implementing high-k dielectrics in a conventional CMOS process, issues such as degraded mobility at low equivalent oxide thickness (EOT), charge trapping induced threshold voltage (VTH) instability, and bias temperature instability (BTI) [2-8] need to be addressed. Nitrided HfO2 and hafnium silicate (HfSiO) are the leading candidates to replace SiON. However, neither of them has been selected as the material of choice by the semiconductor industry. From the thermal stability point of view, HfSiON seems to be desirable [9]. However, is expected that HfO2 can be more scalable due to its slightly higher dielectric [3]. In this paper, the scaling limits of atomic layer deposited HfON and HfSiON are presented. The impact of starting interface, film thickness, post-deposition anneal and metal electrode on EOT scaling is also investigated. Overall, based on the data available it is shown that HfSiON is a robust dielectric and scalable to at least 1 nm EOT with 90% mobility and excellent reliability [10].REFERENCES[1] ITRS, Semiconductor Industry Association, San Jose, CA 95129, 2005.[2] P. D. Kirsch, et al., EESDERC 2005, Grenoble, FR.[3] J. J. Peterson et al. Electrochem. Solid-State Lett., 7 (8) G164-G167 (2004)[4 A. Callegari et al. IEDM Tech. Dig. , 825 (2004).[5] B.H.Lee et al., IEDM Tech. Dig., p.859 (2004).[6] E. P. Gusev et al., IEDM Tech. Dig., p.729 (2004).[7] H. R. Harris et al. Proceedings of IRPS, p.80 (2005).[8] R.Chau et al, EDL v.25,p.408 (2004).[9] A. Shanware et al. IEDM Tech. Dig., p.38-6 (2003).[10] M. A. Quevedo-Lopez, Accepted. IEDM 2005.
12:00 PM - E7.2
Growth and Characterization of Hf-Ti-O Gate Dielectric Thin Films.
Karthik Ramani 1 , Valentin Craciun 1 , Rajiv Singh 1
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractWednesday, 4/19E5.9 (poster)Transferred to E7.2 (oral) 11:00 amGrowth and Characterization of Hf-Ti-O Gate Dielectric Thin Films. Karthik Ramani
12:15 PM - E7.3
A Comparison of Electrical and Physical Properties of MOCVD Hafnium Silicate Thin Films Deposited using Various Silicon Precursors.
Paul Jamison 1 , M. Copel 2 , M. Chudzik 3 , M. Frank 3 , R. Jammy 3 , B. Linder 3 , W. Zhu 1
1 Semiconductor Research and Development Center (SRDC), IBM Microelectronics Division, East Fishkill, New York, United States, 2 , IBM Research Division, TJ Watson Research Center, Yorktown Heights, New York, United States, 3 SRDC, IBM Research Division, TJ Watson Research Center, Yorktown Heights, New York, United States
Show Abstract12:30 PM - E7.4
Correlation of Phase Segregation and Electrical Properties of Low-Power MOSFETs with Hf-based Silicate Gate Dielectric Layers and TaN Metal Gates.
Jasmine Petry 1 , Zacharias Rittersma 1 , Georgios Vellianitis 1 , Vincent Cosnier 2 , Thierry Conard 3 , Olivier Richard 3 , Wim Deweerd 3
1 Module Integration, Philips Research, Leuven Belgium, 2 , ST Microelectronics, Crolles France, 3 MCA, IMEC, Leuven Belgium
Show AbstractHf-based silicates are a promising alternative for SiO2 gate dielectric layers in advanced MOSFETs as they combined a high dielectric constant and a lower defect density than binary HfO2. Several authors have shown that the nitridation of silicates delays phase segregation and hence also crystallization. However, the need for nitridation is still controversial. On one hand, it has not been proven that the nitridation was mandatory to have working devices and on the other hand, it is known to increase the charge density. In this paper, we present a detailed comprehensive study of the role and the need for nitridation of Hf-based silicates deposited by Atomic Layer Deposition (ALD). The results are based on a correlation of Fourier-Transformed Infrared Spectroscopy (FT-IR), X-ray Photoelectron Spectroscopy (XPS), High-resolution Transmission Electron Microscopy (HR-TEM) and electrical measurements. It was observed that the phase segregation in gate dielectrics with 50% Hf is not detrimental for the gate leakage density at room temperature. At higher temperature (100C), the leakage current is increased by a factor 10. For Hf-rich layers (80% Hf), the phase segregation leads to a much stronger increase in the gate leakage current, both at room temperature and at high temperature. In the phase-segregated dielectric, the boundaries between the two phases could be the location of traps that enhance the leakage current. The incorporation of nitrogen was either done by NH3 anneal (at 800C) or by Decoupled Plasma Nitridation (DPN – 25.9kJ). The bonding of the N into the silicate matrix is different in both cases and therefore the result of this nitridation step was not always successful. While the DPN or NH3 anneal prevent phase segregation for 50% Hf silicate, only the NH3 anneal helps against the phase segregation of Hf-rich silicate. From XPS and FTIR analysis, we conclude that the formation of Hf-N bonds is the stabilizing factor. Independently from the total amount of N incorporated, the N profile is similar for DPN and NH3 but strongly depends on the silicate thickness: the thinner the layer, the more uniform the N is distributed in the layer. Furthermore, the NH3 anneal increases the interfacial thickness, which is the cause of a very low gate leakage (4.9E-4 A/cm2 at 1.1V, at 25C) with only 10% loss in mobility at high field (meff = 236 cm2/Vs at E=1MV/cm).As a conclusion, the phase segregation of the silicate does not always lead to shorted devices; it depends on the Hf content of the silicate. However, the phase segregation seems to be responsible for an enlarged trap-assisted conduction mechanism. But even if the 50% Hf silicates non-nitrided leads to working devices, the incorporation of nitrogen in the stack improves the Jg/CET trends and is therefore beneficial.
12:45 PM - E7.5
Physical and Electrical Characterization of Scalable HfO2 and HfSiO Thin Films Deposited by ALD.
Tejal Goyani 1 , Shankar Muthukrishnan 1 , Rahul Sharangapani 1 , Shreyas Kher 1 , Pravin Narwankar 1 , Philip Kraus 1 , Khaled Ahmed 1 , Giusepinna Conti 1
1 , Applied Materials, Inc., Sunnyvale, California, United States
Show AbstractHafnium containing high κ gate dielectrics are widely considered as viable candidates to replace SiO2 in advanced gate dielectric applications. We have successfully demonstrated very low EOT and leakage current for Hafnium oxide and Hafnium silicate, deposited by Atomic Layer Deposition. TEM analyses show that the materials are thermally stable up to conventional source/drain activation temperatures when nitrogen is incorporated into the high κ films. We have been able to incorporate as high as 25% nitrogen in the high κ film and successfully engineer the nitrogen profile in the gate stack. The nitrogen profile can be tailored to maintain the nitrogen concentration peak away from the interface. This profile is required to optimize device performance. We show by Angle Resolved X-ray Photoelectron Spectral analysis that nitrogen is primarily bonded to the silicon. Detailed physical and electrical characterization of high κ/poly-Si and high κ/metal gate stacks will be presented.
E8: Gate Electrode II
Session Chairs
Wednesday PM, April 19, 2006
Room 3008 (Moscone West)
2:30 PM - **E8.1
On The Identification and Integration of Thermally Stable Band Edge Metal Gate Materials on High-k Dielectrics
Prashant Majhi 1 , Hongfa Luan 1 , Rusty Harris 1 , Huang-Chun Wen 1 , Husam Alshareef 1 , Yoshi Senzaki 1 , Kisik Choi 1 , Hong-Jyh Li 1 , C Park 1 , S Song 1 , Paul Kirsch 1 , Rino Choi 1 , Gennadi Bersuker 1 , George Brown 1 , Byoung-Hun Lee 1 , Raj Jammy 1
1 , Sematech, Austin, Texas, United States
Show AbstractThis paper presents a systematic approach to identification of thermally stable metal gate materials on hafnium based high-k dielectrics for potential use in future generation dual metal CMOS. Along with addressing some of the primary causes that complicates the task of identifying candidate materials with appropriate work function values, this paper also discusses material systems and integration pathways that hold promise in engineering metal-highk stacks using the conventional gate first process. Using Hf based electrodes (NMOS) and engineered high-k/metal gate interface layer (PMOS), near band edge characteristics (within ~100meV from band edge) with high mobility are demonstrated on hafnium-based dielectrics after the thermal budget for full CMOS device fabrication (1000 oC, 5sec).
3:00 PM - E8.2
Plasma-enhanced Atomic Layer Deposition of Tantalum Nitride for Gate Electrode Application
Raghavasimhan Sreenivasan 1 , Takuya Sugawara 1 , Krishna Saraswat 2 , Paul McIntyre 1
1 Dept. of Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Dept. of Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractMetal gates are being extensively researched as a replacement for poly-Si gate electrodes for high performance transistors. Poly-Si gates suffer from gate depletion leading to an increase in equivalent oxide thickness and boron penetration into the channel resulting in VT instability. Also, poly-Si electrodes on HfO2 exhibit Fermi level pinning due to the formation of Hf-Si bonds at the poly-Si/HfO2 interface. Tantalum Nitride has been extensively studied as a barrier liner for copper interconnects due to its excellent thermal stability, good diffusion barrier properties and outstanding adhesion characteristics. These attributes also make it a great candidate as a metal gate for front-end applications. Atomic layer deposition (ALD) is a growth technique where complementary, self-limiting reactions occur at the substrate surface. This leads to the growth of highly uniform, conformal, stoichiometric films with excellent control over the film thickness. Tantalum nitride films were grown on Si substrates at 250°C by both thermal and remote plasma-enhanced ALD (PEALD) methods using a novel metal organic precursor – isopropylimino tris(ethylmethylamino) tantalum (IPTEMT). The thermal ALD process consisted of alternately pulsing IPTEMT and NH3 whereas the PEALD approach utilizes a hydrogen/nitrogen plasma as the reducing agent. The plasma is generated by flowing an Ar/N2/H2 mixture through a remote inductively-coupled plasma system attached to the ALD chamber. The Ta:N ratio was 1:1.1 in the as-deposited films. The PEALD films consistently showed a higher nitrogen concentration when compared to the thermal ALD films. Angle resolved XPS studies showed a uniform nitrogen content in the bulk of the films. The nitrogen concentration in the PEALD films increased with an increase in the amount of hydrogen in the plasma gas mixture. About 2-4 at.% carbon was detected in the PEALD films whereas the carbon content in the thermal ALD films was negligible. The films oxidized readily when exposed to air, requiring them to be capped in-situ with an oxygen diffusion barrier layer. A systematic comparison of tantalum nitride films grown by the two methods will be presented. Electrical measurements made on capacitor structures fabricated on TaN/HfO2 stacks will be discussed. The effect of high temperature anneals in vacuum and reducing atmospheres like hydrogen will be analyzed.
3:15 PM - E8.3
Thermal Stability and Device Characteristics of MOSFETs Utilizing Bilayer Metal Gates for Threshold Voltage Control.
Ching-Huang Lu 1 , Gloria Wong 1 , Micheal Deal 2 , Bruce Clemens 1 , Yoshio Nishi 2 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Stanford University, Stanford, California, United States
Show Abstract3:30 PM - E8.4
Ru/Ta Alloying Behavior and its Implications for Laminate Based CMOS Integration.
Judit Lisoni 1 , Schram Tom 1 , Thomas Witters 1 , Nausikaa Van Hoornick 1 , Naoki Yamada 2 , Stefan De Gendt 1
1 SPDT, IMEC vzw., Leuven Belgium, 2 assignee at IMEC, Canon Anelva Corporation, Tokyo Japan
Show Abstract3:45 PM - E8.5
Diffusion Modeling and the Effect of Alloy Composition on Work Function of Metal Gate Electrodes
Gloria M. T. Wong 1 , Ching-Huang Lu 1 , Michael Deal 2 , Yoshio Nishi 2 , Bruce M Clemens 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractShrinking device sizes has necessitated the investigation of alternative materials to replace polycrystalline silicon as the gate electrode in CMOS devices. The use of metals eliminates carrier depletion in the polycrystalline silicon and boron penetration into the dielectric while also offering improved compatibility with high-k dielectrics. However, work function tuning of metal gates remains a considerable challenge. Solutions that have been proposed include the introduction of new materials and novel processing techniques. With these potential solutions it becomes essential to understand the role of the composition and structure of the metal-dielectric interface in the measured gate electrode work function. One technique that demonstrates work function tuning uses a bilayer gate electrode. In this structure, two metals with different work functions are stacked on top of the dielectric. By changing the thickness of the underlayer (the layer closest the oxide), the resulting work function value can be varied from that of one metal to the other. It has been shown that this effect is likely due to interdiffusion of the metal species during annealing. A diffusion model to describe this behavior is presented. This model describes the effect of composition on the work function by using an expression which includes the ratio of the density of states of the two elements. By relating gate composition at the oxide interface to work function, this model predicts interdiffusion lengths and has been shown to agree well with experimental data.One critical component of the diffusion model is the effect of the composition at the metal-dielectric interface on the work function. In order to investigate this, the composition of the gate electrode was directly controlled. Alloy metal gates were fabricated by co-sputtering from elemental targets. This method allows for fine control of the composition, which is verified using Electron Microprobe Analysis (EPMA) and Rutherford Backscattering (RBS). NbxW1-x alloys were incorporated into MOS capacitors and capacitance-voltage characteristics were used to extract the flat band voltage. The Nb-W system was selected because it exhibits complete mutual solid solubility. Thus, the gate electrode composition can be easily varied across the entire composition range and its effect on work function can be elucidated. We extend this study by introducing other metal/metal systems that have also exhibited work function tuning, yet are not fully miscible in each other. In these systems compound formation may occur, which is verified using x-ray diffraction. We then investigate the role of compound formation in work function behavior.
E9: Physical Characterization
Session Chairs
Wednesday PM, April 19, 2006
Room 3008 (Moscone West)
4:30 PM - E9.1
Non-contact Corona-Kelvin based Metrology for High-k Dielectric Characterization with an Extension to Micro-Scale Measurement
Marshall Wilson 1 , Dmitriy Marinskiy 1 , Anton Byelyayev 1 , Alexandre Savtchouk 1 , John D'Amico 1 , Carlos Almeida 1 , Joseph Kochey 1 , Lubek Jastrzebski 1 , Jacek Lagowski 1
1 , Semiconductor Diagnostics, Inc., Tampa, Florida, United States
Show Abstract In-line monitoring of the electrical properties of high-k dielectrics in logic or memory fab-lines has become increasingly important in the semiconductor industry. In-line monitoring of dielectric properties such as dielectric capacitance (EOT or CET), leakage, dielectric charge and flatband voltage is very important for control of dielectric growth or deposition processes. We present a comprehensive suite of non-contact corona-Kelvin based metrologies that can be used to affectively monitor these dielectric properties in-line. We present electrical characterization data on a wide array of high-k dielectrics, including Al2O3, HfO2, HfSiON and SiON of varying compositions, which illustrate the usefulness of this technique.A technique for extraction of true dielectric capacitance and therefore EOT values from C-V curves produced using this metrology is demonstrated. The extraction technique involves the use of a novel C-V simulator that is used to fit the experimental data and extrapolate the C-V curve to the true dielectric capacitance.Another extremely important aspect of this metrology is that it is extendable to the micro-scale that allows measurement of these dielectric properties on test sites as small as 50μm x 70μm. This was achieved through miniaturization of the corona charging apparatus and of the Kelvin probe without a sacrifice in precision or repeatability. This allows for the monitoring of the critical dielectric properties on patterned wafers that can then be returned to the fab-line for continued processing. We also present electrical characterization properties of various high-k dielectrics using this micro corona-Kelvin technique.
4:45 PM - E9.2
High Resolution Spectroscopic Characterization of Thin High-k Gate Dielectric Films and Interfaces.
Patrick Lysaght 1 , Gennadi Bersuker 1 , Joseph Woicik 2 , Daniel Fischer 2 , Monika Hartl 3 , Erik Watkins 3 , Jarek Majewski 3 , Rex Hjelm 3 , Hsing-Huang Tseng 4 , Raj Jammy 5
1 , SEMATECH, Austin, Texas, United States, 2 , NIST @ National Synchrotron Light Source, Brookhaven National Laboratory, Upton, New York, United States, 3 , Los Alamos Neutron Science Center @ Los Alamos National Laboratory, Los Alamos, New Mexico, United States, 4 , Freescale Assignee to SEMATECH, Austin, Texas, United States, 5 , IBM Assignee to SEMATECH, Austin, Texas, United States
Show AbstractHf based gate dielectric thin films have been exposed to post deposition anneal (PDA) processes consisting of NH3 and N2 ambient in order to decouple the influence of N incorporation from that of the thermal cycle alone. We have utilized the fine domain structure resolution of small angle neutron scattering (SANS) and depth profiling capabilities of synchrotron x-ray photoelectron spectroscopy (XPS) to compare microstructure variations in HfO2 and Hf silicate, (HfO2)x (SiO2)1-x, x = 0.7, gate dielectric thin films deposited on Si (100) substrates and exposed to PDA. The NH3 PDA films exhibit a significant amount of N in the bulk film, quantified by nuclear reaction analysis and corroborated by an intense Hf-N peak in the N 1s core level binding energy spectra. By monitoring the Si 2p and Hf 4f core level binding energy spectra during XPS depth profiling it is possible to distinguish the intermediate electron density corresponding to oxygen deficient SiOx and interfacial microroughness from Hf silicate formation at the HfO2/SiO2 interface.Neutron surface profilometry and reflectivity (SPEAR) measurements have been performed on a comprehensive set of samples previously measured by x-ray reflectivity (XRR) and characterized by a unique film system model which converged to an excellent goodness-of-fit for both measurement spectra. The high confidence in the quantification of the microroughness of the high-k/SiOx buried interface of these samples as a function of composition, temperature and ambient based on the resultant model is strengthened by the different scatter length densities for neutrons (real part only) and x-rays (real and imaginary parts) incorporated in the model evolution.In addition, we utilize extended x-ray absorption fine structure (EXAFS) in conjunction with SANS to evaluate the amorphous character of ultra thin (< 2 nm) HfO2 films and distinguish long and short range order phenomena associated with anneal parameters. Finally, Bragg peak periodicity is illustrated in the plane of Hf silicate films that crystallize via the mechanism of spinodal decomposition.
5:00 PM - E9.3
In situ ATR - FTIR spectroscopy of HfO2 deposition on Si(100) from Hf (IV) tert butoxide
Shilpa Dubey 1 , Harish Bhandari 1 , Zheng Hu 1 , C Turner 1 , Tonya Klein 1
1 , University of Alabama, Tuscaloosa, Alabama, United States
Show AbstractHafnium oxide ultrathin films on Si(100) are being developed to replace thermally grown SiO2 gates in CMOS devices. In this work, a specially designed Attenuated Total Reflectance - Fourier Transform Infra Red Spectroscopy (ATR-FTIR) reaction cell has been used to observe chemisorption of Hafnium IV t-butoxide onto a Si and Ge ATR crystal heated up to 200 deg C and under 2 torr of vacuum to observe the initial reaction pathways and species on the substrate surface in real time and under typical process conditions. Chemisorption spectra were compared to spectra of the liquid precursor and to spectra generated by density functional theory (DFT) calculations of liquid, monodentate and bidentate absorbed precursor. An asymmetric stretching mode located at ~1017 cm-1 present in the chemisorbed spectra but not in the liquid spectra indicate that the Hafnium precursor is prevalent as a bidentate ligand according to calculations. Saturation time of the chemisorbed species was dependant on the substrate temperature and precursor partial pressure while absorbance values depended on the saturation time indicating steric hinderance effects.
5:15 PM - E9.4
Interface Analyses of High-k Dielectric stacks.
Maureen MacKenzie 1 , Frances Docherty 1 , Alan Craven 1 , David McComb 2 , Catriona McGilvery 1 2
1 Physics & Astronomy, University of Glasgow, Glasgow United Kingdom, 2 Materials, Imperial College London, London United Kingdom
Show AbstractHfO2 and HfSiO based systems are among the high-k materials currently being investigated for use as the gate dielectric to replace amorphous SiO2 and Si(O,N) in Si MOSFETs. At the same time metal gate electrodes are being introduced to dielectric stacks to remove problems such as depletion and dopant diffusion associated with polysilicon gate electrodes. The final form of the fully processed stack will depend on the thermal budgets involved in processing, the different processing treatments and the actual techniques used for the deposition of the different layers. Thus it is important to develop an understanding of physical and chemical changes which occur during processing as well as differences resulting from the deposition methods used. Advanced analytical electron microscopy techniques provide a way of investigating these effects on a sub-nanometre scale. In many of the systems of current interest, information on all of the elements present can be obtained in a single electron energy-loss spectroscopy (EELS) dataset. Further, analysis of the energy-loss near-edge structure (ELNES) present on the ionisation edges can provide information on the local chemistry, structure and bonding. Thus in suitable systems it is possible to separate out the contributions to an edge from atoms in different phases. This can be achieved by modelling the edge shape as a linear combination of the ELNES from appropriate standards. Combined with high angle annular dark field scanning transmission electron microscopy (HAADF STEM) imaging it provides a powerful method of characterising samples.We apply these techniques to investigation of interface reactions in high-k stacks with both polysilicon and inserted metal electrodes. The specimens are examined in an FEI Tecnai F20 TEM/STEM equipped with a field emission gun, a Gatan ENFINA electron spectrometer and an EDAX energy dispersive X-ray spectrometer. Clear changes in the ELNES have been observed at interfaces in the stacks. With a TiN metal electrode a Si(O,N) phase forms at the TiN/polysilicon interface. Changes in the ELNES at the HfO2/TiN interface are more subtle and further investigation is underway.
5:30 PM - **E9.5
Characterization of Hf-Based High-k Gate Dielectrics Using Monoenergetic Positron Beams.
Akira Uedono 1 2 , Kouhei Ikeuchi 1 , Takashi Otsuka 1 , Kenji Shiraishi 2 3 , Kikuo Yamabe 1 2 , Seiichi Miyazaki 2 4 , Naoto Umezawa 2 , Abudul Hamid 2 , Toyohiro Chikyow 2 , Tsoshiyuki Ohdaira 5 , Makoto Muramatsu 5 , Ryoichi Suzuki 5 , Seiji Inumiya 6 , Satoshi Kamiyama 6 , Yasushi Akasaka 6 , Yasuo Nara 6 , Keisaku Yamada 2 7
1 Institute of Applied Physics, University of Tsukuba, Tsukuba, Ibaraki, Japan, 2 Nanomaterials Laboratory, National Institute for Materials Science, 1-1 Namiki, Tsukuba, Ibaraki, Japan, 3 Institute of Physics, University of Tsukuba, Tsukuba, Ibaraki, Japan, 4 Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter, Hiroshima University, 1-3-1 Kagamiyama, Higashi-Hiroshima, Japan, 5 , National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki, Japan, 6 , Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki, Japan, 7 Nano Technology Research Laboratory, Waseda University, 513, Waseda-Tsurumaki, Shinjuku, Tokyo, Japan
Show Abstract
Symposium Organizers
Raj Jammy SEMATECH
Ajit Shanware Texas Instruments, Inc.
Veena Misra North Carolina State University
Yoshitaka Tsunashima Toshiba Corporation
Stefan De Gendt IMEC
E10: Interface II
Session Chairs
Thursday AM, April 20, 2006
Room 3008 (Moscone West)
9:30 AM - **E10.1
Fundamental Studies of Gate Metal/High-κ Interactions in Advanced CMOS Stacks
Matt Copel 1
1 , IBM T.J. Watson Research Center, Yorktown Hts, New York, United States
Show AbstractBefore we can replace the gate dielectric in silicon CMOS with a high-κ material such as HfO2 or HfSiOx, we must engineer the entire stack to function. This means not only must the stack remain chemically stable, but the capacitance must be superior to current technology, and threshold voltages must be close to band-edge performance. Furthermore, these requirements must be met after thermal processing. Obtaining proper operating thresholds has proved to be daunting, and meeting this requirement has revealed a large gap in our fundamental understanding.Underlying the difficulties is an inability to stabilize metal-oxides in contact with metals. Metals can function both as an oxygen source and an oxygen sink; the former causes growth of interfacial SiO2, the latter induces threshold-shifting defects. Either problem will render a metal-oxide unusable. Fundamental work using medium energy ion scattering (MEIS) and photoemission spectroscopy show that the difficulties can be studied in isolation and traced to basic materials problems. Furthermore, the results are closely correlated with electrical results from realistic devices. Interface width and composition in gate stacks can be accurately measured with MEIS. To get high depth resolution, the gate metal is chemically etched away, and the dielectric functions as an etch stop. With MEIS we are able to show that interface growth occurs even when structures are processed in ultra-high vacuum conditions, indicating that the gate metal is an oxygen source.Threshold voltages are influenced by the metal/dielectric interaction, and undergo substantial modifcation during processing. For the case of a pFET metal on HfO2, thermally induced defects shift the threshold away from the band edge. Photoemission results substantiate the idea that the shift is due to a dipole at the metal/dielectric interface, and the behavior is consistent with charged oxygen vacancies. Because the observations are for highly idealized structures in a laboratory environment, we can conclude that the phenomenon is a fundamental property of metal-oxide interfaces rather than a processing artifact limited to complex FET structures.
10:00 AM - E10.2
Silicate Formation at the Interface of high-k dielectrics and Si(001) Surfaces.
Dieter Schmeißer 1 , Franz Himpsel 2 , Fan Zheng 2 , Hans-J&ürgen Engelmann 3 , Ehrenfried Zschech 3
1 Angewandte Physik-Sensorik, BTU Cottbus, Cottbus, Brandenburg, Germany, 2 Department of Physics, University of Wisconsin-Madison, Madison, Wisconsin, United States, 3 , AMD Saxony, Dresden Germany
Show Abstract10:15 AM - E10.3
Processing Impact on Bulk and Interface Charges in Lanthanum Silicate Thin Films.
Jesse Jur 1 , Daniel Lichtenwalner 1 , Angus Kingon 1 , Naoya Inoue 2 1
1 Material Science and Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 System Devices Research Laboratories, NEC Corporation, Kanagawa Japan
Show AbstractLanthanum silicate has been investigated as an alternate dielectric, exhibiting the ability to minimize an SiO2 interfacial layer and show thermal stability consistent with transistor processing flows. As the case with many alternative dielectrics, the effect of charges on the properties of the transistor and utilization of methods to reduce the density of these charges is poorly understood. Additionally, the use of non-standard gate metals complicates device fabrication and in particular, methods to reduce unwanted charges. This study is intended to show processing effects on the fixed charge and density of interface states of La-Si-O gate dielectric MIS devices by means of electrical measurements. In the experiment, La-Si-O films, with a physical thickness of 1.6 nm, were deposited on a Si substrate using Ta and TaN as the gate electrode. Samples were then rapid thermal annealed up to 1000°C in flowing Ar and N2, followed by electrical characterization to establish discrepancies between the Ta and TaN stack designs. For instance, with Ta as the gate electrode, density of interface state values of 1013 eV-1cm-2 were measured after 700°C annealing (EOT = 0.8 nm) and decreased to 5x1011 eV-1cm-2 after 1000°C annealing (EOT = 2 nm). A concurrent reduction of positive fixed charge to negligible values is observed. In the condition with TaN as the gate electrode, a higher density of interface traps is attained along with an EOT of 1.1 nm after a 1000°C annealing. A suggested mechanism for the observed difference in the interface trap densities for the two gate metals is the amount of oxygen allowed to diffuse to the Si/La-Si-O interface, indicated by the higher EOT and lower interface trap density using Ta. Optimization of the processing method using a low temperature forming gas anneals show further improvements of the electrical properties of the films.
10:30 AM - E10.4
Interface Engineering During Epitaxial Growth of high-K Lanthanide Oxides on Silicon.
H. Joerg Osten 1 2 , Malte Czernohorsky 1 , Eberhard Bugiel 1 , Dirk Kuehne 1 , Andreas Fissel 2
1 Institute of Electronic Materials and Devices, University of Hannover, Hannover Germany, 2 Information Technology Taboratory, University of Hannover, Hannover Germany
Show AbstractThe Si/dielectric interface properties influence the device performance significantly. Often the interface is not stable and changes during and after the growth. The formation of SiO2 and/or metal silicate interfacial layers can occur when these materials are deposited upon silicon or during subsequent annealing processes. The occurrence of an interfacial layer of SiO2 or another low permittivity material will limit the highest possible gate stack capacitance, or equivalently, the lowest achievable equivalent oxide thickness (EOT) value. A good interface requires either that the oxide is amorphous, or that it is epitaxial and lattice-matched to the underlying silicon. Amorphous dielectrics are expected to be able to adjust the local bonding to minimize the number of Si dangling bonds at the interface. The alternative is to use an epitaxial oxide. This involves more effort, but it has the advantage of enabling defined interfaces engineering. Molecular beam epitaxy (MBE), known for its superior capability in atomic level engineering and interface control, has been used in the epitaxial growth of various high-K materials. Here, we will present results for crystalline lanthanide oxides on silicon with the Ln2O3 composition (Ln = Pr, Nd and Gd) in the cubic bixbyite structure grown by solid state MBE. On Si(001) oriented surfaces, crystalline Ln2O3 grows as (110)-oriented domains, with two orthogonal in-plane orientations. MBE in combination with real time reflection high-energy electron diffraction and in vacuo x-ray photoelectron spectroscopy was used to gain a detailed understanding of the interface and film formation during epitaxial growth of Ln2O3 on silicon. For all investigated lanthanide oxides grown under ultra-high vacuum conditions, we observed the formation of crystalline interfacial silicide inclusions. The formation and stability of this silicide-like phase depends on the oxygen chemical potential. Considering the low oxygen partial pressure under UHV conditions (as used in standard MBE), the chemical potential of oxygen can become negative. Thus, silicide formation will be favorable compared to oxide formation. Based on that understanding, the whole growth procedure had to be adapted accordingly. In particular, the partial oxygen pressure during the interface formation and during growth, and the growth temperature are a very critical parameters. We found, that MBE growth under defined oxygen partial pressures can prevent any kind of silicide inclusions or interfacial void formation. On the other hand, the oxygen pressure has to be still low enough to avoid the formation of interfacial SiOx. Experimental results for Ln2O3-based MOS capacitors will be shown displaying EOT values below 1 nm and leakage currents in the mA/cm2 range (at 1 V). This makes MBE-grown epitaxial Ln2O3 layers excellent candidates for application as very thin high-K materials.
10:45 AM - E10.5
Nucleation Behaviour of Atomic Layer Deposited HfO2 Films on Silicon Oxide Starting Surfaces.
Laura Nyns 1 2 , Lindsey Hall 3 1 , Guy Vereecke 1 , Sophia Arnauts 1 , Nausikaa Van Hoornick 1 , Annelies Delabie 1 , Sven Van Elshocht 1 , Chris Vinckier 2 , Marc Heyns 1 , Stefan De Gendt 1 2
1 SPDT/TF, Imec , Heverlee, Vlaams Brabant, Belgium, 2 Chemistry, KULeuven, Heverlee, Vlaams Brabant, Belgium, 3 , Texas instruments, Dallas, Texas, United States
Show AbstractE11: High-k-Hf Based II
Session Chairs
Thursday PM, April 20, 2006
Room 3008 (Moscone West)
11:15 AM - **E11.1
Effects of EOT Scaling on Electron Mobility in PVD TaN-gated HfO2-based nMOSFETs.
Lars-Ake Ragnarsson 1 , Lionel Trojman 1 2 , Simone Severi 1 2 , David Brunco 1 3 , Annelies Delabie 1 , Zsolt Tokei 1 , Barry O Sullivan 1 4 , Vidya Kaushik 1 5 , Guido Groeseneken 1 2 , Kristin De Meyer 1 2 , Stefan De Gendt 1 4 , Marc Heyns 1
1 , Imec , Leuven Belgium, 2 Dept. of Electrical Eng., KU Leuven, Leuven Belgium, 3 , Intel Corp. c/o Imec, Leuven Belgium, 4 Dept. of Chemical Eng., KU Leuven, Leuven Belgium, 5 , Crolles-Alliance c/o Imec, Leuven Belgium
Show AbstractThe performance of Hf-based devices with poly-Si gates has improved significantly over the last few years. Symmetrical threshold voltage (VT), relatively high mobility and low leakage currents have been reported for devices which might be suitable for the 65 nm low standby power node [1]. However, these results show little promise of scalability towards the 45 or 32 nm high-performance nodes. To overcome the performance shortcomings of ultrathin poly-Si/SiON devices, considerably lower inversion thickness (<1.2 nm) and VT values than reported are needed. Replacing the poly-Si with a metal improves on the inversion layer thickness by removing the poly-depletion and Fermi-level pinning effects and by choosing band-edge work function metals lower VT’s can be achieved. However, as a result of exposure to high temperatures commonly used in CMOS process flows, the metal work functions tend to shift towards midgap, and interfacial oxide regrowth limits the EOT scalability. In addition, for low EOT devices the mobility reduction is especially severe [2]. In this talk we demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack manufactured with a self-aligned low thermal budget process with a maximum temperature of 650°C utilizing solid-phase epitaxially-regrown (SPER) junctions. The thinnest devices have an EOT of 0.83 nm, a leakage current of ~1 A/cm2 at VG=1 V, a mobility of 180 cm2/Vs at an effective field of 1 MV/cm and an on-state drive-current (Ion) of 945 µA/µm at an off-state current of 10 nA/µm for VDD=1.2 V. In comparison, devices processed with a traditional CMOS process flow with maximum temperatures between 1000 and 1030°C are 4-5 Å thicker as a result of interface oxide regrowth and the drive current is considerably lower. We show that although improvements can be made in the EOT scaling by reducing the thermal budget, the simultaneous mobility reduction as a result of the thinner interfacial oxide cancels out the expected gain in performance. The observed improvement in drive current for the lower thickness devices is instead shown to be a result of the lower VT which in turn is a result of the lower EOT.Finally, at high thermal budgets, pre-HfO2deposition nitridation of the interface can be used to inhibit the regrowth of the interfacial oxide but at the expense of a severely reduced mobility [3]. We show that other treatments can be used to reduce the regrowth without reducing the mobility.[1] T. Watanabe et al., in IEDM Tech. Dig., p. 507 (2004), [2] O. Weber et al., in IEDM Tech. Dig., p. 867 (2004). [3] M. S. Akbar et al., Appl. Phys. Lett. 86, p. 032906 (2005).
11:45 AM - E11.2
Characterization of HfO2/Si Exposed to Water Vapor at Room Temperature.
Carlos Driemeier 1 , Elizandra Martinazzi 1 , Israel Baumvol 2 1 , Evgeni Gusev 3
1 , Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil, 2 CCET, UCS, Caxias do Sul, RS, Brazil, 3 , QualComm, San Diego, California, United States
Show Abstract12:00 PM - E11.3
Comparison Study of Crystallization and Thermal Stability of HfO2 Thin Film Deposited by Direct and Remote O2 Plasma-enhanced Atomic Layer Deposition
Inhoe Kim 1 , Seoungwoo Kuk 1 , Seokhoon Kim 1 , Choelhwyi Bae 2 , Hyeongtag Jeon 1 , Youngtag Keum 3
1 Division of materials science and engineering, Hanyang University, Seoul Korea (the Republic of), 2 , Samsung Electronics Co., LTD., Yongin-City, Gyeonggi-Do Korea (the Republic of), 3 Division of Mechanical Engineering, Hanyang University, Seoul Korea (the Republic of)
Show AbstractHigh-k gate dielectrics become one of the solutions in providing increased capacitance and reduced leakage currents without significantly increasing actual equivalent oxide thickness (EOT) of gate dielectrics. Among the high-k dielectrics, HfO2 is mainly studied with the alternative materials of the SiO2, because of its high dielectric constant (k=25~30) and large band gap (~5.68 eV). However, HfO2 crystallize at temperatures lower than 500 °C. Crystallization of HfO2 can affect the thermal stability and electrical property of HfO2 thin filmIn this research, we studied and compared on the effect of O2 plasma to the crystallization and thermal stability of HfO2 thin film deposited by using two different deposition methods which are direct and remote plasma-enhanced atomic layer deposition (DPALD & RPALD) process.The HfO2 layer was partially crystallized with DPALD process and the thickness was about 3.1 nm with 35 cycle of DPALD process. However, in case of the RPALD process, the crystallization of HfO2 was retarded. In addition, the HfO2 films, which were deposited by using DPALD method, have thicker Hf-silicate interfacial layers than the HfO2 films deposited by using RPALD process. And, we investigated the chemical state of the interface with Si-substrate by using MEIS, the result shows that O2 plasma shifted the Si peak slightly toward low binding energy and increased the oxygen content in the HfO2 thin film as increasing the cycles in the DPALD process.We used XPS, AES, TEM, and MEIS to analyze chemical, surface, and interface characteristics of the HfO2 thin films. Also C-V and I-V experiments were performed for electrical analysis of those HfO2 thin films.
12:15 PM - E11.4
Scaling ALD HfSiO gate stacks for LSTP applications
Johan Swerts 1 , Jan Willem Maes 1 , Changgong Wang 2 , Eric Shero 2 , Glen Wilk 2 , W. Deweerd 3
1 , ASM Belgium, Leuven Belgium, 2 , ASM America, Phoenix, Arizona, United States, 3 , IMEC, Leuven Belgium
Show Abstract Hafnium Silicate (HfSiO) is widely considered as the primary high-k material candidate for integration in planar 45 nm Low Standby Power (LSTP) devices, replacing SiON-based gate dielectrics. Atomic Layer Chemical Vapor Deposition (ALCVD) enables deposition of high-quality ultra-thin HfSiO films with precise thickness and composition controllability. This makes ALCVD a very promising technique for gate stack engineering and offers excellent scalability. Because of the good layer quality of ALD-based HfSiO, scaling down towards sub-1.2 nm EOT’s is possible with good wafer-to-wafer reproducibility. In this work, we present an extensive study on the effect of nitridation and the hafnium content in order to further optimize the electric properties of ALCVD HfSiO gate dielectrics for LSTP applications. Nitridation of the HfSiO is required for obtaining good device performance with poly electrodes, especially with respect to reducing VT-instability. Therefore thermal nitridation by NH3 annealing, was performed in order to optimize/balance the effect of the incorporated nitrogen on the k-value of the layers, i.e. the Equivalent Oxide Thickness (EOT), on one hand and the leakage current on the other hand. Screening of various post annealing conditions was performed on 2 nm thick HfSiO layers at different temperatures and partial pressures. The electric properties were evaluated in MOS capacitors with polysilicon electrodes. Nitridation characteristics were studied by ARXPS/XPS techniques and correlated to the observed electrical properties. The effect of the Hf-content on the threshold voltage (VT) is studied in both n- and pFET devices with poly silicon gates. It is shown that the pFET VT scales unfavourably with the increasing Hf content, whereas the nFET VT is independent on the Hf-content. The influence of the Hf-content on EOT and gate leakage has been investigated on MOS capacitors with TaN electrodes with compositions between 40 % - 80 % Hf and various layer thickness (2 nm - 4 nm). The EOT scales down with decreasing layer thickness and increasing Hf content. The gate leakage, however, is mainly determined by the physical layer thickness and does not depend on Hf-content. For a fixed EOT, the lowest leakage is observed for the layers with the highest Hf-content. In the case of the TaN metal gate capacitors, EOT values of 1.3 nm and 1.5 nm and leakage values of ~ 1.0E-03 A/cm2 and ~ 1.0E-05 A/cm2 (at Vfb –1V in accumulation) have been obtained for a 2 nm and 3 nm HfSiO film (80 % Hf), respectively.
12:30 PM - E11.5
Area-Selective Atomic Layer Deposition by Selective Surface Modification for Gate Stack Fabrication
Rong Chen 1 , Stacey Bent 2
1 Department of Chemistry, Stanford University, Stanford, California, United States, 2 Department of Chemical Engineering, Stanford University, Stanford, California, United States
Show AbstractAtomic layer deposition (ALD) is a promising thin film deposition method for a variety of materials due to its ability to produce high quality films with excellent conformality and precise film thickness control. Typically, the process permits nano-scale control of materials in the vertical direction. To develop the method for three-dimensional control of materials, we are investigating an area-selective ALD technique which will enable micro-, and ultimately nano-scale definition of the lateral structure. Our approach is to chemically modify the substrate surface in order to impart spatial selectivity to ALD. The materials we focus on are high-K dielectrics (e.g. HfO2 and ZrO2) and gate metals (e.g. Pt). We have previously demonstrated organosilane based self-assembled monolayers (SAMs) to be effective monolayer resists for the ALD process on SiO2 substrates, and have developed a successful area-selective ALD process by using the intrinsically selective adsorption behavior of deactivating molecules on patterned SiO2/Si. Recently, many studies have been carried out to evaluate Ge as an alternative semiconductor material in MOSFETs, because of its higher intrinsic carrier mobility and smaller band gap for supply voltage scaling. Unlike on Si, however, there is no stable native oxide on Ge. To solve the passivation problem on Ge substrates and extend the area-selective ALD process, we are exploring monolayers formed from reaction of 1-alkenes and 1-alkynes with H-terminated Ge substrates. Similar chemistry is also being applied on Si-H substrates. By utilizing various analytical techniques, we show that these covalently bonded monolayers can block ALD chemistry on both Si and Ge substrates. The addition of the alkene/alkyne based chemistry, which allows for direct attachment at unoxidized semiconductor surfaces, opens up new patterning schemes for the area-selective ALD process. Area selective ALD on a patterned SiO2/Si sample by 1-octadecene selective adsorption is presented. Furthermore, it is shown that by using selective surface modifications with either alkyltrichlorosilanes or 1-alkenes on SiO2/Si samples, both negative and positive pattern transfer can be achieved. These two methods are shown to be complementary. The ability to achieve area-selective ALD for both gate dielectrics and gate metals enables the potential fabrication of an in-situ gate stack, providing for an additive patterning scheme that has several advantages over the subtractive patterning used in current CMOS process flow.
12:45 PM - E11.6
Thin-Film DSC for Evaluation of Interfacial Stabilities in Gate Stack Materials.
Lawrence Cook 1 , Richard Cavicchi 1 , Christopher Montgomery 1 , Peter Schenck 1 , Mark Vaudin 1 , Martin Green 1 , Stephen Semancik 1
1 , NIST, Gaithersburg, Maryland, United States
Show AbstractThe interfacial properties of gate stack materials in CMOS devices have become critically important as further scaling to small dimensions occurs. In particular, as new materials are developed to replace traditional silicon-based dielectrics, the nature of electrode/dielectric and dielectric/semiconductor interfacial stabilities must be determined for each potential combination. It is essential that the problem of interfacial stability be addressed from both thermodynamic and kinetic perspectives. While thermodynamic prediction of interfacial stability is in principle possible, for many materials combinations, data for such calculations are lacking. Furthermore, the fact that a given combination is predicted to be unstable, does not necessarily mean that it is unsatisfactory – the kinetics of interfacial reaction may be slow enough that there is negligible interaction during processing. Also, there may be surface effects on the interfacial stability due to a surface energy contribution, giving different results than for the equivalent bulk materials. Consequently, an experimental evaluation of interfacial stability is necessary for the majority of applications. Since interfacial reaction is in general an enthalpic process, it is ideally suited for investigation by calorimetric means. In this paper, we describe a thin-film differential scanning calorimeter (DSC) capable of detecting enthalpic changes of 100 nJ or less in 1 ng or less of material. The DSC sensors consist of dual 60 μm x 100 μm pads with embedded thermopiles situated on a suspended MEMS platform. On one side of the sensor, thin-films of the materials to be measured are sequentially deposited by pulsed laser deposition or other suitable methods, thereby creating a planar interface. Enthalpic changes during heating are measured by a differential method in which the coated sensor is ramped at the same rate as the uncoated side (reference), and the thermopile signals are compared. Kinetic data can be obtained by varying the temperature scan rate over a wide range. Progress in applying these devices to the study of interfacial reactions in selected thin-film systems relevant to gate stack materials will be described.
E12: Gate Electrode II
Session Chairs
Thursday PM, April 20, 2006
Room 3008 (Moscone West)
2:30 PM - E12.1
Investigation on the Work Function of Tungsten and Thermal stability of W/SiO2/Si, W/SiON/Si and W/HfO2/Si Gate Stacks.
Pei-Chuen Jiang 1 , Jen-Sue Chen 1 , K. H. Cheng 2 , T. J. Hu 2 , K. B. Huang 2 , F. S. Lee 2
1 Department of Materials Science and Engineering, National Cheng Kung University, Tainan Taiwan, 2 , Taiwan Semiconductor Manufacturing Company, Tainan Taiwan
Show Abstract2:45 PM - E12.2
Electrical and Material Evaluation of the MOCVD TiN as Metal Gate Electrode for Advanced CMOS Technology.
Raghunath Singanamalla 1 2 , Isabelle Ferain 1 2 , Judith Lisoni 1 , Olivier Richard 1 , Laure Carbonell 1 , Tom Schram 1 , Stefan Kubicek 1 , Stefan De Gendt 1 2 , Malgorzata Jurczak 1 , Kristin De Meyer 1 2
1 , IMEC vzw, Kapeldreef 75 , Leuven Belgium, 2 , K.U.Leuven, Kasteelpark Arenberg 10, Heverlee Belgium
Show AbstractTo meet the ITRS specification for node 45 nm and beyond the poly-Si gates will have to be replaced by metal gate electrodes. Metal gate electrodes not only eliminate the gate depletion and dopant penetration problems in CMOS transistors, but also reduce the gate sheet resistance. In selecting metal gate materials for device integration, the metal work function (WF) is an important consideration since it directly affects the threshold voltage and the performance of a transistor. Integrating metal gate electrodes in a CMOS process is a challenging task because of issues of thermal stability under the conventional CMOS process thermal budget. TiN, an extensively studied material used in the back-end-of-line, was investigated as a metal gate electrode candidate for CMOS. The possibility to modulate its WF through the nitrogen content has already been reported [1]. In the present work, we will characterize the physical and electrical properties of TiN films with certain amount of C (Ti(C)N) as a candidate for metal gate CMOS technology. Ti(C)N was deposited by Metal Organic Chemical Vapor Deposition (MOCVD). This deposition technique is more compatible with the conventional CMOS process and it is more conformal compared to the physical vapor deposition (PVD). For these reasons, it makes it an excellent candidate for the future advanced architecture CMOS devices such as FinFETs. The microstructural characterizations of the Ti(C)N films were performed on the blanket wafers by depositing Ti(C)N films of 5 nm and 10 nm thickness. Crystallinity, and morphology of the Ti(C)N films were investigated by transmission electron microscopy (TEM) and the sheet resistance (Rsheet) was measured by four point probe method. The composition and thermal stability of the Ti(C)N films were evaluated by thermal desorption spectrometry (TDS) using atmospheric pressure ionization. The LOCOS based isolation method was employed to fabricate the capacitors for electrical characterization of the metal gate stack. The metal gate stack consisted of MOCVD Ti(C)N capped with n+ Poly, p+ Poly and PVD TiN on SiO2 and HfO2 dielectrics. The C-V characteristics were measured to extract the Vfb and EOT values for each of the gate stacks using the Hauser-fit program [2]. A slant etch based approach [3] was used to extract the WF of MOCVD Ti(C)N on SiO2 and HfO2 gate dielectrics and its evolution with different anneal temperature ranging from 520 °C to 950 °C. In-situ (N2:H2) plasma and post anneal treatments were implemented to reduce the hydrocarbon content and to promote the crystal growth in the MOCVD Ti(C)N films. The effect of these treatments on the WF of the metal and the Ti(C)N gate electrode and the dielectric integrity will be discussed.References:1.H Wakabayashi et al., IEDM Tech. Dig. , 1999, pp.2532. 2.Hauser Model, J.R. Hauser and A. Ahmed, Conference on characterization and metrology for ULSI technology:, pp.235, 1998.3.V. Kaushik et al., to be published.
3:00 PM - E12.3
Combinatorial Exploration of Nb-W-Pt and Ni-Ti-Pt Ternary Metal Gate Systems on HfO2
Kao-shuo Chang 1 2 , Martin Green 1 , John Suehle 1 , Eric Vogel 1 , Hao Xiong 1 , Joseph Kopanski 1 , Ichiro Takeuchi 2 , Jason Hattrick-Simpers 2 , Olugbenga Famodu 2 , Parhat Ahmet 3 , Toyohiro Chikyo 3 , Prashant Majhi 4 , Huang-chun Wen 4 , Byoung-Hun Lee 4 , Mark Gardner 4
1 Materials Science and Engineering, NIST, Gaithersburg, Maryland, United States, 2 Materials Science and Engineering, U. of Maryland, College Park, Maryland, United States, 3 , NIMS, Tsukuba Japan, 4 , Sematech, Austin, Texas, United States
Show AbstractThe traditional gate stack (poly-Si/SiO2) suffers from high leakage current and poly-Si depletion problems with further scaling, and must now be totally replaced. The exploration of the new gate stack includes many fundamental and complicated issues such as electrical characteristics and thermal stability and their interfaces. Combinatorial methodology is ideal to solve these issues because it incorporates high throughput and rapid characterization experiments. In this talk, we focus on systematically investigating the compatibility of metal gate electrodes deposited with HfO2 dielectric layers, and the band structures of the metals. Two ternary systems, Nb-W-Pt and Ni-Ti-Pt, will be demonstrated. TEM and X-ray analysis were used to understand the interfaces between the metals and HfO2, as well as their crystal structures. Wavelength dispersive spectroscopy (WDS) was used to map the compositions. We found the combinatorial methodology to be very effective, as smooth and continuous variations of work function were observed with composition. Electrical properties such as leakage current (I) and capacitance (C) were measured on hundreds of capacitors using an autoprobe station. In the Nb-W-Pt system, we found higher leakage current close to the W-rich corner than at the Nb- and Pt-rich corners. This trend was supported by the extracted work functions, which are directly related to barrier heights: lower work functions close to the W-rich corner and higher work functions at the Nb- and Pt-rich corners. In the Ni-Ti-Pt system, a reasonable trend was also found: higher I (lower work functions) close to the Ti-rich corner and lower I (higher work functions) at the Ni- and Pt-rich corners.
3:15 PM - E12.4
Metal Electrodes Work Function Measurement at Deca-Nanometer Scale using Kelvin Probe Force Microscope: a Step Forward to the Comprehension of Deposition Techniques Impact on Devices Electrical Properties.
Nicolas Gaillard 1 2 , Denis Mariolle 3 , Francois Bertin 3 , Mickael Gros-Jean 1 , Ahmad Bsiesy 2 4
1 , STMicroelectronics, Crolles France, 2 , CEA-DRFMC / Spintec Laboratory, Grenoble France, 3 , CEA-LETI, Grenoble France, 4 , Universite Joseph Fourier, Grenoble France
Show AbstractNumerous metals and stacks are currently investigated to replace polysilicon electrodes of MOSFETs in order to suppress high resistance and depletion phenomena. To address those issues, advanced researches are focused on new metals deposition processes and work function (WF) tunability. Electrode WF is a key parameter since it governs major devices electrical characteristics such as MOSFETs threshold voltage and Metal/Insulator/Metal (MIM) capacitors leakage currents. Thus, the understanding of deposition processes impact on metal WF value and also its fluctuations within layer becomes an important issue in sub-0.1 µm technologies.We report in this paper metal WF mappings performed at deca-nanometer scale with a Kelvin Probe Force Microscope (KFM). Based on charges transfer annulations between a Pt/Ir coated AFM tip and the metal sample connected as a capacitor, KFM is a spatially resolved technique adequate to characterize local WF variations with a better than 10 meV noise level.We first demonstrate the KFM accuracy through characterizations of polycrystalline samples. A 51 meV WF variation over a 30*30 µm2 copper area has been measured and gradual WF transitions between adjacent grains has been clearly observed. Coupled to an Electron Back Scattered Diffraction (EBSD) analysis of the same Cu area, the KFM measurement allows linking directly for the first time each grain WF to its crystallographic orientation over a wide area. This experimental observation is in agreement with Smoluchowski’s smoothing theory: the denser the crystallographic face, the higher the WF. Once this relation established, KFM turns into a precise surface crystallography analyser and allows assigning grain orientation of nanometric films whereas EBSD probes at least 50 nm thick layers.In a second part, WF measurements of TiN, W, WN, WNC and Ru films deposited by Atomic Layer Deposition (ALD) on various substrates are presented. Among numerous stacks, one can note for example a 400 meV WF increase between a conventional sputtered TiN film and an ALD WN layer, both 10 nm thick and deposited on Cu substrates. We have also measured a 280 meV WF difference between two TiN films (30 nm thick) sputtered on Al and SiO2 substrates. X Ray Diffraction (XRD) analyses indicate that TiN preferential grain orientation differs between Al and SiO2 substrates confirming once again the impact of crystalline structure on WF value through the substrate dependence of growth mechanisms.
3:30 PM - E12.5
Study of Magnetron Sputter Deposition of Metal Gate Electrodes.
Mengqi Ye 1 , Zhendong Liu 1 , Peijun Ding 1 , Steven Hung 2 , Khaled Ahmed 2
1 Thin Films Group, Applied Materials, Inc., Santa Clara, California, United States, 2 Front End Products Group, Applied Materials, Inc., Santa Clara, California, United States
Show AbstractThe problems of poly silicon gate depletion, high gate resistance, and boron penetration in traditional poly gate become more severe with the continued scaling of gate length and gate oxide thickness in complementary metal-oxide-semiconductor (CMOS) technology, driven by higher performance and circuit density requirements. Metal gate is a promising technology that can overcome these issues and has been researched extensively. The major challenges are to find metals with suitable work functions and good thermal stability, and to integrate them into CMOS process. The desirable gate work functions for bulk n- and p- metal-oxide-semiconductor field effect transistors (MOSFET) are at silicon conduction and valence band edge levels respectively. In addition, gate metal deposition can not degrade the ultra-thin gate dielectrics, and the metal gate structure can not be damaged during subsequent high temperature process steps.Magnetron sputtering, with low operation cost, high flexibility and high maintainability, is an established manufacturing method for many metallization applications. Sputtering is more effective for evaluating various metal gate candidates than atomic layer deposition (ALD) or chemical vapor deposition (CVD). However, one of the most challenging problems with sputter deposition is how to prevent the underlying ultra-thin dielectrics from plasma damage during gate electrode deposition processes in order to ensure optimum device performance and reliability. In this study, we carried out a systematic study of magnetron sputter deposition of metal gate electrodes using both experimental and numerical methods. The effects of charging damage and energetic particle bombardment were evaluated. Langmuir probe and ion probe were used to measure electron and ion characteristics. Capacitance-voltage (C-V) measurement of MOS capacitors was used to evaluate film and device properties. Charge monitoring wafers was used to evaluate charging damage. We will also present how variation of the dielectrics thickness affected the film interface defect levels. The method of using stacked ALD deposited and magnetron sputter deposited films will also be discussed.