Symposium EL08—Next-Generation Interconnects—Materials, Processes and Integration

The effective resistivity of conventional Cu interconnect lines increases by more than two orders of magnitude as their width decreases from 30 to 6 nm. Alternative metals have the potential to mitigate the resulting resistivity bottleneck by (a) facilitating specular interface scattering with an insulating lattice-matched liner, (b) increasing the grain size or the grain boundary transmission through Fermi surface matching, and (c) choosing a metal with a low product of the bulk resistivity times the bulk electron mean free path. Electron transport measurements on epitaxial metal layers in combination with first-principles simulations are used to quantify the resistivity scaling for a series of metals including Cu, W, Ru, Mo, Co, Rh, and Ir, and to provide insight into the interface structure and chemistry requirements that lead to specular electron scattering and therefore a low resistivity for narrow interconnect lines.
J. Appl. Phys. 127, 050901 (2020). https://dx.doi.org/10.1063/1.5133671

Device integration in modern electronics has become complicated with increasing complexity in new generation of devices. Photolithography based conventional techniques are widely used for patterning materials for various electronics applications. These conventional techniques require multiple steps and high vacuum processing, which increase the fabrication cost. Direct printing of metallic interconnects in room temperature without mask and post processing step (high temperature thermal annealing) to achieve the electrical properties close to bulk can significantly reduce the manufacturing cost. Along with low manufacturing cost, superior quality of the printed metal is also highly demanding to be fit in the electronics applications.
Here, an additive printing process based on localized electrodeposition (LED) is demonstrated to print pure metallic interconnects at micro- and meso-scale on rigid and flexible substrates. LED is a 3D electrochemical nano-, micro-, meso- scale printing technology that allows the direct printing of high density, high aspect ratio, and good quality 3D metals and alloys structures at room environment. In the LED process, a nozzle containing the electrolyte of the metal or alloy of interest functions as the printing tool bit. A combination of SEM, XRD, FIB, AFM, nanoindentation, DSC, and electrical characterizations was used to characterize the structure and the properties of the printed interconnections. Microscopy and spectroscopy showed that the printed metal is solid with no porosity, smooth, and with low impurities. Electrical resistivity close to the bulk ( ∼2-time) was obtained without any thermal annealing. Mechanical characterization confirmed the mechanical strength close to the bulk with good adhesion strength of the printed interconnects to the silicon wafer. Thermal analysis further confirmed the melting point of the printed interconnects is close to the bulk. Promising electrical, thermal, and mechanical properties and good adhesion strength make this process attractive candidate for next -generation integrated circuit (IC) applications. Using this process, Cu or Ni micropillar bumps can be directly printed for flip chip interconnections and microscale interconnections for device integration. Such a process can also be used to fabricate functional devices.

Recently we have demonstrated that hydrogen evolution assisted (HEA) electroplating can be used for rapid lateral growth of copper across a gap between two copper traces on a printed circuit board (PCB). In this work, the HEA approach has been applied for growing copper traces on three different fabrics of 1000 Denier Coated Cordura Nylon, Laminated Polyester Ripstop, and 100% Virgin Vinyl. To provide the conductive path for the electroplating, first, the desired pattern was applied as a template on the fabric using a conductive ink including multiwalled carbon nanotubes (MWNTs). The template was then metalized by lateral coating with copper. The fastest copper growth rate was achieved in 1000 Denier Coated Cordura Nylon sample (370.96 μm/s), while 100% Virgin Vinyl sample showed the slowest growth rate of 99.57 μm/s. Further study of the morphologies using the scanning electron microscopy technique showed that the material and the texture of the fabric directly affect the morphology of the electroplated copper. The results are very promising for developing a new method of fabricating wearable electronics by direct printing copper on different fabrics.

In the fabrication of microelectronic devices, which include DRAM capacitors, transistors, and back-end-of line (BEOL) interconnects, copper (Cu) films are widely studied. However, in this field, silver (Ag) is of particular interest due to its low electrical resistivity and low residual stress compared to Cu. Moreover, a downscaling to less than 100 nm is possible without a considerable increase in resistivity. [1] All these arguments impose Ag as a potential replacement of Cu for contacts and interconnects. Besides microelectronics field, the outstanding optical properties of silver make it a good choice for several applications including optical coatings for plasmonics, windows or lenses, mirrors or sensors, while its chemical reactivity is used in antibacterial surfaces. More and more of these applications require a conformal growth of ultra-thin silver layers, which represents a challenge for most deposition methods. [2]

The deposition of highly uniform and conformal conductive ultra-thin films is also of great interest in the microelectronics industry where the miniaturization of semiconductor devices introduces complex three-dimensional structures with high aspect ratio. [3,4] Consequently, one of the main challenges is to be able to uniformly fill the metallic films into these structures. Conductive ultra-thin silver films are commonly deposited by line-of-sight methods (mainly sputtering) that do not allow conformal deposition on 3D structures with complex morphology such as in microelectronic devices, and have strong uniformity limitations for non-flat substrates such as curved glass. On the other hand, non-line-of-sight methods, such as chemical vapor deposition or atomic layer deposition, usually produce non-electrically-conductive films for low thickness, due to island growth mode. [4,5]

Our new approach relies on an original two-step plasma-enhanced chemical vapor-phase deposition [2], allowing us to reach the electrical performances of silver films obtained by physical approaches without the need of additional wetting layer. Indeed, we synthetized highly conductive and uniform Ag films with a critical thickness lower than 15 nm and a sheet resistance of 1.6 Ω/sq. for 40 nm thin film, corresponding to a resistivity of 6.4 µΩ.cm. The high reflectance (up to 94%) and low absorbance (3%) in the infrared region further demonstrate the optical quality of the films, despite a still large rms roughness of 8.9 nm and justify the relevance of the product for high-performance IRR coatings. Moreover, we successfully demonstrate the high conformality of the deposited film on complex lateral high aspect ratio structures (up to 100), with better coverage than the one reported up to now for atomic layer deposition of silver.

This new processing approach opens a very promising route for the use of ultra-thin silver films for electronic and optoelectronic applications, and could be extended to other metals deposited from metal-organic precursors, in particular copper and gold, for which the deposition using chemical vapor based methods is a very active field.

[1] Amusan et al., J. Vac. Sci. Technol. A 2016, 34, 01A126.
[2] Wack et al., ACS Appl. Mater. Interfaces 2020, 12, 36329.
[3] Cremers et al., Appl. Phys. Rev. 2019, 6, 021302.
[4] Hagen et al., Appl. Phys. Rev. 2019, 6, 041309.
[5] Wack et al., J. Phys. Chem. C 2019, 123, 27196.

The recent years have proven to be a prime time for materials scientists, process and integration engineers working on interconnect technologies. Even a cursory look at the interconnect roadmap for the next 5 – 10 years will reinforce the observation that a sizeable portion of the periodic table is at play! The semiconductor industry continues to address several daunting challenges at an aggressive dimensional scale by introducing new materials and novel processes to meet modern processor requirements. These changes are not limited to just critical dimension interconnects. We also see rapid evolution for far-back-end technologies. Across the board, the challenge is developing new materials and techniques while meeting more stringent requirements for reliability, variability, and process control. However, identifying the sources of variability and resolving these issues is becoming more difficult as the complexity evolves. New metrology techniques are needed to address these challenges; however, the mindset for process control back-end-of-line process control lags behind the materials' engineering advances. Fabs either live with older technologies or, in many cases, run the processes blind. The introduction of new integration schemes such as Selective Deposition further extends the need for novel metrology capabilities. We will explore the advent of new metrology techniques with better sensitivity and higher resolution to solve challenges for advanced interconnects in my talk. We will also discuss the unique implementation of materials and dimensional metrology techniques across a few different application types and highlight future development needs in metrology, algorithms, and machine learning techniques to advance the interconnect technology roadmap.

Heterogeneous and scalable back-end-of-line (BEOL) compatible integration of high-quality crystalline III-V semiconductor materials and devices are fundamentally limited by two factors: (i) the lack of a crystalline growth surface and (ii) the <400^°C thermal budget. Here, we demonstrate high electron mobility single-crystal InAs templated mesas can be monolithically integrated on amorphous substrates at a growth temperature of 300^°C by low temperature templated liquid phase (LT-TLP) method. Importantly, a room temperature mobility of 5880 cm²/V-s and peak mobility of 6750 cm²/V-s at 50 K are measured, the highest mobility reported for any thin-film semiconductor material system directly grown on a non-epitaxial substrate. Detailed modeling of the scattering mechanisms in the grown material indicates that mobility is limited by surface roughness scattering, not the intrinsic material quality. The projected room temperature mobility can reach 10,000 cm²/V-s when reducing the RMS surface roughness of InAs from 1.8 to 1 nm, and result in ~20,000 cm²/V-s at 0.5 nm RMS surface roughness, essentially identical with unencapsulated InAs thin films hetero-epitaxially grown by MOCVD or MBE. These results pave the way for the growth of high-mobility materials directly onto the back end of silicon CMOS wafers, and other non-epitaxial substrates such as glass, and polymers for flexible electronics.

Low temperature direct bonding became a mass production technology used for various applications in the microelectronics and microsystems industries. From the first optical system elaboration in the sixties to emerging and promising 3D applications, processes continue to grow in maturity thanks to a progressive understanding of the direct bonding mechanisms. Nevertheless, many research areas still deserve further investigations.
We will first review the general requirements and the most common characterizations needed to track important parameters influencing the quality and reliability of bonded structures. Bonding strength energy measurement, acoustic microscopy, X Ray Reflectivity and Fourier Transform Infrared Spectroscopy, to name a few, are most useful help to fully understand the role of various process parameters.
Silicon and thermal silicon dioxide have been widely studied for the last thirty years as their assembly without any added layers is required for SOI fabrication. These stable and reproducible materials are very interesting to describe the chemical and mechanical mechanisms at play in confined bonding interfaces. We will put some emphasis on the key role water has during and after bonding. Adsorbed water on the surfaces is indeed trapped at the bonding interface. A post bonding annealing is usually performed to strengthen the structures. It is then quite obvious that water management plays a key role. Hydrophilicity, asperities hydrolization, silanol to siloxane bonds conversion and water stress corrosion are fundamental notions to depict and understand the behavior of bonded structures. We will also describe the common surface preparation technics used to improve the bonding strength and quality.
However, many microelectronics and microsystems applications require other material at the bonding interface. Previous considerations remains exact, however. New behaviors, models and mechanisms will benefit from such a background. Simply replacing thermal oxide with deposited oxide is not so easy, for instance. We will then have to deal with silanol groups in the oxide layer, as they will have an impact on water management. Other researches focus on alternative dielectrics and we will describe the specificity of alumina, silicon nitride and porous ultra low k materials.
We will then present some of the specificities of metallic direct bonding, with a focus on copper-to-copper direct bonding mechanisms. This technology can indeed address the growing 3D market, as it yields electrical contacts between microelectronic devices. To achieve such stacking, perfect hybrid surfaces (Silicon oxide and Copper) have to be prepared, aligned and contacted. We will discuss the surface topologies requirements and the latest bonding alignment improvements yielding stacks with connection pitches as low as 1µm.
Finally, we will discuss the main advantages and drawback of direct bonding compared to other bonding solutions, in order to propose a guideline to choose the best assembly technic.

Atomic precision advanced manufacturing (APAM) is a promising platform for creating quantum structures and advanced silicon based electrical devices at the absolute limit of doping in silicon – at activated concentrations higher than achievable by ion implantation. In this process, a hydrogen-terminated Si(100) surface is patterned by selectively removing the bound hydrogen with an scanning tunneling microscope tip in chosen areas, leaving behind a depassivated (bare silicon) pattern. Subsequent exposure to phosphine molecules leads to dissociative chemisorption of phosphine molecules in the depassivated regions only, then the entire pattern is then protected with an epitaxial silicon cap. This creates a 2D delta layer of highly conductive phosphorous in silicon that can carry 2 mA/μm of current. This ultra-doping of Si provides unprecedented electronic behavior, virtually unrecognizable to traditional Si devices, and enables its future use in advanced silicon devices and interconnects.

Our recent work focuses on exploring various aspects of integrating APAM directly into CMOS architectures, as well as the consequences of APAM on potential Beyond Moore silicon devices. Our first focus involves overcoming traditional cryogenic temperature limitations of APAM devices, and we have recently demonstrated the use of APAM phosphorus nanostructures at room temperature, overcoming previous limitations. Our second goal is to assess the compatibility of APAM delta layers with operational CMOS conditions. We recently performed accelerated aging studies at high temperatures and drive currents and will discuss the robustness and failure mechanisms of the APAM materials. Lastly, we are exploring the chemical selectivity of hydrogen and silicon depassivated surfaces to achieve patterned atomic precision deposition (APD) and etch (APE).

This work was supported by the Laboratory Directed Research and Development Program at Sandia National Laboratories and was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. Sandia National Labs is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC. The views expressed in the article do not necessarily represent the views of the DOE or the U.S. Government.

Cryogenic etching process was introduced more than 30 years ago by a Japanese team [1]. The idea was to cool the substrate to a very low temperature (-100°C) in order to freeze the chemical reactions on vertical sidewalls while maintaining them with silicon at the structure bottom submitted to the ion bombardment. A plasma of SF₆ was used to perform these experiments. However, it was shown later that oxygen was playing an important role by forming a SiOxFy passivation layer at the sidewalls [2]. Oxygen contamination was probably coming from SiO₂ sputtering in the reactor. SF₆/O₂ plasmas in interaction with a cooled silicon wafer can be used to form high aspect ratio structures. However, until recently, Bosch process [3] was usually preferred by companies to etch high aspect ratio silicon microstructures, for its better robustness and because it is a room temperature process, which does not require any liquid nitrogen to cool the substrate. Etching at low temperature of the substrate may have many advantages: reactions of interest mainly occur on cooled surfaces, higher etch rate can be obtained, it can be used for nanometric patterns and surface diffusion can be minimized … [4] Moreover, new chillers are now available to cool down the wafer to very low temperatures without using liquid nitrogen. These assets make cryoetching generate more and more interest in the semiconductor industry.
In particular, cryogenic etching offers new opportunities for next generation interconnects. It can be used to anisotropically etch porous low-k materials. It is well known that ultra low-k material, which is used for the first levels of interconnection in CMOS technology, can be strongly damaged by plasma etching processes. Porous SiOCH is a typical low-k material used in microelectronics. Methyl depletion due to radical diffusion and reactions through the pores are some of the observed unwanted effects. Ion bombardment and VUV exposure can also damage the low-K material, leading to an increase of the k value [5]. In order to reduce Plasma Induced Damage, a technique based on the cryogenic process was introduced in 2013 [6]. It consists in cooling the substrate to a low temperature in order to reduce species diffusion and create a passivation layer on the sidewalls and on the pore surface. Several processes have been successfully tested involving C₄F₈/SF₆ plasma chemistry at -120°C. [7, 8]. The idea was to fill in the porous material by condensation of C₄F₈ before etching, and prevent plasma damage of the low-k material. Anisotropic etched profiles were obtained with an enhanced selectivity in SF₆/C₄F₈ plasma process at low temperature. The effect of the low temperature was clearly observed on the equivalent damage layer (EDL), which was evaluated by ex situ Fourier transform infrared (FTIR) spectroscopy and in situ ellipsometry. An anneal step at 350 °C was also used to completely desorb the remaining CF_x species from the pores. An equivalent process at higher temperature was proposed using organic molecules having a higher boiling point (HBPO – Higher Boiling Point Organic).
[1] S. Tachi, K. Tsujimoto and S. Okudaira Appl. Phys. Lett. 52 616 (1988)
[2] J. W. Bartha et al. Microelectron. Eng., 27 453 (1995)
[3] F. Laermer and A. Schilp US Patent 5498312 (assigned to Bosch GmbH) (1996)
[4] R. Dussart et al., J. Phys. D: Appl. Phys. 47 123001 (2014)
[5] M. R. Baklanov et al. J. Appl. Phys., 133 041101 (2013)
[6] L. Zhang et al., J. of Solid State Sc. and Technol., 2(6), N131 (2013)
[7] F. Leroy et al., J. Phys. D: Appl. Phys. 48 435202 (2015)
[8] L. Zhang et al., J. Phys. D: Appl. Phys. 49 175203 (2016)

As the critical dimensions of semiconductor devices are reduced for high performance, fast speed, and low operating power, copper has been used as the interconnect metals because it has low resistance and less electromigration. For the realization of copper interconnect into the devices, the etching of copper thin films are necessary. However, the conventional dry etching of copper is difficult because conventional etching gases such as Cl₂, HCl, HBr are formed nonvolatile by-products on the copper films. Currently, the damascene process is used for copper pattering. However, as the critical dimensions are further reduced down to 10s nm scale, the damascene process shows its limitation. Therefore, new etch process containing new gases needs to be developed.
In this study, the copper thin films were etched using non-corrosive gas mixture in pulse-modulated RF plasma. We investigated the effect of pulse-modulated RF plasma etching on etching characteristic compared to using the conventional continuous wave (CW) plasma etching. This modulated plasma can provide the specific plasma conditions modified by special matching system that can change on-off duty ratio of 13.56 MHz RF power and frequency on the specific duty ratio. In this research, the etching characteristics of copper thin film masked with nanometer-scale patterns were investigated in non-corrosive gases using pulse-modulated inductively coupled plasma reactive ion etching (ICP RIE). The effects of on-off duty ratio and frequency of pulsed plasma on the etch characteristics of copper were examined. Then, the etch profiles of copper thin films were observed by scanning electron microscopy and the etch mechanism was investigated using optical emission spectroscopy and X-ray photoelectron spectroscopy.
Acknowledgments
This research was supported by the MOTIE(Ministry of Trade, Industry & Energy (10080450) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Coper interconnect, which has low resistivity, high electromigration resistance, and good mechanical properties, has replaced aluminum interconnect as the semiconductor devices are scaled down. However, copper interconnect could not be patterned by the conventional plasma etching technics because copper has very low reactivity and its etch byproducts are nonvolatile. Thus, copper patterning has been accomplished using ‘damascene’ process. However, as the critical dimensions of the devices decreased to nm scale, the resistivity of copper interconnect increased than that of the bulk resistivity. It occurs due to the surface scattering and grain boundary scattering of the copper as its dimensions are shrunk. Therefore, conventional dry etching method which can directly utilize low resistivity of the copper films should be developed.
Previously, dry etching of copper films using various halogen gases such as Cl₂, SiCl₄, HCl, and CCl₄ was performed, and the results were unsatisfactory due to the copper halide byproducts which were remained on the copper surface. On the other hand, organic chelator materials such as hexafluoroacetylacetone was used to the dry etching of the copper. Recently, inductively coupled plasma reactive ion etching using several organic materials were performed and good etching profile in the mm-scale copper line pattern was achieved.
In this study, nanometer-scale patterned copper thin films have been etched using organic chelate materials with additives in inductively coupled plasma reactive ion etching. The influences of etch parameter such as gas concentration, ICP source power, bias voltage to the substrate, and process pressure have been investigated. The etch rate, etch selectivity, and etch profile of the copper film were examined by surface profilometer and field emission scanning electron microscopy. Then, the etch mechanisms were investigated using X-ray photoelectron spectroscopy and optical emission spectroscopy.

Acknowledgments This work was supported by Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (MOTIE) (0008458, PBL Oriented Semiconductor Equipment Engineer Recruits (POSEER), 2020 The Competency Development Program for Industry Specialist)

In semiconductor industry, SiCOH films with low dielectric constant (k ≤ 4.0) have been widely used as inter-metal dielectric (IMD) materials in the interconnects of semiconductor chips, to reduce a resistance-capacitance delay. In this study, the SiCOH films were deposited on silicon substrates using the plasma enhanced chemical vapor deposition of tetrakis(trimethylsilyoxy)silane (TTMSS) and cyclohexane (CHex) precursors. The chemical structure and materials performances of the SiCOH films strongly depended on deposition temperatures and flow rate ratios of TTMSSS/CHex. Deposition temperatures varied in the range between room temperature and 400 ^oC. The flow rate ratios of TTMSS/CHex were determined by the control of argon carrier gas which transports each vaporized precursor from the bubblers to a process chamber. Physicochemical structures including porosity, density, and chemical composition of the SiCOH films affected their mechanical and electrical properties. The chemical bonds and compositions of the SiCOH films were investigated using Fourier transform infrared spectroscopy and X-ray photoelectron spectroscopy. The chemical bonds related with hydrocarbon and Si-O were the main characteristics of the SiCOH films. The mechanical properties including hardness and elastic modulus were measured by using a nanoindentation. The k values and leakage current density were determined by capacitance-voltage (C-V) and current-voltage (I-V) curves. The competition among hydrocarbon and Si-O bonds depending on deposition conditions affected the k values and mechanical strengths of the films. The enhanced mechanical and electrical performance with the optimized deposition conditions suggested the possibility of applying SiCOH films as IMD materials.

Despite their unusual properties, the reliable integration of low-k dielectric hybrid organosilicate glasses into interconnects for microelectronic device technologies is challenging due to their poor elastic and fracture properties. It is therefore crucial to explore the structure-property relationships of these materials to be able to design mechanically stiff and fracture resistant low-k dielectric hybrids for their successful integration into next generation interconnects. With our computational modeling, which is based on molecular dynamics simulations, we can generate highly accurate models of low-k dielectric hybrid organosilicate glasses with a wide range of structural characteristics and explore the effects of these structural characteristics on the resulting elastic and fracture properties. Our model low-k dielectric hybrid glasses have a range of different mean network connectivity, condensation degree and porosity; and they are derived from precursor molecules with a variety of geometrical features in terms of precursor chain length, molecular planarity and symmetry. Using molecular dynamics simulations, we can predict the structural stiffness of the model glass networks we generate and relate aforementioned structural features to the resulting elastic properties. As for the fracture properties, we have developed an algorithm named Min-Cut Cohesive Fracture Model which is based on a novel graph-theory approach to predict the fracture bond density and fracture morphology of our model hybrid glasses. In this approach, the glass network is treated as a graph where nodes and edges in the graph become atoms and bonds respectively. The algorithm operates on this mathematical framework and predicts the fracture path of the glass network to be the minimum cut that separates the graph, allowing us to explore fracture bond density and fracture patterns of several different low-k dielectric hybrid glass networks. Similar to elastic properties, we observe significant variations in the fracture path properties of low-k dielectric hybrid glass networks depending on their structural features. Remarkably, our results demonstrate that the hyperconnected low-k dielectric hybrid glass networks that are derived from cyclic and planar precursor molecules simultaneously enhance elastic and fracture properties. Specifically, the use of hyperconnected and cyclic planar precursors lead to ultrastiff networks which are stiffer than fully dense silica, and up to three times stiffer networks in comparison to traditional examples of low-k dielectric glasses such as the ethane-bridged oxycarbosilane (Et-OCS) glasses, while maintaining low density and low dielectric coefficient. Likewise, such networks also tend to exhibit more planar fracture paths (less fracture path meandering) with higher fracture bond density thereby significantly improving the fracture energy. This is a very important step towards the design of mechanically reliable and fracture resistant hybrid organosilicate low-k dielectric glasses for their successful integration to next generation interconnects in microelectronic applications.

In Si-LSI metallization technology and 3D-LSI, it is very difficult to obtain materials around metallization at low temperature and in a structurally- and thermally-stable state, because stability and temperature are generally inversely proportional. We have succeeded in forming at low temperatures insulating barriers and diffusion barriers. In particular, the sputtering method using radical reaction can form a thin film with excellent thermal stability without heating. I will explain the characteristics of the barrier film obtained by these technologies and an example of research on low-temperature deposition of barriers using the latest technology.

Understanding the electrical conduction properties of a single nanostructure is essential for an insight into the fundamental charge transport through the 1D materials and also for exploring the collective behavior of an array of such nanostructures. TiO₂ nanostructures, such as electrochemically grown nanotubes, have been widely studied in recent times for several applications. The electrolyte plays a vital role in deciding the morphology, which, in turn, govern charge transport behavior. Here we present a comparative study of the charge transport through a single TiO₂ nanotube grown by electrochemical anodization using Ethylene Glycol and Dimethyl Sulphoxide electrolytes. The individual nanotubes are assembled into nanodevices using photolithography without relying on complex and sophisticated processes like electron beam lithography or focused ion beam deposition. The electric field dependent charge transport properties show Schottky emission at lower field regime and Poole-Frenkel emission in the higher region. The temperature-dependent electrical conduction (110K - 410K) is mediated by two thermal activation processes, attributed to shallow impurities in the low-temperature range (T < 230 K) and to the donors at deep intermediate levels at higher temperatures (T > 230 K). The activation energies for EG based nanotubes are found to be higher than that of DMSO nanotubes owing to the doubled wall morphology of the formed tubes. Also, the study of the electrical breakdown phenomena of these nanotubes reveals three distinct categories of collapse. ‘Model A’ type breakdown is characterized by a stepwise rise of current up to the breakdown point and fall to zero following a non-uniform step by step decrement, which is driven by crack formation near the electrode interface and it’s propagation. ‘Model B’ shows a transient rise and fall in current, leading to breakdown due to electromigration. Whereas ‘Model C’ type breakdown observed in a bundle of nanotubes shows a mixed trend of ‘Model A’ and ‘Model B.’ The data and analysis provide insight into the current limit through an individual nanotube or bundle of nanotubes and will be useful for designing prototype nanodevices from titania nanostructures.

The electrical resistance in the back-end-of-line (BEOL) and middle-of-line (MOL) is becoming a critical factor more and more with recent shrinkage of Si CMOS. For interconnects, a thinner barrier film is required to keep the conductance in a narrower structure. Many researchers have already addressed this problem using various materials against Cu diffusion; yet, a new barrier material is strongly required. For the source/drain in transistors, Co is now a promising electrode; however, Co has a very high diffusivity in Si and a low reaction temperature easy to form silicide with Si; additionally, the Co/Si direct junction has a high contact resistance arising from a high electron Schottky barrier height (SBH) of ~0.6−0.7 eV for n-Si, owing to the Fermi-level pinning effect at the Si interface. The Co/Si junction therefore needs a diffusion barrier layer capable of the low SBH for Si. A promising solution is to use an atomically designed and engineered ultrathin barrier film.
In this work, we demonstrate a novel barrier material with excellent barrier properties against Cu and Co diffusions and the low SBH for the Co/Si junction: the WSi_n (n ≤ 12) composed of W-atom-encapsulated Si_n cage clusters.[1] The WSi_n film was prepared by the newly developed Cluster-Preforming Deposition (CPD) method.[2] In a hot-wall thermal deposition system, hydrogenated W-atom-encapsulated WSi_nH_x clusters with well-controlled n values (n ≤ 12) are preformed by reaction of WF₆ and SiH₄ in the gas phase. The WSi_nH_x clusters are then deposited onto a substrate, where they are thermally dehydrogenated and coalesce to the WSi_n film with less hydrogen content. The formed films have an amorphous structure similar to the hydrogenated amorphous Si, but they are extremely stable against annealing up to 1100 °C. We also confirmed that the WSi_n film exhibits an excellent step coverage over a high-aspect-ratio hole array with 40-nm diameter and 2-μm depth. [1]
The barrier properties of the WSi_n film against Cu diffusion were investigated using the two test structures with Cu electrodes: MOS capacitors with a 20-nm thermal oxide and p⁺-n diodes (junction depth of 100 nm) with and without the WSi_n insertion (n = 12, thickness = 5 nm). The WSi_n film exhibited excellent diffusion barrier properties for Cu contact; from the TDDB lifetime of the Cu MOS capacitors, the diffusion barrier height was estimated to be 1.33 eV under 5 MV/cm stress and the Cu on Si diodes were stable against annealing up to 600 °C.[3]
The contact properties for n-Si were investigated using the Co/Si Schottky diode with the WSi_n insertion (n = 8, thickness = 5 nm). Insertion of the WSi_n film reduced the electron SBH to 0.43 eV at Co/n-Si junctions. This is because the film is a semi-metal with a low work function close to the conduction bend edge of Si.[4] These junctions have an excellent stability against annealing up to 700 °C, leading to no appreciable interdiffusion. We directly observed that the WSi_n film prevented the Co diffusion by cross-sectional TEM and EDX.[5] These excellent diffusion barrier properties are because in the WSi_n film, all the Si atoms are strongly bonded to the W atoms forming W-atom-encapsulated clusters, suppressing the diffusion of Co and Cu atoms.
In conclusion, the WSi_n film exhibited excellent diffusion barrier properties for Cu and Co: a high barrier stability against annealing up to 600−700 °C. Consequently, this film is a promising barrier and contact material in advanced CMOS.

[1] IEDM, 22.5, (2017). [2] J. Chem. Phys., 144, 084703 (2016). [3] IITC (2018). [4] APEX 13, 061005 (2020). [5] IITC (2019).

The electric current-induced chemical reaction in Cr thin film by a micro/ nano-probe has been recently reported with detail characterization. Although the phenomenon has been employed for micro-nano fabrication and the technique is called electrolithography, this acts as a reliability failure of interconnection lines in the structure, where Cr is used as an adhesion layer, or main interconnects in microelectronic circuits. Here, for the first time, we present an investigation on the role of electric current density for such failure using a specifically designed sample. A 100 µm width, and 100 nm thin Cr film was deposited perpendicular to the Pt film of similar dimensions. The anode probe (20 µm diameter) was placed onto the Pt film whereas cathode probe onto the Cr film. The chemical reaction for an applied voltage initiated at the edge of the Pt film and not at the cathode probe. The analysis based on the COMSOL multiphysics simulation shows that the chemical reaction evolves at the high current density locations. The localized chemical reaction causes to damage the interconnection line. The study also builds a fundamental understanding of the mechanism of evolution of micro-nano patterning by electrolithography.

The low-cost, high-throughput electro-less (EL) plating method has several potential advantages over the commonly used atomic layer deposition or physical vapor deposition processes to uniformly deposit barrier and seed metal layers inside the high aspect-ratio (AR) through-Si-via (TSV) interconnections for their immense applications in both the 2.5 D and 3D (three-dimensional) heterogeneous integration. By using an all-wet approach for TSV metallization, we have been able to fill the 8~10 mm-width Cu-TSVs with AR > 10 in Si-interposer for packaging applications. Also, the successful solid-filling of the sub-micron sized TSVs with AR close to 20 by EL plating of Ni enables one to achieve the vertical interconnections on 300 mm LSI wafer for the 3D-IC integration. Micro-structural and resistivity data on both sub-μm as well as 10 μm-width conventional Cu-TSVs with AR 12 to 17 revealed that the conformal Ni layer formed by EL-Ni plating is a very good seed layer for Cu electroplating. It is also evident from the morphological and the elemental analysis data that the EL-Ni plating forms nearly-uniformly thick metal layer all along the TSV sidewall and TSV bottom, which is otherwise difficult to realize by the even sophisticated PVD tool. Therefore, the EL plating method is proved to be a highly promising method for the conformal formation of barrier/seed layers inside the high AR TSVs for future 3D integration and packaging applications.