2022 MRS Spring Meeting & Exhibit Landing Banner

40 Years of Semiconductor Research Corporation

2030 Decadal Plan for Semiconductors Panel Discussion and Student Poster Showcase

Thursday, May 12
1:30 pm – 5:00 pm
Hawaiʻi Convention Center, Level 3, Room 324

The Semiconductor Research Corporation (SRC) celebrates its 40th anniversary in 2022.

This session will feature a Ted Talk-style panel discussion with experts in the field of semiconductors from industry and academia who will discuss the 2030 Decadal Plan for semiconductors. Innovation in semiconductor technology is needed to advance information and communication technologies (ICT) critical to economic growth and national security. The Decadal Plan provides an overview of the global drivers and constraints for the future ICT industry, focusing on creative solutions and measured impact. Advances in semiconductor technology will be needed to manage the exponential amount of data to be moved, stored, computed, secured and converted to end-user information.

The panelists will address the five seismic shifts that will define the future of semiconductors and ICT:

  • Analog data deluge
  • Growth of memory and storage demands
  • Communication capacity vs. data generation
  • ICT security challenges
  • Compute energy vs. global energy production

The discussion will be moderated by a student host, Emma Pawliczak, Binghamton University, The State University of New York.

This will be followed by an interactive poster session with students whose research is funded through SRC.

Decadal Dish Panel

Robert ClarkRobert D. Clark
Tokyo Electron Limited

Steffen Hellmold
Twist Bioscience

Marie KrysakMarie Krysak

Matthew MarinellaMatthew J. Marinella
Arizona State University

Heike RielHeike Riel
IBM Research-Zurich

Emma PawliczakEmma Pawliczak
Binghamton University, The State University of New York

Student Poster Showcase

Click each name to see the abstract.



Mostafa Abuseada, Min Jong Kil and Timothy S. Fisher

Mechanical and Aerospace Engineering Department, University of California, Los Angeles, CA 90095

In high-performance packages such as those for power amplifiers, heat spreading is an important attribute that improves overall thermal management and performance. Through an approach of direct transformation of polymers into graphitic films discussed in this work, this heat spreading capability is expected to improve significantly. We report a custom vacuum deposition process that synthesizes thin graphitic layers on organic substrates through direct pyrolysis. The process utilizes a concentrated 10 kWe xenon light source to produce a peak heated zone of approximately 3 cm diameter with a maximum heat flux of 3.2 MW/m2 through rapid flashes. The light source provides ultrafast heating and improves graphitic growth rates over relatively larger areas compared to a laser, and also mitigates porosity in the graphitic layers that impedes heat spreading. The approach substitutes an energy-intensive manufacturing process with a green alternative that employs direct, concentrated solar energy. The enhanced organic substrates are analyzed using Raman spectroscopy and thermal diffusivity measurements, which indicate successful graphitic conversion with enhanced thermal properties. Process optimization involves variation of parameters such as flash duration (30-90 sec), number of flashes (1-5), and time between flashes (10-20 sec). Conditions for maximum graphitization and heat spreading enhancement are reported.

Ezer Castillo, Michael Njuki and Nikolay Dimitrov

Department of Chemistry, Binghamton University, The State University of New York, P.O. Box 6000 Binghamton, NY 13902-600 USA

In microelectronics, nanostructured materials have been of interest as new alternative materials for traditional chip-to-substrate interconnects. Specifically, nanoporous Cu (np-Cu) is an excellent candidate for such application due to its high surface area-to-volume ratio that results in lower melting temperature, compared to its bulk metal counterpart. Furthermore, it is hypothesized that the incorporation of Sn on np-Cu would further lower the sintering temperature and generate a Cu-Sn intermetallic-based joint. The foundation of our work relies on the fabrication of np-Cu/Sn composites that will feature fine length scales and a bi-continuous network of ligaments and pores. In this work, np Cu-Sn composites were prepared using two all-electrochemical approaches. The first approach involved the coating of pre-prepared np-Cu films with a thin layer of Sn. np-Cu films were prepared via controlled dealloying of electrodeposited Cu-Zn precursor alloys. The resulting np-Cu films were then coated with Sn via galvanic square-wave pulse deposition. The second approach involved the formation of mixed np-CuSn by etching of electrodeposited Sn-rich Cu-Sn alloys, thereby bypassing the Sn-coating step used in the first approach. The preparation and characterization of the resulting materials using either approach will be presented in detail.

Kisung Chae1,2, Andrew C. Kummel1 and Kyeongjae Cho2

1 Department of Chemistry and Biochemistry, University of California San Diego
2 Department of Materials Science, The University of Texas at Dallas

Ferroelectric field-effect transistors (FEFETs) based on fluorite-based ferroelectric (FE) oxides (hafnia, zirconia and their alloys) are promising due to robust FE behaviors in large process window and favorable processing conditions with the modern semiconductor manufacturing procedures. One of the challenges, however, is to lower the polarization switching voltage of about 4V. The high external bias required for polarization switching is mainly due to the large intrinsic energy difference between the polar orthorhombic phase and the transient tetragonal phase (ΔE) which is roughly 100 meV/HfO2 in bulk. Here, density functional theory is employed to propose the tetravalent doping (Si and Ge) in HfO2 as a novel method to lower the intrinsic polarization switching energy barrier. Energy landscape during the polarization switching process was calculated by using nudged elastic band, revealing that both the ΔE and energy barrier for switching are sensitive to the tetravalent dopant concentration. The local atomic arrangement at the dopant site differed significantly depending on the phase of the HfO2. When tetragonal HfO2 was doped with tetravalent dopant, favorable tetrahedral configuration was formed; conversely, relatively unfavorable, distorted octahedron was formed in the orthorhombic phase due to the low crystal symmetry.

Cindy Y. Chen, Yu-Chuan Lin, Azimkhan Kozhakhmetov, Ke Wang, Haiying Wang, Michael Labella, Jess Kachian, Joshua A. Robinson

2D transition metal dichalcogenides (TMDs) exhibit a spectrum of interesting electronic and optical properties that motivates the development of scalable synthesis processes. While 2D layers are hailed as having no out-of-plane bonding, these systems are rarely defect-free, and the atomic thickness leads to a high susceptibility to environmental factors that reduce layer stability and electronic performance. In this work, we explore atomic layer deposition of ultrathin (2-10 nm) boron nitride as a scalable, non-water-based, low-temperature process for 2D TMD encapsulation. Two routes of ALD, plasma-enhanced (PE) and thermal (Th), are explored to understand the impact of ALD precursor and processing parameters on the resulting morphology, chemical composition, and structural properties of boron nitride. ThALD, utilizing sequential injections of NH3 and BCl3, results in fully amorphous BN, whereas the increased energy from N2 plasma generation in PEALD yields nanocrystalline BN with higher surface roughness. X-ray photoelectron spectroscopy and electron energy loss spectroscopy reveals that amorphous BN exhibits both sp2- and sp3- bonded B-N coordination environment. Furthermore, using MoTe2 as a test 2D TMD system, we find that BN-capped MoTe2 is significantly more resistant to oxidation and material degradation after prolonged periods (> 1 month) of time in air. Finally, we will discuss the impact of ALD-BN on the electronic and optical properties of a range of TMDs, with discussion of implications on using ALD-BN as a robust dielectric for 2D-based electronics.

High-end electronic systems increasingly demand advanced packaging solutions such as fan-out wafer level packaging (FOWLP) to enable a broad array of system-in-package (SiP) devices at a competitive price point. In addition to design re-use, multi-chip integration at the package level may combine circuits and devices from multiple process technologies, including MEMS transducers, optical components, magnetic materials, biosensor substrates, or low-loss RF materials. In parallel, advances in 3D-printing have enabled additive micro-manufacturing of both dielectrics and conductors, offering unique opportunities for rapid prototyping microelectronic systems. Leveraging FOWLP alongside high-resolution 3D-printing of conductive materials provides a framework for highly reconfigurable fabrication of redistribution layers and rapid prototyping of sensor-system-in-package devices. In this work, a process is presented for incorporating micron-scale 3D-printing of conductive interconnects to ICs integrated using a FOWLP process, where 3D-printing may be leveraged both before and after the compression molding process. Preliminary electrical characterization of interconnects yields sheet resistances of less than 50mΩ/square for post-mold prints. Additionally, a sensor die was used to demonstrate the process flow for post-mold 3D-printing of interconnects to embedded ICs.

Sanjay Gopalan, Maarten L. Van de Put, Massimo V. Fischetti

Theoretical models are critical for evaluating two-dimensional materials as possible channel materials in future field-effect transistors (FETs). The majority of modelling attempts concentrate on electronic transport in ideal free-standing layers, ignoring the dielectric environment’s effect on transport characteristics. We study the effect of the dielectric environment on carrier transport in monolayer MoS2 by extending our Monte-Carlo model for a free-standing monolayer to include dielectric screening and remote-phonon scattering in a double-gate. We find that the dielectric screening can significantly improve the carrier mobility of the TMDs on a variety of dielectric substrates, but the addition of remote-phonon scattering reduces the mobility considerably, in most cases, below its free-standing value. We then extend our model to simulate a 2D material based field effect transistor (FET), considering monolayer MoS2 as the channel material[1][2].

[1] Gautam Gaddemane, Maarten L Van de Put, William G Vandenberghe, Edward Chen, and Massimo
V Fischetti. Monte carlo analysis of phosphorous nanotransistors. arXiv preprint arXiv:
2007.14940, 2020.
[2] Maarten L Van de Put, Gautam Gaddemane, Sanjay Gopalan, and Massimo V Fischetti. Effects
of the dielectric environment on electronic transport in monolayer mos 2: Screening and remote
phonon scattering. In 2020 International Conference on Simulation of Semiconductor Processes
and Devices (SISPAD), pages 281–284. IEEE.

Photolithography based cleanroom micro-nanofabrication to create micro to meso scale structures in silicon has revolutionized world technology. However, cleanroom based processing suffers from one major limitation – it is only able to make single-level structures, but not complicated multiple levels of structure monolithically off a single wafer. The primary challenge in the conventional route arises during the multiple rounds of lithography needed to make these multiple levels on top the wafer which already has few micron features etched in it. These features interfere with the spin coating dynamics and leads to failure of the subsequent steps.

In this context, we have delineated a multi-lithography based approach that circumvents the aforementioned issue. The solution involves introducing a thin layer of silicon dioxide (SiO2) between the photopolymer and the Si substrate underneath. Multiple rounds of lithography is then performed to pattern the thin (< 3 – 4 um) SiO2 layer – this does not pose any challenge in spin-coating since the etched features in the SiO2 is ultra-thin and does not mess up the spinning process of the photoresist. To establish process robustness, reliability and repeatability, the technique was carried on multiple times to give rise to several different kinds of multi-level structures.

As 5G technologies gradually launched, researchers are looking for the next generation of wireless communication (6G). D-Band (110 GHz to 170 GHz) is a promising frequency range for 6G applications. There are several challenges for integrating the RFICs into a functional module at D-band, namely low loss interconnects, antenna integration, and thermal management. In this poster, we present the design and fabrication of the glass package for an RF module which includes CMOS transmitter (Tx) and InP power amplifier (PA) chips. We use glass as the core substrate to embed both kinds of dies. An antenna array is also integrated on the low-loss redistribution layer (RDL) formed with Ajinomoto Build-up Film (ABF). Dummy dies with coplanar waveguide (CPW) structures on high resistivity silicon dies are fabricated for electrical characterization. For thermal management, we developed the double side carrier process to expose the backside of the dies. Thick glass carriers and thermal release tapes are used for the process. With the backside of the die exposed, thermal interface materials are applied to attach the heat spreader.

Atharv Jog and Daniel Gall

Department of Materials Science and Engineering, Rensselaer Polytechnic Institute, 110 8th St, Troy, NY 12180, USA

The resistivity contributions from electron scattering at surfaces and grain boundaries in Rh and Ir are quantified to determine their potential as replacement metals for narrow interconnect lines. The measured resistivity vs thickness data from epitaxial Rh(001) and Ir(001) layers indicate products of bulk resistivity times electron mean free path ρoλ = (4.5 ± 0.4)×10-16 and (3.8 ± 0.6)×10-16 Ωm2 which are 1.5 and 1.8 times smaller than for Cu, indicating great promise. However, the grain boundary reflection probabilities for 111-textured Rh and Ir layers are 1.4 and 1.7 times higher than for Cu, cancelling some of the conductivity benefits. Both air exposure and Ti capping layers cause a considerable resistance increase for Cu(001) and Co(0001) layers but a five times smaller effect for Rh(001). Transport measurements on many metals including W, Mo, Ir, Ru, Rh, Cu and Co suggest that electronegative metals suppress the resistance increase caused by a potential perturbation at the surface due to liners or dielectrics, indicating a conductance benefit for Ir, Rh, and Ru. The overall results indicate that in the limit of narrow wires (< 15 nm) and sufficiently large grains (> 10 nm) both Rh and Ir are more conductive than Cu.

Karsu I. Kilic, Reinhold H. Dauskardt

Department of Materials Science and Engineering Stanford University, Stanford, CA 94305

While low-k dielectric hybrid organosilicate glasses (OSG) are widely used in interconnected device applications such as shallow trench isolation as insulating units, the process of gap filling between conducting units has been challenging. One of the challenges is related to the undesired formation of nanovoids in the low-k dielectric material confined inside the trench geometry. Importantly, the effects of such nanoscale device constraints on the structure and mechanical reliability of low-k dielectric hybrid materials are not very well understood. To close this lack of understanding and guide the related experimental efforts we performed molecular dynamics simulations where we explore the role of the molecular structure and connectivity of different low-k dielectric OSG precursors under nanoscale confinement, and predict the resulting elastic and fracture properties. We demonstrated that hyperconnected OSG precursors with aromatic rings, such as the 1,3,5-benzene molecule, pack more homogenously under confinement leading to smaller nanovoids and better mechanical reliability compared to conventionally bridged OSG precursors, such as the ethylene bridged Et-OCS molecule.

Sushant Kumar1, Christian Multunas2, Benjamin Defay1, Daniel Gall1 and Ravishankar Sundararaman1,2

1Department of Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180, USA
2Department of Physics, Applied Physics and Astronomy, Rensselaer Polytechnic Institute, Troy, NY 12180, USA

The electrical resistivity of narrow metallic wires increases dramatically with decreasing dimensions due to electron scattering from surfaces and grain boundaries. This has become a major bottleneck in the miniaturization of integrated circuits as it adversely impacts its RC delay and consequently, the efficiency of nanoelectronic devices. Hence, there is a push to search for highly conductive metals beyond the currently used copper which exhibit better resistivity scaling. Classical models show that the product of the bulk resistivity ρ times the electron mean free path λ can be employed to screen metals which have the potential to replace copper as next-generation interconnect material. The strategy is to look for metals with the lowest value of ρλ which corresponds to the largest ballistic conductance. We show that this descriptor over-predicts the increase in resistivity for metals with highly anisotropic Fermi surfaces.

We propose a new descriptor that takes into account the effect of the Fermi surface anisotropy on the resistivity scaling of narrow wires and thin films. We use first-principles calculations to predict the value of the proposed anisotropic conductance descriptor of around 4,000 different metallic compounds from the Materials Project database and shortlist highly conductive metals. We find numerous new classes of compounds, particularly intermetallics and metallic oxides, which could potentially outperform copper at nanoscale dimensions. These calculations also show that layered metallic carbides and nitrides (MAX phases) show promise as thin films but lose the advantage when forming narrow wires due to increased scattering from side walls.

Jimmy-Bao Le1, Choong-Un Kim1, Hung-Yun Lin2

1University of Texas at Arlington, Arlington, Texas 76019
2Texas Instruments, Inc., Dallas, TX 75243

This paper concerns the highly desired industry need to reliably detect failures and damages to effectively develop greater quality devices. Challenges arise in developing a suitable characterization method with the increased intricacy of fully packed devices and their metal interconnects, as the failures can occur in any location of the packaged assembly or BEOL interconnects. Alternative characterization methods have proven costly as well as time consuming, while also requiring some form of sample destruction. Previous attempts at creating a suitable nondestructive metrology included DC measurements such as DC resistance and leakage current, however these methods exhibited poor selectivity and sensitivity to damages. Our investigation postulates that the larger defects and damages within these devices are susceptible to low frequency measurements, which leads us to our proposed method of the unfamiliar low-frequency impedance spectroscopy. AC resistance and derived parameters (i.e., capacitance and inductance) have displayed suitable selectivity and sensitivity to these larger damages that can occur in the dielectic layer and metal interconnects. This method has also presented sufficient immunity to other parasitic signals in fully assembled test chips such as: probe/pad contact resistance and molding compound capacitance.

Keywords- silicon-package-interaction, interconnect failures, low-frequency impedance spectroscopy, nondestructive damage detection

Hafnium zirconium oxide (HfxZr1-xO2, or HZO), a well-known ferroelectric (FE) material system, has emerged as a highly attractive functional material for next generation device technologies, such as non-volatile memories (FeRAM), as a result of their exceptional scalability, retention, endurance, and CMOS compatibility. However, due to the polycrystalline nature of this material in thin film form, for which microstructure can vary drastically, understanding the relationships between process, structure, and performance for this class of materials has remained particularly challenging. Microscopic features – interfacial dynamics, phase, grain size and orientation, etc. – play major roles in the phase stability leading to the characteristic ferroic responses observed in HZO-based capacitors. Through systematic advanced microscopy analysis, the fundamental microstructural properties responsible for the FE behavior observed in HZO thin films can be identified. Using atomic resolution scanning transmission electron microscopy (STEM), coupled with dark-field transmission electron microscopy (DF-TEM) and nanobeam electron diffraction (NBED), the grain size distributions, phase, texture, and local epitaxy are probed in HZO-based heterostructures. Such studies will enable engineering of electrode/substrate microstructure, leading to precise control of grain texture and phase in nanoscale ferroelectric and antiferroelectric thin films for use in novel memory device technologies.

On-wafer measurements at microwave and mm-wave frequencies are sensitive to calibration, probe parasitics, multimode propagation and surface waves. Not understanding these effects when analyzing results can lead to error-prone models. This poster presents the measurement and simulation study of coplanar waveguide (CPW) transmission lines operating up to 325GHz that have been fabricated on a 525-micrometer thick high-resistivity siliconwafer. On-wafer measurements were performed in three frequency bands from 10MHz-110GHz, 140-220GHz and 220-325GHz. At frequencies greater than 140GHz, leakage energy has been observed which is believed to be a function of the substrate thickness due to surface waves and multimode propagation. The simulation study confirms that this can be minimized by thinning the substrate and an attempt to validate this with measurement has been done. Electromagnetic (EM) models for port simulation have been explored using Ansys HFSS to account for probe parasitics and understand the limitations. The wafers were placed on a glass spacer to avoid parallel plate moding between the device under test (DUT) and the metallic chuck. This influence has been considered in the simulation to mimic the measurement setup. The attenuation of the lines over the frequency band is also presented.

M. Njuki1, S. Thekkut2, P. Borgesen2, and N. Dimitrov1

1Department of Chemistry
2Department of Systems Science & Industrial Engineering
Binghamton University, P.O. Box 6000, Binghamton, New York, 13902, USA

The sporadic formation of Kirkendall voids between BGA or SMT solder joints and Cu pads is a
well-known concern. Although relatively rare and usually not publicized it has led to billion-dollar
losses in the industry. The problem was shown to be related to the quality of the electroplated Cu
and systematic studies over most of a decade eventually led to practical guidelines for how to test
for it and prevent it. However, recent results suggested that the propensity for voiding within the
Cu3Sn layer is much greater in micro-joints with thickness near or below 5 - 30μm.

The present work confirms this propensity and shows important differences in systematic trends
for joints on scales typical of 2.5/3D assemblies. Like in larger joints the voiding increases as the
intermetallic grows over time after the reflow process, but in micro-joints the voiding level
corresponding to a given Cu3Sn thickness is very sensitive to both the peak reflow temperature
and the subsequent thermal history, in this case the supersaturation of vacancies created by the
Kirkendall effect increases with temperature and is greater for thin Sn (where IMC grows faster).
If temperature is high enough and enough impurities are presence it will help in reducing
nucleation barrier, and we get more voids. Another important difference is that the voiding is
strongly enhanced by multiple reflows. This is of particular concern in 3D assembly.

Emma Pawliczak, Bryce Kingsley and Paul Chiarot

Electrospray printing is a low-cost, versatile additive manufacturing technique that uses a high electric potential to atomize a liquid suspension into a plume of droplets. In this work, our suspension consists of a polymer (polyimide) dispersed in a volatile solvent (dimethylformamide). In electrospray, the solvent rapidly evaporates in-flight, leaving behind polymer nanoparticles that aggregate to form continuous thin films. The film thickness is passively controlled by the evanescent electric charge on the printed particles, and the deposit characteristics are governed by the electrical properties of the target substrate. We evaluate the ability of electrospray printing to conformally coat substrates with complex geometries (e.g. wires and trenches) and report on how the film thickness, adhesion, and surface coverage are governed by the processing conditions, including polymer concentration, print time, flow rate, and printhead location relative to the target. We show that electrospray printed polyimide films can conformally coat non-flat features even without a direct line-of-sight to the target. We further measured the performance of the printed polyimide films, including corrosion resistance, electrical isolation, and adhesion.

Thermal boundary resistances (Rth,B’s) govern the thermal transport in a wide variety of nanostructured systems (FinFETs, interconnects, and vias) due to the increased density of interfaces. The dissimilarity of materials, interfacial planarity, and nanomanufacturing processes/conditions all affect TBRs in ways that have yet to be fully explored. In this work, we study the interfacial thermal transport between a nonreactive metal (Pt) and a dielectric by engineering two differing bonding characters: (i) the mechanical adhesion/Van DerWaals bonding offered by the physical vapor deposition (PVD) and (ii) the chemical bonding generated by PEALD.We continue our exploration of tuning Rth,B with plasma-enhanced atomic layer deposition (PEALD) to capitalize on increasing bond strength due its unique ability to chemically tune deposition processes by first introducing 40 cycle (~ 2 nm-thick), nearly continuous PEALD Pt films between 98 nm PVD Pt and dielectric materials (8.0 nm TiO2 on Si and 11.0 nm Al2O3 on Si) treated with either O2 or O2+H2 plasma. By correlating the treatments through thermal transport measurements using time-domain thermoreflectance (TDTR), we find that the Rth,B’s are consistently reduced with the same increased treatment complexity that has been demonstrated in the literature to enhance mechanical adhesion. We then introduce 10, 20, 40, 100, and 150 cycle PEALD Pt films deposited with O2 plasma between 94 nm PVD Pt and 7.3 nm Al2O3 on Si and find a minimum thermal resistance due to the augmented area provided by nucleation growth.

High contact resistance is a key limiter to the electronic performance of two-dimensional (2D) semiconductors like MoS2. Some of the best contacts to monolayer (1L) MoS2 to date are made with non-oxidizing metals like Au and Ag. However, these metals deposit as islands and can cause damage to 2D semiconductors, limiting their ability to form good contacts. Here we study, for the first time, the role of an ultrathin Ge interlayer for Ag contacts to 1L MoS2. We find the Ge interlayer improves the uniformity of the interface, reduces MoS2 damage, and improves contact resistance. We demonstrate with 1 nm Ge interlayer contacts a maximum on-state current of 220 μA/μm and contact resistance as low as 340 Ω.μm using transfer length method structures, >10x improvement over pure Ag contacts, and among the best in the world today. We further characterize the Ge/Ag contact stacks using atomic force microscopy, scanning electron microscopy, Raman spectroscopy, and X-ray photoelectron spectroscopy.
This is an important advance which may also be extended to improve contacts using Au or other metals to 2D semiconductors.

Chelsea Swank, Michelle Chen, Woojae Lee, Andrew Kummel and Eric Pop

University of California, San Diego, La Jolla, California, USA
Stanford University, Stanford, CA, USA

Polymers are one of the most widely used and diverse materials with the ability to be finely tuned for specific applications; however, most polymers suffer from a low thermal conductivity. Diamond composites are favorable for heat spreader applications including high-power semiconductors and high-frequency devices due to diamond’s thermal conductivity exceeding that of copper by 5x while being insulators. The keys to having a high thermal conductivity in a diamond-polymer composite are the diamond fraction must be high and there must be a high contact area between the diamonds. Polymermicrodiamond composites were fabricated with 10 μm monocrystalline microdiamonds and producing a slurry with water. Films were molded, and ultrasound was applied during solution evaporation to provide energy for the diamonds to overcome gravity and friction, induce edge-to-edge contacts, and obtain high packing density. The microdiamonds were then infilled with trimethylolpropane polymer as a matrix. The microdiamond composites showed a 4X improvement in the thermal conductivity, 2.16 W/mK, compared to the polymer alone 0.57 W/mK. To obtain another 10x improvement in thermal conductivity, the diamonds will be fused by Al2O3 ALD prior to polymer infill.

Ferroelectricity on HfO2 and its alloyed variants provides novel opportunities for emerging information storage applications; for example, the ferroelectric field-effect transistor (FEET) is one of the leading candidates for next generation memory technology, due to its area, energy efficiency and fast operation. In a FEFET, a ferroelectric layer is deposited on Si, with an SiO2 layer of ~1 nm thickness inevitably forming at the interface. This interfacial layer (IL) increases the gate voltage required to switch the polarization and write into the memory device thereby increasing the energy required to operate FEFETs and makes the technology incompatible with logic circuits. In this work, it is shown that a Pt/Ti/thin TiN gate electrode in a ferroelectric HfZrO2 based metal-oxide-semiconductor (MOS) structure can remotely scavenge oxygen from the IL, thinning it down to ~0.5 nm. This IL reduction significantly reduces the ferroelectric polarization switching voltage with a ~2× concomitant increase in the remnant polarization and a ~3× increase in the abruptness of polarization switching. The large increase in remnant polarization and abruptness of polarization switching are consistent with the oxygen diffusion in the scavenging process reducing oxygen vacancies in the HZO layer thereby depinning the polarization of some of the HZO grains.

Xinglu Wang, Yaoqiao Hu, Seong Yeoul Kim, Kyeongjae Cho and Robert M. Wallace

Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson TX, 75080

Transition metal dichalcogenides (TMDs) are intriguing due to their unique properties and potentials for the application in the next generation electronic devices. However, strong Fermi level pinning manifests at the metal/TMD interfaces, which could tremendously restrain the carrier injection into the channel. In this work, we illustrate the origins of Fermi level pinning for Ni and Ag contacts on TMDs in the aspects of interface chemistry, band alignment and intrinsic defects by x-ray photoelectron spectroscopy and scanning tunneling microscopy.The reaction mechanism between the metal contacts and TMDs, which is studied by density function theory, is correlated to the interface chemistry and surface morphology.The implications of interface chemistry and intrinsic defects on the true band alignment of Ni and Ag contacts on the Mo and W-based TMDs is going to be discussed.

This work was supported in part by NEWLIMITS, a center in nCORE, a Semiconductor Research Corporation (SRC) program sponsored by NIST through award number 70NANB17H041.

Zheng Wang1, Jae Hur1, Nujhat Tasneem1, Winston Chern1, Shimeng Yu1, and Asif Khan1,2

1 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta GA
2 School of Material Science and Engineering, Georgia Institute of Technology, Atlanta GA

Fluorite-structure ferroelectrics (FEs) and antiferroelectrics (AFEs) such as HfO2, its variants, and ZrO2 have gained significant attention from the semiconductor community, because they enable CMOS-compatible platforms for high-density, high-performance energy efficient non-volatile memory technologies that are well-suited for data-intensive computing. Even though HfO2 and its variants have been extensively studied over the past few years, little has been done to aggregate those data into ferroelectric properties to provide the insight necessary to create a predictive model for ferroelectrics due to lack of automated parameter extraction tools. On the other hand, direct determination of ferroelectric parameters, such as polarization and coercive field, from ferroelectric hysteresis characteristics leads to underestimation due to disturb from linear dielectric response, polarization offset, and asymmetric coercive field.

To overcome the problem, we present a fast and robust modeling framework that automatically fits experimental ferroelectric hysteresis loops based on the Preisach model that had been widely adopted to model hysteresis of ferroelectrics in the past, and we further extend this model to describe antiferroelectric. The model can also reconstruct saturated hysteresis loops from a measured few minor loop. We benchmarked our modeling framework and extracted ferroelectric model parameters from experimental ferroelectric hysteresis reported in the literature, demonstrating great agreement between the model and the measurement. We further observed that ferroelectric polarization and dielectric constant decrease with increasing coercive field in general.

Embedded two-phase capillary-fed boiling in porous media is a promising energy efficient technology in the thermal  management of power electronics and data centers. Here, we study a wick-based 3D μ-cooler (w3Dμ-cooler) that couples copper inverse opals (CIO) wicks with a 3D liquid-distribution and vapor-extraction manifold structure. Such a structure not only preserves the high heat flux and low superheat boiling in the CIO, but also eliminates the wicking-distance constraints of capillary-fed boiling via distributed fluid transport. However, the interaction between the wick with the 3D manifold is not well understood. In this work, we first examine the correlation of critical heat flux of the w3Dμ-cooler with its design. Further, we develop a model in COMSOL which enables thermofluidic coupled modeling of the w3Dμ-cooler by treating the highly non-linear heat transfer in a reduced-order approach. It reveals the temperature field, pressure drop, and effective critical heat flux at dry-out limits of the w3Dμ-cooler under uniform heat loads or hotspot cooling scenarios. Further, the model depicts the self-regulating behavior of capillary-fed boiling. It also indicates significant footprint scalability enhancements using the w3Dμ-cooler. The modeling framework developed here is also valuable for future studies of capillary-fed boiling in complex devices and systems.

Wenwen Zhao1, Mohammad Javad Asadi2, Lei Li2, Reet Chaudhuri2, Kazuki Nomoto2, Huili Grace Xing2,3,4, James Hwang2,3 and Debdeep Jena2,3,4

1 Applied and Engineering Physics, 2 Electrical and Computer Engineering, 3 Materials Science and Engineering, 4 Kavli Institute at Cornell for Nanoscale Science
Cornell University, Ithaca, NY 14850, USA

High-speed communication systems require efficient and compact filters in the 10-40 GHz frequency window. These frequencies are beyond the capacity of conventional surface acoustic-wave resonators, and are challenging for bulk acoustic-wave resonators. Single crystalline AlN grown by molecular-beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) promise high frequency (>10 GHz) acoustic resonators and filters. Epitaxial AlN layers also open new frontiers for integration of high-frequency filters with AlN/GaN based RF HEMTs. Using epitaxial aluminum nitride (AlN) developed for ultraviolet photonics and high-speed electronics, we demonstrate suspended AlN thin-film bulk acoustic resonators (FBARs) that operate around 10 GHz. Individual resonators show a Qmax over 610 and figure of merit 𝑓 × 𝑄 >5.5 THz. These epi-AlN FBARs show the promise for the monolithic integration with AlN/GaN/AlN quantum well HEMTs on the same SiC substrate. A unique RF front end can be enabled by the convergence of the FBAR and HEMT material layers, and such FBARs can enable integration with epitaxial nitride superconductors for microwave filters for quantum computing.

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