Symposium Organizers
C. Fred Higgs Carnegie Mellon University
Ashok Kumar University of South Florida
Subramanian Balakumar National Center for Nanosciences and Nanotechnology
Chad S. Korach State University of New York-Stony Brook
E7: CMP Process Simulation, Monitoring, and Experimentation
Session Chairs
Wednesday PM, April 15, 2009
Room 2005 (Moscone West)
4:00 PM - E7.1
Models for Prediction of Correlations Between Properties of CMP Molded Pads and Polishing: Optimization of Process Quality and Pad Selection.
Alex Tregub 1 , Thomas Bramblett 1 , Paul Fischer 1 , Hebrert Barnett 1 , Gwang-soo Kim 1 , Karson Knutson 1 , Lei Jiang 1 , Jessica Xu 1
1 , Intel, Santa Clara, California, United States
Show AbstractModels for prediction of correlations between properties of CMP molded pads and polishing: optimization of process quality and pad selection
4:15 PM - **E7.2
Real-Time Shear Force and Down Force Measurement and Analysis in CMP.
Ara Philipossian 1 2 , Yun Zhuang 1 2 , Yasa Sampurno 1 2
1 , University of Arizona, Tucson, Arizona, United States, 2 , Araca, Inc., Tucson, Arizona, United States
Show AbstractThis work highlights various case studies where shear force and down force have been measured in real-time using novel 200 and 300 mm polishers and tribometers in an effort to shed light on several key process attributes such as: (1) pattern evolution in STI CMP, (2) endpoint detection in STI and barrier CMP, (3) detection of abnormalities in slurry nano-particles during ILD CMP, (4) avoidance of certain settings (such as wafer pressure and platen rotation rate) for avoidance of tool vibration when cerium oxide slurries are used, (5) detection of end of pad life and (6) completion of pad and retaining ring break-in intervals. Results underscore the importance of real-time shear force and down force measurement in process development and high-volume manufacturing.
4:45 PM - E7.3
Surface and Lateral Deformations Observed from Nanoscale Scratch Testing of Cu/low-k Dielectric Line Patterns.
Joo Hoon Choi 1 , Chad Korach 1
1 Department of Mechanical Engineering, SUNY-Stony Brook, Stony Brook, New York, United States
Show AbstractIn this work, the goal is to measure the affects of frictional forces on copper/low-k dielectric line patterns applied by the analog of a single CMP particle. During polishing, undesired surface damage can be caused by excessive contact pressure on substrates, resulting in surface scratches and line deformation. This may be caused by particle agglomeration or uncontrollable irregularities in the polishing pad or slurry. The particle analog is represented by a diamond-coated probe with a nanoscale radius, which is used in a scanning probe microscope equipped with a wet cell to perform nanoscratching of the patterns in KOH. The patterned substrates are composed of line structures, which have variations in width of Cu interconnects and material properties in the form of two silica-based low-k dielectrics. The nanoscratched surfaces were investigated with AFM and SEM to observe the scratch depths and line deformations. Critical loads to initiate the observed defects were estimated for each structure.
5:00 PM - **E7.4
Friction and Removal Rate Studies Using Diluted Ceria and Colloidal Silica Abrasive Slurries
Ahmed Busnaina 1 , Nam-Goo Cha 1 2 , Jingoo Park 2 1
1 NSF Center for Microcontamination Control, Northeastern University, Boston, Massachusetts, United States, 2 Department oif Materials Engineering, Hanyang University, Ansan Korea (the Republic of)
Show AbstractIn this study, removal rates and friction behaviors of diluted ceria and colloidal silica slurries were investigated for oxide CMP process. Diluted ceria slurries contained 1.5 (original), 0.75, 0.15, 0.1, and 0.05 wt% and diluted colloidal slurries contained 20 (original), 8, 2, 0.2, and 0.05 wt% were considered. For the diluted ceria slurries, the removal rates increased with increasing pressure at range 2 to 6 psi and decreased at over 6 psi. The COF values increased as the dilution increased with the high dilution slurry (0.05 wt%) exhibiting the highest COF values. In case of diluted colloidal silica slurries, removal rates increased with increasing pressure at range 2 to 8 psi. But the COF values did not vary with the increasing dilution. High dilution slurries (0.2 and 0.05 wt%) showed similar COF values of abrasive-free slurry (DI water). The original ceria slurry showed ‘mixed lubrication’ behavior. As the dilution increased, the ceria particles, the pad roughness, and the surfaces of wafer were all in direct contacts with one another during the polishing processAlso original colloidal silica slurry showed ‘mixed lubrication’ behavior. As the dilution increased, the Stribeck curve (at 0.2 and 0.05 wt%) exhibited a similar behavior to abrasive-free slurry (DI water). Normalized removal rates of diluted ceria slurries did not vary with the increasing dilution. However, diluted colloidal silica slurry removal rates did decreased with the increasing dilution.
Symposium Organizers
C. Fred Higgs Carnegie Mellon University
Ashok Kumar University of South Florida
Subramanian Balakumar National Center for Nanosciences and Nanotechnology
Chad S. Korach State University of New York-Stony Brook
E9: Alternative Planarization Techniques and CMP in Emerging Technologies
Session Chairs
Thursday AM, April 16, 2009
Room 2005 (Moscone West)
9:00 AM - E9.1
Reverse Selectivity: Selective Removal of Silicon Nitride at a High Rate Over Silicon Dioxide.
Veera Pradeepa Dandu 1 , Suryadevara Babu 1
1 Department of Chemical Engineering & Center for Advanced Materials Processing, Clarkson University, Potsdam, New York, United States
Show AbstractBeyond the conventional selectivity of high oxide and low nitride removal for the Shallow Trench Isolation (STI) process, there are certain applications (eliminating the wet etching of silicon nitride in STI, replacement gate technique, etc.) for which the reverse, where the nitride removal rate exceed that of the underlying oxide, is desirable. However, enhancing or even maintaining the nitride removal rate while simultaneously suppressing the oxide removal rate is generally thought to be impossible due to the extreme hardness of silicon nitride when compared to silicon dioxide. In spite of this, we show in this presentation that a high nitride removal rate ( ~ 80 to 100 nm/min) can be achieved by modifying the silica abrasive surface using a silicon nitride reactive species in the slurry. Either covalent bonding or electrostatic addition can be used to modify the silica particle surface for this purpose. With these modified or functionalized abrasives, the oxide rate remains low. Furthermore, the ratio of the nitride/oxide removal rate can be tuned by varying the amount of covalently bonded species on the silica abrasive and the polishing parameters. Zeta potential, FTIR, frictional coefficient and thermo gravimetric analysis were used to explain the role of this additive species in achieving the desired tunable removal rates of oxide and nitride at different pH values.
9:15 AM - E9.2
Novel CMP technology for Ultra Large 450 mm Wafers.
Abhudaya Mishra 2 , Rajiv Singh 1 , Deepika Singh 2 , T. Jayaraman 2
2 , Sinmat Inc., Gainesville, Florida, United States, 1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractWith the continuous increase in the size of wafers (up to 450 mm) to reduce manufacturing costs, novel challenges are expected in CMP process technology. This is because the CMP technology is not inherently scalable as a large number of process variables can cause widespread fluctuations in the polishing uniformity. Thus it is expected that yield will decrease if standard equipment is deployed for larger wafers. We have proposed a new CMP process that will substantially decrease the polishing non-uniformity. Such a process also has low sensitivity to CMP process parameters, thus making it ideally suited to large wafer polishing. This talk will show results obtained by this technology on copper and low k material systems. The polishing non-uniformity was reduced to less than 2%, with minimization of edge defects.
9:30 AM - E9.3
An Alternative Approach to Planarization Using the Electrokinetic Phenomenon
Cheng Seng Leo 1 , David Butler 1 2 , Sum Huan, Gary Ng 2 , Chun Yang 1 , Stephen Danyluk 3
1 School of Mechanical & Aerospace Engineering, Nanyang Technological University, Singapore Singapore, 2 , Singapore Institute of Manufacturing Technology, Singapore Singapore, 3 George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractSince its introduction in the early 1980s, Chemical Mechanical Planarization (CMP) has been the pre-eminent means of achieving local material removal on a global scale. However, CMP suffers from a variety of issues such as scratching of the wafer by detached diamonds from the dressing wheel or excessive removal of material near prominent features. With the drive to producing smaller features on increasingly thinner wafers, CMP characteristics such as pad deformation have become a concern.In this paper, the authors will present an alternative material removal approach which utilises the electro-kinetic phenomenon where charged abrasive particles in an electric field can be subjected to movement and control through the combination of both AC and DC fields. This research has demonstrated that the removal rate can be precisely controlled by varying the AC frequency and field strength as well as the flow rate of the particles across the surface. The material removal rate is generally in the range of 100-500nm for a variety of electrical (ac and dc) and flow conditions.The technique is currently being refined to achieve precise material removal over a larger area with the intention that it could become an alternative to current established planarization technologies.
E10: CMP in Memory and Data Storage Technologies
Session Chairs
Thursday PM, April 16, 2009
Room 2005 (Moscone West)
9:45 AM - **E10.1
Issues and Challenges of Chemical Mechanical Polishing for Nano-scale Memory Manufacturing
Choonkun Ryu 1 , Jonghan Shin 1 , Hyungsoon Park 1 , Nohjung Kwak 1 , Sungki Park 1
1 R&D Division, Hynix Semiconductor Inc., Icheon-si Korea (the Republic of)
Show AbstractAs memory devices shrink down to nanoscale, there have been varieties of issues and challenges in both device performance and process integration. The CMP process also has faced lots of hurdles toward the successful nanoscale process integration. The number of the CMP process has increased gradually due to the complexity of integration scheme. The CMP processes for global and local planarization have been implemented to replace conventional planarization processes since the planarity requirement for nano-lithography becomes more stringent. The CMP for isolation has increased significantly because the isolation process of metal contact plugs and damascene metallization at nanoscale has been successfully enabled by the CMP. There is a great demand on the reduction of CoO since the addition of the CMP process causes the rise of the manufacturing cost. The CMP process has evolved for varieties of new materials and integration schemes which have been introduced to resolve critical issues of device performance and patterning in nanoscale regime. The CMP selectivity, which depends strongly on the chemistry of the slurry, must be tuned for the various new materials. Recently, in order to get over the limitation in lateral shrinkage of the memory device, several novel vertical integration approaches such as Wafer-direct-bonding and Through-Silicon-Via have been investigated extensively. The vertical integration needs the new CMP process such as high removal rate Cu CMP. The advanced device structures such Fin- FET and vertical transistor will have different combination of materials to be polished. The control of dishing and erosion is critical for the isolation of the nano-scale patterning. Next generation memories such as Phase Change Memory, Resistive RAM, and Magnetic RAM need the CMP process for new materials such as GeSbTe, conductive oxide, and magnetic materials. The introduction of the new slurries in an existing consumable set must be qualified in terms of cross-contamination and reliability. Since the control of defects and particles on wafers is the most critical task for achieving high yield, the CMP post clean must be done thoroughly to prevent nanoscale residues and particles. The drying after wet clean should be done without any watermarks and residues. Since any nano-size scratch may be a killer defect at the nanoscale memory, both the CMP equipment and the consumables must be maintained with tighter degree of control specifications. In this paper, current issues and challenges of the CMP in nano-scale memory manufacturing are discussed.
10:15 AM - **E10.2
Chemical Mechanical Planarization in Disk Drive Head and Media Fabrication.
Jay Jayashankar 1
1 , Seagate Technology, Pittsburgh, Pennsylvania, United States
Show AbstractChemical Mechanical Planarization is a critical technology in the manufacture of advanced hard disk recording heads and media for data storage. Not only has CMP played an important role in the miniaturization of longitudinal and perpendicular recording head components and in the areal density increase, but it continues its enabling role in the development of future data storage technologies such as Heat Assisted Magnetic Recording (HAMR) and Bit Patterned recording Media (BPM) fabrication. In contrast to semiconductor planarization processes which are mainly focused on copper, tungsten, oxides and low K dielectrics, hard drive CMP focuses on an alphabet soup of magnetic and optical materials, noble metals and conductors. These pose considerable scientific and engineering challenges in terms of CMP process removal rates, selectivity, topography , corrosion control and post CMP cleans. This talk will provide examples of the implementation of CMP in longitudional, perpendicular, and other advanced recording head fabrication processes. Fundamental electrochemical aspects of CMP and ECMP as applied to planarization process requirements of data storage elements will also be discussed
10:45 AM - E10.3
A Stochastic Analysis of the Lapping Process of Magnetic Recording Heads.
Huaming Xu 1 , Kyriakos Komvopoulos 1
1 Mechanical Engineering, University of California, Berkeley, California, United States
Show AbstractChemical mechanical polishing (CMP) is the standard planarization process of integrated circuit technology. CMP uses the combined effects of chemical and mechanical surface interactions to achieve local and global planarization of multilevel circuits and different materials, such as silicon oxide, metals, and polycrystalline silicon. Despite the relatively high material removal rate, CMP also produces a good surface finish. Because the abrasive particles in the slurry are not embedded into one of the interacting surfaces, CMP is classified as a third-body abrasive process. Lapping is known as the process of polishing the ceramic heads of magnetic recording devices. There are two main differences between CMP and lapping. First, the nanometer-sized diamond particles used to polish the ceramic surface are embedded into the soft (tin) surface layer of a lapping plate. Therefore, lapping is classified as two-body abrasion process. Second, the lapping fluid does not react chemically with the lapped surface but lubricates the surfaces to increase the lapping efficiency by minimizing friction and flushes out the removed material. For ultrahigh magnetic recording densities, the surface of the ceramic head must be polished down to a root-mean-square roughness of less than 0.2 nm, significantly less than the typical roughness obtained with CMP. This implies that knowledge of the removal of material at the nanoparticle scale is essential for optimizing the lapping process. The analysis of the lapping process is further complicated by the fact that nanoscale particle-surface interactions resemble a stochastic process. The objective of the present work was to develop a stochastic analysis of the lapping process that provides estimates of the material removal rate and final roughness of the ceramic head surface in terms of the applied pressure, nanoparticle size, lapping speed, and topographies of the lapping plate and original ceramic surface.
E11: Challenges in CMP for Next-Generation 45NM and Beyond
Session Chairs
Thursday PM, April 16, 2009
Room 2005 (Moscone West)
11:30 AM - E11.1
Quantitative Roadmap for Optimizing CMP of Ultralow-k Dielectrics.
Taek-Soo Kim 1 , Tomohisa Konno 2 , Tatsuya Yamanaka 2 , Reinhold Dauskardt 1
1 , Stanford University, Stanford, California, United States, 2 , JSR Micro, Inc., Sunnyvale, California, United States
Show AbstractDamage in the form of cracking, delamination, and an increase in the effective k value of ultralow-k dielectric (ULK) materials remains a significant challenge for direct CMP of ULK. The evolution of cracks in interconnect structures during CMP is a kinetic process involving the synergistic effects of process stress and chemistry, although damage has mostly been attributed to the effects of stress. However, chemical composition of the CMP slurry may have more significant effects on the growth of cracks and associated damage compared to mechanical loads. Surprisingly, slurries and post-CMP cleaning solutions have never been optimized to reduce the growth of such defects. In this study we present a quantitative road map for optimized CMP of ULK in which critical factors such as defect evolution, CMP damage, diffusion, effective k increase, and CMP removal rates are for the first time all correlated. We are particularly interested in the effects of common nonionic surfactants and the implications for defect evolution and solution diffusion in ULK materials. Careful control of surfactants in slurry formulations for enhanced wetting, removal rates, slurry stability and selectivity is vital for optimized CMP. However, their role on the formation and growth of damage is largely unknown. Small changes in the lengths of hydrophobic and hydrophilic chains and molecular structure of surfactants are shown to have dramatic effects on the growth rate of cracks. An optimized blend of surfactants and electrolytes can significantly retard defect evolution. Possible explanations for the suppression of the crack growth involving crack bridging phenomena by surfactants are presented. Surfactants are also shown to enhance the diffusion of aqueous solutions in nanoporous ULK films despite the strong hydrophobicity of the films. A wide range of nonionic surfactants including monomeric (linear) polyoxyethylene alkyl ethers and dimeric (branched) gemini surfactants were selected for study. We demonstrate that the surfactant molecules themselves can diffuse into ULK films. The diffusion coefficients were found to be sensitive to molecular weight, hydrophilic-lipophilic balance, and molecular structure of surfactants. Analysis of the measured diffusion coefficients reveals that short-chain surfactants exhibit reptation based diffusion in the nanoscopic pore confinements.
E12: Tool/Process Development such as eCMP and Low-shear CMP
Session Chairs
Thursday PM, April 16, 2009
Room 2005 (Moscone West)
2:30 PM - **E12.1
Damageless CMP Process for the Next Generation Cu Interconnects.
Seiichi Kondo 1
1 , Semiconductor Leading Edge Technologies, Inc. (Selete), Tsukuba, Ibaraki, Japan
Show Abstract To reduce mechanical damage on porous low-k films, we have developed an electro-CMP (e-CMP) pad that does not use metal electrodes but has electro-cells (cathode cells) and uses conductive carbon as an anode [1-2]. Our e-CMP pad is attached to a conventional CMP platen with an adhesive sheet, and it can easily be replaced with a conventional CMP pad in about ten minutes. Because our e-CMP pad does not require a down force of more than 1 psi, it can be used for a low-pressure, high-speed CMP. Although our carbon pad was effective for polishing porous SiOC/Cu wafers with low mechanical strength, the choice of carbon material was very important because a high-density electric current flows through the carbon electrode under polishing friction in an electrolyte. The e-CMP pad that we newly developed does not use any contact electrodes with Cu wafers to increase the process window of the conventional e-CMP pad. Instead of using contact electrodes for anodes, our e-CMP pad has anode cells to hold electrolyte for keeping the electric current from anode electrodes at the bottom of the cells to the Cu wafer surface through the electrolyte indirectly [3]. Therefore, this new e-CMP pad has both anode cells for maintaining electric current to the Cu surface and cathode cells for Cu electro-polishing. We tested our e-CMP pad using 3-12 inch wafers and obtained a removal rate of 1400-6300 nm/min and a within-wafer non-uniformity of less than 6%. Our e-CMP pad using non-contact electrodes has possible application in the 32-45 nm node porous SiOC/Cu damascene process, as well as TSV and MEMS processes.References[1] S. Kondo et al., Proceedings of International Interconnect Technology Conference (IITC), pp. 203-205, (2005). [2] S. Kondo et al., Microelectronics Engineering, 84, pp. 2615-2619, (2007).[3] S. Kondo et al., Proceedings of International Interconnect Technology Conference (IITC), pp. 82-84, (2008).
3:00 PM - E12.2
Optimization of Material Removal Efficiency in Low Pressure CMP
Sinan Muftu 1 , Dincer Bozkaya 1
1 Department of Mechanical Engineering, Northeastern University, Boston, Massachusetts, United States
Show AbstractIn chemical-mechanical polishing (CMP) material removal efficiency (MRE) can be defined as the fraction of the total pressure distributed on the abrasives, and it depends on the interplay between the direct contact of the pad-to-wafer, and the contact of the abrasives with the wafer. The MRE can be increased by minimizing pad-wafer direct contact, as this is not likely to help material removal, significantly. The objective of this work is to investigate parameters that control material removal efficiency especially for low-pressure CMP. Pad-abrasive-wafer and pad-wafer contacts were recently modeled at different scales by using a combination of finite element modeling and abrasive size distribution as described by the authors [1]. This model includes the interactions of abrasives entrapped between a hyper-elastic deformable pad and a rigid wafer. The effects of particle size distribution and particle density are analyzed for a single pad asperity. In the present work, the single asperity model is expanded to a multi-asperity model to analyze contact of a rough polishing pad-with a wafer with abrasives trapped in the interface. In addition, the effects of abrasive and adhesive wear models on material removal, and the effects of pad porosity on the contact and material removal are also investigated. Polishing pads are typically made of porous polymeric materials; and, the elastic modulus of the porous pad, Ep, is typically ¼-to-1/3 of the elastic modulus of the polymer’s solid elastic modulus, Es. Considering the relative size of the abrasives with respect to the pad asperity, we assume that the pad’s local interactions with the abrasives are dominated by the solid pad elastic modulus Es. On the other hand, the multi-asperity contact of the pad with the wafer is influenced by the pad’s porous elastic modulus, Ep. The results of this study show that MRE is strongly affected by the Es/Ep-ratio, where higher values of Es/Ep increases MRE. This is explained by noting that higher solid pad elastic modulus retards direct contact, and lower porous pad elastic modulus causes real contact pressure at pad-wafer interface to be smaller. An optimum abrasive concentration that marks the transition from pure pad-wafer-abrasive contact to mixed contact (combination of pad-wafer-abrasive and pad-wafer contacts) is found to exist for a given pad porosity. Optimization of abrasive concentration as a function of pad porosity (Es/Ep), solid pad elastic modulus (Es) and pad surface parameters (pad roughness and asperity radius) is explained. Modeling results for material removal rate are validated by comparing with experiments from literature. Reference[1] D. Bozkaya and S. Müftü, 2008 “The Effects of Interfacial Particles on the Contact of an Elastic Sphere with a Rigid Flat Surface,” ASME Journal of Tribology, 130:4, 041401.
3:15 PM - E12.3
Role of Phosphoric Acid in Copper Electrochemical Mechanical Planarization Slurries.
Serdar Aksu 1
1 Research and Development, SoloPower, Inc., San Jose, California, United States
Show AbstractIn addition to its conventional use for copper electropolishing, phosphoric acid has recently become an important component in reactive slurries of copper electrochemical mechanical planarization (ECMP). In this paper, the electrochemical behavior of copper in aqueous solutions containing phosphoric acid is investigated to understand its role in the Cu ECMP slurries. Since the literature lacks the fundamental thermodynamic diagrams, first both aqueous solubility and potential-pH diagrams were established for copper-phosphate-water system at a variety of dissolved Cu and phosphate {CuT} and phosphoric acid {OPT} activities using Cu3(PO4)2 and Cu(PO4)2.3H2O as the cupric-phosphate solid phases. This is followed by the examination of the predictions of the diagrams using the results from potentiodynamic polarization experiments and as well as prior experimental data in the literature. Good correlations were found between the diagrams and the experimental data. The potential-pH calculations showed that at the combinations of lower {CuT} and higher {OPT} values, phosphoric acid is expected to increase the solubility range of copper through formation of aqueous copper-phosphate complexes. It was shown that phosphoric acid increases the solution electrical conductivity and accelerates copper dissolution from the protruding regions during Cu ECMP at slightly acidic pH values. Potential-pH diagrams demonstrated that neither native copper oxides nor copper-orthophosphate solids can form at the acidic pH values of Cu ECMP, therefore passive film formation on the copper surface heavily relies on corrosion inhibitors such as benzotriazole (BTA). The planarization mechanism during the Cu ECMP process in slurries containing phosphoric acid was delineated using the experimental data from in situ electrochemical polarization experiments and open-circuit potential measurements.
3:30 PM - E12.4
Fluid System Component Solutions for Advanced CMP Slurry Delivery.
John Baxter 1
1 , Swagelok Semiconductor Services Company, Santa Clara, California, United States
Show AbstractNewer chemistries and process parameters employed in semiconductor manufacturing are pushing the limits of current systems. For example, abrasive slurries used in CMP processes contain more aggressive particles susceptible to shear forces. These changing parameters require higher standards for purity and improved design and materials for fluid system components. OEMs, toolmakers and integrators are calling for longer life cycles, easier maintenance, resistance to permeation and reduced particle shedding in valves and other components. Plus, these parties are looking to curb the rising cost of ownership (CoO) for semiconductor manufacturing. This paper will focus on advanced fluid system component solutions that may be employed to address issues of slurry health, system design and CoO.Slurry Health. SEMI Standard F57-0301 provides baseline standards for purity, which are attainable assuming proper material selection, methods of design, manufacturing and quality control testing. SEMI F57 specifies minimum performance requirements for ultrahigh-purity polymer components used in semiconductor ultrapure water and chemical distribution systems. Fluid system component designers should consider exceeding, where practical, SEMI F57 requirements by focusing on the most challenging process requirements, such as those involving CMP and acids.Fluid system components must not affect slurry health. If slurries break down in a valve body, larger agglomerations may occur that could scratch a wafer during CMP. Particle shedding from valve actuation must also be minimized.Material selection is critical. PFA has traditionally been used for wetted components. However, PFA has its shortcomings. PTFE is inherently less reactive than PFA and has superior chemical resistance, better mechanical properties and qualities for purity.The flow path within a valve is critical for purity, particle minimization and avoidance of slurry agglomeration. Computational Fluid Dynamics can be used to optimize internal valve geometries and flow paths to minimize pressure drop and improve slurry health.Concentration monitoring may be employed to verify blending of a component in a slurry or ensure the blend meets customer specifications before delivery to process tools. Monitors can provide highly accurate, point-of-use measurements for real-time data. Newer monitors using index of refraction technology have been proven to rival other technologies. Three case studies will be discussed.System Design. Various components used in semiconductor manufacturing can offer benefits such as consistent operating pressures and constant loops. Both manifolds and sweep elbows offer a variety of benefits.CoO. Considerations for slurry health and system design also provide opportunities for wafer manufacturers to reduce total CoO. In particular, concentration monitors can increase yields, efficiencies and productivity while reducing chemical consumption, waste streams and wafer scrap.
E13: Advanced CMP Process Control Techniques
Session Chairs
Thursday PM, April 16, 2009
Room 2005 (Moscone West)
4:45 PM - **E13.2
CMP for High Mobility Strained Si/Ge Channels.
Kentarou Sawano 1
1 , Musashi Institute of Technology, Tokyo Japan
Show Abstract Si/Ge heterostructures are one of the most promising performance boosters for next generation CMOS circuits. Lattice mismatch between Si and Ge enables us to manipulate lattice strain, that is, strain engineering is made possible. The strain highly alters band structures and gives rise to band splitting and/or effective mass reduction, which brings significant mobility enhancement of the carriers in the strained channel. High mobility channels such as strained-Si and strained-Ge can be formed on strain-relaxed SiGe buffer layers called SiGe virtual substrates (VS). Since the property of the SiGe VS directly affects that of the overgrown channel layer, creating high-quality SiGe VS is highly required to obtain high performance devices. One critical problem is very large surface roughness arising on the SiGe VS. So-called crosshatch pattern appears on the surface, irrespective of growth methods. Since strain field coming from the underlying misfit dislocation arrays is responsible for this roughness formation, it is very difficult to create a roughness-free surface. For the purpose of eliminating the roughness, we employed chemical mechanical planarization (CMP). Since CMP is established technology for Si wafer production, it is reasonably applicable to SiGe. Adopting the similar process as Si CMP, we demonstrated that the initial roughness of larger than 10 nm was reduced considerably down to less than 1 nm. Post-CMP cleaning is an additional issue of great importance for regrowth of device channel structures. We found that the roughness increased during post-CMP cleaning process due to laterally nonuniform etching rate of the SiGe surface. To avoid this roughness increase, we optimized the cleaning procedure, especially cleaning solution, and successfully obtained very smooth surface with RMS roughness of less than 0.4 nm, the lowest value ever obtained for SiGe VS surfaces. The planarized SiGe VS was applied to strained channel structures. Strained-Si modulation-doped structure was fabricated on the planarized SiGe VS with a Ge concentration of 30%. The obtained electron Hall mobility was found to be 4 times higher than the reference structure fabricated without CMP, which is a clear evidence that the roughness-related carrier scattering can be well suppressed by CMP. Strained-Ge channel modulation-doped structure was also fabricated on the SiGe VS with much higher Ge concentration (65%). Although the roughness was much larger than 10 nm due to the high Ge concentration, the surface smoothness less than 1 nm was obtained by CMP. As a result, hole mobility enhancement factor over the reference sample without CMP was found to reach as high as 8 at low temperature and 1.8 at room temperature. These results clearly indicate that CMP is very promising technology for high performance strained Si/Ge based CMOS circuit.
5:15 PM - E13.3
Novel End-point Detection Method by Monitoring Shear Force Oscillation Frequency for Barrier Metal Polishing in Advanced LSI
Xun Gu 1 , Takenao Nemoto 2 , Ara Philipossian 3 4 , Jiang Cheng 4 , Yasa Adi Sampurno 3 4 , Yun Zhuang 3 4 , Akinobu Teramoto 2 , Takashi Ito 1 , Tadahiro Ohmi 2
1 Graduate school of engineering, Tohoku University, Sendai, Miyagi, Japan, 2 New Industry Creation Hatchery Center, Tohoku University, Seidai, Miyagi, Japan, 3 , University of Arizona, Tucson, Arizona, United States, 4 , Araca,Inc., Tucson, Arizona, United States
Show AbstractAs technology node progressing, the Chemical Mechanical Planarization (CMP) process becomes a crucial process in integrated circuit (IC) fabrication. Replacement of non porous polymer fluorocarbon as an advanced ultra low dielectric constant (k < 2.0) film has been proposed to realize super-efficient of semiconductor system1. Indicating benefits of non porous structure to process integration, reduction of damage during LSI fabrication, especially in CMP, is desired. The end point detection (EPD) is one of the key technologies to reduce dishing/erosion and avoid damage introduction. The EPD by monitoring COF (Coefficient of friction) has been investigated on the substrate with Cu/Ta/low-k. However, the COF values depend on the kinematic parameters, slurry concentration, and chemical properties. So, in some cases, the difference in COF values of Ta and dielectric film becomes insignificant Therefore, an alternative EDP is anticipated to improve accuracy. Monitoring frequencies of shear force oscillation during Tantalum (Ta) CMP by applying a frequency analysis is proposed as a novel method to determine an end point on damascene interconnects in this paper. 10nm-Ta deposited by the sputtering was prepared on dielectric substrate. CMP was carried out with silica abrasive slurry and a polyurethane pad with 1.5PSI (10340Pa) down force. Shear force and down force were monitored by equipped loadcells. When a carrier rotation rate was changed from 25rpm to 63rpm with a constant platen rotation rate, 25rpm, the predominant frequency of shear force oscillation on dielectric were changed from them on Ta. At carrier rotation rate 25rpm, for example, the predominant frequency of shear force is 0.8Hz on Ta and 0.4Hz on dielectric. These frequencies on dielectric and Ta were well agreed with the frequency of carrier rotation and twice of that, respectively. This result is valid to different studied rotation rate. The predominant frequencies of shear force oscillation only depend on the kinematic parameters of the polishing process, not slurry concentration, and chemical properties. Analysis of frequency of shear force oscillation can be used to monitor in the real-time polishing progress during Ta/TaN CMP. To investigate characteristic of wafer contact on pad, a pressure sensing sheet was placed between them. When the carrier rotates, two lower pressure spots at wafer edge were found. A twice frequency of carrier rotation was observed by monitoring pressure at wafer edge. This result indicates that the frequency of shear force oscillation depends on the characteristic of contact between substrates and pad. While the number or position of lower pressure spots may depends on tool setting, shear force oscillation should remain unless perfect uniform process established, therefore monitoring frequency of shear force should be a usual EPD.[1] A. Itoh, A. Inokuchi, S. Yasuda, A. Teramoto, T. Goto, M. Hirayama and T. Ohmi, J. Phys. Appl. Phys. D, 47(4), 2515 (2008).
5:30 PM - E13.4
Surface Morphology Control during Polishing of SiC Substrates.
Purushottam Kumar 1 , Rajiv Singh 1 , Arul Chakkaravarthi Arjunan 2 , Dibakar Das 2 , Deepika Singh 2
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States, 2 , Sinmat Inc., Gainesville, Florida, United States
Show AbstractSilicon Carbide is an important substrate material for fabrication of optoelectronic and power electronic devices. As epitaxial films are grown on these substrates it is important to control the surface microstructure during the CMP polishing process. We have observed 3 distinct types of surface morphology during CMP: (i) delineation of atomic terraced structure (ii) delineation of defects such as micropipes and dislocations emanating from the substrates and (iii) unterraced smooth featureless morphology with rms roughness < 1 Å. We have developed a polishing model to explain the genesis of such features. The model is based on the synergistic chemical and mechanical action during the polishing process. We typically observe that for low polishing rates, the defect features are highlighted during the polishing process. This talk will discuss the ability of the model to predict different surface morphologies obtained during polishing of SiC substrates.