Symposium Organizers
Michael Dudley State University of New York-Stony Brook
C. Mark Johnson University of Nottingham
Adrian Powell Cree, Inc.
Sei-Hyung Ryu Wayne State University
Symposium Support
Cree Inc
Sula Technologies
D1: Bulk Growth
Session Chairs
Tuesday PM, March 25, 2008
Room 2004 (Moscone West)
9:30 AM - **D1.1
Bulk Growth of SiC.
Peter Wellmann 1 , Sakwe Aloysius Sakwe 1 , Philip Hens 1 , Matthias Stockmeier 2 , Katja Konias 2 , Rainer Hock 2 , Andreas Magerl 2 , Michel Pons 3 , Mikael Syväjärvi 4 , Rositza Yakimova 4
1 Materials Department 6, University of Erlangen, Erlangen Germany, 2 Physics, University of Erlangen, Erlangen Germany, 3 LTPCM, Institut National Polytechnique, Grenoble France, 4 Physics, University of Linkoeping, Linkoeping Sweden
Show AbstractToday, SiC single crystals as substrate for electronic device applications are fabricated by seeded sublimation growth. Commercially, 3 inch and 4 inch high quality wafers, prepared by the so called physical vapor transport (PVT) growth technique are “state of the art”. (i) The paper will review the basics of SiC bulk growth and discuss current and possible future concepts to improve crystalline quality. In-situ process visualization using x-rays, numerical modeling and advanced doping techniques will be presented which support growth process optimization. (ii) In a short overview the “pure” PVT technique will be compared with related developments like the so called Modified-PVT, Continuous-Feeding-PVT, High-Temperature-CVD and Halide-CVD concepts. (iii) Special emphasis will be put on dislocation generation and concepts to reduce dislocation density during SiC bulk crystal growth. The dislocation study is based on a statistical approach. Rather than following the evolution of a single defect, statistic data which reflect a more global dislocation density evolution are interpreted. In this context a new approach will be presented which relates thermally induced strain during growth and dislocation patterning in networks.
10:00 AM - D1.2
Unseeded Sublimation Growth of High Quality 3C-SiC Single Crystals.
Didier Chaussende 1 , Irina-Georgiana Galben 1 , Jessica Eid 1 , Michel Pons 2
1 LMGP, CNRS - Grenoble INP, Grenoble France, 2 SIMAP, CNRS - Grenoble INP - UJF, Saint-Martin d'Hères France
Show AbstractBulk growth of 3C-SiC single crystals has not been demonstrated to date. Different attempts have already been reported, but they did not give very convincing results. Indeed, all of them have encountered two main problems: i) the availability of high quality 3C seeds and ii) the availability of an adapted growth process. As a consequence, they resulted in poor quality material. The Continuous Feed Physical Vapour Transport (CF-PVT) method has been successfully applied to the growth of the 3C polytype. By an appropriate control of the nucleation rate/ growth rate ratio, only a few nuclei are formed and their growth is performed under close to equilibrium conditions, at 2100°C and 0.2 mm/h. The resulting crystals, with an average diameter of 5 mm, exhibit perfectly faceted habits. Similarly to the well-known Lely crystals, they are of very high structural quality, with no measurable mosaicity and residual strain. The FWHM of the (111) and (100) X-ray diffraction rocking curves are less than 20 arcsec. Only a few defects are revealed by the KOH etching. The results are discussed with respect to a future development of 3C-SiC ingots.
10:30 AM - **D1.4
Influence of Crystal Growth Conditions on Nitrogen Incorporation During PVT Growth of SiC.
Darren Hansen 1 , Roman Drachev 1 , Seung-ho Park 1 , Mark Loboda 1
1 , Dow Corning Compound Semiconductor Solutions, Auburn, Michigan, United States
Show AbstractThe control and understanding of the incorporation of nitrogen during SiC PVT continues to play an important role in SiC crystal growth. Nitrogen acts both as a dopant and an impurity depending on the growth conditions and desired resistivity. Epitaxial growth by CVD provides some insight into N incorporation in terms of the face effects, temperature, and impact of the chemical species in terms of the C/Si ratio. This paper will present experimental results showing trends regarding nitrogen incorporation during SiC PVT. Various crystal growth processes operated under static nitrogen partial pressures were found to produce wide ranges of SiC resistivity. These effects will be analyzed in light of the process impact on gas phase elemental composition, crystal stress, dopant activation and crystal defectivity. The goal of this paper is to provide additional insights regarding nitrogen incorporation during SiC PVT, and in turn drive towards a more holistic approach to control the resistivity of 4H SiC material, linked with basic understanding established from SiC epitaxy technology.
11:00 AM - D1: Bulk
BREAK
Symposium Organizers
Michael Dudley State University of New York-Stony Brook
C. Mark Johnson University of Nottingham
Adrian Powell Cree, Inc.
Sei-Hyung Ryu Wayne State University
D6: Deep Level Defects and Carrier Lifetime
Session Chairs
Wednesday AM, March 26, 2008
Room 2004 (Moscone West)
11:30 AM - **D6.1
Deep Levels and Lifetime-Killing Defects in 4H-SiC Epilayers.
Tsunenobu Kimoto 1 2 , Katsunori Danno 1
1 Electronic Science & Engineering, Kyoto University, Kyoto Japan, 2 Photonics and Electronics Science and Engineering Center, Kyoto University, Kyoto Japan
Show AbstractProperties of deep levels and their origins in SiC have not been well understood. In this paper, the authors describe deep levels in the whole energy range of bandgap, based on extensive DLTS measurements on n-type and p-type as-grown (and irradiated) 4H-SiC epilayers in the wide temperature range from 100K to 860K. Impacts of growth parameters on formation of deep levels, thermal stability, and possible origins are presented. Correlation with carrier lifetime is also discussed. Both n- and p-type 4H-SiC{0001} epilayers were grown by hot-wall CVD at 6-50 μm/h. The dominant electron traps commonly observed in n-type 4H-SiC are Z1/2 and EH6/7 centers located at Ec – 0.65 eV and Ec – 1.55 eV, respectively. Formation of these centers is significantly suppressed when growth is performed under C-rich condition, and the trap concentration can be reduced to a mid 1011 cm-3. The trap concentration showed remarkable increase in epilayers grown at high temperature, especially above 1650oC. Both Z1/2 and EH6/7 centers are thermally stable, at least up to 1600oC, and can be intentionally introduced by low-energy (120-160 keV) electron irradiation, by which only carbon atoms are displaced. The absolute trap concentration, the C/Si ratio dependence during growth, introduction rate by electron irradiation, and thermal stability are always the same for the Z1/2 and EH6/7 centers, indicating that these centers may originate from one microscopically same point defect but with different charge states. In DLTS measurements on as-grown p-type 4H-SiC, four major hole traps were detected, the D center (Ev + 0.47 eV), HK2 (Ev + 0.79 eV), HK3 (Ev + 1.27 eV), and HK4 (Ev + 1.44 eV) in the concentration range of 1011-1012 cm-3. The HK3 and HK4 centers can be annealed out by thermal treatment at 1400oC, and HK2 at 1550oC. The results are compared with theoretical study as well as EPR study published in literatures. Carrier lifetime in SiC has been rather short (typically 0.3-1 μs) in spite of its indirect band structure. Carrier lifetimes in 4H-SiC epilayers were investigated by μ-PCD measurements. A long lifetime over 5 μs could be obtained from thick high-quality epilayers. Extensive lifetime mapping and DLTS mapping study revealed that the Z1/2 or EH6/7 center works as an effective recombination center when the concentration is higher than low 1013 cm-3. When the carrier lifetime is limited by the Z1/2 or EH6/7 center, the lifetime shows positive dependence on the injection level. On the other hand, other recombination paths such as surface/substrate recombination limits carrier lifetimes when the trap concentration is lower than 1013 cm-3. In this case, the carrier lifetime decreases by increasing the injection level. The hole traps located in the lower half of bandgap have minor effects on the lifetime. By controlling the Z1/2 and EH6/7 concentrations by low-energy electron irradiation, control of carrier lifetimes could be realized.
12:00 PM - D6.2
Comparison of Deep Levels and Injected Carrier Lifetimes of 4° and 8° off-axis 4H-SiC Epitaxial Layers.
Rachael Myers-Ward 1 , Kok-Keong Lew 1 , Brenda VanMil 1 , Paul Klein 2 , Evan Glaser 2 , Charles Eddy 1 , Kurt Gaskill 1
1 Code 6882, Naval Research Laboratory, Washington , District of Columbia, United States, 2 Code 6877, Naval Research Laboratory, Washington , District of Columbia, United States
Show AbstractLong injected carrier lifetimes are needed for SiC bipolar devices to permit effective conductivity modulation. Extended [1] and point defects [2], surface recombination [3], and low angle grain boundaries [4] have all been shown to limit injected carrier lifetime. The main electron trap of concern in 4H-SiC is the Z1/2 defect, which has been shown to reduce injected carrier lifetimes when in concentrations >5x1012 cm-3 [5]. While much progress has been made increasing the lifetime, more research is needed. This work investigates how the influence of the Z1/2 defects on the low-injection (~2x1014 cm-3) lifetime varies for both intentionally and unintentionally low-doped (ND-NA< 1015 cm-3), n-type 4H-SiC films grown on 4° and 8° off-axis material. Epitaxial layers were grown in an Aixtron/Epigress VP508 horizontal hot-wall chemical vapor deposition (CVD) reactor. Deep-level transient spectroscopy was used to investigate the electron trap concentrations of the Z1/2 and EH6/7 defects. The low-injection lifetime was determined by room temperature band-band PL decay at 391 nm. The electrical properties of the films were analyzed using Hg probe and Schottky diode capacitance-voltage measurements. The total nitrogen concentration was determined by 2 K photoluminescence analysis using an Ar+-244 nm laser.The experimental results show that for unintentionally doped films on 8° off-axis substrates, a correlation exists between higher electron concentrations and shorter lifetimes [6]. Further, the lifetime dependence on Z1/2 trap concentrations is consistent with previous work in the literature [5]. However, for intentionally doped films in the same electron concentration range, significant variations in the lifetime were observed for samples with essentially the same Z1/2 trap concentration. A similar observation was made for films grown on 4° off-axis substrates, where for intentionally doped material, the lifetime decreased with increasing electron concentration and the Z1/2 trap concentrations had similar values for various lifetimes. Overall, these results suggest that the Z1/2 defect is not the only cause for limiting the lifetime, but may be influenced by surface recombination and/or other defects. [1]R.E. Stahlbush, M.E. Twigg, J.J. Sumakeris, K.G. Irvine, and P.A. Losee: Mater. Res. Soc. Symp. Proc. Vol. 815 (2004), p. J6.4.1.[2] J. Zhang, L. Storasta, J.P. Bergman, N.T. Son, and E. Janzén: J. Appl. Phys. Vol 93 (2003), p. 4708.[3]A. Galeckas, J. Linnros, M. Frischholz, K. Rottner, N. Nordell, S. Karlsson, and V. Grivickas: Mater. Sci. Eng.,B Vol. 61-62 (1999), p. 239.[4]E. Janzén, A. Henry, J.P. Bergman, A. Ellison, and B. Magnusson: Mater. Sci. Semicond. Process. Vol. 4 (2001), p. 181.[5] P.B. Klein, B.V. Shanabrook, S.W. Huh, A.Y. Polyakov, M. Skowronski, J.J. Sumakeris, M.J. O’Loughlin: Appl. Phys. Lett. Vol 88, p. 052110.[6]E. Janzén and O. Kordina: Mater. Sci. Eng., B Vol 46 (1997), p. 203.
12:15 PM - **D6.3
Mapping Point and Extended Defects in Wide Bandgap Substrates, Epitaxial Films, and Device structures by Luminescence Techniques.
Jaime Freitas 1 , M. Murthy 2 , S. Maximenko 1 , P. Klein 1 , J. Caldwell 1 , O. Glembocki 1 , Y. Chen 3 , R. Balaji 3 , M. Dudley 3 , B. Vanmil 1 , R. Myers-Ward 1 , D. Gaskill 1 , C. Eddy 1 , G. Chung 4 , M. Laboda 4
1 ESTD, Naval Research Laboratory, Washington, District of Columbia, United States, 2 Department of ECE, George Mason University, Fairfax, Virginia, United States, 3 Department of MSE, Stony Brook University, Stony Brook , New York, United States, 4 , Dow Corning Compound Semiconductors Solutions, Midland, Michigan, United States
Show AbstractWednesday, March 26New Presentation Time and Paper Number*D6.4 @ 11:30 AM to *D6.3 @ 11:15 AMMapping Point and Extended Defects in Wide Bandgap Substrates, Epitaxial Films, and Device structures by Luminescence Techniques. Jaime A. Freitas
Symposium Organizers
Michael Dudley State University of New York-Stony Brook
C. Mark Johnson University of Nottingham
Adrian Powell Cree, Inc.
Sei-Hyung Ryu Wayne State University
D10: Devices I
Session Chairs
Thursday AM, March 27, 2008
Room 2004 (Moscone West)
9:30 AM - **D10.1
Considerations on Bipolar Power Devices.
Wolfgang Bartsch 1
1 , SiCED GmbH & Co. KG, Erlangen Germany
Show Abstract10:00 AM - D10.2
Design and Fabrication of High-Voltage N-channel DMOS IGBTs on 4H-SiC Free-standing Epilayers.
Xiaokun Wang 1 , James Cooper 1
1 School of Electrical and Computer Engineering and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana, United States
Show AbstractIn this paper we describe a high-voltage n-channel DMOS IGBT fabricated on a 4H-SiC free-standing epilayer. The IGBT is structurally similar to a vertical DMOSFET except that the substrate of the DMOSFET is replaced by a layer with opposite polarity. In the on-state, the drift region of the IGBT is conductivity modulated, resulting in a linear dependence of the power dissipation on the on-current, in contrast to the quadratic dependence of the DMOSFET. This property makes the IGBT superior to the DMOSFET for high-voltage, low-frequency applications. In 1996, GE and RPI reported the first n-channel SiC IGBTs [1], but the device performance was limited by the high resistance of the thick SiC p+ substrate. In this work we employ a novel inverted-growth process to obtain a thin (3 µm) p+ anode layer on the back of a thick (180 µm), lightly-doped (2x1014 cm-3) n- epilayer. With proper edge terminations, this epilayer should block at least 20 kV. The n- drift layer, n+ buffer layer and p+ anode layer are first grown on the silicon face of an n+ substrate. Then the n+ substrate is removed (leaving only the free-standing epilayers), the wafer is flipped over, and IGBTs are fabricated on the top surface of the n- blocking layer (the carbon face).The on-state performance of the IGBTs are optimized using 2-D numerical simulations. A JFET width of 12 µm is selected for these devices. The on-state performance depends critically on the ambipolar lifetime in the drift layer. Measurements on two wafers used in this work show that the ambipolar lifetime in the drift layer is at least 1 µsec. A self-aligned short-channel process is employed to achieve a channel length of 0.5 µm. Completed devices carry 27.3 A/cm2 at a power dissipation of 300 W/cm2. Unlike the DMOSFET, this performance is almost independent of temperature from room temperature to over 175 °C. [1].N. Ramungul, et al., IEEE Device Research Conf., Santa Barbara, CA, June 24-26, 1996
10:15 AM - D10.3
Power Device Degradation due to Dislocations and Stacking Faults in 4H-SiC Epitaxy.
Robert Stahlbush 1 , Sei-Hyung Ryu 2 , Qingchun Zhang 2 , Husna Fatima 2 , Sarah Haney 2 , Anant Agarwal 2
1 , Naval Research Laboratory, Washington, District of Columbia, United States, 2 , Cree, Inc., Durham, North Carolina, United States
Show AbstractWhile it has long been known that many of the physical properties of SiC make it an ideal material for power devices, it is only recently that its potential has begun to be realized. A significant factor in this progress has been the reduction of extended defects resulting from improved bulk and epitaxial growth. Wafers free of micropipes have been grown. The density of basal plane dislocations, which are responsible for the Vf drift in PiN diodes, has been reduced by more than two orders of magnitude. Further improvements to the device performance and reliability will rely heavily on the ability to rapidly and accurately measure and characterize extended defects in the epitaxy.Whole-wafer ultraviolet photoluminescence (UVPL) imaging is a recently developed technique for mapping dislocations and stacking faults in the lightly doped epitaxial layers used in power devices. It has several advantages compared to other commonly used methods for examining dislocations. It is both non-contact and non-destructive making it possible to screen wafers before fabrication. The setup is simpler than that for x-ray topography and the extended defects can be imaged through the whole epitaxial layer even for the thick layers typically used for 5 – 10 kV devices.In this presentation, UVPL imaging is used to map the locations of dislocations and stacking faults in the epitaxy of four 3 inch wafers before fabricating MPS and PiN diodes on those wafers. The devices are designed to have 10 kV blocking and have n- epitaxial drift layers that are 115 µm thick. UVPL maps reveal a number of types of dislocations and stacking faults within the device areas. Some diodes are free of basal plane dislocations (BPDs), some have a single BPD and some have 10s of BPDs. The BPDs are present in multiple forms including individual BPDs and pair arrays. Threading edge dislocation density ranges from >105/cm2 in regions with low-angle grain boundaries to <103/cm2. Single or multiple in-grown faults are present in some diodes.Preliminary testing has already indicated that UVPL wafer screening is an accurate predictor of device performance and degradation. The electrical behavior is very different for two MPS diodes, which also have different dislocations within their drift regions. One of the diodes contains about 10 pair arrays – a form of BPDs. After operating at forward bias at 100 A/cm2 both its forward and reverse biased performance was degraded. This included a decrease in the majority carrier mobility and a 10X reverse leakage increase. The second diode was free of BPDs. When stressed its forward and reverse conduction did not change and it maintained a breakdown > 10 kV. Work is in progress to test the electrical effects of the other types of dislocations and stacking faults present in the diodes on the four processed wafers.
10:30 AM - D10.4
Influence of Shockley Stacking Fault Propagation and Contraction on the Electrical Behavior of 4H-SiC Bipolar and Unipolar Devices.
Joshua Caldwell 1 , Robert Stahlbush 1 , Orest Glembocki 1 , Karl Hobart 1 , Eugene Imhoff 1 , Marko Tadjer 1 , Kendrick Liu 1
1 Power Electronics, Naval Research Lab, Washington , District of Columbia, United States
Show AbstractSilicon carbide is a desirable material for high power and temperature bipolar and unipolar electronic devices, such as high blocking voltage pin and Schottky diodes, respectively. However, the presence of electron-hole pair (ehp) recombination at basal plane dislocations (BPDs) in the drift layer of bipolar devices has been observed to nucleate Shockley stacking faults (SSFs). Continued ehp injection causes the SSFs to expand, which in turn induces an increase in the forward voltage drop (Vf). Furthermore, while the effect of SSFs upon SiC-based devices and the kinetic processes involved in there expansion are well understood, the thermodynamic driving force for SSF expansion and contraction are still in doubt.
A number of thermodynamic driving force models for SSF expansion have been previously proposed. The most prominent model to date speculated that the 3C-SiC structure of the SSFs is thermodynamically favorable in comparison to the native 4H-SiC lattice. However, we previously reported that SSFs can be contracted back to the original BPDs from which they nucleated via low-temperature annealing (400-7000C) and that this contraction is associated with a complete recovery of the Vf drift. These results clearly contradict the aforementioned driving force mode. This leaves only the model that was proposed by Lambrecht and Miao,1 which states that SSF expansion is driven by the electronic energy gain associated with the trapping of conduction electrons within the quantum wells associated with the 3C-SiC like SSFs, however, our results show that this model is still incomplete.
While SSFs are known to be an issue within any hexagonal SiC bipolar device, it has also been reported that hole injection from the body diode of a DMOSFET induces an increase in the specific on-state resistance of high power 4H-SiC DMOSFETs.2 Other reports have indicated that similar degradation occurs in other unipolar devices such as JBS and MPS diodes. It was presumed that such degradation is from the creation and expansion of SSFs. We report here that this degradation may be reversed, leading to a full recovery of the electrical characteristics of the devices via low temperature annealing (300-6000C), which is consistent with SSFs being the defect responsible for the electrical degradation. The results presented here in both bipolar and unipolar 4H-SiC devices clearly indicate that the detrimental effects of SSFs are wide-spread and have improved our understanding of SSF dynamics. These observations have allowed for the development of a thermodynamic driving force model that is qualitatively consistent with these results.
1. W. R. L. Lambrecht and M. S. Miao, Phys. Rev. B 73, 155312 (2006).
2. A. Agarwal, H. Fatima, S. Haney, et al., IEEE Electron Device Lett. 28, 587 (2007).
10:45 AM - D10.5
Performance of SiC Microwave Transistors in Power Amplifiers.
Sher Azam 1 , Rolf Jonnson 2 , Erik Janzen 1 , Qamar Wahab 1 2
1 Physics (IFM), Linköping University, Linköping Sweden, 2 Swedish Defense Research Agency (FOI), Swedish Defense Research Agency (FOI), Linköping Sweden
Show AbstractI. IntroductionSuperior physical properties of SiC (high saturated carrier velocity, high thermal conductivity and high breakdown field) allow SiC microwave transistor to deliver high power density. These qualities are utilized in the development of different generations of power amplifiers [1]. SiC transistors also offer higher impedance than LDMOS and GaAs FET devices, which simplifies matching networks. In this paper we are presenting performance of SiC microwave transistors in power amplifiers based on measured results of fabricated class-AB power amplifiers and pulse input in class-C switching response results of physical structure of fabricated and tested SiC MESFET[2] using load-pull simulation technique[3] in TCAD. II. Simulation results of Pulse input in class-C switching responseWe applied 5% square pulses at the gate. The results are; efficiency of 71.4 %, power density of 1.0 W/mm with a power gain of 31 dB. The switching loss was 0.424 W/mm even higher and the device show resistive loss behavior. The electron current density in the channel at peak resistive area during turn off time is 1.6E+05 A/cm-2, while ideally it should be zero. The drain current took longer time to turn off and current and voltage have simultaneously high values in contrast to the ideal operation. This simultaneous high current and voltage at the same time increases switching loss, which in turn reduces the efficiency. III. Fabrication and measurement results of class-AB power amplifiersWe designed and fabricated two class-AB power amplifiers (30 -100 MHz and 200-500 MHz).The designs are based on measured S-parameters of the transistors. The 30-100 MHz amplifier showed 45.6 dBm (~36 W) at 50 MHz output power at 1 dB compression (P1dB). The power added efficiency (PAE) is 48 % together with 21 dB of gain. The maximum output power at 2 dB gain compression was 46.1 dBm (~41 W). One power sweep was performed at a drain bias of 60 V, Vg= -8.5 V. At this bias point the P1dB was 46.7 dBm (~47 W). The typical results obtained in 200-500 MHz amplifier are; at 60 V drain bias the P1dB is 43.85 dBm (24 W) except at 300 MHz where only 41.8 dBm was obtained. The maximum out put power was 44.15 dBm (26 W) at 500 MHz corresponding to a power density of 5.2 W/mm. The PAE @ P1dB [%] at 500 MHz is 66 %. References[1]S. Azam, R. Jonsson, Q. Wahab “Single-stage, High Efficiency, 26-Watt power Amplifier using SiC LE-MESFET” IEEE Asia Pacific Microwave Conf. (APMC), Yoko Hama (Japan), pp. 441–444, December 2006.[2]J. Eriksson, N. Rorsman, H. Zirath, R. Jonsson, Q. Wahab, S. Rudner, “A comparison between Physical Simulations and Experimental results in 4H-Si C MESFETs with Non-Constant Doping in the Channel and Buffer Layers”, Material Science Forum, 2001, Vols. 353-356, pp. 699-702.[3]S. Azam, C. Svenson and Q. Wahab. “Pulse Input Class-C Power Amplifier Response of SiC MESFET using Physical Transistor Structure in TCAD.” In press, J. of Solid State Electronics.
11:00 AM - D10: Devices1
BREAK
D12: Devices and Applications II
Session Chairs
Thursday PM, March 27, 2008
Room 2004 (Moscone West)
2:30 PM - **D12.1
SiC-based Power Converters.
Madhu Chinthavali 1 , Burak Ozpineci 1 , Leon Tolbert 1 2 , Hui Zhang 2
1 Power Electronics and Electric Machinery Research Center, Oak Ridge National Laboratory, Knoxville, Tennessee, United States, 2 Electrical Engineering and Computer Science, The University of Tennessee, Knoxville, Tennessee, United States
Show AbstractThe theoretical advantages that SiC materials offer are being realized by using prototype or experimental devices in many different power electronic applications ranging from medium voltage to high voltage. In pursuit of mass production of hybrid electric vehicles, the automotive research industry has set some goals such as reducing the size and weight of the power electronics and cooling systems and increasing their efficiency. SiC devices are capable of operating at higher voltages, higher frequencies, and higher junction temperatures, which result in significant reduction in weight and size of the power converter and an increase in efficiency. The objectives of research efforts on SiC-based device applications at Oak Ridge National Laboratory (ORNL) in the FreedomCAR programs are*Assess the impact of replacing silicon (Si) power devices in transportation applications with SiC devices*Develop device models for drive train system level simulation studies and analyze the impact of SiC devices on the system performance.*Build prototype SiC-based prototype inverters/converters to validate the performance of SiC devices. *Build high temperature packages for SiC power devices to operate at 200°C. In this paper the characterization of several different SiC devices (Schottky diodes, JFETs, MOSFETs) and their behavior models will be presented. The static and dynamic behaviors of the devices will be analyzed to extract device parameters to study their impact on the system performance. ORNL collaborated with Cree and Semikron to build a hybrid 55-kW (Si IGBT–SiC Schottky diode) inverter by replacing the Si pn diodes in Semikron’s inverter with Cree’s SiC Schottky diodes. A comparison of performance between all-Si and the hybrid inverter will be presented. The test results of a benchtop prototype Si-SiC hybrid inverter built with 600 V, 300 A devices will also be presented. One of the most important characteristics of SiC power devices is that they can operate at much higher temperatures (>300°C) than Si power devices. Presently, SiC devices use Si device packages that limit the operation temperature (~125°C). Tests at ORNL have shown that at high temperatures, these packages break open and leave the devices inoperable. ORNL collaborated with Univ. of Arkansas and Univ. of Idaho to build several high temperature packages to demonstrate high temperature packages that can operate at 200°C ambient. Two different packages with SiC Schottky diodes were tested at ORNL and the test results will be shown in this paper. These studies revealed some important results, which can be used by the device researchers to further improve the design and fabrication of future SiC power electronics.
3:00 PM - D12.2
3D Thermal Stress Models for Single Chip SiC Power Sub-Modules.
Bang-Hung Tsao 1 , Jacob Lawson 1 , James Scofield 2
1 , University of Dayton Reserach Institute, Dayton, Ohio, United States, 2 , Air Force Research Labratory, WPAFB, Ohio, United States
Show AbstractThree dimensional models of single chip SiC power sub-modules were generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes, and heat transfer coefficients on temperature and thermal stress contours. Silicon nitride, aluminum-nitride, alumina were compared as substrates with or without an additional layer of CVD diamond on either top or bottom of the surfaces. Simulated heat fluxes of 100 to 300 watts/cm2 resulted in device junction temperatures in the range of 377 to 535 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 3350 watts/m2 K, SiC chips operated at 300 watts/cm2 power density maintained junction temperatures Tj < 535 K. Both the maximum and minimum chip temperature decreased with increasing heat transfer coefficient from 50 to 5000 watts/m2 K. In the applied heat flux range, the minimum and maximum Von Mises stress of a simulated single SiC device sub-module was between 946 MPa to 1.31GPa. If consistent with simulation results, CVD diamond integrated substrates should be superior to those comprised of only AlN, Al2O3, or Si3N4. Experimental validation of ANSYS results and more extensive multiple-chip power module simulations will also be explored.
3:15 PM - D12.3
Numerical Modeling and Characterization of a 4H-SiC DMOSFET.
Siddharth Potbhare 1 , Neil Goldsman 1 , Aivars Lelis 2
1 Electrical and Computer Engineering, University of Maryland, College Park, Maryland, United States, 2 , US Army Research Laboratory, Adelphi, Maryland, United States
Show Abstract3:30 PM - D12.4
Evaluation of Nitrogen and Aluminum Doping Impurities in Epitaxial 4H-SiC for Avalanche Photo Diode Applications.
Kurt Gaskill 1 , Brenda VanMil 1 , Evan Glaser 1 , Kok-Keong Lew 1 , Rachael Myers-Ward 1 , Charles Eddy 1 , Larry Wang 2 , Peter Zhao 2
1 , Naval Research Laboratory, Washington , District of Columbia, United States, 2 , Evans Analytical Group, Sunnyvale, California, United States
Show AbstractRecently 4H-SiC avalanche photo diodes (APD) that operate in Geiger mode were reported [1]. Optimization of the n and p-type doping and growth rates were required for the APD. Here we pro-vide details on the doping control. Epitaxial growths were performed in a horizontal hot-wall reactor (VP508, Epigress/Aixtron) at 1580°C and 100mbar using propane and silane at a C/Si ratio of 1.8. Nitrogen gas and trimethylaluminum (TMAl) were used as n and p doping sources using single and dou-ble-dilution doping manifolds connected to a pressure-balanced vent-run growth manifold; additional details are in [2]. Secondary ion mass spectrometry (SIMS), using the raster scan technique [3], was employed in conjunction with low-temperature (2K) photoluminescence and Hg CV-probing to evaluate the intentional and unintentional impurities in the epitaxial layers. Initially, SIMS was used to determine the background Al, B, Ti and V impurity levels of unintentionally doped films. The Al and B concentrations were 1.7x1014 and 2.2x1014 cm-3, respectively, and roughly constant over an 11 month interval except for a brief “burn-in” period when the reactor was first started. The Ti and V impurity concentrations were smaller.The Al doping calibration was extracted from the SIMS analysis of a single epitaxial growth at 2 μm hr-1 where the TMAl flow was monotonically ramped. The Al incorporation was linear with TMAl flow except for low flows. The abruptness of the transition for a two-fold increased in Al dop-ing transition was about 100Å. For concentration changes of two orders of magnitude the transition width was about 270 Å. A stabilization time of about 30 minutes in the double dilution manifold was required to achieve uniform doping profiles.For the case of nitrogen doping, transition widths were 600Å for a growth rate of ca. 5 μm hr-1. Comparing the SIMS concentration of N with CV measurements indicates that for samples with Nd-Na below 1015cm-3 the films were compensated. Using SIMS, the compensating impurities were found to be Al and B, with the concentrations described above. PL measurements were also used to extract out the N concentration assuming all donors were incorporated on the C sub-lattice. These results were found to be approximately linear down to 5x1014cm-3, extending the previous work by Glaser et al[4]. A SIMS doping profile of an APD will be presented and key doping issues for using these results to grow the Geiger mode APD will be discussed.[1] J.Hu, X.Xin, P.Alexandrov, J.H.Zhao, B.L.VanMil, D.K.Gaskill, K-K. Lew, R.Myers-Ward, and C.Eddy, Jr., Intl Conf. on SiC and Related Materials, Otsu, October 2007 and in press[2] B.L.VanMil, K-K.Lew, R.L.Myers-Ward, R.T.Holm, D.K.Gaskill, and C.R.Eddy, Jr., Materials Science Forum, 556-557, 125 (2007)[3] L. Wang, Materials Science Forum Vols. 457-460 (2004)[4] E.R. Glaser, B.V. Shanabrook, and W.E. Carlos, Appl. Phys. Lett. 86, 052109 (2005)
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