A1: Film Growth I
Session Chairs
Tuesday PM, April 10, 2007
Room 3001 (Moscone West)
9:30 AM - **A1.1
Experimental and Numerical Studies on a Large Area Amorphous Silicon Film Deposition Using Capacitively Coupled Very High-frequency Plasma.
Koji Satake 1 , Keisuke Kawamura 2 , Hideo Yamakoshi 1 , Yoshiaki Takeuchi 2
1 Advanced Technology Research Center, Mitsubishi Heavy Industries, Ltd., Yokohama Japan, 2 Nagasaki Research and Development Center, Mitsubishi Heavy Industries, Ltd., Nagasaki Japan
Show AbstractPlasma enhanced chemical vapor deposition (PECVD) is a great fabrication tool with respect to the low-temperature preparation of high-quality thin film devices (e.g. photovoltaic solar cells). PECVD has usually been carried out in parallel plate, capacitively coupled radio frequency discharges sustained in gas mixtures. In terms of industrial applications, high-quality films in higher deposition rate and larger area deposition are needed. Very high-frequency (VHF: 30-300 MHz) plasma has the advantage of higher deposition rate and lower ion damage; however, it is difficult to generate the uniform plasma in large area due to standing wave and high stray impedance. In the case of photovoltaic solar cell application, the film uniformity is usually required to be less than 15%. The uniformity of films across the substrate is a serious issue when the reactor dimensions become comparable to a quarter of the free-space wavelength associated with the excitation frequency. In addition, the fact that the deposition uniformity is very sensitive to the external parameters such as the frequency, the gas pressure, and the input power in the VHF plasma makes difficult to obtain the large-area uniform deposition. In order to solve this issue, it is important to understand the behavior of the voltage distribution across the electrode. Here we show measurements of the voltage and plasma distribution. Two kinds of dedicated vacuum chambers are prepared for one and two-dimensional observations of the voltage and plasma distributions. In an one-dimensional chamber with a rod-like electrode, the relationship between the voltage and the plasma distribution is examined. The one-dimensional measurements help us to understand the inhomogeneity problem resulting from the standing wave. A numerical model based on a transmission-line modeling (TLM) taking account the influence of the plasma conditions has been introduced to calculate the voltage distribution on the electrode. The correlation between the model parameters and the plasma conditions is investigated through comparison with the experimental results of the voltage distribution on the one-dimensional electrode. In a large-area rectangular reactor with the ladder electrode, two VHF powers with the phase difference between them are supplied to the electrode through multiple feeding points located at symmetrical positions of the electrode to generate a large-area uniform plasma. From the observation of plasma emissions and numerical results of the voltage distributions at several phase differences of the VHF powers, we found that the phase modulation method achieved the uniform plasma by moving spatially the antinode and the node of the standing wave. Finally we obtained amorphous silicon deposition with a uniformity of <20% over a large substrate of size 100cm x 140cm at 60 MHz.
10:00 AM - A1.2
Atomistic Analysis of the Role of Surface Coordination Defects in the Growth of Amorphous Silicon Thin Films
Mayur Valipa 1 , Tejinder Singh 1 , Dimitrios Maroudas 1
1 Chemical Engineering, University of Massachusetts, Amherst, Amherst, Massachusetts, United States
Show AbstractDevice-quality hydrogenated amorphous silicon (a-Si:H) thin films are deposited typically by plasma deposition under conditions where the SiH
3 radical is the dominant deposition precursor. Growth of the a-Si:H film has been assumed to occur through a combination of surface H abstraction by impinging SiH
3 radicals to create dangling bonds (DBs), and the passivation of these surface DBs by subsequently impinging SiH
3 radicals. However, on a-Si:H surfaces, the DB surface coverage is low (~ 0.001), which is incompatible with the observed high film growth rates. Hence, the precise role of surface coordination defects in mediating the a-Si:H growth process remains unclear.
In this presentation, we focus on a detailed analysis of the role of surface coordination defects in determining the growth mechanism of a-Si:H thin films. Our analysis is based on a synergistic combination of molecular-dynamics (MD) simulations on a-Si:H film surfaces with first-principles density functional theory (DFT) calculations on the hydrogen-terminated crystalline Si(001)-(2×1) surface. We studied the reactions of the SiH3 radical through repeated radical impingement on growth surfaces of a-Si:H films over the temperature (T) range 475 ≤ T ≤ 800 K. Our MD simulations reveal that the SiH3 radical is very mobile on the a-Si:H surface and diffuses with a low activation barrier. Furthermore, the diffusing SiH3 radical incorporates into the a-Si:H film only when it transfers an H atom and forms a second Si-Si backbond, resulting in the immobilization of the radical on the a-Si:H surface, which contributes to the growth of the a-Si:H film. Specifically, the H atom is transferred from the SiH3 radical only when the Si of the radical becomes five-fold coordinated with a floating bond (FB), and, more importantly, the H atom is transferred to a four-fold coordinated Si atom, which also becomes five-fold coordinated after H transfer, resulting in another FB. Such FB-mediated Si incorporation reactions have energy barriers of 0.35-0.5 eV, and occur frequently, leading to growth of the a-Si:H film even when the DB density is low. In contrast, DB-mediated Si incorporation reactions, where the radical either adsorbs onto a DB, or dissociates by transferring an H to a surface DB site, occur in less than 10 % of the cases, consistent with the low surface DB density. Based on our results, we conclude that the dominant mechanism for a-Si:H film growth is mediated by FBs and excludes the involvement of DBs.
These results are consistent mechanistically with our DFT calculations on the H-terminated Si(001)-(2×1) surface, according to which FB-mediated Si incorporation from SiH3 radicals occurs with barriers of 0.4-0.5 eV. Our results also are consistent with experimental measurements of a-Si:H film surface composition, film growth rates, as well as the low surface DB coverage.
10:15 AM - A1.3
Laser Enhanced Deposition of Isotopically Enriched Silicon.
Regis Bisson 1 , Tung Dang 1 , Marco Sacchi 1 , Rainer Beck 1 , Thomas Rizzo 1
1 , EPFL LCPM, Lausanne Switzerland
Show AbstractLaser light is an invaluable tool for detailed experimental studies of chemical reactions and may ultimately be used for controlling surface growth processes. The ability to prepare silane molecules in specific quantum states using laser radiation before impingement on a silicon surface is a key to study the epitaxial growth of Si(100)-2x1 at a microscopic level. In addition to exploring the dynamics of this important reaction, the controlled deposition of isotopically enriched silicon layers via isotope selective laser excitation is of interest to improve transport properties, such as thermal conductivity of silicon-based devices. We present new results for the dissociative chemisorption of SiH4 on Si(100)-2x1, which provide clear evidence of the coexistence of both direct and indirect chemisorption pathways. Moreover, using infrared laser excitation of molecular beam, we demonstrate for the first time that the chemisorption of SiH4 on Si(100)-2x1 is vibrationally activated. This fact opens a way for isotopically enhanced deposition as we succeed to excite the vibration of only one of the three natural isotopes of SiH4. The efficiency of vibrational energy over translational energy to promote the chemisorption of SiH4 on Si(100)-2x1 has been measured and the maximal isotopic enrichment estimated.
10:30 AM - **A1.4
Meter-Scale Deposition of Silicon Thin Films by Slot-Excited Large Microwave Plasma.
Hideo Sugai 1 , Y. Nojiri 1 , Y. Hotta 1 , T. Ishijima 1 , H. Toyoda 1 , A. Masuda 2 , M. Kondo 2
1 Department of Electrical Engineering and Computer Science, Nagoya University, Nagoya, Aichi Prefecture, Japan, 2 Research Center for Photovoltaics, National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki, Japan
Show AbstractOne of current challenges in giant LCD and solar panel manufacturing is high-speed deposition of large-area uniform thin films of amorphous-, micro- and polycrystalline silicon. Plasma-aided low-temperature CVD technology employed here necessitates meter-scale high-density uniform plasma. Such high-density plasmas cannot be obtained conventional RF discharge at 13.56 MHz. Use of a VHF discharge frequency allows us to enhance the plasma density, however the plasma uniformity deteriorates due to standing wave effects and edge effects. Here we present a breakthrough achieved by slot-excited microwave discharge at 2.45 GHz, and further progress using 915 MHz discharge. We successfully produced high-density (~3x E11 cm-3) plasmas with large dimension: 1 m in length and 0.3 m in width at 2.45 GHz, and 2 m in length and 0.5 m in width at 915 MHz. Surface waves were observed to propagate underneath a dielectric plate. The wave mode and amplitude profiles measured by a movable antenna were in good agreement with simulation results based on FDTD method. Thus, the microwave plasma is confirmed to be produced by surface wave absorption. Comparison of 2.45 GHz with 915 MHz leads to several advantages of 915 MHz: First, the free space wavelength of 915 MHz is ~three times larger so that spacing between slots is also three times larger, and hence the slot number is reduced to 1/3 compared with 2.45 GHz. Second, the plasma smoothly startups from very low power, in comparison with 2.45 GHz, owing to the much lower surface-wave-resonance density. Third, high power 915 MHz power supply of 60–100 kW is commercially available. Application of microwave plasma to meter-scale thin films formation is promising in manufacturing giant electronic devices such as solar panel. Using a relatively small size plasma of 30 cm in diameter, we demonstrated high-speed deposition (>10 nm/s) of micro-crystalline silicon films at 500 K obtained in 20 % SiH4/H2 discharge, while poly-crystalline silicon films of large grain size (>200 nm) at 700 K were formed in 2 % SiH4/H2 discharge. Recently, we tried deposition of meter-scale silicon thin films in a 915 MHz two-meter long device. The following two cases were tested: (a) glass substrate (1.8 m in length, 0.2 m in width) at 250 degree C, total pressure of 7 Pa with a flow rate of 25 sccm H2 and 25 sccm SiH4, discharge power of ~6 kW, and (b) polymer film substrate (1.8 m in length, 0.3 m in width) at 180 degree C, total pressure of 7 Pa with a flow rate of 25 sccm H2 and 25 sccm SiH4, and discharge power of ~6 kW. X-ray diffraction (XRD) and Raman spectroscopy analysis of deposited films revealed that the films deposited in case (a) is micro-crystalline and that in case (b) is amorphous. Two times larger plasma CVD device (1 m in width and 2 m in width) is now under construction, where three systems of 915 MHz waveguide and multi-slot antenna will be used.
A2: Defects and Metastability
Session Chairs
Tuesday PM, April 10, 2007
Room 3001 (Moscone West)
11:30 AM - A2.1
Mapping Electron Transport and Recombination in Silicon Thin Films by Scanning Tunneling Microscopy.
Manuel Romero 1 , Woong Choi 2 , Alp Findikoglu 2 , Mowafak Al-Jassim 1
1 , National Renewable Energy Laboratory, Golden, Colorado, United States, 2 , Los Alamos National Laboratory, Los Alamos, New Mexico, United States
Show AbstractThere is a renewed interest in silicon thin films for solar energy research. This attraction is driven by recent steady improvements in conversion efficiencies and, even more critical to the future expansion of the silicon photovoltaic industry, to the awareness in the community that “solar-grade” silicon is becoming a scarce commodity.In thin film silicon solar cells, one of if not the most significant source of degradation is recombination at grain boundaries. Mitigation of their adverse impact is done through passivation, one of the most effective being hydrogen treatment. A second alternative explored by the authors is giving a well-defined preferential orientation to the film, which results in less disruptive (low-angle) grain boundaries. Buffer layers with a strong preferential orientation can be obtained by using an ion beam during growth. Once established, the buffer layer serves as a template for the epitaxial growth of subsequent layers.In this contribution, we investigate how the misorientation of individual grain boundaries affects electron transport and recombination in well-aligned silicon thin films. Hall measurements are commonly used to investigate electron transport in semiconductors but do not provide the resolution needed to resolve individual grain boundaries. Furthermore, the measurement is only representative of those grain boundaries offering minimum series resistance between the terminal contacts. We have developed an innovative approach for electron transport mapping based on the combination of scanning tunneling microscopy (STM) with the local electron excitation in the scanning electron microscope. We investigate the transport across single boundaries using this STM platform.Recombination at grain boundaries is investigated by scanning tunneling luminescence (STL). We show that luminescence can be stimulated in silicon by recombination of secondary electrons and holes generated by impact ionization of hot tunneling electrons –in analogy to photoluminescence. Maps of the photon intensity are generated by synchronizing the lateral scanning of the STM with the readout of a CCD. The superb resolution offered by STL allows for local excitation of grain boundaries without much interference of adjacent grains.
11:45 AM - A2.2
Detection of Coherent Spin Oscillations in the Photocurrent of Microcrystalline pin Solar Cells.
Jan Behrends 1 , Christoph Boehme 1 2 , Stefan Haas 3 , Bernd Rech 1 3 , Klaus Lips 1
1 Abt. Silizium-Photovoltaik, Hahn-Meitner-Institut Berlin, Berlin Germany, 2 Department of Physics, University of Utah, Salt Lake City, Utah, United States, 3 Institute of Photovoltaics, Forschungszentrum Jülich, Jülich Germany
Show AbstractDefects in the band gap of hydrogenated microcrystalline silicon (µc-Si:H) pin solar cells, even at low concentrations, can act as recombination centres and thus, they can influence the electronic properties of the device significantly. A powerful technique to investigate these recombination processes is pulsed electrically detected magnetic resonance (pEDMR). This method is based on transient photocurrent measurements after varying specific recombination or transport rates by coherent manipulation of the spin-states of spin pairs that form during the capture of charge carriers at defects [1]. This allows to address specific defects selectively and hence, to reveal information about the microscopic mechanisms of recombination and transport that involve paramagnetic states. It was previously shown by applying pEDMR at low temperatures (T=10K) to electron cyclotron resonance chemical vapour deposition (ECR-CVD) grown µc-Si:H thin films, that charge carrier recombination is dominated by a direct capture process through excited states at silicon dangling bonds (db) [1,2].In this study we show that we are able to conduct similar experiments directly on state-of-the-art µc-Si:H pin solar cells prepared on ZnO coated glass by radio frequency plasma enhanced chemical vapour deposition (RF-PECVD) [3]. An adapted contact structure was developed by laser scribing techniques, which allows the observation of Rabi oscillations in the photocurrent reflecting coherent spin motion on a time scale much shorter than the coherence time that is usually determined by recombination. By analysing these oscillations, it is possible to discriminate experimentally between different spin-coupling regimes and thus, between strongly coupled spin pairs that indicate a direct capture process and weakly coupled pairs which are characteristic for a tunnelling process involving shallow tail states [2]. In contrast to our previous results achieved on ECR-CVD grown μc-Si:H thin films, we found a much stronger signal originating from weakly coupled spin pairs in the measurements on μc-Si:H solar cells. These results will be discussed with regard to different possible recombination mechanisms.1. C. Boehme, K. Lips, Phys. Rev. Lett., 91 (24), 246603 (2003)2. C. Boehme, K. Lips, J. Non-Cryst. Solids, 338-340, 434 (2004)3. B. Rech, T. Roschek, T. Repmann, J. Müller, R. Schmitz, W. Appenzeller, Thin Solid Films, 427, 157 (2003)
12:00 PM - A2.3
ESR and Transport in Thin Film Hydrogenated Silicon over a Wide Range of Structural Compositions and Defect Densities.
Oleksandr Astakhov 1 2 , Friedhelm Finger 1 , Reinhard Carius 1 , Yuri Petrusenko 2 , Valery Borysenko 2 , Dmitro Barankov 2
1 Institute of Photovoltaics, Forschungszentrum Jülich, Jülich Germany, 2 Institute of Solid-State Physics, Materials Sciense and Technologies, National Science Center Kharkov Institute of Physics and Technology, Kharkov Ukraine
Show AbstractProgress in the field of thin film silicon devices as TFTs or solar cells is in part determined by the understanding of the nature and properties of defects in the material. In particular the optimization of the manufacturing processes demands deeper knowledge in the role of defects in electronic properties of thin film hydrogenated silicon. We investigated defects in amorphous and microcrystalline hydrogenated silicon (a-Si:H and µc-Si:H) with electron spin resonance (ESR) and conductivity measurements. Samples were prepared over the whole range of structure compositions from highly crystalline to completely amorphous with great emphasis on the material prepared before and after amorphous-microcrystalline transition. The controllable variation of the initially low defect density in the material was realized using low temperature (100K) 2MeV electron bombardment and subsequent stepwise annealing. Samples were kept at liquid nitrogen (LN2) temperature prior to measurements in order to prevent uncontrolled annealing at room temperature.A spin density increase over 3 orders of magnitude was observed in the irradiated samples. The resonance intensity predominately increases at the position of the initial resonance assigned to silicon dangling bonds (db), g=2.0055…2.0045. Importantly, strong additional resonances appear as satellites superimposed on the db line at g≈2.000 and g≈2.010. The contribution of the new resonances was estimated assuming persistence of the shape of db-line and makes up to 50% of the total spin density after irradiation. The satellites intensity decreases faster than the intensity of the db-line. The spin density and line shape recover completely after annealing at 160oC.n-doped samples of µc-Si:H show the conduction electron (CE) resonance at g=1.998 after deposition while the db resonance is suppressed or not visible at all due to doping induced shift of the Fermi level. After irradiation n-doped samples show a strong increase of the db resonance while the conduction electron (CE) resonance disappears and the spectrum becomes identical to irradiated intrinsic material with presence of the above-mentioned satellites. With annealing the CE resonance emerges again and the line shape and intensity return to the as-deposited state completely. Dark and photoconductivity in n-doped µc-Si:H decrease nearly equally up to 4 orders of magnitude for 5ppm doped material and only 1 order for 50ppm doped µc-Si:H. The change corresponds to the defect-induced shift of the Fermi level.Dark conductivity of the intrinsic a-Si:H samples shows a slight decrease or does not change after irradiation while the photoconductivity decreases over 3 orders of magnitude due to increase of the density of recombination centers. The photoconductivity exhibits inverse dependence on the spin density for the amorphous material. For all types of samples the initial conductivity was restored by annealing at 160oC.
12:15 PM - A2.4
Defects in Tritiated Amorphous Silicon.
Tong Ju 1 , Janica Whitaker 2 , Stefan Zukotynski 3 , Nazir Kherani 3 , P.Craig Taylor 4 , Paul Stradins 5
1 Physics, University of Utah, Salt Lake City, Utah, United States, 2 , ATK Thiokol Hazard Analysis, Brigham City, Utah, United States, 3 Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada, 4 Department of Physics, Colorado School of Mines, Golden, Colorado, United States, 5 , National Renewable Energy Laboratory, Golden, Colorado, United States
Show AbstractThe appearance of optically or electrically induced defects in hydrogenated amorphous silicon (a-Si:H), especially those that contribute to the Staebler-Wronski effect, has been the topic of numerous studies, yet the mechanism of defect creation and annealing is far from clarified. We have been observing the growth of defects caused by tritium decay in tritiated a Si-H instead of inducing defects optically. Tritium decays to He3, emitting a beta particle (average energy of 5.7 keV) and an antineutrino. This reaction has a half –life of 12.5 years. In these 6 at% tritium-doped a-Si:H samples each beta decay will create a defect by converting a bonded tritium to an interstitial helium, leaving behind a silicon dangling bond. We use ESR (electron spin resonance) and PDS( photothermal deflection spectroscopy) to track the defects. First we annealed these samples, and then we used ESR to determine the initial defect density around 10^16/cm3 ,which is mostly a surface spin density. After that we have kept the samples in liquid nitrogen for almost two years. During the two years we have used ESR to track the defect densities of the samples. The defect density increases without saturation to a value of 7x10^19/cm3 after two years, a number smaller than one would expect if each tritium decay were to create a silicon dangling bond (2x10^20/cm3). This result suggests that there might be either an annealing process that remains at liquid nitrogen temperature, or tritium decay in clustered phase not producing a dangling bond due to bond reconstruction and emission of the hydrogen previously paired to Si-bonded tritium atom. After storage in liquid nitrogen for two years, we have annealed the samples. We have stepwise annealed one sample at temperatures up to 200 C, where all of the defects from beta decay are annealed out, and reconstructed the annealing energy distribution. The second sample, which was grown at 150 C, has been isothermally annealing at 300 K for several months. The defects remain well above their saturation value at 300 K, and the shape of decay suggests some interaction between the defects.
12:30 PM - A2.5
Light Soaking and Thermal Annealing Effect on Micro-electrical Properties of Amorphous and Nanocrystalline Mixed-phase Silicon Solar Cells.
Chunsheng Jiang 1 , Baojie Yan 2 , Helio Moutinho 1 , Mowafak Al-Jassim 1 , Jeff Yang 2 , S. Guha 2
1 , National Renewable Energy Laboratory, Golden, Colorado, United States, 2 , United Solar Ovonic LLC, Troy, Michigan, United States
Show AbstractWe report on the measurement of local current in hydrogenated amorphous (a-) and nanocrystalline (nc-) mixed-phase n-i-p silicon solar cells in the initial, light-soaked, and annealed states by using conductive atomic force microscopy (C-AFM). The C-AFM measurement shows that the local current density in the nc-Si:H aggregation areas significantly decreased after light-soaking and recovered to a value similar to the initial state after annealing at a high temperature in a vacuum. This result supports our previous model of explaining the light-induced Voc increase [1]. The C-AFM measurements show that the local current flows mainly through the nc-Si:H aggregates and is very small on the surrounding a-Si:H matrix. The local current values depend not only on the characteristics of solar cell samples, but also on the measurement conditions such as wearing conditions of both the sample surface and tip after scanning. Therefore, we took C-AFM images on a fresh area in each scan and kept all other parameters the same for the measurements. Because the local current is not uniform within an aggregate, we took an average of the current values over the area of each aggregate. We found that the average local current on the nc-Si:H aggregates increases with the aggregation size in all the initial, light-soaked, and annealed states. This means that the local current measured by the C-AFM not only depends on the material structure directly underneath the tip, but also has contributions from the lateral collection in the area of the nc-Si:H aggregate. Furthermore, we linearly fitted the average current versus the aggregation area to obtain the current density for the three samples. The local current densities on the nc-Si:H aggregates are (9.4±0.7)×10-1, (2.8±0.3)×10-1, and (10±1)×10-1 (nA/μm2) for the initial, light-soaked, and annealed samples, respectively, under a forward bias voltage of 0.75 V. The local current density decreased significantly after the light soaking and recovered after the high temperature annealing. Our previous model explained the light-induced Voc increase with an assumption that the current in the nc-Si:H regions is reduced after light soaking [1]. However, it was a challenge to explain how the forward current changes in the nc-Si:H regions if they are just individual grains. The C-AFM measurements now reveal that the high current regions are not a single grain, but an aggregate of many grains. Second, the current density in the nc-Si:H aggregate indeed decreases after light soaking, which supports our previous model with the modification that the nc-Si:H regions are the aggregates of many grains. Although the mechanism of the light-induced current reduction in the nc-Si:H aggregates is not clear, the defect generation in the grain boundaries inside the aggregates is a logical consideration.[1]. B. Yan, J. Yang, and S. Guha, Proc. of 3rd World Conference on Photovoltaic Energy Conversion, Osaka, Japan, 2003, p. 1627.
12:45 PM - A2.6
Creation Kinetics of the Different Light Induced Gap States in Diluted protocrystallinea-Si:H Thin Films and Corresponding Solar Cells.
Christopher Wronski 1 , X. Niu 2 , Benjamin Ross 3
1 EE, Penn State University, University Park, Pennsylvania, United States, 2 , GE Global Research Center, Niskayuna, New York, United States, 3 , Penn State University, University Park, Pennsylvania, United States
Show AbstractRecently studies have been carried out on hydrogen diluted, protocrystalline a-Si:H films and corresponding solar cells in which the light induced changes in the midgap states were characterized by the carrier recombination through these states. In these studies three regimes in the light induced changes in the midgap states were clearly identified. includeding the extensively reported t1/3 time dependence. However it was also clearly shown that the evolution of just the light induced midgap defect states actually has a t1/2 dependence prior to the transition in kinetics which leads to the degraded steady state [1, 2]. Here we report on a study in which the evolution of just the light induced defect states is characterized for the states at midgap as well as those located closer to the valence band. This is carried out by extending the energies over which the states are characterized in both films and cells to up to 0.4 eV from midgap. In addition, the evolutions of the gap states in the films is characterized with Dual Beam Photoconductivity measurements with different quasi – Femi level splitting that allowed the evolution in the densities of the different gap states to be directly observed. On the other hand the characterization of kinetics in the light induced changes in the corresponding solar cells was extended to include those on Fill Factors. Using these different characterization techniques it was possible to clearly separate the kinetics for the states located within about 0.1 eV and those located about 0.35 eV below midgap as identified with DBP measurements. Amongst the results presented are the further confirmations of the t1/2 dependence for the creation of both types of the midgap states where their individual kinetics could be separated with the DBP measurements. In addition results are presented in which one of the two states can be clearly identified as a “fast” and the other as a “slow” state. Results are also presented in which the evolutions of the gap states located away from midgap have been characterized and their kinetics are shown to be distinctly different from those for the midgap states.From these new results it is possible to self consistently explain the differences observed between the degradation kinetics in films with those in corresponding cells. This is discussed as well as their relevance in drawing new conclusions into the nature of the different light induced defects as well as their possible origins. 1.J.Deng et al., Proceedings of 2006 Material Society Spring Meeting2.B.Ross et al., Proceedings of the 2006 IEEE World Conference on Photovoltaic Energy Conversion .
A3: Solar Cells I
Session Chairs
Tuesday PM, April 10, 2007
Room 3001 (Moscone West)
2:30 PM - **A3.1
Electrical and Optical Modelling of Thin-Film Silicon Solar Cells.
Miro Zeman 1 , Janez Krc 2
1 , Delft University of Technology, Delft Netherlands, 2 , University of Ljubljana, Ljubljana Slovenia
Show Abstract3:00 PM - A3.2
Enhancing Light-trapping and Efficiency of Solar Cells with Photonic Crystals.
Rana Biswas 1 2 3 , Dayu Zhou 4 2
1 Physics & Astronomy; Electrical & Computer Engineering, Iowa State University, Ames, Iowa, United States, 2 Microelectronics Research Center, Iowa State University, Ames, Iowa, United States, 3 Ames Laboratory, Iowa State University, Ames, Iowa, United States, 4 Electrical and Computer Engineering, Iowa State University, Ames, Iowa, United States
Show AbstractIncreasing light trapping in thin film solar cells is a major route to improving solar cell efficiency. Traditional light trapping solutions involve use of a textured back reflector. We investigate alternative light trapping schemes that do not use metallic back-reflectors, thereby avoiding optical losses and enhancing optical path lengths. We investigated using both photonic band gap structures and distributed Bragg reflectors (DBR) behind the absorber layer for forming a reflecting band at near-IR/optical wavelengths. Such photonic crystals need to be combined with a grating[1] to diffract light at oblique angles within the cell, thereby increasing the path length and absorption. We have modeled the reflectivity and absorption of such solar cell structures with a rigorous 3-d scattering matrix approach where Maxwell’s equations are solved in Fourier space[2], and the electric/magnetic fields are expanded in plane waves. Within this approach any number of dielectric layers or 2-d periodic structures can be introduced. A square grating of etched cylinders in an oxide layer behind the absorber, increases absorption by a factor of ~2 over a DBR in the 0.4-1.1 micron wavelengths. Specific results will be presented for a a-Si:H and a nc-Si absorber layers, and optimized grating configurations will be presented. The light-trapping efficiency will be compared with metallic back-reflectors. Gratings in front of the absorber will be considered. Comparisons with a c-Si absorber will be presented. The advantages/drawbacks of 3-d photonic crystals will be discussed. Supported by the Catron Foundation and Dept. of Energy.[1] L. Zeng et al, Appl. Phys. Lett. 89, 111111 (2006). P. Bermel et al(to be published).[2] R. Biswas et al, Phys. Rev. B. 74, 045107 (2006).
3:15 PM - A3.3
Optical Properties of Ag/ZnO Interfaces and Associated Losses in Back-Reflectors for Thin Film Si Photovoltaics.
Deepak Sainju 1 , Anuja Parikh 1 , Nikolas Podraza 1 , Peter van den Oever 2 , Maarij Syed 3 , Xunming Deng 1 , Robert Collins 1
1 Department of Physics and Astronomy, University of Toledo, Toledo, Ohio, United States, 2 Department of Applied Physics, Eindhoven University of Technology, Eindhoven Netherlands, 3 Department of Physics and Optical Engineering, Rose-Hulman Institute of Technology, Terre Haute, Indiana, United States
Show AbstractReal time spectroscopic ellipsometry (SE) has been applied to investigate the optical properties of Ag/ZnO interfaces in the back-reflector structures of thin film Si n-i-p solar cells. Initially, opaque silver (Ag) films are deposited by rf magnetron sputtering onto oxide-covered crystal silicon substrates (c-Si/SiO2) and studied in real time using multichannel SE (0.75 - 6.5 eV). Variations in substrate temperature are used to control the thickness of the surface roughness layer (ds) on the Ag films from a minimum of 6 Å to > 100 Å. Zinc oxide (ZnO) layers, also deposited by rf magnetron sputtering and observed in real time by SE, are then deposited onto the silver-covered c-Si/SiO2 substrates in order to replicate the back-reflector structure of the solar cells. The deposition of ZnO onto the Ag film results in the formation of a Ag/ZnO interface region with distinctly identifiable optical properties. As a check of these optical properties, ex situ reflectance measurements of the final Ag/ZnO structures in normal incidence geometry are consistent with the optical models deduced from polarization analysis. The thickness of the Ag/ZnO interface region increases with increasing initial roughness thickness on the Ag surface, and the optical properties of the interface region exhibit clear trends as well. The most prominent new feature in the dielectric functions (ε1, ε2) of the Ag/ZnO interface regions as determined from real time SE is a plasmon absorption band near 2.75 eV. This band appears under all conditions of Ag surface roughness and Ag/ZnO interface thickness; however, due to its high energy, it exerts no detrimental effect on solar cell performance. Increased roughness thicknesses on the Ag surface (entering the macroscopic roughness or "textured" regime) yield interface regions with stronger absorption (as indicated by their ε2 spectra) possibly due to the appearance of a lower energy plasmon band in the near infrared range where it will impact solar cell quantum efficiency. The detrimental impact of the interface region has been quantified by optical modeling of the complete solar cell. From this cell modeling, it can be seen that as the Ag/ZnO interface region increases in thickness (i.e., increasing texture) interface absorption losses increase up to the equivalent of ~ 1-2 mA/cm2. In this study, the role of screening by ZnO in determining the plasmon energies and solar cell losses is explored by measuring the interface region under different ambients after etching back the ZnO to the interface with the Ag film.*Research supported by NREL TFPPP Subcontract No. ZXL-5-44205-06.
3:30 PM - A3.4
High Open-circuit Voltage in Silicon Heterojunction Solar Cells.
Qi Wang 1 , Matt Page 1 , Eugene Iwaniczko 1 , Yueqin Xu 1 , Lorenzo Roybal 1 , Russell Bauer 1 , Dean Levi 1 , Yanfa Yan 1 , Tihu Wang 2 , Howard Branz 1
1 , NREL, Golden, Colorado, United States, 2 , Suntech Power, Wuxi, Jiangsu, China
Show AbstractHigh open-circuit voltage (Voc) silicon heterojunction (SHJ) solar cells are fabricated in double-heterojunction a-Si:H/c-Si/a-Si:H structures using low temperature (<200°C) hydrogenated amorphous silicon (a-Si:H) contacts deposited by hot-wire chemical vapor deposition. On p-type c-Si float-zone wafers, we used an amorphous n/i contact to the top surface and an i/p contact to the back surface to obtain a Voc of 667 mV in a 1 cm2 cell with an efficiency of 18.2%. This is the best reported p-type SHJ voltage. In our labs, it improves over the 652 mV obtained with a front amorphous n/i heterojunction emitter and a high-temperature alloyed Al back-surface-field contact. On n type c-Si float-zone wafers, we used an a Si:H (p/i) front emitter and an a-Si:H (i/n) back contact to achieve a Voc of 710 mV on 0.05 cm2 and 691 mV on 1 cm2 cell. Though not as high as the 730 mV reported by Sanyo on n-wafers, this is the highest reported Voc for SHJ c-Si cells processed by the HWCVD technique. We found that the proper c-Si surface clean and double-heterojunction are the key to the high Voc. Transmission electron microscopy reveals that high Voc cells require an abrupt interface from c-Si to a-Si:H. If the transition from the base wafer to the a-Si:H incorporates either microcrystalline or epitaxial Si at c-Si interface, a low Voc will result. Lifetime measurement shows that the BSRV can be reduced to ~15 cm/s through a-Si:H passivation. Dark current measurements quantify the corresponding dark current reduction in the cells. By optimizing the back-surface doped layer conductivity, we are able to obtain good fill factors. Amorphous silicon heterojunction layers on crystalline wafers thus combine low-surface recombination velocity with excellent carrier extraction. This work was supported by the U.S. Department of Energy under Contract DE AC39 98 GO10337.
3:45 PM - A3.5
Breaking the 600 mV Barrier of Thin Film Microcrystalline Silicon Solar Cells.
Menno van den Donker 1 , Stefan Klein 1 , Friedhelm Finger 1 , Bernd Rech 1 , Erwin Kessels 2 , Richard van de Sanden 2
1 IPV, Forschungszentrum Juelich GmbH, Juelich, Nordrhein-Westfalen, Germany, 2 Applied Physics, TU Eindhoven, Eindhoven Netherlands
Show AbstractThe open-circuit voltage (Voc) of state-of-the-art thin film microcrystalline silicon (µc-Si:H) solar cells continuously increases for decreasing crystalline volume fraction of the absorber layer. However, a sharp drop in fill factor (FF) and short-circuit current (Jsc) normally limits the solar energy conversion efficiency for a crystalline volume fraction below ~60%, corresponding to an optimum Voc around 520-550 mV. In this contribution µc-Si:H solar cells with an open-circuit voltage higher than 600 mV will be presented. A hot wire deposited buffer layer inserted between the p-i interface and controlled SiH4 flow profiling during the RF parallel plate plasma deposition of the absorber bulk prevented the sharp drop in FF and Jsc from occurring. This careful redesign of bulk and interfaces facilitated an efficient charge carrier collection from an absorber layer with an unusually low crystalline volume fraction, determined by Raman spectroscopy, of 30%. Judging from the infrared absorption and excellent charge carrier transport the opto-electronic properties of this material were still dominated by the crystalline rather than the amorphous volume fraction. A solar energy conversion efficiency of 9.8% was obtained at an open-circuit voltage of 603 mV. This result shows that material with a low crystalline volume fraction of ~30% shows superior electronic properties and is highly suitable for µc-Si:H applications. Moreover, the high Voc, which lies in the range of multi-crystalline wafer-based solar cells, paves the way to extremely efficient thin film silicon solar cells.
Tuesday PM, April 10, 2007
Room 3001 (Moscone West)
4:30 PM - **A4.1
μc-SiC:H Grown with HWCVD for Photovoltaic Applications: Structure and Electronic Properties.
Reinhard Carius 1 , Stefan Klein 2 , Friedhelm Finger 1 , Arup Dasgupta 1 , Yuelong Huang 1 , Lothar Houben 3 , Martina Luysberg 3
1 Institute of Photovoltaics, Research Center Juelich, Juelich Germany, 2 , Applied Materials GmbH & Co. KG, Alzenau Germany, 3 Institute of Solid State Research, Forschungszentrum Juelich, Juelich Germany
Show AbstractMicrocrystalline silicon carbide (µc-SiC) was prepared at low substrate temperatures using Hot Wire chemical vapor deposition (HWCVD) and Monomethylsilane as process gas. Similar to µc-Si:H high crystalline volume fractions were achieved at high hydrogen dilution and a transition to the growth of amorphous films is observed towards lower dilution. The influence of the hydrogen dilution, filament temperature, deposition pressure and substrate temperature on the microstructure and the electronic properties investigated by Raman spectroscopy, Transmission Electron Microscopy (TEM), X-Ray diffraction, IR spectroscopy, dark- and photo-conductivity, Photothermal Deflection Spectroscopy will be addressed.By adjusting the deposition parameters the dark conductivity can be varied by more than 13 orders of magnitude. High conductivities of 0.1 S/cm are achieved in highly crystalline material without intentional doping and are accompanied by high optical absorption below the band gap, indicating free carrier absorption. We have implemented highly conductive µc-SiC:H as an n-layer into amorphous and microcrystalline silicon n-i-p solar cells. Open circuit voltages of more than 850 mV have been achieved for the amorphous silicon i-layer cells. An increase of the blue response for an n-side illuminated microcrystalline silicon solar cell demonstrates the good transparency of the µc-SiC:H films. Cross-section TEM results on the high conductivity material show a columnar morphology of the crystallites with typical column diameters of ~50 nm. Transmission electron diffraction patterns show that both cubic and hexagonal SiC phases are present in such films. In amorphous films with low sub-gap absorption conductivities < 10E-14 S/cm are obtained. The determination of the crystalline volume fraction, which serves as a very useful parameter for the classification of high quality microcrystalline silicon is very difficult in SiC likely due to the coexistence of different poly-types of SiC in the samples. High spin densities from 5*10E17 cm-3 to 1*10E19 cm-3 are found in the µc-SiC:H films investigated so far but a clear correlation with sub-gap optical absorption is not observed.
5:00 PM - A4.2
Effects of Nitrogen Addition on the Properties of a-SiCN:H Films Using Hexamethyldisilazane.
Amornrat Limmanee 1 , Michio Otsubo 1 , Tsutomu Sugiura 1 , Takehiko Sato 2 1 , Shinsuke Miyajima 1 , Akira Yamada 3 , Makoto Konagai 1
1 Physical Electronics, Tokyo Institute of Technology, Tokyo Japan, 2 Material & Processing Technology Department, Mitsubishi Electric Corporation, Kanagawa Japan, 3 Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, Tokyo Japan
Show AbstractIn our previous work, we have found that hydrogenated amorphous silicon carbon nitride (a-SiCN:H) films by hot wire chemical vapor deposition (HWCVD) using hexamethyldisilazane (HMDS) and H2 can act as an antireflection coating and provide good surface passivation. The efficiency of cast poly-Si solar cell with these a-SiCN:H films as a passivation layers reached 13.75% (2cm x 2cm). The effective reflectivity of cell surface was found to be high, indicating that the optical property of the films was still needed to be optimized. Reducing the refractive index of a-SiCN:H films is thought to be an effective way to lower surface reflectivity leading to an improvement of short circuit current (JSC) and efficiency of the cells. By use of only HMDS and H2, the optical properties of a-SiCN:H films are hard to be adjusted. Therefore, in this work we introduced N2 to our process for the purpose of providing more variation of the optical property of the films. The effects of N2 flow rate on the structural, electrical, optical and interface properties of a-SiCN:H films were examined. We observed slight increase in N content, from 10 to 14%, as N2 flow rate was varied from 0 to 100 sccm. FT-IR results indicated that hydrogen bonding decreased with increasing N2 flow rate. The amount of C-H bond decreased rapidly while the decrease in Si-H bond was relatively slight. The refractive index of a-SiCN:H films at the wavelength of 650 nm decreased from 2.4 to 2.3 when N2 flow rate became 60 sccm. When N2 flow rate increased above 60 sccm the refractive index tended to become lower but there was a sharp drop in the effective lifetime. The drop of the effective lifetime at high nitrogen flow rate coincided with the decrease in the amount of Si-H bond. According to C-V results, the amount of the positive fixed charges in a-SiCN:H films became larger as the N2 flow rate became higher. We prepared cast poly-Si solar cells using a-SiCN:H films with the refractive index of 2.3 in order to verify the effects due to N2. The reflectivity of cell surface was obviously reduced. We found the improvement in JSC and the efficiency of the cells. JSC increased from 31.75 to 33.42 mA /cm2 and the cell efficiency reached 14.16% (2cm x 2cm). It can be concluded that N2 addition had great effects on the optical and interface properties of a-SiCN:H films. We succeeded in adjusting the refractive index of the a-SiCN:H films by introducing N2 to our process. The a-SiCN:H films prepared by HMDS, H2 and N2 can act as a good antireflection coating and provide sufficient surface passivation. The advantage of adding N2 to the process was demonstrated by the improvement in JSC and the efficiency of cast poly-Si solar cells.
5:15 PM - A4.3
Dependence of the Electronic Properties of Hot-Wire CVD Amorphous Silicon-Germanium Alloys on Oxygen Impurity Levels
Shouvik Datta 1 , J. Cohen 1 , Yueqin Xu 2 , A. Mahan 2 , Howard Branz 2
1 Physics, University of Oregon, Eugene, Oregon, United States, 2 , National Renewable Energy Laboratory, Golden, Colorado, United States
Show AbstractWe have found that intentional introduction of up to roughly 1020 cm-3 of oxygen impurities into hydrogenated amorphous silicon-germanium alloy (a-Si0.7Ge0.3:H) films grown by hot-wire chemical vapor deposition (HWCVD) improves the electronic properties of these films, while somewhat higher levels of oxygen become deleterious. We previously used transient photocapacitance spectroscopy to deduce remarkably narrow Urbach tails and a very high level of minority carrier (hole) collection in such HWCVD samples, rivaling those of the best a-Si,Ge:H alloys grown by plasma-enhanced CVD technique. Our samples were produced in a Ta-wire HWCVD growth system in which the oxygen level was varied from about 1017 to 5 x 1020 cm-3 using a controlled air leak. At the same time, this air leak resulted in very little variation in the nitrogen incorporation within the films, which remained at or below 4 x 1016 cm-3. Employing admittance spectroscopy below room temperatures we have also demonstrated that oxygen contamination introduces a modest level of n-type doping. This is observed by the increase of capacitance at temperatures below 200K where the deeper defects cannot respond. The degree of doping increases as the oxygen content increases to about 1020 cm-3, but it appears to saturate above this value. We also observe an increase of deep defect density for alloys that have the highest oxygen content, and this may help account for the observed saturation in effective doping. Transient photocapacitance (TPC) spectra indicated that the samples with moderate oxygen levels exhibited the lowest Urbach energies ever observed for a SiGe:H with 30at.% Ge: below 40meV for 1020 cm-3 of oxygen. By comparing the TPC spectra with transient photocurrent spectra we could determine that the hole collection fractions of these samples in the annealed state improved from about 96 % for a a-Si,Ge:H sample grown without any intentional contamination to nearly 99% in the sample with 1020 cm-3 of oxygen. Drive level capacitance profiling was used to estimate the deep defect densities before and after these samples were degraded at 10 sun intensity (employing a tungsten-halogen light source with a 610nm long pass filter). After 100 hours of light-soaking, we detected almost no light induced changes for the a-Si0.7Ge0.3:H alloy film containing 1020 cm-3 of oxygen. In contrast, the deep defect densities of the alloy samples, with either smaller or higher oxygen content, did increase somewhat after prolonged light soaking. Interestingly, the observed light induced changes increase with the measured Urbach tail energies.
5:30 PM - A4.4
High Quality a-Ge:H Films and Devices Through Enhanced Plasma Chemistry.
Erik Johnson 1 , Pere Roca i Cabarrocas 1
1 LPICM, Ecole Polytechnique, Palaiseau Cedex France
Show AbstractWe present a material and device study on PECVD-grown a-Ge:H showing that device-quality a-Ge:H can be produced without using the conventional techniques of high power or powered electrode substrate placement. We demonstrate the production of material with PDS signatures superior to material produced at ten times higher power density. This is achieved through the use of Ar and H2 dilution and by growing the films at high pressures under conditions where nanoparticles and nanocrystals formed in the gas phase contribute significantly to the growth. Raman scattering, temperature-dependent conductivity, and spectroscopic ellipsometry measurements are used to fully characterize the films resulting from growth in this regime. Additionally, the quality of the material is demonstrated through its application in nip-configuration diodes, where a forward/reverse current ratio of two orders of magnitude and a spectral response at 0.9μm of 0.3 are demonstrated. An AM1.5 efficiency of 1.3% is achieved utilizing an absorber layer thickness of only 80nm.
5:45 PM - A4.5
Dielectric Properties of Ultra Dense (3 g/cm3) Silicon Nitride Deposited by Hot Wire CVD at Industrially Relevant High Deposition Rates
Zomer Silvester Houweling 1 , Vasco Verlaan 1 , Karine van der Werf 1 , Hanno Goldbach 1 , Ruud Schropp 1
1 Faculty of Science, Department of Physics and Astronomy, SID, Physics of Devices , Utrecht University, Utrecht , Utrecht, Netherlands
Show AbstractUltrahigh deposition rates of over 7.3 nm/s (438 nm/min) have been reached for thin film silicon nitride (a-SiNx) with Hot Wire CVD using only SiH4 and NH3. By simultaneously increasing process pressure and SiH4 gas flow at a high filament temperature of 2300 oC, transparent and dense films have recently been achieved at these high rates. For a-SiN1.2 deposited at 3 nm/s, the mass-density reached a very high value of 3.08 g/cm3. Such high densities have thus far never been reached for PECVD even when applied at substrate temperatures higher than 500 oC[1], because PECVD leads to materials that are too H-rich at high N concentration. In our HWCVD process, the substrate temperature was limited to 450 oC by radiation from the wires only. Etch rates in a 16BHF solution confirm the high mass density. The thus found etch rate of 7 nm/min is much better than that for PECVD layers made at a much lower deposition rate[2]. The good passivating properties of these high-density a-SiN1.2 films deposited at high deposition rates of 3 nm/s are proven by a high efficiency of 15.7% on multicrystalline Si solar cells.These a-SiN1.2 films have been analyzed in metal-insulator-semiconductor structures with p- and n-type c-Si wafers for characterization of electrical properties. C-V measurements were performed at a high signal frequency of 1 MHz. From C-V measurements performed on n-type structures we deduced a dielectric constant ε of 7.1 from the capacitance under electron accumulation. For the p-type structures, negative flatband voltages and the formation of an inversion layer indicate the presence of positive fixed charge. We deduced a low positive fixed nitride charge density of 10^16 cm-3 from the flatband voltage and the capacitance under hole accumulation. These C-V results show little hysteresis for the backward sweep and from that we deduced an interface trap density of 10^11 cm-2. I-V measurements showed electrical breakdown fields that exceed 2.8 MV/cm for thick films of 400 nm. The measuring setup reached its limit before breakdown but decreasing the film thickness will yield higher breakdown fields. The rms roughness is smaller than 1 nm, which is necessary for high field-effect mobility in thin-film transistors. The films also possess very low (tensile) stress of 50 MPa, which will be helpful in for instance, plastic electronics. The low H concentration of 9 at.%, specifically the low Si-H bond density, is an advantage for the use as sidewall and liner material in ULSI p-MOS transistors[3]. To conclude: HWCVD provides a-SiNx materials with dielectric properties at least as good as PECVD does, though at a much higher deposition rate. This is mainly due to the fact that higher atomic N/Si ratios can be achieved while the H concentration can be kept low.[1] Dekkers et al, Applied Physics Letters 89 (2006) 13508[2] Masuda, et al, Thin Solid Films 501 (2006) 149. [3] Akasaka, Ext. Abstr. of the 4th Conf. on Hot-Wire CVD Process, Takayama, Jap., 2006.
A5: Poster Session: Alloys
Session Chairs
Virginia Chu
Hsiao Wen Zan
Wednesday AM, April 11, 2007
Salon Level (Marriott)
9:00 PM - A5.1
Low Temperature Deposition of nc-3C-SiC:H films by VHF-PECVD Under High Pressure and High Power Conditions.
Shinsuke Miyajima 1 , Makoto Sawamura 1 , Akira Yamada 2 , Makoto Konagai 1
1 Physical Electronics, Tokyo Institute of Technology, Tokyo Japan, 2 Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, Tokyo Japan
Show AbstractGroup IV nanocrystalline materials have been attracted much attention as materials for silicon based solar cells. Properties of narrow gap materials, such as hydrogenated microcrystalline silicon and silicon germanium films, have been intensively studied by many researchers. However, there are a few researches on wide gap group IV nanocrystalline materials, such as nanocrystalline hydrogenated cubic silicon carbide (nc-3C-SiC:H). In our recent works, we successfully deposited nc-3C-SiC:H films by hot wire chemical vapor deposition (HWCVD) and very high frequency plasma enhanced chemical vapor deposition (VHF-PECVD). VHF-PECVD is widely used for fabrication of thin film silicon based solar cells, thus deposition of nc-3C-SiC:H films by VHF-PECVD is suitable for the solar cell applications. However deposition rate of nc-3C-SiC:H by VHF-PECVD was very low compared with that by HWCVD. In the case of hydrogenated microcrystalline silicon, high deposition rate and low defect density are realized by using high pressure depletion conditions in which deposition pressure and plasma power are higher than that of conventional deposition conditions. In this study, we deposited nc-3C-SiC:H films by VHF-PECVD under high pressure and high power conditions, and investigate optical and electrical properties of the films. nc-3C-SiC:H films were deposited by VHF-PECVD. Monomethylsilane (MMS) and hydrogen (H2) were used as reactant gases. VHF frequency of our system was 60 MHz. Deposition pressure, VHF-power and substrate heater temperature was kept constant at 600 Pa, 175 W and 430 degrees centigrade, respectively. We investigated the influence of the ratio of H2 to MMS (H2/MMS) on film properties. The films were deposited on Corning 7059. Spectroscopic ellipsometry, Raman scattering spectroscopy and conductivity measurements revealed that the films deposited at H2/MMS larger than 167 were nc-3C-SiC:H films. Optical and electrical properties of nc-3C-SiC:H is almost same as that of the films deposited by HWCVD. The deposition rate of the films increased from 0.036 to 0.101 nm/sec with decreasing H2/MMS from 500 to 167. These deposition rates are comparable to that of the films deposited by HWCVD. This results clearly indicates that the high pressure and high power condition is beneficial for the deposition of nc-3C-SiC:H by VHF-PECVD at low temperatures.
9:00 PM - A5.2
Crystalline Silicon Surface Passivation by PECVD Deposited Amorphous Silicon Oxide Films.
Thomas Mueller 1 , Reinhart Job 1 , Wolfgang Duengen 1 , Maximilian Scherff 1 , Wolfgang Fahrner 1
1 Mathematics and Computer Science, University of Hagen, Hagen Germany
Show Abstract9:00 PM - A5.3
Amorphous Silicon Germanium n-i-p Devices Deposited by HWCVD Using a Tantalum Filament Operated at 1800°C.
Harv Mahan 1 , Yueqin Xu 1 , Howard Branz 1 , Jeff Yang 2 , Baojie Yan 2
1 , NREL, Golden, Colorado, United States, 2 , United Solar Ovonics Corporation, Troy, Michigan, United States
Show AbstractWe report the results of incorporating a-SiGe:H alloy films grown by HWCVD into n-i-p solar cell devices. A-SiGe:H alloy films grown by HWCVD were previously found to exhibit remarkably narrow Urbach tails and a high level of minority carrier (hole) collection. In particular, for Ge film contents less than 50 at.%, the Urbach energies were well below 50 mV [1], while for a Ge content of 30 at.%, the hole collection fraction was 75% [2]. The significant improvement in material properties was achieved by changing the filament material from tungsten to tantalum (Ta), and operating the Ta filament at 1800°C. To test this material in devices, a PECVD n-layer and a HWCVD i-layer are deposited at NREL onto United Solar Ovonics (USOC) textured Ag/ZnO back reflectors, and then USOC completes the device structure. Previous results [3] on a small area substrate enabled an initial 0.25 cm2 device efficiency of 7% for a double graded Ge profile, with the highest Ge content near the p-layer to improve hole collection. For the present work, the PECVD and HWCVD chambers have been modified to handle larger deposition areas. This has significantly improved the 0.25 cm2 device yield, and preliminary results have enabled initial device efficiencies of > 9% for a-Si:H and > 7% for an ungraded a-SiGe:H i-layer containing ~ 30 at.% Ge (no Ge profiling). Deposition rates for both i-layers are ~ 4Å/s. Details of the device measurements will be presented for these devices and for new devices which incorporate both single and double Ge profiling. [1] J.D. Cohen, S. Datta, Y. Xu, A.H. Mahan, and H.M. Branz, Proc. 4th Int’l Conference on Hot-Wire CVD (Cat-CVD) Process (October 2006), Thin Solid Films (in press). [2] S. Datta, Y. Xu, A.H. Mahan, H.M. Branz, and J.D. Cohen, J. non-Cryst. Sol. 352 (2006) 1250. [3] A.H. Mahan, Y. Xu, L.M. Gedvilas, R.C. Reedy, D.L. Williamson, S. Datta, J.D. Cohen, B. Yan, and H.M. Branz, Proc. 31st IEEE PVSC (January 2005), pg. 1397.
9:00 PM - A5.4
Effect of Boron Doping on Microcrystalline Germanium Carbon Thin Films
Yasutoshi Yashiki 1 , Seiichi Kouketsu 1 , Shinsuke Miyajima 1 , Akira Yamada 2 , Makoto Konagai 1
1 Department of Physical Electronics, Tokyo Institute of Technology, Tokyo Japan, 2 Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, Tokyo Japan
Show AbstractDoping effect on microcrystalline germanium carbon alloy (μc-Ge1-xCx:H) thin films has been investigated. This new material is one of the candidates of the absorber layer of solar cell because of its high absorption coefficient like a crystal Ge and its bandgap shift up into the optimum solar range by alloying with small amount carbon. We have successfully deposited μc-Ge1-xCx:H using monomethylgermane (MMG) and its properties has been reported elsewhere. However, it is not clear about doping effect and electronic properties of doped films. Therefore, μc-Ge1-xCx:H was doped by boron and its electronic properties were characterized in detail. Films were prepared by hot wire chemical vapor deposition (HWCVD) technique using MMG with hydrogen dilution as a source gas. 1% hydrogen diluted diborane was used as the p-type doping gas. Four rhenium (Re) wires with a diameter of 0.5 mm and a length of 6 cm were employed as hot filaments. The distance between the filaments and the substrate was 5 cm. The substrate temperature and the filament current were 300 deg C and 13A, respectively. MMG flow rate was kept constant at 2 sccm. Total flow rate of hydrogen (H2) and diborane (B2H6) was 40 sccm and B2H6/H2 flow ratio was varied. Films were deposited on Corning 7059 glass and low resistance n-type Si (001) substrate. Film structure and carrier concentration were measured by Raman scattering spectroscopy and Hall measurement. For the measurement of conductivities and activation energies, Al electrodes were evaporated on the top surface of the films in a coplanar configuration. The Raman scattering spectroscopy revealed that crystalline volume fraction of B-doped μc-Ge1-xCx:H films decreased with increase of B2H6 flow rate. This behavior is very similar to that for B-doped μc-Si:H by B2H6 dilution. The conductivity of the films changed from 7.5 x 10-3 to 1.3 S/cm with B2H6/MMG ratio from 0 to 0.1. The carrier concentration of 1.7 x 1020 cm-3 was achieved with B2H6/MMG ratio 0.1. The activation energy decreased from 0.37 to 0.037 eV. We also fabricated p-type μc-Ge1-xCx:H/n-type c-Si heterojunction diodes. The diodes showed rectifier characteristics. Typical ideality diode factor and rectifier ratio 3.7 x 103 at ±0.5 V. These results clearly indicate that p-type μc-Ge1-xCx:H films were successfully prepared by HWCVD. In summary, we deposited boron doped p-type μc-Ge1-xCx thin films by HWCVD technique using MMG and B2H6. The conductivity of 1.3 S/cm and carrier concentration of 1.7 x 1020 cm-3 were achieved. We have shown that boron doped μc-Ge1-xCx:H is one of the promising candidates for doped layer of thin film solar cell.
9:00 PM - A5.5
Characterization of Silicon Carbide Thin Films Obtained Via Sublimation of a Solid Polymer Source Using Polymer-Source CVD Process
El Hassane Oulachgar 1 , Cetin Aktik 1 , Starr Dostie 2 , Subhash Gujrathi 3 , Mihai Scarlete 2
1 Nanofabrication and Nanocharacterization Research Center (CRN2), Electrical & Computer Engineering Department, Sherbrooke University, Sherbrooke, Quebec, Canada, 2 Chemistry Department, Bishop's University, Lennoxville, Quebec, Canada, 3 Thin Film Physics and Technology Research Center (GCM), Physics Department, Montreal University, Montreal, Quebec, Canada
Show AbstractSilicon carbide thin films have been deposited via sublimation of a solid organosilane polymer source using atmospheric pressure chemical vapour deposition process (PSCVD). The advantages of this new process include high deposition rate, compatibility with batch process, hazard-free working environment and low deposition cost. The silicon carbide (SiC) thin films obtained through this process exhibit a highly uniform film thickness, highly conformal coating, and very high chemical resistance to acids and alkalis solutions. These proven characteristics make the SiC thin films obtained by PSCVD process very attractive as a structural material for micro-electro-mechanical systems (MEMS) and as a coating film in a wide range of other applications. These SiC thin films are also expected to be attractive as a semiconductor material provided that the defects and oxygen contamination can be reduced and efficiently controlled. In this work we have investigated the chemical, structural, electrical and optical properties of these films, using elastic recoil detection (ERD), Fourier transform infrared (FTIR) spectroscopy, photospectroscopy, ellipsometry, and capacitance-voltage measurements. The electrical and optical properties of these silicon carbide thin films were correlated with their chemical and structural composition.
9:00 PM - A5.6
SiCOI Structure Fabricated by Hot-mesh Chemical Vapor Deposition
Kanji Yasui 1 , Hitoshi Miura 1 , Yuichirou Kuroki 1 , Masasuke Takata 1 , Tadashi Akahane 1
1 Electrical, Electronic and Information, Nagaoka University of Technology, Nagaoka Japan
Show AbstractFabrication of SiC on insulator (SiCOI) structures has been investigated for use in sensors and micro electromechanical systems (MEMS) applications operating at physically and chemically harsh environments, because of its mechanical strength and chemical inertness[1-3]. For the fabrication of the SiCOI structures, the epitaxial growth of SiC on SOI substrates with thin top Si layer can be employed. The high temperature processes required for SiC growth, however, degrade the thin top-Si layer of SOI substrates owing to thermal instability of the top-Si layer [4, 5]. In a previous study by us, 3C-SiC epitaxial films were successfully grown on Si substrates at 750C using a hot-wire chemical vapor deposition (CVD) method, which utilizes hot-tungsten wires arranged in a mesh as a catalyzer and an organosilicon compound such as monomethylsilane and hydrogen as source gases [6]. As a result of the catalytic reaction on the hot-tungsten mesh surface, high-density hydrogen radicals could be generated and desorption of the hydrogen atoms from the source molecules on the growing film surface could be induced. Thus hot-mesh CVD is considered to be an effective technique for achieving low-temperature growth of SiC on SOI substrates. In this paper, the results of growing 3C-SiC on SOI substrates by hot-mesh CVD are reported. The SiC films were grown on SOI substrates which had a 100-nm-thick top-Si layer and a 200-nm-thick buried oxide layer. The SiC films were grown using a mesh temperature of 1200-2000C and a substrate temperature of 700-1000C. The SiC films were epitaxially grown on the top-Si layer at substrate temperatures above 750C. While SiC growth at substrate temperatures above 800C induced the formation of voids in the top-Si layer, growth at 750C did not. For applications of piezoresistive sensors, gage factor (GF) was evaluated using a bridge circuit. From the variation of the resistivity with tensile stress applied to the SiC layer grown at 750C, GF was estimated to be –27. This value is approximately the same as that (GF=-31.8) a SiC epitaxial film on Si(100) grown at 1360C using atmosphere pressure CVD[9]. Some MEMS structures were also fabricated using a reactive ion etching and a wet etching.Reference[1] F. Letertre, et. al., Mater. Sci. Forum, 433-436 (2003) 813.[2] L. Di. Cioccio, et. al, Mater. Cs. & Eng., B46 (1997) 349.[3] M. Mehregany, et. al, Proc. IEEE, 86, No-8 (1998) 1594. [4] Y. Ono, et.al., Jpn. J. Appl. Phys. 34 (1995) 1728-1735.[5] B. Legrand, et. al., Appl. Phys. Lett. 76, No.22 (2000) 3271-3273.[6] K. Yasui et. al., Jpn. J. Appl. Phys., 44, No. 3 (2005) 1361-1364.[7] Y. Narita, et. al., Jpn. J. Appl. Phys., Part 2, 44, No.25 (2005) L809 - L811.[8] T. Fuyuki, et. al., phys. stat. sol. (b) 202 (1997) 359-378.[9] J. S. Shor, et. al., IEEE Trans. Electron Devices, 40, No.6 (1993) 1093.
9:00 PM - A5.7
A Study of a-SiC:H Films Deposited by Remote PECVD System using HMDS Precursor with C2H2 Dilution Gas.
Sung Hyuk Cho 1 , Doo Jin Choi 1 , Tae Song Kim 2
1 Department of Ceramic Engineering, Yonsei University , Seoul, Seoul, Korea (the Republic of), 2 , Korea Institute of Science and Technology, Seoul, Seoul, Korea (the Republic of)
Show AbstractSilicon carbide has been a very attractive material as a candidate for replacing silicon in micro-Electromechanical systems(MEMS) applications for its mechanical strength, chemical inertness, wide bandgap and other superior properties. Among many deposition techniques, deposition of silicon carbide by plasma enhanced chemical vapor deposition (PECVD) system has been researched for many years because the PECVD method can reduce the deposition temperature. In general, silicon carbide thin film deposited by PECVD at low temperature shows amorphous structures and hydrogenated properties between organic and inorganic polymer since source gases are decomposed into complex mixtures of monomers under plasma and this mixtures of monomers react on the substrate at low temperature. In this study, we deposited a-SiC:H films on (100) silicon wafer by remote PECVD system in the temperature range of 250 °C ~ 450 °C. Hexamethyldisilane (HMDS) and H2 gas were used as a precursor and a carrier gas, respectively. C2H2 dilution gas was also used in order to increase carbon contents in the film. The plasma power varied from 200 to 400W. The stoichiometric and bonding properties of deposited films were investigated by the FTIR spectrometer and the XPS. The thickness of deposited films was measured by ellipsometer. The hardness of deposited films with various deposition condition was measured by nano-indentor. The growth rate of SiC:H films decreased with the increase of deposition temperature from 250 °C to 400 °C, however, increased again at 450 °C deposition. The growth rate of film increased with the plasma power for all deposition conditions. It is showed that the carbon contents in the film deposited with C2H2 diluent gas were more than 30% for all deposition conditions. As deposition temperature increased, the sp3/sp2 ratio increased, which affected the growth behavior and properties of the films. Higher activation energy and lower potential energy of sp3 reaction make sp3 reaction occur dominantly consuming more energy as deposition temperature increase. This causes thickness decrease with the increase of deposition temperature. The hardness of deposited film changed with increase of carbon ratio and sp3 bonding ratio in the film.
9:00 PM - A5.8
Low Temperature High Quality Growth of Silicon-Dioxide Using Oxygenation of Hydrogenation-Assisted Nano-Structured Silicon Thin Films
Nima Rouhi 1 , Behzad Esfandyarpour 1 , Shams Mohajerzadeh 1 , Bahman Hekmatshoar 2 , Michael Robertson 3
1 School of ECE, University of Tehran, Thin Film Lab., Nanoelectronics center of excellence, Tehran Iran (the Islamic Republic of), 2 Electrical engineering, Princeton University, Boston, Massachusetts, United States, 3 Physics, Acadia University, Wolfville, Nova Scotia, Canada
Show Abstract There have been many attempts to develop a high quality low temperature oxidation process due the high demand in inter-level dielectrics, gate dielectrics in MOSFETs and thin film transistors. In this paper we develop a low temperature high quality oxide growth of nano-structured silicon thin films obtained through a hydrogenation-assisted PECVD technique followed by a plasma enhanced oxidation process. The processed layers were investigated and compared with respect to their physical, optical and stoichiometric properties by means of TEM, electron diffraction, ellipsometry, Rutherford backscattering (RBS), Raman spectroscopy and FTIR spectroscopy. Also the electrical characteristics of the layers have been examined using a current-voltage and capacitance-voltage measurement on MOS structures. A 100nm-thick layer of amorphous silicon was deposited on RCA-cleaned Si(100) substrates using an e-beam evaporation and at a temperature of 350°C. Subsequently a hydrogenation-assisted DC PECVD technique was used to obtain a nano-structured silicon film. This hydrogenated step was carried out at a plasma power of 2W/cm2, a temperature of 250°C and with a hydrogen gas flow of 20sccm, followed by a post treatment at a temperature of 300°C for 30 min. with the plasma “off”. The crystallinity of the samples were investigated by TEM and electron diffraction, exhibiting a Si nanostructure with an average grain size of 2-4nm. The presence of silicon-hydrogen bonds was investigated using FTIR analysis before and after the post treatment process, confirming the evolution of O-Si-O bonds. After hydrogenation, the samples were placed in a standard RF-PECVD system and heated up to 350°C to perform the plasma oxygenation step. An RF power of 0.4W/cm2 and an oxygen pressure of 150mtorr were used for this step, taking an extended period of two hrs to ensure that the growth reaches its saturation and optimal electrical properties are obtained. The thickness of the oxide layer, measured using a stylus profilometer was 30-50nm, depending on the growth conditions and further confirmed using an RBS analysis. The grown oxides were used to fabricate metal-oxide-semiconductor structures by depositing and patterning a 100nm-thick Al layer. The tunneling current and capacitance characteristics of samples were studied by I-V and C-V measurements showing a leakage current less than 10nA/cm2, a flat-band voltage of -0.98V and a relative permittivity of 4.1. The oxide interface and stoichiometric properties were investigated by a TEM apparatus showing the SiO(2-0.05) structure for silicon dioxide. The Raman spectroscopy showed a hump corresponding to the SiO2 on Si-substrate. Also ellipsometry is being used to investigate the optical constants of silicon dioxide thin films. Since all the processing temperature for the oxide layer is below 350°C, regular glasses can be used as the substrate. Realization of thin film transistors on such substrates is being pursued.
9:00 PM - A5.9
Influence of Prepartion Conditions on the Stressing Behavior of Plasma Deposited Silicon Dioxide Films.
Vikram Dalal 1 , Vishwas Jaju 1
1 Elec. and Computer Engr., Iowa State University, Ames, Iowa, United States
Show AbstractIn this paper we report on the breakdown strength and stability under stress of an n-channel MOSFET fabricated using electron cyclotron resonance (ECR) plasma grown gate silicon oxide. Gate oxide films (~ 100 Å) were grown by direct oxidation of silicon wafer using O2/He plasma at a temperature of 450 C in an ECR reactor. MOSFET and MOS devices were fabricated to evaluate the electrical properties. Si-SiO2 interface defect density was found to be ~ 1-2 X 1011 cm-2 eV-1 and breakdown strength was in the 7-12 MV/cm regime. The reliability of ECR grown gate oxide under electrical stress was measured and it was compared with thermal oxide grown at temperature of 950 C in dry oxygen. We found that the as-grown ECR oxide showed a poorer stressing (lower mobility, changes in threshold voltage) results by approximately 2 orders of magnitude compared to thermal oxide, but after annealing at higher temperatures ~ 500 C, the channel degradation properties under stress became comparable to the thermal oxide. Investigations to address the reasons for poorer channel behavior under stress include possible plasma damage, excess H bonding at the interface and electron trapping at excessive traps within the oxide. The stress results will be compared to these potential problems and solutions to solving this problem will be identified.
A6: Poster Session: Crystallization Techniques and Epitaxy
Session Chairs
Virginia Chu
Hsiao Wen Zan
Wednesday AM, April 11, 2007
Salon Level (Marriott)
9:00 PM - A6.1
A Novel Bonding Technique Using Metal-Induced Crystallization of Amorphous Silicon.
Markus Ong 1 , Reinhold Dauskardt 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States
Show AbstractMetal induced crystallization (MIC) of amorphous silicon can occur at temperatures below 200 C. In the present study we exploit this low temperature reaction to create a novel bonding mechanism between two silicon substrates. Aluminum induced crystallization of amorphous silicon was selected due to the low temperature for the crystallization reaction (< 170 C) and the established use of both amorphous silicon and aluminum in CMOS device processing. The intent is to develop a strong bond at low temperature that may be used in advanced 3-D device structures that is fully compatible with existing device processing. Thin-film interconnect structures containing Cu and low-k dielectric films on silicon wafers were selected as test structures for the study. These structures had well characterized adhesive and cohesive properties. Controlled combinations of amorphous silicon and aluminum films were deposited onto the top of the stack structures. The film thicknesses and order was selected to improve the MIC reaction to form a strong bond containing polycrystalline silicon. Similar films were deposited onto blank silicon wafers. The wafers were bonded together under controlled temperature and pressure. Interface fracture experiments were conducted to characterize the adhesion of the resulting bond and its dependence on the crystallization temperature and reaction time. The technique was successfully used to bond the silicon substrates and the dependence on bonding parameters and MIC reaction kinetics is discussed. Additionally, it was found that bonding at lower temperatures could be achieved with longer holding times. Successful low-temperature bonding could be an important tool in the quest to fabricate three-dimensional structures in microelectronic devices.
9:00 PM - A6.10
High Aspect Ratio Nanostructures by Excimer Laser Crystallisation of Thin PECVD Silicon Films.
Saydulla Persheyev 1 , Mohammed Shaikh 1 , Kevin ONeill 1 , Yongchang Fan 1 , Charlie Main 1 , Mervyn Rose 1
1 Electronics Engineering and Physics, University of Dundee, Dundee United Kingdom
Show AbstractThe excimer laser crystallisation of amorphous silicon films for fast growing applications such as thin film transistors, solar cell and field emission is one of the controllable and wide spread methods. Search for robust, simple and clean technologies is essential and it is becoming one of the trends of modern electronic industry.This paper deals with a new high aspect ratio silicon structures that have been achieved by excimer laser processing of thin 100nm amorphous silicon films on chromium and molybdenum backplane metals. In this method amorphous silicon film was deposited by conventional PECVD process using silane gas as a precursor on backplane metals with 100nm thickness deposited by DC reactive ion sputtering on glass substrates. Hydrogen content in our silicon films was kept constant with the value of 10 at.%. By varying excimer laser beam energy, scan and repetition rate authors demonstrate that different aspect ratio nanocrystalline structures will be grown. At laser beam energies around 200mJ/cm2 and repetition rate 100 Hz the highest aspect ratio structures are obtained.
9:00 PM - A6.11
Co-deposition of Silicon Nanoparticles into Amorphous Silicon Films for Seed-nucleated Recrystallization
C. Anderson 1 , C. Blackwell 2 , J. Kakalios 2 , U. Kortshagen 1
1 Department of Mechanical Engineering, University of Minnesota, Minneapolis, Minnesota, United States, 2 School of Physics and Astronomy, University of Minnesota, Minneapolis, Minnesota, United States
Show AbstractVarious forms of amorphous silicon films with embedded nanocrystallites (a/nc-Si:H) have been extensively studied over the past ten years. Improved conductivity and greater stability to light-soaking have been the main motivations for such research. Protocrystalline, polymorphous, and even microcrystalline films can be generally classified as forms of a/nc-Si:H, due to the common presence of nanocrystals in an amorphous matrix. A typical approach for the deposition of these films involves a single capacitively-coupled plasma reactor operating with hydrogen-diluted SiH4 under temperatures from around 250°C or greater. Hydrogen dilution, total pressure, discharge power and system temperature gradients are all thought to play a crucial role in the microstructure of the film. Consequently, the control of the film structure is not easily achieved, wherein a new approach to a/nc-Si:H can be imagined. In this study, we investigate the role of silicon nanocrystallites in a/nc-Si:H films as recrystallization seeds for the amorphous phase. The production of the amorphous and crystalline phases of the film have been decoupled into separate plasma processes. An aerosol suspension of crystalline silicon nanoparticles is produced in a flow-through plasma reactor, and is then fed into a parallel-plate discharge chamber where the nanocrystals are “co-deposited” in a growing amorphous silicon film. We show that one can control the crystalline content of the film in a completely unambiguous way by varying the production rate of crystalline nanoparticles from the first reactor, in addition to varying the deposition rate of the amorphous film in the second reactor. Raman spectra of post-deposition annealed films reveals that recrystallization of the initial amorphous fraction can proceed at 600°C without a substantial incubation period. In contrast, purely amorphous films grown under the same conditions require several hours at 600°C before the onset of crystallization. The effects of nanocrystallite diameter and density variations in the film will also be presented. This work was partially supported by NSF grants NER-DMI-0403887, IGERT grant DGE-0114372, and the University of Minnesota.
9:00 PM - A6.12
Epitaxy at 100 nm/min by Hot-Wire Chemical Vapor Deposition onto Silicon Wafers at 500 to 700°C.
Charles Teplin 1 , Qi Wang 1 , Howard Branz 1 , Kim Jones 1 , Paul Stradins 1
1 , NREL, Golden, Colorado, United States
Show AbstractWe find that increasing the substrate temperature above 600°C during hot-wire chemical vapor deposition dramatically improves silicon epitaxy and growth rates (>100 nm/min) compared with lower-T growth. With a tantalum hot-wire operating at 11.5 A (~1900°C), phase-pure epitaxy is observed at 77 nm/min on (100)-oriented wafers at 650°C. With a tungsten hot-wire operating at 16 A (~2100 °C) phase-pure epitaxy is faster than 100 nm/min from 620 to 700°C. At these temperatures, epitaxy does not appear to be thickness-limited; successful growth of 11 µm epitaxial layers at 110 nm/min is confirmed by transmission electron microscopy, x-ray diffraction and in-situ ellipsometry. Films grown at these temperatures and rates could be suitable for photovoltaics made by low-cost, high-quality silicon epitaxy on c-Si seeds fabricated on low-cost substrate such as borosilicate glass. For films grown near 650°C, transmission electron microscopy studies reveal that dislocations originate at the substrate interface, suggesting that improved surface preparation before growth could decrease the defect density. Surprisingly, between 450 and 600°C, there appears to be a region where epitaxy is poor – even in comparison with epitaxy grown at 200 to 400°C. We suggest that thermal dehydrogenation of the growing surface is key for high quality and fast epitaxy. The electronic quality of these films, as well as the influence of gas depletion chemistry, is currently is under study and will also be reported.
9:00 PM - A6.13
ESR Study of Crystallization of Hydrogenated Amorphous Silicon Thin Films.
Tining Su 1 , P. Taylor 1 , Pauls Stradins 2 , Yueqin Xu 2 , Falah Hasoon 2 , Qi Wang 2
1 , Colorado School of Mines, Golden, Colorado, United States, 2 , National Renewable Energy Laboratory, Golden, Colorado, United States
Show AbstractSolid-phase crystallization and the subsequent re-hydrogenation of the amorphous silicon thin films provides a low cost approach for thin-film crystalline Si:H-based photovoltaic devices. During the hydrogen effusion, significant lattice reconstruction occurs, as hydrogen is driven out of the film, accompanied by creation and migration of a large number of dangling bonds. We used electron-spin-resonance (ESR) to study evolution of the local order surrounding these dangling bonds during crystallization. When samples made by both plasma enhanced chemical vapor deposition (PECVD) and the and hot wire CVD (HWCVD) are heated to 560oC, hydrogen effuses within 30 min, giving rise to H-effused defect densities of about 5x1018 cm-3. Further heating at 560oC results in crystallization in the HWCVD sample after about 200 min. On the other hand, PECVD samples crystallize only when heated up to 580oC, and then only after much longer times (~ 1300 min) [1,2]. ESR defects in both samples persist at the 5x1018 cm-3 level as long as the sample remains amorphous during the grain nucleation period. As the crystallites appear, the defect densities gradually decrease and saturate at about 3x1017 cm-3 as the crystallization is completed, both in HWCVD and PECVD samples.In the H-effused states before crystallization, the ESR signals for both the HWCVD and PECVD samples show significant exchange-narrowing, suggesting that the defects are probably clustered. As the sample crystallizes, the defect clustering largely disappears, yet the line-widths in fully crystallized films are somewhat narrower than those in typical micro-crystalline silicon thin films as reported earlier [3]. This difference is probably due the specific structures of the grain boundaries in the present study. The effect of re-hydrogenation on both the H-effused amorphous and crystallized states will be discussed. References[1]P. Stradins, D. Young, Y, Yan, E. Iwaniczko, Y. Xu, R. Reedy, H. M. Branz, and Q. Wang; Appl. Phys. Lett. 89, 121921, (2006).[2]D. L. Young, P. Stradins, Y. Xu, L. Gedvilas, R. Reedy, A. H. Mahan, H. M. Branz, Q. Wang, and D. L. Williamson, Appl. Phys. Lett, 89, 161910 (2006).[3]M. M. de Lima, Jr, P. C. Taylor, S. Morrison, A. LeGeune, and F. C. Marques, Phys. Rev. B 65, 235324-1 (2002). (and references therein)
9:00 PM - A6.14
Growth of Epitaxial Si Layers on a Poly-Si Seed Film by Hot Wire CVD for Low Temperature Poly-Si TFTs.
Seung Ryul Lee 1 , Kyung Min Ahn 1 , Kye Ung Lee 1 , Byung Tae Ahn 1
1 Materials Science & Engineering, Korea Advanced Institute of Science & Technology, Daejeon Korea (the Republic of)
Show Abstract There has been a increasing interest in low temperature polycrystalline silicon (poly-Si) thin films for thin-film transistors (TFTs), which are used in display electronics such as active matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting displays (AMOLEDs). Generally, poly-Si thin films are fabricated by the solid phase crystallization (SPC) of amorphous Si (a-Si) thin films due to larger grains and better crystal quality compared to those of directly deposited poly-Si thin films. Unfortunately, the SPC process requires tens of hours to crystallize a-Si films even at 600oC, which is too high temperature for large area glass substrates. Therefore, many methods such as metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), metal-induced crystallization through a cap (MICC), and vapor-induced crystallization (VIC) have been employed to enhance the crystallization of a-Si films. However, poly-Si films fabricated by these methods utilizing the reaction between metals and a-Si films inherently contains a high density of metal impurities and surface defects, resulting in deteriorating the electrical properties of the low temperature poly-Si TFTs. In this paper, we propose a new approach to fabricate the high quality poly-Si films by a two-step process with the process temperature below 500oC : the first step is the preparation of the poly-Si seed films at 480oC by vapor induced crystallization, and the second step is the growth of the epitaxial Si layer at 450oC by hot wire CVD on the VIC poly-Si seed films. The crystal structure, crystallinity, and surface morphology of the poly-Si films fabricated by this approach were investigated in order to estimate the structural character and the quality. From this approach, it is confirmed that the grain size of the poly-Si films was enlarged and the metal contaminations such as Al and Ni at the film surface were sharply lowered.
9:00 PM - A6.15
Novel Crystallization Method on the Highly Ordered Porous Anodic Alumina for High Uniformity Top Gate Polycrystalline Si Thin Film Transistors.
Jong-Yeon Kim 1 , Jin-Woo Han 1 , Young-Hwan Kim 1 , Byung-Yong Kim 1 , Dong-Hun Kang 1 , Dae-Shik Seo 1
1 electrical and electronic engineering, Yonsei university, Seoul Korea (the Republic of)
Show AbstractIn recent years, formation of highly ordered nanostructures has extensively studied due to a wide variety of applications in different fields such as in electronic, photonic devices, etc. In particular, nanoporous alumina has attracted considerable interest more recently built on original explorations a decade earlier. The nanopores in the anodic alumina formed under carefully controlled condition can self-arranged into highly ordered arrays, be uniform in diameter and in spacing and oriented normal to the plane. Their unique structural and electronic properties have great potential for use in novel crystallization for decently uniform polycrystalline Si thin film transistors (poly-Si TFTs). In the conventional crystallization method, the poly-Si TFTs show poor device-to-device uniformity because of the random location of the grain boundaries. However, our new crystallization method introduced in this paper employed substrate-embedded seeds on the highly ordered anodic alumina template to control both the location of seeds and the number of grain boundaries intentionally. In the process of excimer laser crystallization (ELC), a-Si film deposited on the anodic alumina by low pressure chemical vapor deposition (LPCVD) is transformed into fine poly-Si grains by explosive crystallization (XC) prior to primary melting. At the higher energy density, the film is nearly completely melted and laterally grown by super lateral growth (SLG) from remained small part of the fine poly-Si grains as seeds at the Si/anodic alumina interface. Resultant grain boundaries have almost linear functions of the number of seeds in concavities of anodic alumina which have a constant spacing. It reveals the uniformity of device can be enhanced prominently by controlling location and size of pores which contains fine poly-Si seeds under artificial anodizing condition. This kind of crystallization method can be applied to both top gate TFTs and bottom gate TFTs. However, it could be expected that poor interface between gate dielectric and anodic alumina and crystallization efficiency degrade performance of device in the bottom gate TFTs. In general, Top gate is preferred to employ due to eminent efficiency and expedient fabrication process in excimer laser-induced crystallization of thin Si films. Therefore, we also combined our anodic alumina template for embedded seeds with the top gate TFTs. Under further optimized anodizing condition, high yield was achieved, allowing for better device-to-device uniformity and offering simple method for fabrication of seed-template without any exposure mask or resist. This novel structure can be expected to have favorable applications and promising utilities in various high end devices.
9:00 PM - A6.16
Epitaxial Thickening of Large-Grain Poly-Crystalline Silicon Seed Layers on Glass by Hot-Wire Chemical Vapor Deposition
Charles Teplin 1 , Kim Jones 1 , Manuel Romero 1 , Paul Stradins 1 , Howard Branz 1 , Stefan Gall 2
1 , NREL, Golden, Colorado, United States, 2 , Hah-Meitner-Institue, Berlin Germany
Show AbstractWe thickened large-grain polycrystalline Si seed layers on borosilicate glass using hot-wire chemical vapor deposition. The seed layers were formed by Al-induced crystallization of amorphous silicon and have weakly (100) textured grains with typical areas between 3-45 µm2. The 200-nm-thick seed was polished and its oxide coating removed before deposition. The layer was epitaxially thickened at ~100 nm/min using hot-wire chemical vapor deposition from pure silane near 650°C. At this temperature, the glass softened but maintained its structural integrity. Successful epitaxy on all grain orientations was confirmed using X-ray diffraction, electron backscatter diffraction (EBSD) and transmission electron microscopy. EBSD measurements, in particular, showed identical grain sizes and intra-grain defect structures both before and after thickening. TEM revealed that existing intra-grain defects were propagated into the epitaxial layer, but that few new defects were introduced by thickening. Additionally, we did not observe different growth rates on different grain orientations. The thickening of large-grained silicon seeds could result in low-cost thick Si films with electrical properties superior to that of the small-grained nanocrystalline and polycrystalline Si materials currently used in photovoltaic applications.
9:00 PM - A6.17
Grain Size Control by Means of Solid Phase Crystallization of Amorphous Silicon.
Jordi Farjas 1 , Pere Roura 1 , Pere Roca i Cabarrocas 2
1 Physics, University of Girona, Girona, Girona, Spain, 2 LPICM (UMR 7647 CNRS) , Ecole Polytechnique, Palaiseau France
Show AbstractSolid phase crystallization (SPC) of a-Si:H thin films results in better transport properties (mobility and conductivity) as well as in higher stability against light induced degradation. For this reason many studies have been devoted to the optimization of a-Si:H deposition parameters as well as the annealing conditions in view of controlling the crystallized grain size. The aim is to obtain a microstructure with larger grains. In this communication we will report on theoretical and experimental studies which set the limits for the grain size achievable by thermal treatments. In addition to single isothermal annealings, the possibilities offered by non-isothermal and more complex thermal histories are explored. To this aim, an original and powerful numerical method has been developed to predict the crystallization kinetics as well as the final microstructure. The predictions are, then, tested by calorimetric experiments and microscopy. It will be shown that a substantial increase in the grain size is obtained when the usual isothermal step at low temperature (<600○C) is done after a pre-treatment which controls the density of nuclei. Complementary improvements can be reached when the isotherm is reached at a low heating rate because the relaxation processes occurring during this heating ramp homogenize the a-Si nanostructure and, consequently, reduces the nucleation rate.
9:00 PM - A6.18
Solid Phase Epitaxial Regrowth of Amorphous Silicon Layers through Microwave Heating.
D. Thompson 1 , J. Decker 1 , T. Alford 1 , J. Mayer 1 , N. Theodore 2
1 School of Materials, Arizona State University, Tempe, Arizona, United States, 2 Wireless & Packaging Systems Lab., Freescale Semiconductor Inc., Tempe, Arizona, United States
Show AbstractMicrowave heating is used to activate solid phase epitaxial growth of amorphous silicon layers on single crystal silicon substrates. Top layers of single crystal silicon samples were made amorphous through ion implantation with varying doses of boron or arsenic. Microwave processing occurred inside a 2.45 GHz, 1300 W cavity applicator microwave system for time-durations of 2 - 120 minutes. Sample temperatures were monitored using optical pyrometery. Rutherford backscattering spectrometry in a channeled orientation, and cross-sectional transmission electron microscopy were used to monitor crystalline quality in as-implanted and annealed samples. Rutherford backscattering spectra of channeled samples demonstrate that boron implanted samples regrow single crystal silicon with microwave heating only. Microwave co-heating through the use of silicon carbide microwave susceptors was done to initiate solid phase epitaxial regrowth of arsenic implanted samples. Dopant activation was monitored using four point probe testing. Sheet resistance calculations show dopant activation occurring in both boron and arsenic implanted samples. In samples with large doses of arsenic, precipitates and/or micro clusters are seen in transmission electron micrographs. Materials properties are used to explain microwave heating of silicon and demonstrate that the damage created in the implantation process serves to enhance microwave absorption.
9:00 PM - A6.19
Electrical Characterization of Low Temperature Epitaxial Silicon Thin Films.
Mahdi Farrokh Baroughi 1 , Hassan El-Gohary 1 , Siva Sivoththaman 1
1 ECE, University of Waterloo, Waterloo, Ontario, Canada
Show AbstractLow temperature (LT) epitaxial Si thin films obtained by PECVD technique on c-Si substrates, so called “quasi-epitaxial” Si (qEpi-Si) films, have been reported recently. Previous studies were limited to the development of thin intrinsic epitaxial Si films and the material characterization was mainly limited to the structural studies using transmission electron microscopy. Therefore, the electrical properties of the material are still unknown and parameters like electrical conductivity, free carrier mobility, and doping efficiency yet to be thoroughly studied. However, electrical characterization of qEpi-Si thin films is challenging because the underlying substrate significantly disturbs the measurement signal. This work presents a comprehensive study of electrical characterization of qEpi-Si thin films. We used UV Raman, conductivity and Hall measurement, and secondary ion mass spectroscopy (SIMS) analysis for characterization of the qEpi-Si films.qEpi-Si thin films of 100 nm thickness were grown by PECVD technique on high resistivity FZ c-Si substrates using the following process conditions: RF power = 60W, pressure =400 mT, temperature = 280oC, and SiH4 flow = 25 sccm, H2 flow = 275 sccm, and PH3 flow= 0.1 sccm. The phosphorous doping ensures that the film is electrically isolated from the underlying substrate. UV Raman analysis at 328 nm, used for characterizing the crystallinity of the film, penetrates less than 10 nm inside the qEpi-Si thin film. This ensures that the reflected signal only originates from the qEpi-Si film. Comparison of the peaks of the Raman shifts of the qEpi-Si film and a c-Si reference wafer at 521 cm-1 revealed that the qEpi-Si film is highly crystalline. Therefore, Raman analysis predicted high conductivity and mobility values. Conductivity of the qEpi-Si film was measured using direct electrical probing and contact-less sheet resistance measurement techniques and values in the range of 680 – 800 ohm-1cm-1 were obtained. Such conductivity values are much higher than any extrinsic LT Si thin film and are comparable to the conductivity of high temperature (n+) c-Si emitters obtained by high temperature diffusion. In addition to the conductivity measurement we conducted Hall measurement to extract free carrier concentration and mobility. Using Hall measurement the free carrier concentration in the range of 7x1019 – 9x1019 cm-3 and an approximate electron mobility of 57 cm2/v/sec was obtained. Considering the phosphorous concentration of 2.05x1020 cm-3, obtained from SIMS analysis, and taking the degeneracy of the film into account a near unity doping efficiency is obtained.The Raman analysis, the conductivity and Hall measurements all confirm that the quality of the qEpi-Si thin film in terms of the conductivity and the electron mobility is comparable to the parameters of single c-Si material of the same doping level. Furthermore, we observed a near-unity doping efficiency in the qEpi-Si thin films developed at LT.
9:00 PM - A6.2
The Electrical Properties of Unidirectional Metal-Induced Lateral Crystallization Poly-Si TFTs.
Nam-Kyu Song 1 , Young-Su Kim 1 , Min-Sun Kim 1 , Shin-Hee Han 1 , Seung-Ki Joo 1
1 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Show AbstractPolycrystalline silicon (poly-Si) Thin Film Transistors (TFTs) is necessary for Active Matrix Liquid Crystal Display and Organic Light Emitting Diode. Solid Phase Crystallization is the most widely employed method but the crystallization temperature is too high (around 600°C) for commercial glass substrates. Excimer Laser Annealing (ELA) methods were developed in order to achieve high performance of TFTs. ELA methods, however, contain critical problems for industrialization, such as non-uniform crystallinity due to the inevitable scan overlap and surface roughness caused by the liquid-solid phase transformation, that are yet to be solved. It was reported that a thin layer of Ni or Pd deposited and patterned on a-Si thin films induce lateral crystallization at a temperature as low as 550°C. This phenomenon is called Metal-Induced Lateral Crystallization (MILC). In the case of Pd-MILC, it is not applicable to the fabrication of TFTs because of the many micro-twin defects in poly-Si. However, In the case of Ni-MILC, it is known that formed Ni silicides, for which the lattice mismatch is only 0.4 % with Si, act as catalyst for c-Si and then, the lateral growth of poly-Si with good quality occurs. Ni-MILC process enables crystallization of a-Si thin films with less micro-defects, such as Ni silicides and micro-twins, and therefore, most studies have focused on Ni MILC due to the good electrical properties of Ni-MILC TFTs. However, the relatively high leakage current and low electron mobility are regarded as problems for employing this technology and much research related to overcome the problems in MILC TFTs has been undertaken. The general consensus is that the MILC/MILC Boundary (MMB) formed at the center of the channel is responsible for these problems.It has been known that adjacent Pd enhances the crystallization rate in Ni-MILC without additional energy. In this work, we have verified this phenomenon and proposed a noble process to enhance the growth rate of Ni-MILC without any degradation of TFTs. Moreover, we have fabricated the unidirectional MILC TFTs using a noble structure, which eliminates the MMB formed at the center of TFT channel in a normal MILC TFTs. The electrical properties of unidirectional MILC TFTs improved considerably comparing to those of MILC TFTs containing the MMB. The leakage current and field-effect mobility, which have been regarded as obstacles for industrialization of MILC process, measure to be 18.9 pA and 62.8 cm2/V-sec, respectively.
9:00 PM - A6.3
Effects of Deposition and Layer Parameters on Aluminum- Induced Crystallization of PECVD Amorphous Silicon.
Kendrick Hsu 1 , Jermey Ou-Yang 1 , Grant Pan 1 , Liping Ren 2
1 Electrical Engineering, University of California at Los Angeles, Los Angeles, California, United States, 2 , Nanoelectronics and Nanophotonics Laboratory, Global Nanosystems, Inc., Los Angeles, California, United States
Show AbstractFlexible displays on plastic substrates require novel thin film transistors (TFTs) that are made of high carrier mobility materials, fabricated at low temperatures below 200 °C, composed of self-aligned scalable MOS structures, and compatible to large-area flexible display processing. It has been recently reported that large grain polycrystalline silicon (c-Si) can be formed by aluminum-induced crystallization (AIC) of amorphous silicon (a-Si) at a temperature as low as 200 °C if the aluminum layer is placed on top of the amorphous silicon before the AIC reaction. In order to further reduce the AIC temperature and to achieve device grade AIC c-Si for its use in flexible displays, the effects of deposition and layer parameters on AIC of a-Si from plasma-enhanced chemical vapor deposition (PECVD) were extensively investigated. This includes, but is not limited to, AIC kinetics, microstructure evolution, crystallinity, and overall quality of c-Si, etc. The PECVD parameters investigated are temperature, pressure, gas flow rate, and power density; the layer parameters studied are the thickness of both Al and a-Si, and the thickness of silicon oxide interlayer before Al deposition. All of the PECVD deposition was carried out in a PlasmaTherm 790 System and all of the AIC reactions were performed in a N2 protection at a temperature below 200 °C. Optical microscopy and scanning electron microscopy were used for the investigation of the microstructure evolution, while transmission electron microscopy and X-ray thin film diffraction analyses were employed for the crystallinity and microstructures at high magnification. It was found that the power density among other parameters of the PECVD a-Si deposition plays the most essential role in the overall quality of c-Si, its microstructure evolution, and AIC formation temperature. For the investigated power ranging from 15 to 300 W, it was seen that lower power density results in a lower AIC temperature and better overall c-Si thin film quality. It was determined that the AIC process is a diffusion process of silicon and can be described with the Avrami equation as a function of AIC temperature and time when the deposition and layer parameters are prefixed. The activation energy deduced from the Arrhenius equation is strongly dependent on the deposition power density and the thickness of both Al and a-Si. A lower energy and a higher thickness of both Al and a-Si result in a lower activation energy. The activation energy ranges from 0.83 eV to 1.95 eV. With our optimized deposition and layer parameters, high quality device grade polycrystalline thin films from AIC of PECVD amorphous silicon were achieved at an AIC temperature as low as 120 °C for the first time, making it possible for the fabrication of polysilicon thin film transistors used for flexible displays.
9:00 PM - A6.4
Aluminum Induced Crystallization of Amorphous Silicon on Different Substrates Blow and Above Eutectic Temperature.
Meijun Lu 1 2 , Ujjwal Das 1 , Steven Hegedus 1 , Brian McCandless 1 , Robert Birkmire 1 2
1 Institute of Energy Conversion, University of Delaware, Newark, Delaware, United States, 2 Department of Physics and Astronomy, University of Delaware, Newark, Delaware, United States
Show AbstractAluminum induced crystallization (AIC) of electron beam evaporated amorphous silicon on three substrates, glass (Corning-1737), single crystalline silicon wafer and ceramic, are studied both below (450oC) and above (600oC) eutectic temperature (EuT) with stacking structure of a-Si/Al/substrate. Samples were analyzed with optical microscopy, X-ray diffraction, Raman spectroscopy and Scanning Electron Microscopy. For samples grown on glass substrates, continuous crystalline silicon film with grain size of about 30μm has been achieved below EuT, while discontinuous crystalline Si “islands” are formed above EuT. For samples grown on (100) oriented Si wafer, no crystallization has been observed below EuT in our experiment; above EuT, AIC process happens while Al also interacts with bottom Si wafer, and a crystalline silicon network is formed on the top. For samples grown on ceramic substrate, similar results as on glass-substrate are obtained for both below and above EuT, but with smaller grain size. Our results suggest that for a-Si/Al/substrate stacking sequence, glass and ceramic substrates are two promising, low-cost substrate candidates for AIC to achieve large-grain crystalline silicon at low temperature. These crystallized Si films can be useful as very conductive P-type seed layers for subsequent epitaxial thickening for thin crystalline silicon solar cells on low cost substrates.
9:00 PM - A6.5
Small-Grained Si Films Obtained via Single-Laser-Pulse-Induced Nucleation-Initiated Solidification of Amorphous Si Films: a New Crystallization Method.
Yikang Deng 1 , Sharona Hazair 1 , Alexander Limanov 1 , Ui-Jin Chung 1 , Paul Van der Wilt 1 , Adrian Chitu 1 , James Im 1
1 Applied Physics and Applied Mathematics, Columbia University, New York, New York, United States
Show AbstractIt has become apparent in recent years that there can be polycrystalline-Si-based TFT applications wherein the overall uniformity of the devices can be identified as being the most critical device parameter; the pixel-controlling TFTs that are utilized in AMOLED displays represent a potentially important and timely example. In this paper, we propose and present a new melt-mediated crystallization method that requires only a single laser pulse. We are presently exploring this approach as a potentially efficient way to produce polycrystalline Si films with small equiaxed grains that may be well suited for realizing highly uniform TFTs. This approach is physically and fundamentally distinct from all other laser crystallization techniques that have been investigated to date in that the process invokes complete melting of the irradiated films, so as to initiate crystallization via nucleation-initiated solidification of supercooled liquids. Our samples consisted of 50 to 200 nm amorphous Si films on SiO2-coated glass substrates. An excimer-laser-based system (308 nm) was used to irradiate the films at various pulse durations (30 to 250 nsec), energy densities, and substrate temperatures (RT to 600°C). Extensive in situ transformation analysis was carried out using front-side and backside transient reflectance measurements at multiple wavelengths. TEM was employed as a primary characterization instrument for investigating the microstructure of the irradiated films. A 3-D simulation tool developed previously within the group was used to indirectly study and analyze the transformation and thermal evolution-related details.In general, when Si films on SiO2 are fully melted by a short-pulse-duration laser pulse, the films cool rapidly via thermal conduction into the substrate and eventually solidify by way of nucleation and growth. In fact, and surprisingly so, a wide variety of apparently distinct microstructures ranging from fully amorphized Si to one consisting of relatively large grains with an unusual “flower-shaped” interior structure have been obtained over the years. Among these, we explicitly identify the microstructure that consists of small equiaxed grains (~ tens of nm) as being the most suitable candidate for producing uniform TFTs, in that the grains are found to be (1) relatively defect-free and (2) uniformly distributed throughout the material. In comparison, the other microstructures can be viewed as being either more defective and/or microstructurally heterogeneous. In this paper, we will also present a growth-based physical model that focuses on the post-nucleation thermal and transformational evolution as being important. In contrast to other more nucleation-centric models that have been proposed previously, our model appears to be capable of accounting for all the microstructures that have been obtained from processing within the complete-melting regime.
9:00 PM - A6.6
Analysis of Intra-Subgrain Defects Observed in Directionally-Solidified Si Films Obtained via Line-Scan SLS
Ui-Jin Chung 1 , Paul van der Wilt 1 , Adrian Chitu 1 , Alex Limanov 1 , James Im 1
1 Applied Physics & Applied Mathematics, Columbia University, New York, New York, United States
Show AbstractLine-scan sequential lateral solidification (SLS) corresponds to a particularly simple version of SLS in which a single line beam generated from a pulsed laser source is employed to produce Si films with either a directionally-solidified microstructure or a large-grained polycrystalline “2-shot” microstructure. The directionally-solidified Si films obtained via SLS are well appreciated as being an enabling material for realizing high-mobility TFTs (~300 to greater than 400 cm2/Vs for n-channel devices). However, the overall device uniformity from a set of such high-mobility TFTs has been previously revealed as being not as good as that of the otherwise identically prepared set of TFTs that were made using the line-scan SLS processed 2-shot material.The work presented in this paper focuses on first identifying and characterizing the intra-subgrain planar defects that are found in the directionally SLS-processed Si films, and then examines the spatial variations in the type and density of the defects and correlates these to the crystallographic orientation of the corresponding regions; such details are recognized as being capable of profoundly dictating the overall uniformity of resulting devices. The samples consisted of 50 and 100–nm thick amorphous Si films on SiO2-coated glass substrates. The samples were processed using an excimer-laser-based irradiation system at per-pulse translation distances of 0.5 and 1.0 μm. The crystallized films were subsequently characterized using SEM, TEM, AFM, and EBSD.The microstructural analysis of the films reveals that, in addition to previously recognized presence of subboundaries and grain boundaries, it is possible to further identify the presence of intra-subgrain defects in the material. Here, we suggest that it may be useful to categorize and recognize the existence of (1) nearly defect-free subgrains, (2) highly defective subgrains that contain what appears to be stacking faults, and (3) highly defective subgrains containing twin boundaries that run parallel to each other approximately in the direction of the scan. The spatially-resolved EBSD mapping of the regions containing such subgrains reveals a strong correlation that apparently exists between the aforementioned subgrain types and the crystallographic orientation of the subgrains. Specifically, it is found that the nearly defect-free and highly defective subgrains (as well as moderately defective ones) were found to all reside within (100)-RD (rolling (i.e., scan) direction) textured grains while the subgrains containing parallel-running twin boundaries were always found to exist within (110)-RD textured grains. We will elaborate on the physical factors that can be identified and deduced as being potentially responsible for the observed results, and also discuss the implications of the findings as regards potential issues and solutions concerning the overall uniformity of the TFTs that are fabricated on line-scan SLS processed Si films.
9:00 PM - A6.7
Microstructure and Orientation Analysis of Low-Defect-Density Crystal Domains Created via Dot-SLS of Amorphous Si Films.
P. Van der Wilt 1 , B. Turk 2 , A. Chitu 1 , U. Chung 1 , A. Limanov 1 , James Im 1
1 Program in Materials Science and Engineering, Department of Applied Physics and Applied Mathematics, Columbia University, New York, New York, United States, 2 , Coherent, Inc., Santa Clara, California, United States
Show AbstractSequential lateral solidification (SLS) is a particular pulsed-laser crystallization method for producing polycrystalline Si films suitable for fabrication of high-performance TFTs on glass or plastic substrates. The approach has demonstrated itself to be particularly flexible and effective in that a variety of low-defect-density microstructures have been generated using a number of technically distinct SLS schemes and irradiation systems. SLS entails inducing complete melting of spatially confined regions in the film followed by precise translation and overlapped re-irradiation to induce epitaxial lateral growth seeded from the laterally solidified grains obtained from the previous pulse.An advanced SLS scheme, referred to as “dot-SLS”, uses multiple shadow dots to create location-controlled low-defect-density crystalline domains; here, a domain is generated from a single shadow dot. Depending on the specific spatial arrangement of the dots, as defined by the mask, a set of isolated domains that are surrounded by small nucleated grains, to a set of domains that are bordered by other domains (thereby forming a continuous low-defect-density polycrystalline film) can result. Dot-SLS is noteworthy in that it can potentially lead to efficient generation of location-controlled single-crystal regions needed for fabricating ultra-high-performance TFTs.In this paper, we present detailed microstructure and texture-related results that have been recently obtained in the course of investigating dot-SLS of as-deposited amorphous Si films. The 100 nm Si films on SiO2-coated glass substrates were irradiated using a XeCl excimer laser (308 nm) and a mask-projection system. Films were characterized using SEM, TEM, AFM, and EBSD. It is found that (1) the process is quite effective in eliminating random high-angle grain boundaries within the domains, (2) the faceted mode of solidification may have prevailed during at least a part of the growth, and (3) the process is found to not induce any surface or in-plane textures. We have further discovered that there exists a strong correlation between the microstructural details of the domains (in terms of the presence and spatial distribution of planar defects within the domains) and the crystallographic orientation of the dot-shadowed regions or “seeds”. For instance, {100}-surface-oriented seeds were observed to result in predominantly defect-free domains, while for seeds with other orientations, prevalent formation of Σ=3 CSL boundaries was observed; the generation of these boundaries were found to typically, but not always (e.g., as in {111} and {213}), lead to a change in the surface orientation. We will discuss how the findings suggest possible technical schemes for generating ultra-low-defect-density single-crystal Si regions and may yield fundamental insights regarding the formation of planar defects during rapid lateral solidification of Si films.
9:00 PM - A6.8
A Simple Explanation on The Phase Transformation Kinetics of CW Laser Crystallization of Amorphous Silicon Thin Film on Glass.
Seong Jin Park 1 , Yu Mi Ku 1 , Ki Hyung Kim 1 , Jae Hwan Oh 1 , Jin Jang 1
1 Advanced Display Research Center, Kyung Hee University, Seoul Korea (the Republic of)
Show Abstract9:00 PM - A6.9
Structural and Electronic Characterization of P-Doped Laser Crystallized Polycrystalline Silicon Films
Rosari Saleh 1 , Norbert Nickel 2 , Karsten Maydell 2
1 Department of Physics, Universitas Indonesia, Depok Indonesia, 2 , Hahn-Meitner Institute, Berlin Indonesia
Show AbstractA7: Poster Session: Micro- and Nanocrystalline Silicon
Session Chairs
Virginia Chu
Hsiao Wen Zan
Wednesday AM, April 11, 2007
Salon Level (Marriott)
9:00 PM - A7.1
Relation between Electronic Properties and Density of Crystalline Agglomerates in Microcrystalline Silicon.
Paula Bronsveld 1 , Tomas Mates 2 , Antonin Fejfar 2 , Jatin Rath 1 , Ruud Schropp 1
1 Faculty of Science, Utrecht University, Utrecht Netherlands, 2 Institute of Physics, Academy of Sciences of the Czech Republic, Prague Czech Republic
Show AbstractIt is often observed that hydrogenated silicon layers deposited just over the amorphous to microcrystalline transition edge consist of cone-shaped crystallites, embedded in amorphous material [1]. For our samples, which were deposited by VHFPECVD at substrate temperatures of 40 °C, 70 °C and 100 °C, changing the crystallinity by an increase of the hydrogen to silane dilution ratio primarily changes the density of these cones, while their diameters and opening angles remain similar. Such effects have also been reported at higher substrate temperatures [1], but the lower the substrate temperature, the slower the hydrogen dilution dependent transition from amorphous to microcrystalline growth, which makes it easier to tune the nucleation density and study the effects of an increase in cone-density.Dilution series were made and coplanar contacts were deposited on top to measure the dark conductivity. At a certain hydrogen dilution, the conductivity increases from an amorphous value (~10-12 Ω-1cm-1) to a microcrystalline value (~10-7 Ω-1cm-1). Here, a percolation path has been formed between the contacts by cones that are connected at the surface, where the cones first meet at an increase of cone-density and form a field of randomly distributed overlapping circles [2] with straight boundaries at their connection points. In optical microscope images the cones can be spotted as dark circles and the surface coverage (on a scale comparable to the distance between the contacts) can be estimated. From this it can be determined whether a layer has also crossed the geometrical percolation threshold, which lies at a surface coverage of 67% [2]. From this surface coverage value and with the help of AFM and X-TEM images, also the cone-density and the average contact surface between cones can be calculated.We find that the geometrical and electronic percolation threshold coincide reasonably well. Furthermore, for layers above the percolation threshold the conductivity increases when annealed for equal periods at temperatures between 50 °C and 170 °C at each annealing step, an effect which increases with increasing cone-density, reaching about a factor of 103 at high density. Since in FTIR annealing spectra at these low annealing temperatures we found an increase in bound oxygen, which was believed to reside in the relatively open connection points between cones (visible in X-TEM), we believe that the dominant percolation path goes through the boundaries of the cones as was noted before [3] and that the lateral conductivity is determined by the amount of oxygen that can be effectively built in as a donor.[1] Fujiwara et al., Phys. Rev. B 63, 115306 (2001)[2] Y.-B. Yi and M. Sastry, Phys. Rev. E 66, 066130 (2002)[3] D. Azulay et al., Phys. Rev. B 71, 113304 (2005)
9:00 PM - A7.10
The Role of Hydrogen in Photoluminescence of Si/SiO2 Multilayers.
Zhengyue Xia 1 , Peigao Han 1 , Deyuan Chen 1 , Jiaxin Mei 1 , Jun Xu 1 , Wei Li 1 , Zhongyuan Ma 1 , Ling Xu 1 , Xinfan Huang 1 , Kunji Chen 1
1 Physics, Nanjing University, Nanjing , Jiangsu, China
Show AbstractNanocrystalline Si (nc-Si)/SiO2 multilayered structure is one of the potential candidates for the application in Si-based optoelectronic devices. An intense light emission has been achieved at room temperature from this structure though the luminescence mechanism is still an open question. During the fabrication of nc-Si/SiO2 structures, high temperature annealing is usually adopted and the luminescence behavior is quite complicated due to the existence of many kinds of luminescence centers. It was also reported that hydrogen plays an important role in the luminescence characteristics in nc-Si/SiO2 multilayered structures.In the present work, amorphous Si/SiO2 multilayered structures were fabricated in plasma chemical vapor deposition system by alternatively changing the process of a-Si:H deposition and in-situ O2 plasma oxidation with 40 periods, in which the thickness of a-Si:H and SiO2 are less than 4 nm and about 4-10 nm, respectively. The formation of nc-Si was realized by step-by-step thermal annealing with the temperature increased from 350 to 1100°C. It was found that the luminescence position and intensity were different at the different annealing temperature which can be attributed to the various luminescence centers. Since the high temperature annealing results in the effusion of the hydrogen and some previously passivated defects, such as dangling bonds (Pbs), are depassivated. These unpassivated states can act as the nonradiation recombination sites to suppress the luminescence efficiency.On the basis of the research of photoluminescence on a-Si/SiO2 multilayers through step-by-step thermal annealing, hydrogen passivation was carried out for Si/SiO2 mulitilayered structures annealed at 450°C and 1100°C. The sample is divided into four pieces, which are annealed at 300-600°C with an increment of 100°C in pure H2 ambience in conventional thermal furnace for an hour, respectively. It was found that after hydrogen annealing treatment, the photoluminescence from nc-Si/SiO2 is still stayed at 750 nm , however , the intensity is increased obviously. The PL intensity of these four samples (300-600 °C) annealed in H2 ambience become approximately twice as much as that of nc-Si/SiO2 without H2 annealing, among which, PL intensity after 400 °C hydrogen annealing reaches its maximum. It is suggested that the strong PL peak at 750 nm of nc-Si/SiO2 is come from localized states of interfacial Si=O around nc-Si. The hydrogen diffuses into the interface of nc-Si and SiO2 in high temperature annealing and passivated the non-radiative states around nc-Si that compete with Si=O, which results in the significant elevation of the photoluminescence.
9:00 PM - A7.2
Optimisation of Microcrystaline Silicon Deposited by Expanding Thermal Plasma Chemical Vapor Deposition for Solar-Cell Application.
Raul Jimenez Zambrano 1 , Rene van Swaaij 1 , Richard van de Sanden 2
1 DIMES-ECTM, Delft University of Technology, Delft Netherlands, 2 Department of Applied Physics, Eindhoven University of Technology, Eindhoven Netherlands
Show AbstractExpanding thermal plasma chemical vapor deposition (ETP) has been used successfully to deposit intrinsic amorphous silicon (a-Si:H) as well as microcrystalline silicon (μc-Si:H) at high deposition rates of up to 10 nm/s and 3.7 nm/s, respectively. In an earlier stage of development, μc-Si:H solar cells with 2% efficiency were obtained. The μc-Si:H films deposited using this method have peculiar infrared absorption spectra that show a low contribution at 2000 cm-1, a shoulder at 2135 cm-1 and a double peak at 2080 and 2100 cm-1. These peaks appear at the onset of microcrystallinity and could be explained by H on the boundaries of crystallites in the material, although this has been reported only for material with a high crystalline fraction. In this work we will study the origin of the infrared absorption spectra and discuss the influence of deposition conditions, with or without an applied rf bias, on the structural properties of μc-Si:H grown by ETP.The observed influence of the H2 dilution of the precursor gases on the bonding structure is as follows. When starting from μc-Si:H growth conditions, decreasing the H2 flow leads to an increase of H content in the material. The H is incorporated not only as bulk monohydrides (Si-H), but also in more complex structures: bulk dihydrides (Si-H2) and a mixed phase of (Si-H2)n chains and Si-H3 on voids. The presence of these last configurations is concluded from the absorption increase of the peaks centered at 2106-2112 cm-1 and of the two peaks at 860 and 905 cm-1, respectively, which indicates an increase of the void fraction. However, the position of the Si-H peak shifts from 2028 to 2005 cm-1, indicating a decrease of the void fraction. From these apparent contrasting results we suggest that the material consist of two phases: a phase containing isolated Si-H that accounts for the densification, and a phase in which (Si-H2)n chains and voids are created. The latter phase accounts for the increase in absorption in the region 840-905 cm-1. The double peak at 2080 and 2100 cm-1 observed from the onset of crystallinity may then be ascribed to a narrowing of the peak of bulk Si-H2 and the formation of surfaces Si-H bonds. By applying an rf bias to the substrate we are able to limit the void formation, while entering the amorphous phase, as deduced from the disappearance of the peak of surface (Si-H2)n and an uniform peak of bulk Si-H2 The μc-Si:H grown under these conditions shows the presence of dense amorphous silicon in between the crystallites, which was not observed without biasing.A more detailed description of the understanding of the growth process of μc-Si:H using the ETP technique will be presented. In the near future we intend to implement this material in a solar-cell structure.
9:00 PM - A7.3
Optimization Strategy for the Integration of Microcrystalline Silicon Films Deposited at Very High Deposition Rates in to pin Solar Cells using the MHC-VHF Technique.
Arno Smets 1 , Takuya Matsui 1 , Michio Kondo 1
1 Research Center for Photovoltaics, National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki, Japan
Show AbstractIn this contribution we report on the deposition of hydrogenated microcrystalline silicon (μc-Si:H) at high deposition rates using the novel multi-hole-cathode very high frequency (MHC-VHF) technique at high pressures conditions (~10 Torr). The MHC-VHF technique is based upon the confinement of electrons and ions in small holes in the powered showerhead electrode creating high density plasma spots. These spots operate as efficient dissociation zones of the in the spot injected precursor gasses. Since the dimension of the plasma spots is much smaller than the typical VHF wavelength the MHC-VHF technique has the advantage that the deposition area is not limited by the so-called standing waves at VHF conditions. If μc-Si:H films deposited at lower deposition rates are integrated in to solar cells, it is well known that the optimum material properties are deposited very close to the a-Si:H to μc-Si:H transition. However, the parameter window to deposit solar grade material becomes unfortunately narrower at high deposition rates. As a consequence a strategy for the optimization of μc-Si:H deposition conditions of the MHC-VHF or any other technique, without the necessity to integrate every film into solar cells devices, is desirable. In our strategy we use as reference material a μc-Si:H film deposited under conventional VHF at 2.3 nm/s and when integrated in to the single junction pin device, resulting in a record efficiency of 9.3 % at high deposition rates [1]. The reference material properties are characterized by dense material, long grains, the relative low bulk oxidation of the films, an absence of the narrow high stretching modes (NHSM) at 2083, 2103 and 2137 cm-1 and the presence of broad low and middle stretching modes (LSM and MSM) at ~1996 and ~ 2040 cm-1 in the infrared spectrum. The NHSM reflects hydrogen bonded to the crystalline grain boundaries in the pores, which are the main sites for the post deposition bulk oxidation. In our interpretation the LSM’s reflect the hydrogen incorporated in the a-Si:H tissue between the microcrystalline grains and MSM are the hydrogen at platelet configurations at coalesced grain boundaries. We demonstrate the importance of the initial growth (reduction of the amorphous incubation layer) and hydrogen profiling to obtain the same microstructure as the reference samples at high deposition rates using IR and Raman analyses. The first integration of optimized MHC-VHF films in to a pin-device at 2.0 nm/s, resulted in a promising efficiency of 7.0 %, considering the two vacuum breaks before and after the intrinsic film deposition.[1]T. Matsui, A. Matsuda, and M. Kondo, Mat. Res. Soc. Symp. Vol. 808, A8.1.1. (2004)
9:00 PM - A7.5
Synthesis and Characterization of Nanocrystalline Diamond Thin Films by Electron Cyclotron Resonance Chemical Vapor Deposition.
Jae Seok Lee 1 , Tae Kon Kim 1 , Arul Arjunan 1 , Rajiv Singh 1
1 Materials Science of Engineering, University of Florida, Gainesville, Florida, United States
Show Abstract9:00 PM - A7.6
A Kinetic Model of Stress Evolution During Coalescence and Growth of Polycrystalline Thin-films.
Juan Tello 1
1 , Brown University, Providence , Rhode Island, United States
Show AbstractWe have developed a simple continuum model of the stresses that result from the coalescence and growth of islands during deposition of a polycrystalline thin film. Our model includes a detailed description of attractive forces between neighboring islands, and also accounts for mass transport along surfaces and grain boundaries. The finite element method was used to calculate the island shape changes as well as the stresses and elastic deformation in the film during the growth process. Two competing mechanisms for generating tensile and compressive stress emerge naturally from the model. The model reproduces several experimental observations, including the variation of stress with film thickness, the range of observed growth stresses and the effects of deposition flux and grain boundary diffusivity on stress.
9:00 PM - A7.7
Boron Doping Effects in Microcrystalline Silicon
Wolfhard Beyer 1 , Lars Niessen 1 , Frank Pennartz 1
1 , Institute of Photovoltaics, IEF, Forschungszentrum Jülich GmbH, Jülich Germany
Show AbstractHighly conductive microcrystalline silicon films are of interest for application as contact layers in thin film silicon solar cells. Recently we reported high conductivity values for boron-doped microcrystalline silicon films prepared by plasma-enhanced chemical vapor deposition (PECVD) from tetrachlorosilane-hydrogen-diborane gas mixtures. Room temperature conductivities of nearly 300 S/cm were reached (1,2) while the maximum conductivities reported for silane-based boron-doped material are more than a factor of 10 lower. Here we investigate the peculiarities of this B-doped chlorinated material and we explore if such high conductivities in B-doped microcrystalline silicon can be reached otherwise. It is found that the high conductivity originates from a high concentration of doping-active boron atoms incorporated in microcrystalline silicon material of high crystalline fraction. These films grow (250°C substrate temperature) with relatively low chlorine and hydrogen concentrations of a few percent and they have (according to effusion measurements of hydrogen and implanted helium) a relatively compact structure. Highly boron-doped films based on silane and silane-tetrachlorosilane mixtures usually cannot be produced with a high crystalline fraction under standard deposition conditions. Results for fluorinated microcrystalline silicon films will also be discussed.1. W. Beyer, R. Carius, M. Lejeune, and U. Zastrow, MRS Symp. Proc. 808 (2004) 3892. W. Beyer, R. Carius, and U. Zastrow, MRS Symp. Proc. 862 (2005) 139
9:00 PM - A7.9
Study of Optical Emission Spectroscopy During Preparing Nano-crystalline Silicon Intrinsic Layers with VHF-PECVD
Feng Zhu 1 , Prabhat Kumar 1 , Josh Gallon 2 , Jian Hu 2 , Arun Madan 1 2
1 Metallurgical and Materials Engineering, colorado school of mines, Golden, Colorado, United States, 2 , mvsysteminc, Golden, Colorado, United States
Show AbstractUse of very high frequency in plasma enhanced chemical vapor deposition (VHF-PECVD) technique has attracted considerable attention as this approach can increase the deposition rate of nano-crystalline silicon (nc-Si) for electronic device applications. However, the properties of materials and devices deteriorate with increasing deposition rate and are linked to the growth mechanism. In an attempt to understand this, we have used optical emission spectroscopy (OES) technique to characterize the state of plasma during deposition of nano-crystalline silicon intrinsic layers. The OES can provide useful information about radicals such as SiH*, Hβ*, Si* and Hα* in the plasma. Generally, to increase the deposition rate, the radicals in plasma should be enhanced with increasing excitation power. However, increase of excitation power from 10W to 100W leads to a decrease in the ratio SiH*/Hα (from ~1.8 to ~0.6) and Si*/Hα (from ~1.2 to ~0.4), and enhances ion bombardment. As a result, a higher crystalline fraction occurs in nc-Si films whose properties deteriorate. Increasing silane concentration (SC) from 2% to 8% in the gas phase, enhances the ratio SiH*/Hα (from 0.85 to 1.9) and Si*/Hα (from 0.5 to 0.8), leading not only to an increased deposition rate but an increased extant of the amorphous phase in the film. Increasing the pressure and total flow during the deposition has the same effect as increase the SC. We provide systematic data that high-quality nc-Si films can be fabricated under high-pressure silane depletion condition, where SiH*/Hα and Si*/Hα ratios are maintained at ~1.1 and ~0.5, respectively. In this case, the deposition rate increases, as evidenced by an increase of radicals shown from OES.
A8: Poster Session: Thin Film Growth
Session Chairs
Virginia Chu
Hsiao Wen Zan
Wednesday AM, April 11, 2007
Salon Level (Marriott)
9:00 PM - A8.1
Phase Control and Stability of Thin Silicon Films Deposited from Silane Diluted with Hydrogen.
Gijs van Elzakker 1 , P. Sutta 2 , F. Tichelaar 3 , M. Zeman 1
1 ECTM/DIMES, Delft University of Technology, Delft Netherlands, 2 New Technologies – Research Centre, University of West Bohemia, Plzen Czech Republic, 3 National Centre for HREM, Delft University of Technology, Delft Netherlands
Show Abstract9:00 PM - A8.3
First-Principles Theoretical Analysis of Surface Hydride Dissociation on Plasma-Deposited Amorphous Silicon Thin Films.
Tejinder Singh 1 , Mayur Valipa 1 , Dimitrios Maroudas 1
1 Chemical Engineering, University of Massachusetts, Amherst, Amherst, Massachusetts, United States
Show AbstractDuring plasma-assisted deposition of hydrogenated amorphous silicon (a-Si:H) thin films, the chemical state of the a-Si:H surface, in terms of its silicon hydride, SiH
x (x = 1,2,3), composition, assumes fundamental importance as it can influence a-Si:H film growth by determining the interactions of gas-phase species with the surface. The surface hydride composition also provides information on surface chemical reactions which, in turn, help us understand how surface species incorporate into the bulk a-Si:H film.
This presentation focuses on a detailed analysis of various SiHx (x = 1,2,3) dissociation pathways governing the surface hydride composition of a-Si:H thin films. Our analysis is based on a synergistic combination of first-principles density functional theory (DFT) calculations on the hydrogen-terminated crystalline Si(001)-(2×1) surface with molecular-dynamics (MD) simulations of radical precursor dissociation on a-Si:H film surfaces. According to our DFT calculations, surface trihydride (SiH3) species dissociate sequentially to form surface dihydrides (SiH2) and surface monohydrides (SiH) via thermally activated reaction pathways with reaction barriers over the range 0.1-0.5 eV. Two types of hydride dissociation reaction mechanisms, mediated by floating bonds (FBs) and dangling bonds (DBs), respectively, were found to be operative. In FB-mediated reactions, the H atom of the radical is transferred to adjacent surface Si atoms, which become five-fold coordinated after H transfer, resulting in barriers of 0.4-0.5 eV. In DB-mediated reactions, the radical dissociates by transferring an H atom to a surface DB site, resulting in reaction barriers of 0.15-0.3 eV. We have also analyzed the dissociation of SiH2 to SiH, with reaction barriers of 0.2-0.4 eV. Furthermore, we find that steric repulsion effects can raise the barrier for hydride dissociation reactions. Based on our results, we conclude that the presence of DBs lowers the barrier for surface hydride dissociation reactions; however, other H transfer mechanisms are operative that are not mediated by DBs.
The results are consistent with the findings of our MD simulations of repeated impingement of SiH3 radicals on a-Si:H film growth surfaces. We studied the surface reactions of the SiH3 radical and monitored the chemical composition of the a-Si:H surface over the temperature (T) range 475 ≤ T ≤ 800 K. The MD simulations revealed that the a-Si:H surface consists mostly of SiH2 species at lower T (T ~ 500 K) and SiH species at higher T (T > 650 K); the surface trihydride concentration decreases with increasing T due to dissociation reactions mediated both by FBs and DBs, consistently with the DFT results. Our results also are consistent with experimental measurements of a-Si:H film surface compositions using in situ ATR-FTIR spectroscopy.
9:00 PM - A8.4
The Effect of Near Mono-energetic Ion Bombardment on Remote Plasma Deposited a-Si:H
Ina Martin 1 , Michiel Blauw 1 , W. Kessels 1 , Richard Engeln 1 , M. van de Sanden 1
1 Applied Physics, Technical University of Eindhoven, Eindhoven Netherlands
Show AbstractThe role of neutrals during expanding thermal plasma (ETP) deposition of a-Si:H has been thoroughly studied in the literature. Less attention has been paid to ions, both because ion flux is low compared to neutral flux, and the remote nature of the plasma source results in low ion energies, < 2 eV. However, substrate biasing can be used to increase the energy of the bombarding ions, changing the properties of the deposited materials.1 Ion bombardment effects depend on ion energy as different thresholds exist for enhancing vs. damaging processes. We have applied both rf and pulse-shaped bias techniques to ETP deposition of a-Si:H, and our results indicate that the pulse-shaped bias technique is a more controlled method for increasing the ion energy. This method, originally developed by Wendt and coworkers, results in a near constant substrate voltage, which allows for a near constant ion energy.2 In contrast, rf biasing results in broad, bimodal energy distributions. Spectroscopic ellipsometry (SE) and FTIR data demonstrate that both methods of substrate biasing can result in an increase in refractive index, and a decrease in the microstructure factor (R*) of a-Si:H. Decreased R* values are related to increased photoconductivity, which is important for the applications of a-Si:H in p-i-n solar cells. Rf biasing, however, is a less controlled technique, the application of which leads to the formation of an extra plasma in front of the substrate, as measured by optical emission spectroscopy. Although the application of rf bias results in an initial increase in the refractive index of the materials, a decrease occurs at -Vdc > ~ 70 V. The application of rf bias also results in a linear increase in deposition rate. In contrast, the application of the pulse-shaped bias results in a nearly constant deposition rate, and in increase in refractive index over the entire range studied (Vsub ~ -110 V). Film characterization results as a function of rf and pulse-shaped bias will be discussed, and results are compared to other materials deposited using a pulse-shaped bias. 1 A. H. Smets, W. M. M. Kessels and M. C. M. van de Sanden, manuscript submitted to J. Appl. Phys. (2006)2 S. B. Wang and A. E. Wendt, J. Appl. Phys. 88, 643 (2000)
9:00 PM - A8.5
Reliability of Silicon Nitride Gate Dielectric in Vertical Thin-Film Transistors.
Maryam Moradi 1 , Denis Striakhilev 1 , Isaac Chan 1 , Saeed Fathololoumi 1 , Arokia Nathan 2
1 ECE, university of waterloo, Waterloo, Ontario, Canada, 2 London Centre for Nanotechnology, University College London, London United Kingdom
Show AbstractVertical thin film transistor (VTFT) with its inherent structural attributes of short channel length and small device area offers an excellent opportunity for bringing up a new generation of low-cost, high-speed, and high-resolution flat-panel electronics. Following this vision, it is imperative to understand the impact of gate dielectric thickness on the short channel effects in VTFT with submicron to nanoscale channel lengths. This paper reports on the thickness evolution of physical properties and electrical characteristics of silicon nitride films in the range of 50 to 300 nm. Silicon nitride films were deposited by conventional 13.56MHz plasma enhanced chemical vapor deposition (PECVD) using silane and ammonia gas precursors at substrate temperature of 300 °C. Cross section Scanning Electron Microscopy, Atomic Force Microscopy, and Infrared Spectroscopy measurements were employed in order to study the effect of thickness and substrate properties on film structure and composition. The electrical breakdown strength for 150-300nm thick films was approximately 7 MV/cm, whereas the value dropped to ~3MV/cm for 50nm thick films deposited under the same process condition. The lower breakdown strength was accompanied by an increase of pinhole density by a factor of 20 and a noticeable increase of SiH absorption in infrared spectra. We also found that the breakdown strength of silicon nitride films deposited on metallized planar substrate was higher than that of the same films deposited on vertical sidewall. In this article, we discuss the requirements of gate dielectric in VTFTs with respect to device dimensions and the dependence of electrical properties on film thickness, in terms of the film composition and growth behavior.
9:00 PM - A8.6
Cyclohexasilane (Si6H12) for Silicon-Based Materials
Xuliang Dai 1 , Douglas Schulz 1 , Philip Boudjouk 1
1 , North Dakoda State University, Fargo, North Dakota, United States
Show Abstract9:00 PM - A8.7
Effects of Ion Bombardment on the Properties of Hydrogenated Amorphous Germanium
Kristin Pollock 1 , Tobin Kaufman-Osborn 1 , Jonas Hiltrop 1 , Kyle Braam 1 , Steven Fazzio 1 , James Doyle 1
1 Department of Physics, Macalester College, St. Paul, Minnesota, United States
Show AbstractWe present a study of the effects of ion bombardment on the electrical and structural properties of hydrogenated amorphous germanium (a-Ge:H) deposited by dc reactive magnetron sputtering (RMS) of germanium in argon and hydrogen. In previous PECVD and RMS studies, it has been proposed on indirect grounds that ion bombardment is crucial for the production of high quality a-Ge:H. In our system a direct test of this hypothesis is carried out using an unbalanced magnetron together with an externally applied magnetic field that can systematically vary the plasma density near the substrate while keeping growth rate, substrate temperature, and working gas pressure constant. The plasma density and floating potential is measured using Langmuir probes and the ion flux is calculated from the Bohm relation. At low levels of ion bombardment the dark conductivity of the a-Ge:H films is high and the photosensitivity is low. With increasing ion flux the dark conductivity decreases dramatically and is accompanied by an increase in photosensitivity, consistent with an increase in electronic quality of the films. It is verified that the observed changes are not due to an increase in temperature due to plasma heating. The influence of ion bombardment on hydrogen bonding and film stress will also be discussed.
9:00 PM - A8.8
Deposition Uniformity Control in a Commercial Scale HTO-CVD Reactor
Shigeru Sakai 1 , Masaaki Ogino 1 , Ryosuke Shimizu 2 , Yukihiro Shimogaki 3
1 Fuji Electric Advanced Technology Co.Ltd., 4-18-1,Tsukama, Matsumoto Japan, 2 Fuji Electric Advanced Technology Co,Ltd,, 1,Fuji-machi,, Hino Japan, 3 The University of Tokyo, 7-3-1,Hongo, Tokyo Japan
Show Abstract
A9: Electronics on Flexible Substrates
Session Chairs
Wednesday AM, April 11, 2007
Room 3001 (Moscone West)
9:30 AM - **A9.1
Fabrication of Flexible Thin Film Transistors Using Self-Aligned Imprint Lithography and Roll-to-Roll Processes.
Craig Perlov 1 , Marcia Almanza-Workman 1 , Steve Braymen 2 , Alison Chaiken 1 , Frank Jeffrey 2 , Robert Garcia 1 , Jason Hauschildt 2 , Warren Jackson 1 , Albert Jeans 1 , Han-Jun Kim 1 , Hao Luo 1 , Ohseung Kwon 1 , Ping Mei 1 , Carl Taussig 1
1 , Hewlett Packard Laboratories, Palo Alto, California, United States, 2 , Powerfilm, Inc, Boone, Iowa, United States
Show AbstractInexpensive large area electronics on flexible substrates will enable many new products that cannot be cost effectively manufactured by conventional means. This paper presents a new approach for low cost manufacturing of electronic devices using roll-to-roll (R2R) processes exclusively. Compared to conventional batch fabrication and photolithography, R2R fabrication of electronic devices on continuous plastic webs offers the possibility of greatly diminished cost. Despite its potential advantages, technical challenges have stymied the transition to R2R manufacturing. These challanges include the following: (1) plastic substrates impose a lower process temperature ceiling making it more difficult to obtain high performance thin film transistors (TFTs). (2) A critical technical challange for R2R is the capability to pattern and align micron scale features on large dimensionally unstable substrates. (3) Photolithography is expensive and difficult to implement on continuous plastic webs.In this talk, a solution to these problems is presented. A R2R based self-aligned imprint lithography (SAIL) process provides an innovative solution to the patterning and registration of device features on flexible substrates. The SAIL technique integrates all the pattern and alignment information for the complete device fabrication into a single 3D mask that is imprinted on the substrate. Since this monolithic masking structure distorts with the substrate, layer to layer alignments are preserved throughout subsequent processing. A series of etches are applied to the 3D mask to reveal the patterns for each level. The imprint process eliminates the complexity and cost associated with photolithography.We have implemented these processes on a 50μm polyimide substrate with an amorphous silicon TFT stack. This SAIL process along with an improvement in low temperature TFTs have yielded devices with on/off ratios of >107, on-currents as large as 100μA with good mobility. These devices will enable a wide range of applications including, for example, an active matrix backplane for a variety of displays.
10:00 AM - A9.2
Channel Length Scaling of High Performance Transistors on Flexible Substrates Fabricated Using Imprint Lithography
Warren Jackson 1 , D. Veksler 2 , A. Koudymov 2 , M. Shur 2 , M. Almanza-Workman 1 , S. Braymen 3 , A. Chaiken 1 , R. Garcia 1 , J. Hauschildt 3 , A. Jeans 1 , F. Jeffrey 3 , H. Kim 1 , O. Kwon 1 , H. Luo 1 , P. Mei 1 , C. Perlov 1 , C. Taussig 1
1 , HP Labs, Palo Alto, California, United States, 2 , Rensselaer Polytechnic Institute, Troy, New York, United States, 3 , Power Film, Inc, Boone, Iowa, United States
Show AbstractSelf-aligned imprint lithography (SAIL) can produce submicron aligned device layers on dimensionally variable materials such as flexible plastic films. Using this submicron alignment capability, transistors with short channel lengths, L, (~1μm) can be produced using roll-to-roll imprint fabrication methods on large area, non-rigid substrates in manufacturing quantities. Typically, small channel lengths are difficult to fabricate on flexible large substrates because even a small temperature change or moderate stress results in significant cumulative misalignment between layers. The limiting switching speed of a transistor depends linearly on mobility but inversely as the square of the channel length. Hence, the ability of SAIL to make short channel devices enables high speed, large on-current transistors even using relatively low mobility material such as amorphous silicon. In order to realize this potential of short channel devices, the parasitic contact resistance must be minimized. In previous work, the properties of short channel devices have been dominated by contact resistance; a resistance modeled as a single resistance independent of source, drain and gate biases. Such model was not correct and resulted in the extracted mobility values of devices below L=10μm being typically significantly worse than those for longer channel devices (L>10μm). In this talk we present results of L scaling of a-Si:H SAIL transistors produced on flexible 50μm polyimide substrates. For the devices with short channels, the on-current is dominated by a contact resistance that is highly nonlinear and depends on both the drain-source and the gate-source voltages. By measuring the characteristics of devices with L ranging from 1 to 100μm, the contact I-V characteristics were obtained. The contact resistance was also measured using a four probe transistor structure where the voltage drop across the contacts could be separated from the voltage drop within the channel. We show that the contact resistance should be modeled as a contact transistor that turns on through the application of the gate and source drain voltages. For short channel devices, the contact transistor electrical characteristics dominate while for long channel transistors, the channel characteristics prevail. By optimizing the device, deposition and fabrication parameters, the contact resistance could be minimized so the on-current scaled as L-1 down to 1-2 μm. As a result, on-currents in excess of 100 μA for W/L=100μm/2μm devices are achieved. This level of performance is enough to drive OLED displays and demonstrates that with appropriate fabrication methods, high performance flexible backplane electronics are achievable.
10:15 AM - A9.3
Flexible a-Si:H-based Image Sensors Fabricated by Digital Lithography.
William Wong 1 , TseNga Ng 1 , Michael Chabinyc 1 , Rene Lujan 1 , Raj Apte 1 , Scott Limb 1 , Robert Street 1
1 Electronic Materials and Devices Laboratory, Palo Alto Research Center, Palo Alto, California, United States
Show AbstractThe scaling of large-area electronics will become increasingly complex with conventional methods of device processing, such as photolithography, reaching a practical limit. Novel processing methods using conventional electronic materials with flexible platforms will create new functionality at reduced costs for applications such as flexible a-Si:H image sensors.a-Si:H-based thin-film transistor (TFT) arrays were fabricated using jet-printed, digital lithographic processing in place of conventional photolithography. The print-patterned arrays were processed on polyethylene naphthalate substrates with a maximum process temperature of 150°C. The TFT device performance was comparable to devices fabricated at high temperatures on glass. A low-temperature p-i-n sensor layer was then integrated onto the flexible 75 dpi resolution, 180×180 pixel array. The sensor layer possessed a linear light response with a measured quantum efficiency of ~ 70% at 488 nm with a dark current of 10-8 Amps/cm2 at a reverse bias voltage of 2V. A comparison of the a-Si:H-based sensor arrays with a poly-fluorene-based sensor array, on a flexible a-Si:H TFT backplane, will also be presented.
10:30 AM - A9.4
Instability of Amorphous Thin Film Transistors under Prolonged High Compressive Strain.
Jian Chen 1 , I-Chun Cheng 1 , Sigurd Wagner 1 , Craig Perlov 2 , Warren Jackson 2 , Carl Taussig 2
1 Electrical Engineering, Princeton University, Princeton, New Jersey, United States, 2 , Hewlett Packard Laboratories, Palo Alto, California, United States
Show AbstractWe report permanent changes in the electrical characteristics of amorphous-silicon thin-film transistors that are subjected to prolonged and extremely high compressive mechanical strain. This finding is the first clear evidence for a permanent effect of mechanical strain, as earlier studies detected only temporary, reversible, changes, mostly of the electron mobility. The a-Si:H TFTs were fabricated by a standard process on 50-micrometer thick Kapton E polyimide foil substrates at the TFT stack deposition temperature of 150oC. The TFTs were stressed by bending around an axis perpendicular to the channel length, and were evaluated in the flattened state. Tensile bending up to the fracture strain of 0.2% to 0.3% had no permanent electrical effect. Compressive bending to just below the fracture strain of ~2% changed the TFT permanently. Application of 1.8% compressive strain for up to 23 days increases the threshold voltage and reduces the already small OFF and gate leakage currents. We also observed a rise in the gate leakage current just before the TFTs breaks down as the compressive strain is increased to 2% and more. These results show that mechanical strain has only a minor long-term effect on a-Si:H TFT performance, in contrast to electrical gate bias strain. Thus the circuits designed for compensation of threshold voltage shifts in AMOLED circuits caused by gate bias easily can compensate for shifts caused by mechanical strain. We also conclude that mechanical strain caused by roll-to-roll processing and imprinting will have no long-term effect on TFT performance.
10:45 AM - A9.5
Single Grain Si TFTs Fabricated at 100°C for Microelectronics on a Plastic Substrate.
Ming He 1 , Ryoichi Ishihara 1 , Tao Chen 1 , Wim Metselaar 1 , Kees Beenakker 1
1 , Dimes_Tudelft, Delft Netherlands
Show AbstractSingle grain Si thin film transistor (SG-TFT) exhibits similar characteristics as SOI-FETs [1]. TFTs are fabricated within location-controlled grains at a low process temperature. However the maximum process temperature of 550oC, which is at LPCVD for a-Si film, is higher than resistant temperature of plastic substrate. If such a high performance TFT could be fabricated at an ultra-low process temperature, the device could be applied to a direct formation of system circuits as well as a high quality display on a plastic foil. In this paper, high performance SG-TFTs can be fabricated at 100oC. a-Si is sputtered at 100oC and crystallized by the excimer-laser without substrate heating. High quality gate SiO2 is deposited at 80oC by inductively coupled plasma enhanced CVD (ICPECVD). First, optimization of the sputtered Si is performed as it is easily ablated with excimer-laser. a-Si is sputtered with various bias conditions. a-Si film is crystallized with excimer laser at room temperature. a-Si film is easily ablated during laser crystallization when a bias is applied during sputtering. However, a-Si film deposited without bias can be crystallized without ablation. For a 140 nm-thick a-Si film, the grain has a diameter of 1.8 mm after ELC. The m-Czochralski process [2] is combined with sputtered a-Si to obtain location-controlled grains. A 250 nm-thick a-Si is sputtered on oxidized Si wafers with grain filters. Single shot of excimer-laser light is irradiated to the structure. Grains with a diameter of 4 mm can be obtained at the predetermined positions. After patterning the Si into an island, a 100 nm-thick gate SiO2 is deposited at a temperature of 80oC by ICPECVD. An ICP source with a frequency of 13.56 MHz and power of 500 W is used. SiH4 and O2 are used as precursors. The density of interface trap states is estimated to be as low as 3.2×1010 cm-2eV-1. Breakdown field strength and resistivity are 5.4 MV/cm and 4.7×1014 Ωcm, respectively.Subsequently, Al is sputtered at a room temperature and patterned as a gate. The channel is made inside the grain and positioned outside the grain filter. Field-effect mobility for electrons, defined at a low-drain voltage, is 290 cm2/V.s with the gate SiO2 deposited at 80oC. Subthreshold slope of the SG-TFTs with the gate SiO2 deposited at 80oC is 0.49 V/dec.In conclusion, high performance single grains TFTs can be fabricated at a maximum process temperature of 100oC. TFTs fabricated with above channel and gate oxide have an excellent performance. These high performance TFTs fabricated at an ultra-low temperature are promising devices for microelectronics on plastic substrate.Reference:[1]: R. Vikas et. al., Proc. of IEDM 2005, p. 941.[2]: P. C. van der Wilt, B. D. van Dijk, G. J. Bertens, R. Ishihara, and C. I. M. Beenakker. Appl. Phys. Lett. 79 1819 (2001).
A10: Novel Applications
Session Chairs
Wednesday PM, April 11, 2007
Room 3001 (Moscone West)
11:30 AM - **A10.1
Deformable Thin-film Electronics for Biomedical Prosthetics and Diagnostic Tools.
Stephanie Lacour 1 , Barclay Morrison 2 , Sigurd Wagner 3 , Mark Blamire 1 , James Fawcett 4
1 Materials Science, University of Cambridge, Cambridge United Kingdom, 2 Biomedical Engineering, Columbia University, New York, New York, United States, 3 Electrical Engineering, Princeton University, Princeton, New Jersey, United States, 4 Centre for Brain Repair, University of Cambridge, Cambridge United Kingdom
Show AbstractWe are developing a new class of electronic devices with biomechanical properties comparable to those of biological tissues. Brain, nerves, and skin have no equivalent in today’s microelectronics’ world. They are made of soft visco-elastic materials evolving in wet, ionic extracellular fluid, and can compute enormous amount of information quickly. Today’s integrated circuits can provide high level of sensing and computation but cannot stretch. Thin-film electronic devices embedded in polymeric substrate that can conform to and comply with the movements of biological tissues are a promising avenue to fully biocompatible electronic interfaces. The technology is based on planar fabrication at ultra-low temperature (T < 200°C) of thin films on polymeric substrates. The substrate may be a stiff polymer such as a polyimide film or an elastomeric membrane, depending on the kind and degree of deformation required. Polyimide films may be rolled around nerve fibres. Silicone substrates may stretch reversibly like our own skin. Metal films are evaporated or sputtered directly on the polymeric substrate, and patterned as recording & stimulating electrodes and interconnects. Semiconductor (amorphous silicon) and dielectric (silicon nitride) materials are deposited by plasma enhanced chemical vapour deposition (PECVD) at 150°C deposition temperature. Based on three applications -stretchable micro-electrode arrays (SMEAs) for in vitro study of brain trauma, sensory skin for prosthetic limb, and 3D compliant neural implant for nerve repair and regeneration- we will review the fabrication steps of thin-film and transistor devices on soft polymeric substrates, and present their electrical characteristics in air and physiological medium, and upon mechanical deformation cycles.
12:00 PM - A10.2
Performance of Thin Film Silicon MEMS on Flexible Plastic Substrates.
Samadhan Patil 1 , Virginia Chu 1 , Joao Conde 1 2
1 , INESC Microsistemas e Nanotecnologias, Lisbon Portugal, 2 Dept. of Chemical and Biological Engineering, Instituto Superior Tecnico, Lisbon Portugal
Show Abstract12:15 PM - A10.3
Amorphous Silicon Based TFT and MIS Nonvolatile Memories.
Yue Kuo 1 , Helinda Nominanda 1
1 Thin Film Nano & Microelectronics Research Lab, Texas A&M University, College Station , Texas, United States
Show AbstractConventionally, the a-Si:H TFTs are used as the pixel switching devices in liquid crystal displays, imagers, sensors, etc. [1,2,3]. If the a-Si:H TFT can be fabricated into nonvolatile memories, new functions or products can be introduced. Recently, authors reported a new-type of a-Si:H TFT-based nonvolatile device that has a floating-gate structure with a thin a-Si:H layer embedded in the SiNx gate dielectric [4]. The complete TFT was fabricated with a simple two-photo mask process. Electrons were stored and released with the change of the polarity of the gate voltage. In this work, authors further investigated the TFT’s charge trapping mechanism and failure mode. In addition, the floating gate MIS capacitors were prepared and characterized for interface and bulk dielectric properties. Influences of the embedded a-Si:H film thickness and operating voltages on interface density of states, flat band voltages, flat band voltage shifts, leakage current, fixed charge density, and breakdown scheme of the capacitor were studied. The relationship between the MIS capacitor and the TFT characteristics were examined. For example, memory characteristics had been quantified from the hystereses of the TFT’s transfer curve or the capacitor’s C-V and J-V curves. The hysteresis phenomenon was due to the trapped electrons or holes at the embedded a-Si:H sites. When swept in the range of (-20 V, 20 V), the TFT with the 9 nm a-Si:H embedded layer had a DVt of 5.5 V. The MIS capacitor memory with the same embedded layer thickness had a DVFb of 2.6 V and a DJ (at 0 V) of 8 x 10-5 A/cm2. The memory window increased with the increase of the gate bias sweep range. For the same TFT, it had a DVt of 0.8 V in the sweep range of (-10 V, 10 V) and 20.7 V in the sweep range of (-30 V, 30 V), respectively. Stress mismatch between a-Si:H and SiNx layers are responsible for the increase of the Dit with the increase of the embedded a-Si:H layer thickness. Stable “write” and “erase” states and charge retention of at least 3600 seconds have been observed. A large “write” and “erase” window of DVt = 6 V had been achieved. The TFTs and MIS capacitors were fabricated on the Corning 1737 glass substrate using PECVD at 300°C and 13.56 MHz power supply. Molybdenum was used as the source, drain, and gate electrode. The microcrystalline silicon phosphorus-doped film was used as the ohmic contact layer.References:[1]Y. Kuo, “Non-LCD Applications of a-Si:H TFTs,” Amorphous Silicon Thin Film Transistors, p. 485, Y. Kuo, ed., Kluwer, New York (2004).[2]M. Kinugawa, Electrochem. Soc. Procs. TFT Tech. I, PV 1992-24, 145 (1992).[3]Y. Chen, K. Pangal, J. C. Sturm, and S. Wagner, J. Non-Cryst. Solids 266-269, 1274 (2000).[4]Y. Kuo and H. Nominanda, Appl. Phys. Lett., 89, 173503 (2006).
12:30 PM - A10.4
Monolithic Integrated a-Si:H Based Pin-diodes with Orthogonally Liquid Light Guidance Structures for Lab-on-microchip Applications.
Heiko Schaefer 1 , Konstantin Seibel 1 , Lars Schoeler 1 , Marcus Walder 1 , Markus Boehm 1
1 FB 12 IMT/HE, Institute for Microsystem Technologies, Siegen Germany
Show Abstract12:45 PM - A10.5
μ-Watt Enhanced Electroluminescent Power of Silicon Nanocrystal Light-Emitting Diodes Made on Nano-Scale Silicon-Tip-Array Substrate.
Chun-Jung Lin 2 , Gong-Ru Lin 1
2 Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, HsinChu Taiwan, 1 Graduate Institute of Electro-Optical Engineering and Department of Electrical Engineering, National Taiwan University , Taipei Taiwan
Show AbstractA11: Thin Film Transistors I
Session Chairs
Wednesday PM, April 11, 2007
Room 3001 (Moscone West)
2:30 PM - **A11.1
High Mobility Nanocrystalline Silicon TFTs for Display Application
Min-Koo Han 1 , Sang-Myeon Han 1
1 , Seoul National University, Seoul Korea (the Republic of)
Show Abstract The directly deposited nanocrystalline silicon (nc-Si) thin film have attracted considerable attention for various applications because of its high mobility and stability compared with a-Si thin film. nc-Si thin film transistors (TFTs) exhibit superior uniformity compared with low temperature poly-Si TFTs. Various methods such as plasma enhanced chemical vapor deposition (PECVD), hot-wire chemical vapor deposition (HW-CVD) and inductively coupled plasma chemical vapor deposition (ICP-CVD) have been reported to deposit nc-Si film. Conventional PECVD has been widely employed to deposit a-Si film and nc-Si film. Recently, high quality nc-Si film by ICP-CVD has attracted considerable attention. ICP-CVD may provide a certain advantages such as high deposition rate and less ion bombardment damage on the surface compared with PECVD. Recently, very low temperature TFTs (<200oC) on various substrates such as a plastic and a stainless steel have been reported. The purpose of our work is to report the characteristics of nc-Si film deposited by ICP-CVD (13.56MHz) and the electrical characteristics of nc-Si TFT fabricated at 150oC. Our experimental results exhibit a high field effective mobility exceeding 20cm2/Vs and a low subthreshold slope less than 0.5V/dec. We deposited nc-Si film by ICP-CVD at 150oC. ICP plasma power was set to 400W. The process gas was SiH4 diluted with He, H2 and He/H2 mixture. The crystalline volume fractions evaluated from the Raman spectrum of the nc-Si film were above 70%. The crystalline growth structure and thickness of incubation layer of each nc-Si film was observed by cross-sectional high resolution transmission electron microscopy (HR-TEM) and it is found that the thickness of incubation layer is less than 20nm In some samples, the incubation layer is almost diminished. The absence of incubation layer in nc-Si film may be attributed to the superior capability of decomposition of SiH4 gas by high density remote plasma generated by ICP-CVD and the dilution effect of He and H2 on the growth of crystalline Si. The grain size of 30~40nm was measured by cross-section TEM image and scanning electron microscopy (SEM) image of the nc-Si film. The top gate structure nc-Si TFTs was fabricated by ICP-CVD at 150oC. SiO2 as a gate insulator was deposited by ICP-CVD. The fabricated nc-Si TFTs exhibit a high field effective mobility exceeding 20cm2/Vs, a low subthreshold slope less than 0.5V/dec and a low threshold voltage (VTH) of ~2V. These characteristics can be attributed to the nc-Si film, which has a high crystallinity, fairly large grains, and the SiO2 film with a good C-V characteristic fabricated by ICP-CVD at 150oC. Our experimental results show that nc-Si TFTs fabricated at low temperature of 150oC may be suitable for integrated peripheral circuits as well as the pixel driving circuits of flexible displays due to their good electrical characteristics such as a high mobility, a low VTH and a low subthreshold slope.
3:00 PM - A11.2
Self-Aligned Nanocrystalline Silicon Thin-Film Transistor with Directly Deposited n+ Layer.
I-Chun Cheng 1 , Sigurd Wagner 1
1 Electrical Engineering, Princeton University, Princeton, New Jersey, United States
Show AbstractNanocrystalline silicon (nc-Si:H) is a candidate material for CMOS on plastic substrates. Self-aligned gates are desired to realize fast CMOS circuits and to eliminate the overlay misalignment on flexible substrates. However, typical plastic substrates demand ultralow process temperatures that prohibit the conventional self-aligned process of ion implantation followed by a high temperature anneal. Here we demonstrate that a self-aligned structure can be achieved by combining direct deposition with lift-off patterning of the top metal contacts, which is fully compatible with present a-Si:H technology.The TFTs are fabricated in a staggered top-gate, bottom-source/drain structure on Corning 1737 glass. First a ~50-nm thick intrinsic nc-Si:H is deposited as the seed layer, followed by ~50-nm thick evaporated Cr bottom source/drain contacts, and a ~50-nm thick PECVD n+ nc-Si:H layer. After patterning the contact layer to define the source/drain, a ~50-nm thick intrinsic nc-Si:H and a ~300-nm thick SiO2 layer are deposited as channel and gate dielectric layers, respectively. Both the intrinsic and the n+ nc-Si:H are deposited at an excitation frequency of 80 MHz and a substrate temperature of 150°C, while the SiO2 is deposited at standard RF and 250°C. After the contact holes are opened by wet chemical etch and dry plasma etch, a self-aligned photoresist pattern is defined by exposure from the back-side of the sample, with the Cr source/drain contacts as exposure masks. Then a ~150-nm Al layer is thermally evaporated and lifted-off in an ultrasonic aceton bath. This process aligns the gate metal with the doped nc-Si:H source/drain. The source/drain-gate overlap is controlled by the over-exposure time and over-development of the photoresist. Atomic force micrograph shows a resulting ~ 1 to 2-μm source/drain-gate overlap out of 80-μm channel length. The TFTs have similar characteristics to that of the non-self-aligned nc-Si:H TFTs fabricated at identical conditions, which indicates that the UV exposure through the nc-Si:H channel in the self-aligned photolithography process does not cause significant degradation. Electron mobilities of ~ 10 to 25 cm2V-1s-1 are obtained. The high threshold voltage of ~ 15V is associated with the non-optimized gate SiO2 deposited at ultralow temperature.
3:15 PM - A11.3
Contact Effects in High Mobility Microcrystalline Silicon Thin-Film Transistors
Kah Chan 1 2 , Eerke Bunte 2 , Helmut Stiebig 2 , Dietmar Knipp 1
1 School of Engineering and Science, International University Bremen, Bremen, Bremen, Germany, 2 Institute of Photovoltaic, Research Center Jülich, Jülich Germany
Show AbstractHydrogenated microcrystalline silicon thin-film transistors (μc-Si:H TFTs) have recently received significant attentions since devices with high charge carrier mobility can be prepared at low temperature. We present μc-Si:H TFTs fabricated by plasma enhanced chemical vapor deposition at temperatures below 200 °C with high electron mobilities exceeding 35 cm2/Vs. The fabrication of the μc-Si:H TFTs is compatible to the low-temperature fabrication of amorphous silicon TFTs. In particular, the deposition of the microcrystalline material was carried out in the high power and high pressure regime to achieve high deposition rates. We will discuss the electrical behavior of the μc-Si:H TFTs and the influence of drain and source contacts on important device parameters like carrier mobility, threshold voltage and subthreshold slope. As the high carrier mobility and carrier concentration result in high drain currents the performance of the μc-Si:H TFTs is strongly affected by the non-ideal contact behavior. As a consequence, the extracted device mobility decreases with decreasing channel length. The charge carrier mobility drops from 35 cm2/Vs for transistors with long channel lengths (100 μm) down to 7 cm2/Vs for transistors with channel length of 2 μm. We will present a simple analytical model to account for the contact effects on the device parameters. The results will be compared to the data derived by the Transmission Line Method. The extracted device parameters and the contact resistances will be presented and discussed in detail.
3:30 PM - A11.4
Analysis and Modeling of Photo Leakage Current in Poly-Si TFTs under RGB Backlight.
Hsiao Wen Zan 1 , Shih-Chin Kao 1 , Chuan-Shen Wei 1 , Ming Chun Su 1
1 Department of Photonics, Display Institute, HsinChu Taiwan
Show AbstractIn this paper, the photo leakage current of poly-Si thin film transistors (poly-Si TFTs) were studied. Since poly-Si TFTs are widely used in active-matrix liquid crystal displays, they are usually exposed to the scattered light from the backlight system. The photon will be absorbed by the silicon film to excite the generation of electron-hole pairs and therefore to form the photo current. Compared to the leakage current of poly-Si TFTs in the dark environment, the photo current is large and causes pronounced leakage current issues. In our experiment, we firstly tried to study the influence of poly-Si film properties on the photo leakage current. We changed the laser energy in the laser recrystallization process to obtain poly-Si films with various grain sizes. These films were used to serve as the active layer in the poly-Si TFTs. The influence of grain size on the photo leakage current was therefore can be measured. It was found that photo leakage current increases when the grain size was smaller than 3 μm. Since the grain boundaries were amorphous-like crystal structure, they should have better absorptivitiy than the area inside the grain. As a result, when grain size became smaller, the portion of grain boundaries became larger in a unit volume of silicon film. The photo leakage current was therefore increased. Also, various channel length, channel width and the lightly-doped drain (LDD) length were also designed. Their influences on the photo leakage current were investigated.Since the color sequential technology has been proved to be an effective method to greatly improve the luminance of the displays, backlight system generates blue, red, and green light at different time is an unavoidable trend. However, the photo leakage current of poly-Si TFTs under backlight irradiation with different wavelength has not been studied before. In our experiment, we produced the RGB light sources by using simple filtering films on the CCFL backlight system. It was found that under identical luminance, blue light was much more effective to generate photo leakage current. Also, if the color sequential was designed to produce the white light with color coordinate (0.3335, 0.3331), the leakage current in the blue light shining period was more than one order larger than those in red or in green light shining period. The variance of the photo leakage current under different light sources was well explained by consider both the light absorption and the photon energy. When the refraction index and the absorption coefficient of the poly-Si films were extracted by n&k analyzer, the absorbed photon number per unit second can be calculated. By defining certain constant quantum efficiency, the photo current can be obtained by applying simple photo diode model. Good agreement can be found between the modeling result and the experimental results.
3:45 PM - A11.5
Oxygen as an accidental dopant in high mobility microcrystalline Si Thin Film Transistors
John Robertson 1 , Arokia Nathan 2 1
1 Engineering, Cambridge University, Cambridge United Kingdom, 2 London Centre for Nanotechnology, University College London, London United Kingdom
Show AbstractNathan et al [1] were recently able to grow nano-crystalline Si TFTs with very high electron and hole mobilities (450 and 100 cm2/Vs. respectively) by direct RF plasma enhanced chemical vapour deposition from a hydrogen-diluted silane plasma at 150-250C. This was unexpected, as many groups had previously failed to do this. Previously, such high mobilities were only possible by laser re-crystallization. These large mobilities will have large implications for the display industry, so it is important understand the underlying reasons for this advance. SIMS measurements [1] suggest that the key advance is to reduce the oxygen impurity concentration to 1E17 cm-3, consistent with oxygen acting as an accidental donor impurity [2]. Why could oxygen act as a donor, what is its bonding configuration, and what is the band diagram? Oxygen in cz-Si is known to form a ‘thermal donor’ complex [3], but only when heated to ~550C. In a-Si:H, it was once proposed that O might form the 3-fold coordinated positive O site [4], but we find that this is not supported by high quality calculations. We calculate various donor configurations of O. We argue that the O donor in PECVD nc-Si is related to the thermal donor, but note that hydrogen can lower the formation temperature of this complex [5]. We show that the effect of removing donors is to allow the nano-crystalline grains to regain the flat band condition, remove the grain boundary scattering centers, and thus allow the high mobilities.1 C. H. Lee, A. Sazonov, A. Nathan, Tech. Dig. IEDM, p. 937 (2005); A Nathan, MRS (2006); IEDM (2006); APL submitted2 P Torres, et al, App Phys Lett 69 1373 (1996)3 see review R Jones et al, Physica B 308 8 (2001)4 N Ishii, et al, Jp J App Phys 24 L244 (1985); T Shimizu, JJAP 43 3257 (2004) 5 L I Murin, et al, Physica B 302 180 (2001)
A12: Imagers and Sensors
Session Chairs
Wednesday PM, April 11, 2007
Room 3001 (Moscone West)
4:30 PM - A12.1
PECVD Grown p-i-n Si and Si,Ge Thin Film Photodetectors for Integrated Oxygen Sensors.
Debju Ghosh 1 , Ruth Shinar 2 , Vikram Dalal 1 2 , Zhaoqun Zhou 3 , Joseph Shinar 1 3
1 Electrical and Computer Engineering, Iowa State University, Ames, Iowa, United States, 2 Microelectyronics Research Center, Iowa State University, Ames, Iowa, United States, 3 Physics and Astronomy, Iowa State University, Ames, Iowa, United States
Show AbstractRecent efforts to improve photoluminescence (PL)-based oxygen sensors have focused on developing compact, structurally integrated devices both on glass and flexible substrates. This has led to the development of organic light emitting device (OLED)-based sensors with a structurally integrated [OLED excitation source]/[sensing film] module. To additionally integrate a photodetector (PD), PECVD for fabrication of thin-film, p-i-n Si- and Si,Ge-based PDs was employed. O2 concentrations are advantageously determined by monitoring the effect of O2 on shortening the PL lifetime of an oxygen-sensitive dye, rather than on the quenching of the PL intensity. This approach eliminates the need for frequent sensor calibration, and, as pulsed OLED excitation is employed in this mode, the need for optical filters, which lead to bulkier sensors. Therefore, the development of thin-film PDs focused on shortening their response time, and understanding the factors affecting it. In this paper we show that boron diffusion during growth from the p+ to the i layer affects the cut-off frequency f in PECVD grown p-i-n PDs. Incorporating a SiC buffer layer, unlike reduction of the thickness of the p+ layer, and fabricating superstrate structures, where the p+ layer is grown last, increase f. The effects of the bandgap, defect states, nanocrystallinity and grain passivation, as well as the illumination wavelength and reverse bias, on f, are also described. Additionally, PDs fabricated by ECR are compared to those fabricated by VHF PECVD.
4:45 PM - A12.2
Segmented Amorphous Silicon n-i-p Photodiodes on Stainless-Steel Foils for Flexible Imaging Arrays.
Yuriy Vygranenko 1 , D. Striakhilev 1 , R. Kerr 3 , J. Chang 1 , K. Kim 1 , A. Nathan 2 , G. Heiler 3 , T. Tredwell 3
1 Dept. of Electrical and Computer Engineering, University of Waterloo , Waterloo, Ontario, Canada, 3 , Eastman Kodak Company, Rochester, New York, United States, 2 London Centre for Nanotechnology, University College, London United Kingdom
Show AbstractFlexible stainless-steel foils present an excellent alternative to fragile glass substrates conventionally used in large area electronics. A rapid progress in development of thin films transistors (TFTs) on flexible substrates enables a fabrication of light, flexible and rugged displays [1, 2]. It is also very attractive to apply this novel substrate technology to fabricate mechanically flexible and robust imagers for medical applications. This paper discusses the key pixel design requirements for flexible imager and reports the first successful attempt to fabricate amorphous silicon (a-Si:H) n-i-p photodiodes on thin stainless-steel foil substrate.We examine two architectures of n-i-p-photosensor, where the top electrode is based on amorphous or polycrystalline ITO. The impact of critical fabrication steps including the deposition of semiconductor layers, dry etch of the NIP stack, diode passivation and encapsulation, as well as a contact formation on the device performance is presented and discussed. The test structures comprising segmented photodiodes with an active area ranged from 0.126x0.126 to 2x2 mm2 have been fabricated on stainless-steel foils and on glass substrates for the purposes of process characterization. The fabricated samples are evaluated in terms of current-voltage, capacitance-voltage and spectral response characteristics. Diodes on the glass substrates tested at room temperature show a dark current density in the range from 60 to 100 pA/cm2 at a reverse bias of 5 V for different device areas. For 126 μm and 250 μm diodes on the stainless-steel foil substrate a dark current is ~400 pA/cm2, while for diodes of large size a leakage is one order of magnitude higher presumably due to mechanical stress. A quantum efficiency of 76% at a wavelength of 560 nm is achieved for 1-μm-thick diodes with polycrystalline ITO electrodes. Thus, performance of the small area photodiodes on the stainless-steel foils meets the requirements for most medical imaging applications.References:[1] JengPing Lu et al (PARC), “Flexible AMOLED Backplane Based on Excimer Laser Annealed Poly-Si TFT on Metal Foil”, MRS Spring meeting 2006[2] A. Z. Kattamis, I-C. Cheng, S. Wagner, Y.Hong “a-Si:H 2-TFT AMOLED Pixel Circuits on Stainless Steel Foils”, MRS Spring meeting 2006
5:00 PM - A12.3
Transient Current Behavior of Vertically Integrated Amorphous Silicon Diodes.
Gregory Choong 1 , Nicolas Wyrsch 1 , Christophe Ballif 1 , Rolf Kaufmann 2 , Felix Lustenberger 2
1 Institut de Microtechnique, University of Neuchatel, Neuchatel Switzerland, 2 , CSEM SA, Zurich Switzerland
Show AbstractMonolithic image sensors based on Thin Film on CMOS (TFC) Technology are becoming more and more attractive as an alternative solution to conventional active pixel sensors (APS). Imager with high sensitivity, high dynamic coupled with low dark current values (10-100 pA/cm2 @ 104 V/cm) have been developed [1]. However, issues such as light-induced degradation and image lag [2] hinder the commercial development of a-Si:H based image sensors. The problem of image lag is caused by residual current due to the release of trapped charges after the switch off of the illumination.In this paper, we will present a comprehensive study of the transient behavior of the photocurrent in a-Si:H photodiodes deposited on glass, as well as corresponding diode implemented in a TFC image sensor when illumination is switched off or periodically varied. The influence of the pixel architecture by using two different measurement setups has been measured: One setup reproduces the typical 3T APS pixel architecture behavior, in which the bias voltage of the diode varies with the photogenerated charge while the second setup keeps a constant bias voltage applied to the diode by using a charge integrator.The influence of the light-induced defect creation on the performance of the sensors will also been presented and discussed.[1] C. Miazza et al., Mat. Res. Soc. Symp. Proc.,Vol. 910 (2006)0910-A17-03.[2] J. A. Theil, Mat. Res. Soc. Symp. Proc.,Vol. 869 (2005) 1.3.1.
5:15 PM - A12.4
Optical Readout in Pinpi’n and Pini’p Imagers: A Comparison.
Paula Louro 1 , Alessandro Fantoni 1 , Miguel Fernandes 1 , Manuela Vieira 1 , Joao Martins 1 , Guilherme Lavareda 2 3 , Carlos Carvalho 2 3
1 DEETC, ISEL, Lisbon Portugal, 2 DCM, FCT-UNL, Lisbon Portugal, 3 C1, IST, Lisbon Portugal
Show AbstractOptimized multilayer devices based on two different tandem configurations (ITO/pinpi’n/ITO and ITO/pini’p/ITO) are compared and tested for proper image recognition and color separation process. The design attempts to optimize the most important performance attributes of the imager which are the spatial resolution, the color sensitivity and the dynamic range. In both configurations the doped layers (40 nm) are based on a-SiC:H to increase image resolution and to prevent image blurring. To profit from the light filtering properties of the active absorbers, the intrinsic layer of the front diode is based on a-SiC:H (200nm) and the back one on a-Si:H (1000 nm). By switching between forward and reverse bias, and taking the photocurrent generated by an optically addressed scanner, image and colour recognition are simultaneously feasible in both configurations. In each one the effect of the applied voltage on the color selectivity and image intensity is discussed and supported by a self bias model and a numerical simulation. The relative spectral response curves demonstrate rather good separation between the basic colors red, green and blue. The position of the peaks within the spectrum as well as the bandwidth of sensitivity can be controlled by engineering the absorption layers (layer thickness, band gap and mobility-lifetime product). When compared with the signal without light impinging the front diode (dark) in the pinpi’n configuration and short circuit conditions, the red and blue signals are high and opposite in sign and the green signal is almost suppressed, allowing blue and red recognition. The green information is obtained under forward bias, when the blue signal goes down to zero and the red one remains constants. In the pini’p configuration the leakage current of the non-absorbing diode is the restrictive factor. Under reverse bias and red irradiation the red signal is suppressed while under forward bias and blue irradiation blue rejection is achieved. Under green light the signal is the same, either under forward or reverse bias. So, combining the information obtained under positive and negative applied bias a colour image is acquired, using the same technique either in pinpi’n or in the pini’p configuration, without colour filters or pixel architecture.In both configurations, band gap engineering and electrical field tailoring allows a voltage controlled shift of the collection regions. For each RGB wavelength, color discrimination is achieved at a readout voltage that cancels the forward or reverse self-bias induced by the impinging photons across the a-Si:H back absorber. A physical model supported by the electrical simulation gives insight into the methodology used for image representation and color discrimination.
5:30 PM - A12.5
Germanium-silicon Separate Absorption and Multiplication Avalanche Photodetectors Fabricated with low Temperature High Density Plasma Chemical Vapor Deposited Germanium.
Malcolm Carroll 1 , Kent Childs 1 , Darwin Serkland 1
1 , Sandia National Laboratories, Albuquerque, New Mexico, United States
Show AbstractA desire to monolithically integrate near infrared (NIR) detectors with silicon complementary metal oxide semiconductor (CMOS) technology has motivated investigation of poly-crystal and single crystal germanium on silicon (Ge/Si) heterostructures. A challenge to the integration of Ge, however, is the thermal budget required to produce high quality epitaxy (e.g., Tin-situ-clean > 780°C). High temperature is incompatible with the low temperature back-end of the CMOS process flow and represents a significant increase in complexity to integration if introduced parallel with the front-end of the transistor fabrication. Alternatively, it has been demonstrated that p+-Ge/n-Si detectors formed with low temperature poly-Ge (e-beam evaporation) or heavily dislocated single crystal germanium (molecular beam epitaxy, T~450°C) can be made with relatively low dark currents (~ 5 mA/cm2) and responsivities of ~15 mA/W at 1310 nm, despite the large number of defects in and at the Ge/Si interface. Low temperature epitaxial germanium growth with a higher through-put deposition technique (i.e., not MBE) combined with higher responsivity would be desirable improvements. In this paper, we evaluate a low temperature, ~450°C, high density plasma chemical vapor deposition (HDP-CVD) germanium epitaxy process for the fabrication of p+-Ge/p-Si/n+-Si NIR separate absorption and multiplication avalanche photodetectors (SAM-APD).The Ge/Si APD vertical structure consists of an HDP-CVD germanium epitaxy layer, grown at ~450°C with ~1010 cm-2 dislocations, on a (100) p-/n+ silicon epi-wafer. This results in a 20 nm p+-Ge (~2x1018 cm-3) / 400 nm p--Si (~1x1015 cm-3)/n+-Si (~1018 cm-3) vertical stack. Germanium islands were formed by dry etch and a 700°C, 1 hour, N2 anneal was used to activate a boron top contact implant in the germanium island. Both n+-Si and p+-Ge were contacted using Ti/TiN/W plugs through a ~1000 nm thick oxide measured above the silicon after planarization. The SAM-APDs show increased NIR photoresponse at a “punch-through” voltage bias corresponding to full depletion of the p--Si barrier. When the detector is biased slightly above punch-through the dark current density is ~ 0.2 mA/cm2 and the 1310 nm responsivity is found to be ~ 0.5 mA/W. The photocurrent is found to increase 200 times, unambiguously greater than the multiplied dark current, before breakdown ~27V. The device behavior is similar to that predicted numerically indicating that the photomultiplication can be understood as photoexcited electrons being injected into the high avalanche gain silicon. This demonstrates the potential to increase the responsivity in Ge/Si devices with internal gain. Finally, Geiger mode operation of the APDs will also be discussed. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.
5:45 PM - A12.6
Modeling and Characterization of the Hydrogenated Amorphous Silicon Metal Insulator Semiconductor Photosensors for Digital Radiography.
Nader Safavian 1 , Arokia Nathan 2 , Gregory Heiler 3 , Timothy Tredwell 3
1 ECE, university of waterloo, Waterloo, Ontario, Canada, 2 ECE, London Centre for Nanotechnology, London United Kingdom, 3 , Eastman Kodak Company, Rochester, New York, United States
Show AbstractN. Safavian, Y. Vygranenko, J. Chang, Kyung Ho Kim, D. Striakhilev, A. Nathan , G. Heiler, T. TredwellThe most common method for x-ray detection is the conversion of the incident x-ray photons to visible light through a phosphor screen and detection of the light photons by a light sensitive film. This system has been used by radiologists for more than a century. The main drawbacks of this system are storage complexity and digital incompatibility. Amorphous silicon active matrix flat panel x-ray detectors using embedded photosensor and hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) circuits as backplane electronics can be a reasonable replacement for this traditional method.This stems from the desirable characteristics of the a-Si:H technology including low fabrication cost, uniformity over large area, industrial accessibility, and low temperature fabrication for ultimate flexible electronics. The migration from conventional film-based x-ray imaging techniques to fully integrated detector panels offers the potential to high quality digital images, as well as to advanced medical image management, computer-aided and diagnosis.In case of indirect flat panels, there are two distinct possibilities for choosing the photosensor: PIN and MIS. The major advantage of the MIS photosensor over PIN is that the photosensor and the TFT switch can be fabricated simultaneously and with similar layers. This results in effective reduction in the number of required masks. Contrary to PIN, The MIS photosensor does not need P-layer. This characteristic makes the sensor more desirable in terms of fabrication in general purpose fabrication facilities used for producing large area TFT displays. This paper will investigate the feasibility of using MIS photosensors integrated with TFT switches for Digital Radiography. First the fabrication of MIS photosensors on different substrates is discussed followed by the results obtained from transient tests aimed at extracting information about the dark current and photocurrent of the MIS sensor. Measurement experience on the fabricated samples show that the accumulated dark charge density reaches 6×1010 electrons/cm2 for 2 seconds integration time and the sensitivity is 1.8×1012 electrons/cm2-sec. Effective ways to reduce the dark current including changing the time duration and bias amplitude are investigated. The capacitive-voltage(C-V) behavior has been employed to extract the impedance of the MIS photosensor in different modes of operation. The capacitance of the test structures decreases from 26.8 nF/cm2 in refresh mode to 15.3nF/cm2 in integration mode. These results are used to represent the structure with a simple small signal model which is useful for the Verilog modeling of the sensor. Comparison of the measurement results with the requirements of the standard Digital Radiography system demonstrates the feasibility of using MIS photosensors in this type of medical imaging modality.
A13: Crystallization Techniques I
Session Chairs
Thursday AM, April 12, 2007
Room 3001 (Moscone West)
9:30 AM - **A13.1
Disk-shaped Grain Growth of Amorphous Silicon.
Jin Jang 1
1 Department of Information Display , Kyung Hee University, Seoul Korea (the Republic of)
Show AbstractTwo kind of grain growth, needle-like and disk-shaped, can be possible with Ni mediated crystallization of amorphous silicon. The structures of the crystallized films together with the crystallization conditions giving the disk-shaped grain growth were studied. The performance of the TFTs with the disk-shaped grain poly-Si is much better than that of needle-like poly-Si. The p-channel TFT exhibited a field-effect mobility of higher than 100 cm2/Vs and stable operation under hot carrier bias-stress. The method to get good poly-Si on glass by non-laser crystallization will be discussed on the based on our experimental data.
10:00 AM - A13.2
Attainment of Intragrain-Defect-Free and {100}-Surface-Oriented Single-Crystal Si Islands for Ultra-High-Performance TFTs.
P. Van der Wilt 1 , B. Turk 2 , A. Chitu 1 , U. Chung 1 , A. Limanov 1 , James Im 1
1 Program in Materials Science and Engineering, Department of Applied Physics and Applied Mathematics, Columbia University, New York, New York, United States, 2 , Coherent, Inc., Santa Clara, California, United States
Show AbstractThe device characteristics of Si-based TFTs on glass substrates are ultimately dictated and limited by the microstructural integrity of the material from which they are fabricated. For this reason, much work has been devoted in order to improve the quality of Si films by reducing the density of structural defects. Over the years, several glass-substrate-compatible approaches have been demonstrated for creating low-defect-density regions that are at least devoid of any random high-angle grain boundaries and are furthermore sufficiently large to permit placement of small TFTs inside. Thus far, however, these materials possess certain microstructural deficiencies that prevent them from being fully qualified as ideal materials that would permit realization of ultra-high-performance TFTs. The major remaining challenges can be identified as: (1) the control and optimization of the surface orientation as well as (2) the elimination of intragrain planar defects such as subboundaries, twin boundaries, and stacking faults. As these factors are certain to lower the level of device performance and are also potentially capable of substantially degrading the overall device uniformity, it is imperative that they are addressed.In this paper, we report on results we have obtained from a sequential lateral solidification (SLS)-based hybrid crystallization method that is demonstrated to be not only effective at producing large {100} surface-oriented Si regions (i.e., the preferred surface orientation for n-channel devices), but is furthermore yielding single-crystal domains that are essentially free of intragrain planar defects. While the orientation-control capability was expected from this method, as it was designed to this end, its capability to produce intragrain-defect-free single-crystal domains was beyond original expectations.The method as implemented in the present work utilizes a particular SLS scheme referred to as dot-SLS to process a precursor polycrystalline Si film with strong (100) texture, prepared, in turn, via “mixed-phase” zone-melting recrystallization of an as-deposited amorphous Si film. Experimental details include: 100 nm Si films deposited on quartz substrates irradiated using an excimer-laser-based SLS system (308 nm, ~200 nsec) after being scanned using a 2ω-DPSS continuous-wave laser (532 nm). In addition to providing a detailed description of the method and the resulting microstructure (via TEM, SEM, EBSD and AFM analysis), we will also elaborate on those fundamental physical factors that contribute to these results (such as the orientation-dependent defect-formation mechanisms during lateral solidification of Si films). We will also comment on how such a process might be integrated into SLS systems presently being utilized for manufacturing of large-area electronics and the suitability of the approach and the material for being employed in advanced microelectronics.
10:15 AM - A13.3
An Approach to Obtain Single Layer of Nanostructured Si by Laser Irradiation on Ultrathin Amorphous Si Films.
Jun Xu 1 , Zhanhong Cen 1 , Wei Li 1 , Xinfan Huang 1 , Kunji Chen 1
1 Department of Physics and National Laboratory of Solid State Microstructures, Nanjing University, Nanjing210093 China
Show AbstractRecently, Si nanostructures have attracted much attention because of their potential applications in future optoelectronic and nanoelectronic devices. From the viewpoint of device applications, it is very important to develop an approach to obtain the dense and uniform Si nanostructures with controllable size and position. The used techniques must be compatible with the modern Si semiconductor technology. Moreover, it is also desirable to achieve the Si nanostructures on the insulating layers such as SiO2 or SiNx films.So far, many approaches have been proposed to fabricate semiconductor nanostructures, especially nc-Si films. For example, nc-Si embedded in SiO2 was usually prepared by implantation of Si ions into SiO2 films with subsequently high temperature annealing or by directly annealing the substoichiometric SiOx (x<2) films. In this work, an approach to achieve single layer of nanostructured Si array on insulating layer with high density was demonstrated. It was found that a single layer of nanocrystalline Si array can be formed by using KrF pulsed excimer laser irradiation on ultrathin hydrogenated amorphous silicon films (4-20nm) followed by thermal annealing. Under the suitable fabrication conditions, the areal density of formed nanocrystalline Si is as high as 10^11cm^-2 and the lateral size is around 10nm while the height is about 2-4 nm as revealed by AFM and TEM images. By controlling the laser irradiation fluence and the initial a-Si:H film thickness, the grain size, density and crystallization fraction can be changed accordingly. The size of nanocrystalline Si can be confined uniformly when the film is thinner than 15nm, which results in the formation of monolayer Si nanodots. Visible light emission was observed from the obtained Si nanodots at room temperature and the luminescence peak is varied from 660 to 725 nm with increasing the amorphous Si film thickness. The variable luminescence can be attributed to the interface state assisted radiative recombination rather than the quantum size effect.This work is financially supported by National Natural Science Foundation of China (Grant Nos.60425414, 50472066, 90301009) and NSF of Jiangsu province (BK2006715).
10:30 AM - A13.4
Rapid Crystallization of Amorphous Silicon Utilizing the Plasma Annealing at Atmospheric Pressure.
Hajime Shirai 1 , Yusuke Sakurai 1 , Mina Yeo 1 , Tomohiro Kobayashi 2
1 The Graduate School of Science and Engineering, Saitama University, Saitama Japan, 2 , The Institute of Physics and Chemical Research, 2-1 Hiriosawa, Wako Japan
Show AbstractThe rapid crystallization of amorphous silicon (a-Si) utilizing an argon thermal microplasma jet is presented. Highly crystallized Si films were synthesized by adjusting the translational velocity of the substrate stage and flow rate of argon. In addition to the rapid crystallization of a-Si, the activation of phosphorus and boron impurities was promoted. The field effect transistor of a 40-nm-thick crystallized a-Si film showed a field effect mobility of 30-55 cm2/Vs and threshold voltage of 3-5 V. P-i-n crystallized a-Si thin-film solar cells were also fabricated for 1.5-μm-thick crystallized a-Si films, which showed an efficiency of 5.5% and filled factor of 0.52. Transient optical reflectance and conductance measurements revealed that the surface temperature reached ~1400C within 3-5 ms and that the crystallization proceeded with a time constant of 10-30 ms. Crystallization process of a-Si using the VHF thermal microplasma jet is discussed in terms of the viscous flow of the Si-network due to the rapid local heating and melting of a-Si.
10:45 AM - A13.5
High Efficiency Activation of Phosphorus Atoms Induced by Thermal Plasma Jet Crystallization of Doped Amorphous Si Films.
Hirotaka Kaku 1 , Seiichiro Higashi 1 , Tatsuya Okada 1 , Takuya Yorimoto 1 , Hideki Murakami 1 , Seiichi Miyazaki 1
1 Grad. School of Advanced Sciences of Matter, Hiroshima Univ., Higashi-Hiroshima Japan
Show AbstractCrystallization of doped amorphous Si (a-Si) films by ultra rapid thermal annealing technique is one of the most important technological issues for the fabrication of thin film transistors and ULSIs, where formation of low resistivity shallow junction for source and drain is strongly required. Recently, we have proposed the application of thermal plasma jet (TPJ) [1] to the millisecond thermal annealing and crystallization of a-Si films. On the basis of the noncontact temperature measurement technique we have developed [2], phase transformation of a-Si films occurs at a temperature ranging from 1098 to 1284 K with the duration of 0.2 to 1.4 ms [3].In this work, we have extended our research to the crystallization of doped a-Si films using TPJ annealing. The correlation between annealing condition and the activation of phosphorus atoms has been investigated. The details of he experimental set up for the crystallization by TPJ were reported in Ref. [1]. Doped a-Si films with a thickness of 52 nm were formed on quartz substrate from a capacitively coupled plasma of 7.4 % SiH4 and 0.5 % PH3 diluted with H2 at 0.1 Torr with the substrate heating at 250 °C. Samples were linearly moved in front of the TPJ with scanning speed ranging from 400 to 950 mm/s at input power ranging from 1.9 to 2.1 kW. The distance between the plasma source and the substrate was set at 3.0 mm. The substrate surface temperature during the annealing was measured by an optical probe method where the details of the measurement have been reported elsewhere [2].The a-Si films were crystallized by decreasing the scan speed below 950 mm/s. The electrical conductivity (σ) of the crystallized films increased from 9.1 x 102 to 1.6 x 103 S/cm with decreasing scan speed from 950 to 400 mm/s. Since the σ of non-doped Si films crystallized under same conditions is much smaller, it ranges from 6.1 x 10-7 ~ 8.4 x 10-8 S/cm, we confirm that the phosphorus atoms in the films are activated during the millisecond phase transformation. In the case of the sample with highest σ value, the maximum surface temperature and the annealing duration were 1750 K and 2.0 ms, respectively, and we confirmed that the film was melted and recrystallized. The carrier concentration estimated from the σ is 2.6 x 1020 cm-3, which is higher than the density of states at conduction band edge. This means that the films are degenerated and heavily doped Si has been obtained. Application of TPJ to the crystallization and activation of phosphorous doped a-Si films is very effective and promising doping technique. A part of this work is supported by the Industrial Technology Research Grant Program in 2005 from New Energy and Industrial Technology Development Organization (NEDO) of Japan.[1] H. Kaku, et al., Appl. Surf. Sci. 244(2005)pp.8-11.[2] T. Okada, et al., Jpn. J. Appl. Phys. 45(2006)pp.4355-4357. [3] H. Kaku, et al., Proc. International TFT Conference, 2006. (Kitakyushu, Jappn., Jan. 19-20, 2006)pp.214-217.
A14: Thin Film Transistors II
Session Chairs
Thursday PM, April 12, 2007
Room 3001 (Moscone West)
11:30 AM - **A14.1
Thin Film Structure Manipulation and Material Engineering for High Performance Poly-Si TFTs.
Tolis Voutsas 1
1 LCD Process Technology Lab, Sharp Labs of America, Camas, Washington, United States
Show AbstractHigh performance poly-Si TFTs with high mobility and low threshold voltage are needed for the increasingly demanding requirements of coming SOP (System-on-Panel) generations. Studies have shown that advances in formation methods can significantly elevate the crystal quality of the resulting thin poly-Si films. However, some sort of performance plateau appears to have been reached, demanding a leap-frog style improvement towards SOI-like material. Such improvement will require the precise engineering of the poly-Si microstructure including defect and texture control over large areas. In this work, we will discuss efforts towards such goal and the current level of achievement. Methods to manipulate and engineer the microstructure of poly-Si films will be presented and their effectiveness assessed. Metrics of success will be defined in terms of performance & variation of device characteristics, as well as process practicality. Efforts to compensate for material inefficiencies by device design will also be presented and discussed.
12:00 PM - A14.2
Nanocrystalline Si Film Fabricated by Inductively Coupled Plasma Chemical Vapor Deposition at Room-temperature for Thin Film Transistor.
Jung Ji-Sim 1 , Park Kyung Bae 1 , Lee Sang Yoon 1 , Kwon Jang Yeon 1
1 Display Device & Material Lab, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of)
Show AbstractNanocrystalline silicon (nc-Si) thin films prepared at low temperature have attracted significant attention for next generation flat panel display such as AMOLED TV. Nc-Si at low temperature could reduce cost of flat panel display. Because low temperature process make substrate change from conventional soda-free glass to cheap glass (sola-lime glass) or plastic substrate and nc-Si could be form without any addition process like laser or furnace annealing. In the view point of TFT performance, nc-Si film had higher mobility and stability compared with a-Si film. This performance increase output current which is sufficient to drive OLED material and reduce capacitance charging time for high speed driving of AMLCD TV. In our experiment, nc-Si film was successfully deposited by ICP-CVD under the various gas dilution conditions at the room temperature. ICP-CVD may provide a certain advantages such as high deposition rate and improved crystallinity of nc-Si film, can be employed for fabrication of high quality nc-Si TFTs. ICP-CVD employs remote plasma, this reduces troublesome ion bombardment problems issues. It is important to note that ICP-CVD generates high density plasma. The pressure was kept low (30~60mtorr) during the deposition and the RF power applied to reactor was 1kW. The flow rate of He was varied from 20sccm to 100sccm and that of SiH4 was 2sccm. The crystalline volume fractions (C.V.F.) of the nc-Si film by the raman spectrometry were 37at.%, and the grain size measured by the scanning electron microscopy (SEM) was in the range of 30nm. The C.V.F. decreased with the pressure and gas flow rate, indicating that the crystalline quality is improved when gas flow rate and pressure is decreased. Plasma density also decreased with the pressure during the deposition and gas flow rate. The high plasma density (>5x1010cm-3) with a low-potential was generated by process condition in ICP CVD. It will make the high silicon reactive species density, nucleation by the chemical annealing effect and the suppression of ion damage from the plasma to form nc-Si in deposition process. Also, it is reported that high hydrogen dilution in the silane plasma can induce a microstructural change from amorphous to ordered structures even at low temperatures, 300°C thereby producing nc-Si:H. A variety of models has been proposed to explain the role of atomic hydrogen in crystallite formation at low temperatures. On the other hand, we deposited poly si film using a silane and He or Ar mixture with no hydrogen dilution by high density plasma.Finally, coplanar TFTs with 200nm nc-Si channel layer were fabricated. The performance of TFTs were measured at a field effect mobility (μfe) of 30cm2/Vs, a threshold voltage (VT) of 2 V, a subthreshold slope (S.S.) of 0.25 V/dec. and ON/OFF current ratio of over 106. It indicated that nc-Si film deposited by ICP CVD at R.T. could be suitable for active layer of low coat and large area electronic to flat panel displays.
12:15 PM - A14.3
Drain bias dependent pulsed stress in a-Si:H TFT for AMOLED display
Jae-Hoon Lee 1 , Sang-Geun Park 1 , Sang-Myeon Han 1 , Sun-Jae Kim 1 , Min-Koo Han 1
1 Electrical Engineering and Computer science, Seoul National University, Seoul Korea (the Republic of)
Show Abstracta-Si:H TFT has attracted a considerable attention as pixel elements for AMOLED due to an excellent uniformity up to large area. It is well known that the electrical stability of a-Si:H TFT is rather poor. When a positive gate and drain bias is induced, VTH of a-Si:H TFT increases over the stress time. Recently, we have reported that the negative gate bias annealing can cure a degraded a-Si:H TFT due to the hole trapping into SiNx gate insulator. When a negative bias annealing is applied to a-Si:H TFT pixel, the gate electrode of a-Si:H TFT is subjected to the pulsed stress rather than DC negative gate bias stress due to an emission of OLED. The pulsed stress is induced to the gate electrode of the current driving a-Si:H TFT with the drain bias. While pulsed stress for LCD application was previously reported, the drain bias was not considered due to the small (~3V) drain bias for driving LCD.The purpose of our work is to report the drain bias dependent pulsed stress in a-Si TFT for AMOLED backplane. The pulse width dependent VTH shift is also measured and analyzed. An a-Si:H TFT is fabricated by a standard 5-mask process. When a positive pulse is applied to the gate, the resistance of a-Si film is sufficiently low so that the τ (time constant) is the order of μsec. In case of the negative pulsed stress, that the τ is increased up to the order of msec. VTH shift in the negative bias annealing is dependent on the negative bias pulse width. VTH shift of the DC gate bias (VGS=15V, VDS=0V) after 20,000sec is 0.885V. In case of the pulsed stress, VTH shift can be considerably reduced due to the hole trapping into the gate insulator during the negative bias stress. The effective stress duration in the pulsed stress is the positive bias duration in the DC stress for a fairly comparison. When a negative pulse width is increased from 16msec to 5sec, VTH shift without drain bias (VDS=0V) is reduced from 0.601V to 0.44V. These values are 68% and 50% of VTH shift in the DC gate bias stressed sample, respectively.When a drain bias is induced, VTH shift of the DC gate bias (VGS=15V, VDS=15V) after 20,000sec is 0.418V. It is smaller than the DC gate bias with VDS=0V due to decreased electron concentration with increasing drain bias. When the negative pulse width is increased from 16msec to 5sec, VTH shift with drain bias (VDS=15V) is reduced from 0.162V to -0.051V. These values are 39% and 0% of VTH shift in the DC gate bias stressed sample, respectively. When a drain bias is increased from 0V to 15V, VTH shift in the negative bias annealed can be reduced from 0.44V to -0.051V due to large (-30) VGD (VG=-15, VD=15). Large negative VGD accumulates more holes so that a hole trapping into SiNx gate insulator is accelerated. When the pulsed stress is applied to the gate electrode of a-Si:H TFT, the drain bias can reduce VTH shift due to the large negative VGD. The negative bias annealing for a-Si:H TFT is favorable for AMOLED application.
12:30 PM - A14.4
Effect of SiNx Gate Dielectric Deposition Power on the Electrical Stability of a-Si:H TFTs.
Alex Kattamis 1 , I-Chun Cheng 1 , Ke Long 1 , Wagner Sigurd 1
1 Electrical Engineering and Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey, United States
Show AbstractIn flexible display backplanes, silicon nitride (SiNx) thin films often function as substrate passivation, gate dielectric, and as electrical insulation to the overlying display frontplane. Since it is used at so many levels of a flexible display structure, SiNx is an attractive tool for stress compensation in the thin-film transistor (TFT)/substrate structure. The built-in stress of SiNx films can be adjusted from tensile to compressive by going from low to high deposition plasma power [1]. Varying deposition plasma power also affects other SiNx properties besides built-in stress, including refractive index and thin film density. Many of the uses of SiNx can accept a range of these ancillary properties, but in its application as gate dielectric the electrical performance of SiNx and of its interface with the hydrogenated amorphous silicon (a-Si:H) channel layer are of overriding importance. Therefore we studied the electrical characteristics and the stability under gate bias stress of a series of a-Si:H TFTs made under identical conditions, except for variation in deposition power for the SiNx gate dielectric. The a-Si:H TFTs had a bottom gate, staggered top source-drain geometry, and were made at 150 degrees C by a standard PE-CVD process [2]. The a-Si:H TFTs were stressed under constant gate-bias at a range of gate voltages (up to 40V) and stress times (up to 10,000). An increase in deposition power for the SiNx dielectric was directly proportional to a decrease in threshold voltage shift and therefore a more stable TFT. This also correlated with an increase in density of the SiNx film. Also as the deposition power is increased, the refractive index of the film approaches the bulk value. We conclude that gate dielectrics need to be deposited at high plasma power to allow for electrically stable TFTs, and as a consequence, all stress compensation should only be done with the other SiNx layers in the structure.This work was sponsored by the US Display Consortium through the project on Amorphous TFT Backplane Processes on Clear Plastic Substrates.[1] I-C. Cheng, A. Kattamis, K. Long, J. C. Sturm, and S. Wagner. J. Soc. Info. Disp., 13/7, 563 (2005).[2]H. Gleskova and S. Wagner. IEEE Elec. Dev. Lett., 20, 473 (1999).
12:45 PM - A14.5
Noise Performance of High Fill Factor Pixel Architectures for Robust Large-Area Image Sensors using Amorphous Silicon Technology.
Jackson Lai 1 , Yuri Vygranenko 1 , Gregory Heiler 2 , Nader Safavian 1 , Denis Striakhilev 1 , Arokia Nathan 3 , Timothy Tredwell 2
1 Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, 2 , Eastman Kodak Company, Rochester, New York, United States, 3 London Centre for Nanotechnology, University College London, London United Kingdom
Show AbstractLarge-area digital image sensors are revolutionizing medical imaging by enabling electronic storage capability, immediate feedback, and possibilities to support previously unachievable applications related to computer aided image processing. Large area digital imaging made possible by amorphous silicon thin-film transistor (a-Si TFT) technology, coupled with a-Si photo-sensors, provides an excellent readout platform to form an integrated medical image capture system.In conventional imaging array design where the thin-film transistor (TFT) and photo-sensor in a pixel are placed side by side on the same plane, the fill-factor, signal-to-noise ratio and dynamic range are limited. An alternative approach is a vertically integrated high fill factor architecture where the photo-sensor is implemented as segmented [1] or non-segmented continuous layer [2]. In this paper, we propose several novel segmented high-fill factor array architectures with reduced parasitic coupling. We evaluate these pixel architectures in terms of signal propagation timing, noise performance, and manufacturability, and compare them with conventional planar and continuous sensor pixel architectures. The analysis will consider various substrate options including glass and robust substrates such as polymer and metal foil. We will discuss design tradeoffs and benefits for proposed array architectures with respect to substrate options. Our evaluation have shown that electronic noise under 2000 electrons can be achieved with 150 μs frame time for a 2333x2867 imaging arrays on robust substrate.The results of this work demonstrate advancements to present state-of-the-art large area digital radiographic detectors, to pave the way for better image resolution.[1] “Performance analysis of a 127-micron pixel large-area TFT/photodiode array with boosted fill factor,” Weisfield, Richard L;, Yao, William; Speaker, Tycho; Zhou, Kungang; Colbeth, Richard E.; Proano, Cesar, J. Proceedings of the SPIE, Vol. 5368, pp. 338-348 (2004).[2] “Two Dimensional Amorphous Silicon Image Sensor Arrays,”, R.A. Street, X.D. Wu, R.L. Weisfield, S. Ready, R. Apte, M. Nguyen, and P. Nylen, MRS Symp. Proc. 377, p. 757, 1995.
A15: Solar Cells II
Session Chairs
Thursday PM, April 12, 2007
Room 3001 (Moscone West)
2:30 PM - **A15.1
Status of nc-Si:H Solar Cells at United Solar and Roadmap for Manufacturing a-Si:H and nc-Si:H Based Solar Panels.
Baojie Yan 1 , Guozhen Yue 1 , Subhendu Guha 1
1 , United Solar Ovonic LLC, Troy, Michigan, United States
Show AbstractHydrogenated nanocrystalline silicon (nc-Si:H) as a narrow bandgap material has been used in the bottom cell of amorphous silicon (a-Si:H) based multi-junction solar cells because of its superior long wavelength response, low light-induced degradation, and potential reduction of the manufacturing cost. At United Solar, we have been studying nc-Si:H solar cells since 2002 and have made significant progress. We have achieved an initial active-area cell efficiency of 15.1% using an a-Si:H/a-SiGe:H/nc-Si:H triple-junction structure, a stable active-area cell efficiency of 13.3% using an a-Si:H/nc-Si:H/nc-Si:H triple-junction structure, and a stable aperture-area (460 cm2) module efficiency of 9.5% using an a-Si:H/nc-Si:H double-junction structure. We shall discuss research efforts to increase the efficiency further. We shall compare the advantages and disadvantages of using nc-Si:H for substituting a-SiGe:H in the bottom cell in terms of cell efficiency and manufacturing feasibility. We shall also discuss the three key requirements for introducing nc-Si:H in our roll-to-roll manufacturing process. First, solar cells with nc-Si: H in the bottom cell should show a higher efficiency than the conventional a-Si:H/a-SiGe:H/a-SiGe:H triple-junction cells. Second, the large-area uniformity of nc-Si:H needs to be improved to satisfy the high module efficiency requirement and aesthetic appearance of the product. And third, the deposition rate needs to be increased significantly to maintain production throughput without increasing the machine cost. We shall discuss our current activities to address these issues.
3:00 PM - A15.2
Advanced Deposition Phase Diagrams for Guiding Si:H-Based Multijunction Solar Cells.
Jason Stoke 1 , Nikolas Podraza 1 , Xinmin Cao 1 , Xunming Deng 1 , Robert Collins 1
1 Department of Physics and Astronomy, University of Toledo, Toledo, Ohio, United States
Show AbstractIn situ, real time growth and optical property analyses of hydrogenated amorphous silicon (a-Si:H), amorphous silicon-germanium alloys (a-Si1-xGex:H), and nanocrystalline silicon (nc-Si:H) by plasma-enhanced chemical vapor deposition (PECVD) have been performed, and correlations of the results with solar cell performance have been investigated. The motivation of this investigation is to develop and apply advanced deposition phase diagrams for guidance in the multistep fabrication of the i-layers of triple junction solar cells in the n-i-p configuration, as has been first demonstrated for single junction a-Si:H solar cells in the p-i-n configuration.1 Significant advances have been made possible by using (i) a multichannel spectroscopic ellipsometer spanning a very wide spectral range (0.75 - 6.5 eV); (ii) optical modeling that includes improved optical property parameterization for the band gap and broadening parameter(s) associated with the optical transition(s), and a two-layer virtual interface approach for the evolution of the crystalline volume fraction, all in conjunction with (iii) state-of-the-art triple junction n-i-p solar cell fabrication using very-high-frequency (70 MHz) PECVD for elevated rates as well as mixtures of Si2H6+GeH4 for optimum a-Si1-xGex:H. As a result of the advanced analyses and the ability to correlate closely with devices, the deposition phase diagrams are now given in terms of constant contours of crystalline volume fraction in the plane of the hydrogen dilution ratio R and the film thickness db. For ease of analysis in these new studies, the optical beam was reflected from solar cell structures fabricated starting with an a-Si:H n-layer on smooth c-Si/native-oxide substrates. For correlations of the advanced deposition phase diagrams obtained on these substrates with state-of-the-art device performance, additional cell structures were co-deposited on textured Ag/ZnO back-reflectors. Excellent correlations between the In situ, real time analyses and the device performance suggest that the a-Si:H n-layer is effective in erasing the memory of the starting substrate and that the macroscopic texturing does not significantly influence the phase evolution. Correlations for the top a-Si:H cell show that the optimum R is higher for the bulk a-Si:H of the i-layer than it is for the topmost i/p interface -- suggesting strategies for two step (and multistep) processing. Further research is being conducted to apply the advanced phase diagrams for incorporation of controlled fractions of nanocrystallites into the bulk amorphous i-layer.*Research supported by NREL TFPPP Subcontract No. ZXL-5-44205-06.1. For a review see: R.W. Collins, A. Ferlauto, G. Ferreira, C. Chen, J. Koh, R. Koval, Y. Lee, J. Pearce, and C. Wronski, Solar Ener. Mater. Solar Cells 78, 143-180 (2003).
3:15 PM - A15.3
Triple Junction n-i-p Solar Cells with Hot-Wire Deposited Protocrystalline and Microcrystalline Silicon.
Ruud Schropp 1 , Hongbo Li 1 , Ronald Franken 1 , Jatindra Rath 1 , Karine van der Werf 1 , Jan Willem Schuttauf 1 , Robert Stolk 1
1 Faculty of Science, SID - Physics of Devices, Utrecht University, Utrecht Netherlands
Show Abstract3:30 PM - A15.4
High Rate Deposition of Amorphous Silicon Based Solar Cells Using Modified Very High Frequency Glow Discharge.
Guozhen Yue 1 , Baojie Yan 1 , Laura Sivec 1 , Jeffrey Yang 1 , Subhendu Guha 1
1 , United Solar Ovonic LLC, Troy, Michigan, United States
Show AbstractA high deposition rate for making thin film solar cells is always desirable to enhance the throughput and reduce the production cost. However, a-Si:H solar cells made with the conventional radio frequency (RF) glow discharge at high rates exhibit poor quality. The materials contain high densities of defect, microvoids, and di-hydride structures, which lead to a low initial cell efficiency and poor stability after prolonged light soaking. New deposition techniques are needed for increasing the deposition rate without compromising the material quality. Recently, very high frequency (VHF) glow discharge has been widely used in the deposition of a-Si:H and nc-Si:H materials and devices. Compared to the conventional RF technique, at a similar deposition rate, VHF plasma has higher electron density, higher ion flux, and lower ion energy, resulting in a higher deposition rate and an improved material quality. In this paper, we report our recent results on the high rate deposition of a-Si:H based solar cells using the modified VHF (MVHF) technique. a-Si:H and a-SiGe:H component cells with an nip structure were made on bare stainless steel (SS) and Ag/ZnO coated SS substrates at different deposition rates. We found that for a-Si:H top cells, both the initial cell performance and stability are independent of the deposition rate in the range of 1 to 14 Å/s. This phenomenon is different from a-Si:H cells made using RF at high rates. In the RF cells, the degradation rate usually increases, and the cell performance decreases with increasing deposition rate. The a-SiGe:H component cells deposited with MVHF at high rates show a higher light-induced degradation rate than the similar cells made with RF glow discharge at a low rate. The possible mechanisms causing the different behaviors will be discussed. a-Si:H/a-SiGe:H double-junction and a-Si:H/a-SiGe:H/a-SiGe:H triple-junction solar cells were deposited on Ag/ZnO or Al/ZnO coated SS substrates. By combining the optimized component cells made at 10 Å/s, an a-Si:H/a-SiGe:H double-junction solar cell on Ag/ZnO coated SS with an initial efficiency of 11.7% has been obtained. We will also present data for high efficiency triple-junction cells, and discuss the feasibility of using high rate MVHF deposition in production.
3:45 PM - A15.5
Fabrication and Optimization of a-Si:H n-i-p Single-junction Solar Cells with 8 Å/s Intrinsic Layers of Protocrystalline Si:H Materials.
Xinmin Cao 1 , Wenhui Du 1 , Yasuaki Ishikawa 1 , Xianbo Liao 1 , Robert Collins 1 , Xunming Deng 1
1 Department of Physics and Astronomy, University of Toledo, Toledo, Ohio, United States
Show AbstractAt the University of Toledo (UT), we investigated hydrogenated amorphous silicon (a-Si:H) n-i-p solar cells with intrinsic layers deposited at a high deposition rate of ~8 Å/s using our UT multi-chamber load-locked PECVD deposition system with a VHF plasma density of ~ 0.2 W/cm2 and a frequency of 70 MHz. a-Si:H i-layers were grown by using various hydrogen dilutions. It is observed from the current-voltage (I-V) device performances that the open-circuit voltage (Voc) increases with the increase of hydrogen dilution; the Voc reaches a maximum value of 0.986 V and then decreases. Using Si:H phase diagram as guidance, this drop in Voc can be attributed to the transition region (protocrystalline regime) from an amorphous phase into a mixed amorphous-nanocrystalline (a + nc) phase included in the i-layer adjacent to the i/p interface. The Voc values of the solar cells with i-layers made near the protocrystalline regime are very sensitive to the hydrogen dilution ratio R[H2/(Si2H6)]. An initial efficiency of η = 9.99% (Voc = 0.986 V, Jsc = 13.98 mA/cm2, FF = 72.5%) was obtained. Quantum efficiency (QE) measurement has shown that blue light responses increase as the hydrogen dilution increases. Very good blue light spectral responses with QE values over 0.7 at λ = 400 nm have been obtained for a-Si:H cells made under a specified deposition condition, where the protocrystalline silicon materials were adjusted to be grown at the i/p interface region. The light-induced stability in efficiency was also improved for cells with protocrystalline materials made under high H2 dilution.
A16: Crystallization Techniques II
Session Chairs
Thursday PM, April 12, 2007
Room 3001 (Moscone West)
4:30 PM - **A16.1
Laser Crystallization of Silicon for Large Area Electronics
Toshiyuki Sameshima 1
1 , Tokyo University of Agriculture & Technology, Koganei, Tokyo, Japan
Show AbstractLaser crystallization of silicon is discussed for forming polycrystalline silicon thin films used to fabricate polycrystalline silicon thin film transistors (poly-Si TFTs). Laser-induced rapid heating is important for crystalline film formation with a low thermal budget. Structural and electrical properties of poly-Si films are discussed. Reduction of electrical active defects located at grain boundaries is essential for achieving poly-Si TFTs with high performances. The internal film stress is attractive to increase the carrier mobility. Recent development in laser crystallization methods with pulsed and continuous wave (CW) lasers is then reviewed. Control of the heat flow results in crystalline grain growth in the lateral direction, which is essential for fabrication of large crystalline grains. We will also report a crystallization method using a high power infrared semiconductor laser. High power lasers will be attractive for rapid formation of crystalline films over a large area.
5:00 PM - A16.2
Electrical Characteristics of Ni-metal induced lateral crystallization TFTs formed by Cu Induced Unidirectional Crystallization
Young-Su Kim 1 , Nam-Kyu Song 1 , Bong-Kwan Shin 1 , Min-Sun Kim 1 , Sang-Ju Lee 1 , Seung-Ki Joo 1
1 Material Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Show AbstractThin film transistors (TFTs) are essential for the active displays of liquid-crystal displays and for organic light emitting diodes. In addition, the characteristics of a flat panel display device, such as brightness, resolution, and image transport speed, are very much dependent on the electron mobility of TFTs, which in turn depends on the crystallinity of the silicon thin film substrate. Current laser annealing processes, however, suffer from non-uniform crystallinity, due to the inevitable scan overlap involved, as well as surface roughness, due to the liquid solid phase transformation of silicon. On the other hand, metal induced lateral crystallization (MILC) is a batch process so that there is no scan overlap. Besides, MILC does not require extra equipment, such as an expensive laser. For these reasons, MILC is generally agreed to be more appropriate for industrial application than laser techniques. Current MILC TFT, however, shows relatively high leakage current and low electron mobility comparing with those of laser poly TFT. Generally, the lateral crystallization phenomenon propagates from both sides of the source and drain at the same time so that the lateral crystal growth joint is to be formed at the center of the channel. This lateral crystal growth joint is supposed to contain a lot of silicides and crystalline defects such as micro twins etc. The lateral crystal growth joint, hence, is believed to be responsible for high leakage current and low electron mobility. In this work, the lateral crystal joint has been eliminated in the channel by a new method, utilizing the fact that Ni-MILC occurs abnormally fast when Cu is put in the vicinity of Ni. The electrical performance of thus fabricated MILC TFT has been compared with normal MILC TFT. The amorphous silicon thin films, each of 60 nm thickness, were deposited on a glass substrate using an low pressure chemical vapor deposition or a plasma enhanced chemical vapor deposition system. Silane gas was used as a source gas and hydrogen was used as a carrier gas. The substrate temperature was kept at about 450 °C. A Ni thin film of 10 nm thickness was deposited after the lithography for the lift off technique. A conventional tube furnace was used for MILC, which was carried out at the temperature of 550 °C in hydrogen ambient. Ni was deposited only one side of the channel, namely the source region, and Cu on the other side by sputtering. Other processes were carried out according to the common processes for TFT fabrication in a class 100 environment. It turned out that more than 30% reduction in the leakage current (about 10 pA) as well as the high electron mobility like 40 cm^2/Vsec could be obtained in MILC TFT without the crystal growth joint at the center of the channel. These values are thought to be quite acceptable for practical use.
5:15 PM - A16.3
Intra-grain Defect Characterization of Polycrystalline Silicon Layers Obtained by Aluminium induced Crystallization and Epitaxy.
Dries Van Gestel 1 , Ivan Gordon 1 , Lode Carnel 1 , Guy Beaucarne 1 , Jef Poortmans 1
1 , IMEC, Leuven Belgium
Show AbstractThin-film polycrystalline-silicon (pc-Si) solar cells on foreign substrates are a relatively new technology that aims at low-cost devices with energy conversion efficiencies above 10 %. Because of the high recombination rate at grain boundaries, grain size of the polysilicon layers is an important parameter for this technology. To obtain highly efficient pc-Si solar cells, a first milestone was to get columnar grains with a diameter in the order of 10-50 µm on foreign substrates. This was achieved by epitaxial thickening of a silicon seed layer made by aluminum-induced crystallization. Recently, we showed that solar cells made from pc-Si layers with very small grains of 0.2 µm had almost the same open-circuit values (Voc) as solar cells made from AIC-based pc-Si layers with grain diameters of up to 50 µm. Since the Voc of thin-film solar cells is a measure for the electronic quality of the absorber material, the quasi-independence of the open-circuit voltage on the grain size indicates that grain boundaries and grain size distribution are not the only factors limiting the electronic quality of pc-Si layers. We therefore investigated the electrical active intra-grain defects and report the results in this paper. We visualized the intra-grain crystallographic defects by defect etching and electron microscopy. Temperature-dependent electron beam induced current measurements (EBIC) were used to investigate the presence and behavior of the electrically active defects. Photoluminescence (PL) spectra at low temperatures were used to extend our insight in dislocation-related recombination in our polycrystalline layers. After defect etching, intra-grain defects were easily distinguishable from grain boundaries. An intra-grain defect density in the order of 109 cm-2 was found. EBIC images showed the same defect patterns as SEM images of defect-etched layers, indicating that the observed intra-grain defects are indeed active recombination sites. We used a model of Kveder et al. to explain the temperature-dependent contrast of the EBIC images in terms of recombination between shallow and contaminated deep level traps. This suggests that metal impurities are present in our layers, which was corroborated by TXRF (Total reflection X-Ray Fluorescence) measurements. PL spectra showed some of the known dislocation related D1-D4 peaks of silicon.We conclude that the intra-grain defects are electrically active and harmful for the electrical quality of the layers. Beside grain size distribution control, intra-grain quality improvement is a major topic for further investigation in the field of thin-film pc-Si devices, especially for those made by aluminum-induced crystallization.
5:30 PM - A16.4
Comparative Study of Solid-Phase Crystallization of Amorphous Silicon Deposited by Hot-wire CVD, Plasma-Enhanced CVD, and Electron Beam Evaporation
Paul Stradins 1 , Oliver Kunz 2 , David Young 1 , Yanfa Yan 1 , Yueqin Xu 1 , Robert Reedy 1 , Howard Branz 1 , Armin Aberle 2 , Qi Wang 1
1 , National Renewable Energy Laboratory, Golden, Colorado, United States, 2 , The University of New South Wales, Sydney, New South Wales, Australia
Show AbstractIn this work, we investigate both random crystallization (RC) and solid-phase epitaxy (SPE) of amorphous silicon (a-Si), comparing films deposited by hot-wire chemical vapor deposition (HWCVD), plasma-enhanced (PE) CVD, and electron-beam evaporation. The kinetics of both RC (in which crystallites nucleate and grow in the bulk of a-Si) and SPE (in which planar growth proceeds from a structurally coherent c-Si surface of (100) oriented polished silicon wafer) is monitored by in-situ reflectance spectroscopy [1], with structural analysis by transmission electron microscopy. We previously reported 4 times faster RC in HWCVD a-Si as compared to PECVD a-Si, despite similar deposition temperature and rates, void density, and residual hydrogen content [1, 2]. We find now that hydrogen-free e-beam a-Si films randomly crystallize at a similarly low rate as PECVD films. In contrast, the SPE rates in the e-beam and HWCVD a-Si are approximately equal, suggesting that the grain growth rates at least in the (100) direction are similar in both films. We conclude that there is some structural or compositional agent that increases only the random crystallization rate in HWCVD a-Si compared to e-beam and PECVD a-Si, apparently not related to the residual H. The propagation of the SPE crystalline front was found to slow dramatically in HWCVD films thicker than 0.5 micron [3]. We confirm that this effect is related to residual ~ 1019 cm-3 hydrogen: the SPE rate is independent of the film thickness in H-free e-beam deposited a-Si, as well as in HWCVD a-Si after prolonged dehydrogenation.The doping dependences of RC are compared in HWCVD, PECVD, and e-beam evaporated a-Si to gain deeper insight into factors that influence solid-phase crystallization. While phosphorus doping of PECVD a-Si:H is known to speed up the RC [4], we observe the opposite effect in HWCVD films. Boron doping has little influence on the RC rate in HWCVD a-Si. In e-beam evaporated a-Si no final conclusions can be drawn as yet, although our ongoing experiments suggest that crystallization is accelerated by B doping but delayed by P doping. Solar cell samples with the structure n+pp+ crystallized similarly as lightly doped layers of similar thickness, as confirmed by real-time spectroscopy which was used to detect a possible RC initiation layer. To fully evaluate the effect of dopants, a detailed SIMS study of dopants and residual impurities is presented. The implications of the observed doping dependences on device fabrication by thermal crystallization are discussed. This work is supported by DOE contract #DE-AC36-99G010337. 1.P. Stradins, D. L. Young, Y. Yan, et al., Appl. Phys. Lett. 89 (2006) 121921.2.D. L. Young, P. Stradins, Y. Xu, et al., Appl. Phys. Lett. 89 (2006) 161910.3.P. Stradins, Y. Yan, R. Reedy, et al., Mat. Res. Soc. Symp. A Proc. (2006).4.H. Fujiwara, J. Koh, Y. Lee, et al., Mater. Res. Soc. Symp. Proc. 507 (1998) 939.
5:45 PM - A16.5
Crystallization of Amorphous Si Nanowires Through Self-heating
Ali Gokirmak 1 , Nathan Henry 2 , Helena Silva 1
1 Electrical and Computer Engineering , University of Connecticut, Storrs, Connecticut, United States, 2 Electrical Engineering, Michigan Technological University, Houghton, Michigan, United States
Show AbstractIn recent years there has been a considerable effort in building thin film transistors (TFTs) on crystalline Si, instead of amorphous Si (a-Si), due to increased carrier mobility for higher performance and lower power large area electronics. Laser re-crystallization and metal induced crystallization techniques have been developed as possible approaches for crystallization. However, these re-crystallization techniques on large area films lead to poly-Si grain formation which results in significant device-to-device variations. Achieving single crystal Si on glass, or other alternative large scale substrates, will result in minimal device-to-device variations and higher carrier mobilities. CVD growth of Si nanowires using metal catalysts is one of the recent approaches for achieving crystalline Si on glass. However, this technique currently lacks good control on placement and orientation of the wires.In this work we have studied an alternative local thermal annealing technique for crystallization of a-Si nanowires through self-heating. A 75 nm thick phosphorus doped film of a-Si is deposited on 750 nm SiO2 on Si in a low pressure chemical vapor deposition (LPCVD) system. The film is patterned to form a-Si wires attached to large contact pads using optical lithography. The wire widths vary from 200 nm to 450 nm and lengths vary from 1 μm to 5.5 μm. The wires are released from the surface by partially removing the underlying oxide in buffered oxide etch, eliminating stress related factors from the experiments. Short, large amplitude voltage pulses are applied across the a-Si nanowires. Current–voltage (I-V) characteristics before and after pulsing the wires show a very significant change in resistance. The surface texture of the pulsed wires, as observed under SEM, is extremely smooth when contrasted to the pad areas and to wires prior to pulsing. The wires stay as thin ribbons or take a cylindrical form depending on the dimensions of the wires and the details of the electrical pulses.This technique utilizes very short time (~1 μs) pulses and results in local melting and re-solidification of wires while the substrate is kept at room temperature. Keeping the wire width smaller than the thermodynamically favored grain size enforces single crystal formation along the wire. Lithographically defined wires and the pads can be placed and oriented as desired. FETs can be built on these crystalline Si islands by using standard TFT processing techniques.Local heating of the wires with short pulses in oxygen ambient may be used for gate oxide growth while maintaining the substrate at room temperature. This would eliminate the need for deposition of gate insulator. A high quality silicon oxide would further enhance carrier mobility by minimizing interface traps and increase gate dielectric reliability leading to higher performance TFTs.Fabrication processes, results from different electrical pulsing schemes and possible device approaches will be presented.
A17: Poster Session: Thin Film Transistors
Session Chairs
Arokia Nathan
Jeffrey Yang
Friday AM, April 13, 2007
Salon Level (Marriott)
9:00 PM - A17.1
Dependence of Stability of a-Si TFT's Fabricated on Clear Plastic at 285°C on Gate Stress Voltage.
Bahman Hekmatshoar 1 , Kunigunde Cherenack 1 , Alexis Kattamis 1 , Sigurd Wagner 1 , James Sturm 1
1 Princeton Institute for the Science and Technology of Materials (PRISM), Department of Electrical Engineering, Princeton University, Princeton, New Jersey, United States
Show AbstractIn this abstract we report (i) the fabrication of TFT arrays on clear plastic at 285°C, and (ii) the dependence of the stability of the 285°C TFT's on clear plastic on the gate voltage for AMOLED applications. The stability of a-Si TFT's is more important for AMOLED backplanes than for AMLCD's for two reasons – the drive transistor in an AMOLED pixel operates in DC, and in most designs the OLED current depends directly and continuously on the TFT threshold voltage. An increase in the threshold voltage of the driving TFT's over the course of operation time reduces the OLED drive current and therefore decreases the brightness of the pixel. This is in contrast to AMLCD's, where the TFT is driven with low duty cycle pulses, and is used as a digital switch, making the circuit insensitive to threshold voltage shifts. This very high temperature (285°C) for TFT array fabrication on clear plastic is significant because it is well known that the PECVD growth of gate nitride at high temperatures reduces carrier trapping in the nitride, leading to improved device stability. The fabrication of a-Si TFT arrays at such high temperatures on flexible clear plastic is traditionally not possible because of substrate issues. Across gate fields from 2×105 to 2×106 V/cm, the devices are far more stable than those fabricated in our lab with a similar process at 150°C, and similar to those fabricated on glass at similar temperatures. For large gate fields (106 V/cm), typical of those in digital AMLCD applications, the extrapolated threshold shifts over 1 year of continuous DC operation are still on the order of 10V. At lower electric field (2×105 V/cm), however, we find that the gate dielectric results in a sharply lower threshold voltage drift, with extrapolated 1-year DC shifts only on the order of 1V. Array statistics and electrical pixel circuit performance consistent with these drive criteria will also be presented. We acknowledge DuPont for providing the substrates and USDC for support.
9:00 PM - A17.2
Microcrystalline Silicon Thin Film Transistors with High Deposition Rate Using Plasma Enhanced Chemical Vapor Deposition.
Kyung Bae Park 1 , Ji Sim Jung 1 , Jong Man Kim 1 , Sang Yoon Lee 1 , Jang Yeon Kwon 1
1 Display Lab, Samsung Advanced Institute of technology, Yongin-Si, Kyeong Gi-Do, Korea (the Republic of)
Show AbstractRecently, directed-deposited microcrystalline silicon(μc-Si) has been intensively introduced as attractive material for the TFT active layer. Compared to a-Si TFTs, μc-Si TFTs have demonstrated higher electron mobility and Active Matrix display for driving devices. However disadvantages of μc-Si are inhomogeneity due to a complex crystalline structure composed of grains, amorphous silicon layer and grain boundaries, which limit the transport properties and the TFT sizes. It is important to obtain higher crystalline Si layers on large size panel with high deposition rates for reducing the production costs of device. In addition, because of the large and well-established manufacturing base for a-Si TFTs, there is an overwhelming need for μc-Si TFTs fabricated using the conventional 13.56 MHz PE-CVD technique. In an effort to develop a high throughout process to fabricate a higher crystalline si using conventional PE-CVD with highly H2 diluted SiH4 plasma at 350oC. The μc-Si films were characterized using Raman scattering, UV reflectance, Scanning Electron Microscopy(SEM) and Transmission Electron Microscope(TEM). In order to observe high deposition rate and μc-Si of higher crystalline, the μc-Si films are grown by PE-CVD from variety process parameters with a substrate temperature 350oC. The improvement of both the deposition Rate and the crystalline volume fraction were measured when the plasma power increased. Also the deposition rate was characterized when hydrogen ratio decreased, pressure increased. And the crystalline volume fraction was increased when hydrogen ratio increased, pressure decreased. It is thought that plasma power and hydrogen ratio break silicon-hydrogen bonding effectively. They increase the number of nucleation site for crystalline growth. In consequence, nucleation of small crystallite occurs directly on the substrate. But the deposition rate was thought that high power and high pressure lead to maximum ion energies for deposition. The 100nm thick μc-Si channel layer showed as high as 10Å/sec. and a crystalline volume fraction of over 40% through high power, well fitted pressure and Hydrogen ratio. Both n-channel and p-channel thin film transistors are fabricated in a top-gated structure, which is adapted to the evolution of the μc-Si structure throughout its layer thickness. All process temperature was done below 200oC except μc-Si deposition at 350oC.This process produced μc-Si TFTs with both an electron mobility of 10.9cm2/Vs, a threshold voltage of 1.2V, a subthreshold slop of 0.5V/dec at n-channel TFTs and a hole mobility of 3.2cm2/Vs, a threshold voltage of -5V, a subthreshold slop of 0.42V/dec at p-channel TFTs without post-fabrication annealing. These results demonstrated the feasibility of a directly-deposited process and silicon TFT technology for flat panel electronics. Especially AMOLED in the flat panel display will be promising technology without additional capital investment in the manufacturing.
9:00 PM - A17.3
Back Channel Passivated Amorphous Silicon TFTs Fabricated at 3000C on a Clear Plastic Substrate.
Kunigunde Cherenack 1 , I-Chun Cheng 1 , Alex Kattamis 1 , Bahman Hekmatshoa 1 , James Sturm 1 , Sigurd Wagner 1
1 Dept. of Electrical Engineering and Princeton Institute for the Science and Technology of Materials (PRISM), Princeton University, Princeton, New Jersey, United States
Show AbstractWe have fabricated amorphous silicon thin-film transistors (a-Si:H TFTs) at 3000C on an optically clear plastic. To our knowledge this is the highest temperature that a-Si:H TFTs have been fabricated on a plastic substrate, and represents an increase from the previous highest fabrication temperature of 2800C [1]. Our motivation for pushing the process temperature to 3000C is that the quality and stability of a-Si:H TFTs improves with increasing processing temperature. Clear plastic films can be made that support a TFT process temperature of 3000C process, and we use them here. We begin with a description of the properties required from the plastic film substrate. Then we explain the substrate preparation prior to TFT fabrication, including annealing and substrate passivation. To keep the device structure intact during the thermal cycling associated with TFT stack deposition, the TFTs are fabricated with attention to stress compensation in the device films. Organic light emitting displays will need TFTs that are particularly stable in long-term operation. To establish a reliable baseline of data on electrical performance and gate bias-stress stability, in this work we are focusing on a-Si:H TFTs with silicon nitride back channel passivation. We describe the fabrication of the backchannel passivated TFTs at the maximum process temperature of 3000C, their electrical characteristics and bias-stress stability. We conclude with an evaluation of TFT process aspects that are specific to very high temperature and very thin substrate films.We gratefully acknowledge E.I. DuPont de Nemours for supporting this research and for providing substrate materials. This project is sponsored by the US Display Consortium.[1] Long, K.; Kattamis, A.Z.; Cheng, I.-C.; Gleskova, H.; Wagner, S.; Sturm, J.C., "Stability of amorphous-silicon TFTs deposited on clear plastic substrates at 2500C to 2800C," IEEE Electron Device Letters, vol.27, no.2, pp. 111- 113, Feb. 2006.
9:00 PM - A17.5
Effect of Channel Length and Drain Bias on Threshold Voltage of Field Enhanced Solid Phase Crystallization Polycrystalline Thin Film Transistor on the Glass Substrate
Won-Kyu Lee 1 2 , Sang-Myeon Han 1 , Sang-Geun Park 1 , Young-Jin Chang 2 , Kee-Chan Park 2 , Chi-Woo Kim 2 , Min-Koo Han 1
1 School of Electricl Engineering, Seoul National University, Seoul Korea (the Republic of), 2 LCD Business, Samsung Electronics Co. Ltd., Youngin-City, Kyunggi-Do, Korea (the Republic of)
Show AbstractIt is well known that hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs), which have a considerable attention as pixel elements for active matrix organic light emitting diode (AMOLED) due to an excellent uniformity up to large area. However, the electrical stability of a-Si:H TFT, such as threshold voltage (VTH) shift, is rather poor. Polycrystalline silicon (poly-Si) TFTs are stable to electrical bias, but current uniformity of poly-Si should be improved. Recently, field enhanced solid phase crystallization (FESPC) on the glass substrate is reported. FESPC poly-Si TFTs on the glass substrate gain a considerable attention for pixel element of AMOLED due to a better current stability than a-Si:H TFT, and a better current uniformity than poly-Si TFT. The purpose of our work is to report the VTH characteristics of p type poly-Si TFTs employing FESPC on the glass substrate at various channel length and VDS. We have fabricated top gate coplanar poly-Si TFT. Silicon oxide (SiO2) as buffer layer and a-Si layer were deposited on the glass substrate. The a-Si film was crystallized by FESPC under 700°C. After poly-Si islands were defined, SiO2 gate insulator was deposited and gate electrode was patterned. Next, ion doping is followed and inter-layer dielectric (ILD) was deposited. After contact holes are formed, source and drain (S/D) electrodes were patterned. Silicon nitride (SiNx) was deposited as a passivation layer. The width of channel is 5um and channel length is varied from 5μm to 18μm.We have measured I-V characteristics. When drain bias is -10.1V, VTH of 5μm and 18μm length are -5.22V and -6.58V, respectively. The difference of VTH (ΔVTH) is 1.36V which is rather large value. Although 5μm length is not short channel in the present TFT technology, reduction of VTH according to the channel length is distinguished in the FESPC p type poly-Si TFT. When VDS is changed from -0.1V to -20.1V, VTH is varied from -6.14V to -5.71V. The ΔVTH is 0.43V. The results show that VTH is decreased as the reduced channel length and with increasing VDS. For FESPC poly-Si film, its grain size is small, so that number of grain boundaries is much larger than low temperature poly-Si. Energy barrier at each grain boundary can be lowered by drain bias. As the channel length is decreased and VDS is increased, the energy barrier lowering effect in the FESPC poly-Si film is distinguished due to increased lateral electrical field. This energy barrier lowering in the whole channel results in the VTH reduction at shortened channel and elevated VDS.Our results show that the VTH of the TFT which have 5μm channel length is smaller than that of 18μm channel length by 1.36V, which is considerably large value. VTH of p type poly-Si TFT employing FESPC on the glass substrate is affected by channel length and VDS due to energy barrier lowering effect at the grain boundary in the FESPC silicon film by increased lateral electrical field.
9:00 PM - A17.9
Poly-si thin film transistor Fabricated by Nanoimprint Method.
Byung-Yong Kim 1 , Jin-Woo Han 1 , Young-Hwan Kim 1 , Jong-Yeon Kim 1 , Dong-Hun Kang 1 , Dea-Shik Seo 1
1 electrical and electronic engineering, Yonsei university, Seoul Korea (the Republic of)
Show AbstractA18: Poster Session: Solar Cells
Session Chairs
Arokia Nathan
Jeffrey Yang
Friday AM, April 13, 2007
Salon Level (Marriott)
9:00 PM - A:18 PosSolCells
A18.1 TRANSFERRED TO A15.5
Show Abstract9:00 PM - A18.10
A Comparison of Heat Transfer Characteristic of Mediums in a-Si Photovoltaic/Thermal Solar Collectors.
Thipjak Nualboonrueng 1 , Porponth Sichanugrist 1
1 ISET, National Science and Technology Development Agency, Pathumthani Thailand
Show AbstractThe objective of a-Si Photovoltaic/Thermal (PVT) solar collector is to use solar energy as much as possible. The advantages are converting solar energy into both electrical and thermal energy at the same time. The main part of a-Si PVT collector are a-Si solar module and metal plate. The two main part were conbined together with heat transfer dedium such as thermally epoxy or EVA laminated. The a-Si solar cell absorb the visible light and generates the electricity by photovoltaic phenomenal while the metal absorber plate in rear side absorb infrared light and generate heat. More advantage, the a-Si PVT solar collector can operate at high temperature without power loss. The heat is transferred to water as a working fluid that flowing in round cross-sectional copper tubes which is attached under the metalplate.At present, five systems have been installed to difference places, also, difference in applications. The first system, there have 3.07 kW electricity generation, 48 m2 PVT collector area and 2 ,500 litters produced hot water tank. Hot water has been supplied to industrial washers for cleaning infected suits. Second system, there have 2.7 kW electricity generation, 48 m2 PVT collector area and 2,500 litters produced hot water tank. Hot water has been used in the kitchen that is used for cooking and dish washing. Third system, there have 4 kW electricity generation, 40.6 m2 PVT collector area, 20 m2 PV area and 3,000 litters produced hot water tank. Also, hot water has been used for reduce the energy in kitchen. Forth system, there have 9.7 kW electricity generation, 152 m2 PVT collector area and 12,000 litters produced hot water tank. Hot water has been used for hydrotherapy swimming pool. The fifth system was in stalled in Chulalongkorn’s hospital with 5.5 kW electricity, 10,000 liter per day hot water produced.This study is concern about comparison of the heat transfer characteristic of mediums placed in inter-facing between a-Si solar cell and metal plate in a-Si Photovoltaic/Thermal solar collector such as heat transfer coefficient, changing of physical property of bonding materials before and after testing condition. The testing result can provide the suitable materials for PVT applications developers.
9:00 PM - A18.11
Hydrogen Passivation of Thin-film Polysilicon Solar Cells.
Lode Carnel 1 , Ivan Gordon 1 , Dries Van Gestel 1 , Guy Beaucarne 1 , Jef Poortmans 1
1 , imec, Leuven Belgium
Show AbstractOver the last decade, the production of photovoltaic modules has grown by an impressive annual growth rate of more than 30 %. This resulted in a significant shortage of solar grade silicon material and a sharp increase of the silicon feedstock price. Therefore, to reduce the cost price of photovoltaic energy, other technologies need to be developed that use less silicon.The ultimate silicon technology could be a thin (~ 5 µm) polycrystalline silicon layer deposited from the gas phase onto a foreign carrier substrate. Such a technology could lead to a sharp cost reduction while maintaining the efficiency and the stability of a fully crystalline Si absorber. However, current efficiencies are still well below those achieved in bulk silicon solar cells, mainly due to the large number of defects both in the grain and at the grain boundaries. To passivate these electronic defects, hydrogen is introduced into the layers.In this work we studied the hydrogen passivation of defects using both fine-grained (~ 0.2 µm grains) and coarse-grained (~ 5 µm grains) polysilicon. The passivation is carried out using two different methods: a hydrogen plasma treatment and a high temperature anneal of a hydrogenated silicon nitride (SiN:H) layer. Plasma hydrogenation offers an infinite amount of hydrogen, while the SiN:H is a solid source with a finite amount of hydrogen. The passivated layers were studied electronically by electron spin resonance, temperature dependent resistivity measurements and spreading resistance profiling. The amount of hydrogen incorporated in the layers was measured using secondary ion mass spectroscopy using deuterium as an easily traceable isotope of hydrogen. Finally, solar cells were made to compare the methods at device level.We found that both passivation methods reduced the number of dangling bonds in p-type fine-grained material by a factor of 3. The number of hydrogen atoms in the layer exceeded the number of defects by almost a factor of ten, suggesting that many hydrogen atoms are not bound to a defect. On device level, we found that a diffused n+ emitter blocked the penetration of hydrogen, resulting in a worse passivation. An alternative to such a homojunction emitter is to create an amorphous silicon emitter on top of the polycrystalline base. In that case, emitter formation occurs after passivation and therefore does not hinder the passivation. This yielded an increase of the open-circuit voltage (Voc) of 80 mV compared to a homojunction emitter. With the heterojunction emitter, the plasma hydrogenation clearly showed better results than the SiN:H hydrogenation alone. However, a combination of the SiN:H and the plasma treatment resulted in the best passivation. Despite a difference in grain size by a factor of 30, we obtained Voc values close to 540 mV for both fine-grained and coarse-grained polysilicon. These results clearly show the high potential of hydrogen passivation for solar cells made of thin polysilicon layers.
9:00 PM - A18.12
Photocurrent Profile in a-SiC:H Monolithic Tandem Pinpin and Pinip Photodiodes.
Alessandro Fantoni 1 , Joao Martins 1 , Miguel Fernandes 1 , Paula Louro 1 , Yuri Vygranenko 1 2 , Manuela Vieira 1
1 Electronics Telecommunication and Computer , ISEL, Lisbon Portugal, 2 Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada
Show AbstractWe present results about the analysis of the photocurrent in a-SiC:H pinpin and pinip tandem structures. It is well known in literature that, in order to optimize the light power conversion, the geometry of the cell and the thickness of the absorber layers must be adjusted to the light absorption profile. If there is a mismatch between the number of the electron-hole pairs generated in the sub-cells, the total collected current is limited by the sub-cell absorbing the lowest number of photons. We have found the photocurrent profile in these conditions to be dependent on the light absorption profile, which is, on the incident light wavelength and intensity. Our experiments and analysis reveal the photocurrent profile to have a strong nonlinear dependence on the externally applied bias in the range around to the open circuit value, indicating the superposition of different, concurring effects that lead the photocurrent to alternatively increase and decrease before finally entering in its secondary state.Our interpretation point out the cause of such effect to a self biasing of the bottom cell under certain unbalanced light generation of carriers and an asymmetric reaction of the internal electric fields to the externally imposed bias. The possibility to relate such a behavior to the light intensity and color, leave an open discussion on the possibility to use these structures and this effect for color recognition sensors. We present in this paper results about the experimental characterization of the photocurrent, numerical simulations with the program ASCA, curve fitting of the experimental data, and SPICE simulations based on the proposed equivalent model.Transport and optical modeling give insight into the internal physical process. Considerations about conduction band offsets, electrical field profiles and inversion layers will be taken into account to explain the optical and voltage bias dependence of the spectral responseResults show that in both structures the application of an external electrical bias (forward or reverse) mainly influences the field distribution within the less photo excited sub-cell. When compared with the electric field profile under thermo-dynamical equilibrium conditions, the field under illumination is lowered in the most absorbing cell, while the less absorbing one reacts by assuming a reverse bias configuration. Hence, opposite behavior is observed under red and blue background light while under green light condition the redistribution of the field profile is balanced between the two sub-cells and depends strongly on the tested configuration.
9:00 PM - A18.2
Novel Nanocrystalline Solar Cell
Vikram Dalal 1
1 Elec. and Computer Engr., Iowa State University, Ames, Iowa, United States
Show AbstractWe report on the design and fabrication of a novel nanocrystalline Si:H solar cell. The solar cell incorporates an amorphous i layer at the back of the nanocrystalline Si:H base n-type layer. The amorphous layer is incorporated to significantly enhance the absorption of light within the nanocrystalline layer. The amorphous layer is graded in bandgap so as to assist in collection of holes. The amorphous layer is placed within one diffusion length of the front p-n junction of the nanocrystalline cell, so that the holes generated within the amorphous layer can be collected by the nanocrystalline layer. The experimental results show that by incorporating such layers, the infrared QE of nanocrystalline Si cells is enhanced. The paper will discuss the physics of the cell including considerations related to electron affinity, diffusion length, choice of bandgaps, stability etc.
9:00 PM - A18.3
Development of Thin Film Microcrystalline Silicon Solar Cells with Hot-Wire CVD Intrinsic Layer
Hongbo Li 1 , Ronald Franken 1 , Robert Stolk 1 , C. van der Werf 1 , Jatin Rath 1 , Ruud Schropp 1
1 Surfaces, Interfaces and Devices, Faculty of Science, Utrecht University, Utrecht Netherlands
Show Abstract9:00 PM - A18.4
Resistive Losses at c-Si/a-Si:H/ZnO Contacts for Heterojunction Solar Cells.
Florian Einsele 1 , Phillip Rostan 1 , Uwe Rau 1
1 Inst. Phys. Electron., University Stuttgart, Stuttgart Germany
Show AbstractHeterojunctions made from amorphous Si contact layers applied to crystalline Si absorbers are one important technological option for high efficiency solar cells. When used as the Ohmic back contact, the heterojunction interface has to warrant simultaneously low recombination activity for the minority carriers as well as low resistivity for the majority carriers. The contribution concentrates on contacts on p-type c-Si absorbers. We show that a minimum thickness of an intrinsic a-Si:H layer made by Plasma-Enhanced Chemical Vapor Deposition (PECVD) is required for a low interface recombination velocity and a high open circuit voltage VOC. In turn, the high resistivity of this intrinsic layer results in Ohmic losses which decrease the fill factor FF. We find an optimum thickness for this layer that yields a good surface passivation and acceptable resistive losses. Completion of the contact requires an additional highly Boron doped amorphous or microcrystalline Si layer between the intrinsic layer and the ZnO. As sputter deposited Al:ZnO is an n-type semiconductor, electronic transport across this interface must be established by a tunneling mechanism. We reach the aim of a low tunneling resistance by optimizing the Hydrogen / Diborane dilution for the PECVD process. Specifically, the tunnel resistance drops by more than three orders of magnitude down to less than 30 mΩcm2 upon increasing the Hydrogen dilution ratio. We use temperature-dependent current voltage analysis of a variety of those contacts to analyze the details of the charge transport mechanism for the tunnel junctions as well as across the intrinsic layers.
9:00 PM - A18.6
Hydrofluoric Acid Treatment of Amorphous Silicon Films for Photovoltaic Processing.
Michael Burrows 1 2 , Ujjwal Das 1 , Meijun Lu 1 , Stuart Bowden 1 , Robert Opila 2 , Robert Birkmire 1 2
1 Institute of Energy Conversion, University of Delaware, Newark, Delaware, United States, 2 Materials Science and Engineering, University of Delaware, Newark, Delaware, United States
Show AbstractHydrofluoric acid (HF) is commonly used in Si wafer processing as a surface treatment that removes oxide and provides a H-terminated surface passivation that resists contamination within short time scales. At many instances during silicon heterojunction (SHJ) device fabrication a similar oxide removal and surface passivation is desired for doped and intrinsic hydrogenated amorphous silicon (a-Si:H) films . The present work will include our results of HF treated a-Si:H thin films. Variable angle spectroscopic ellipsometry is used to determine the growth rate of native oxide and terminal oxide thickness. X-ray photoelectron spectroscopy is employed to evaluate surface chemical composition, especially with regard to oxygen removal, fluorine incorporation, and resistance to hydrocarbon adsorption. To analyze the effects of a-Si:H native oxide on SHJ cells current-voltage and minority carrier lifetime results on novel test structures are reported. We conclude that a-Si:H treated with HF is effective for oxide removal and provides surface passivation similar to the crystalline counter-part, that fluorine bonding is strongly enhanced for p-type a-Si:H films, and that control of native oxides is essential for optimization of the SHJ photovoltaic cell.
9:00 PM - A18.7
SnO2/ZnO bi-layer Textured Transparent Conductive Oxide: A Substrate for nc-Si:H Solar Cells.
Feng Zhu 1 2 , Ying Zhao 2 , Changchun Wei 2 , Xinhua Geng 2
1 , colorado school of mines, Golden, Colorado, United States, 2 , Institute of Photo-electronic thin film devices and technology, Nankai University,, tianjin, tianjin, China
Show Abstract9:00 PM - A18.8
High-performance, Tandem-type Amorphous Silicon Solar Cell.
Porponth Sichanugrist 1 , Nirut Pingate 1 , Channarong Piromjit 1
1 ISET, NSTDA, Pathumthani Thailand
Show AbstractIntroduction.Microcrystalline silicon oxide (μc-SiO) deposited from the gas mixture of silane and carbondioxide using VHF plasma was reported by authors to be the promising material for amorphous silicon (a-Si) solar cell fabricated on glass substrate, comparing with the conventional amorphous silicon oxide or microcrystalline silicon p-layer. High-performance, tandem-type solar cell with amorphous and microcrystalline cells (double cells) has been achieved by applying this μc-SiO to the p-layer of both cells. On the other hands, cell efficiency of 15% has been reported for a-Si tandem type solar cell with triple cell configuration using a-Si, amorphous silicon germanium (a-SiGe) and microcrystalline Si (μc-Si) as the top, middle and bottom cells, respectively.Experiment. In our present work, we have applied the newly developed μc-SiO to the p-layers of this tandem type solar cell. A cluster-type, multi-chamber system in which various films (Ag, ZnO, a-Si, a-SiO, a-SiGe, μc-Si and μc-SiO films) can be deposited on 30 cm x 40 cm area without breaking the pressure has been used. High VHF frequency of 60 MHz and carbon dioxide gas are used for μc-SiO deposition while TMB and phosphine is used here as the doping gas. Thin ZnO layer is coated by DC sputtering on tin oxide coated glass substrate in order to promote the crystallization of the μc-SiO p-layer. Furthermore, in order to increase the voltage of the top cell, amorphous silicon oxide (a-SiO) has been used as the i-layer. Hydrogen dilution with profiling has been used in the a-SiGe and μc-Si i-layer in order to increase the cell performance. N-type μc-SiO has also been used in order to minimize the optical loss due to the absorption. ZnO interface layer deposited by DC sputtering has been added between the middle a-SiGe cell and bottom μc-Si in order to increase the current of the middle a-SiGe cell. Some treatments have been done to improve the cell interface properties. Results. As the results, higher cell efficiency of more than 15.7% has been achieved with the above-mentioned tandem type a-Si solar cell. This efficiency is the highest one reported so far for a-Si solar cell.
9:00 PM - A18.9
Modeling of Amorphous/Crystalline Silicon Heterojunction Solar Cells on the Base of Spectral Characteristics
Andrzej Kolodziej 1 , Pawel Krewniak 1
1 Department of Electronics, AGH University of Science and Technology, Kraków Poland
Show AbstractA19: Poster Session: Imagers, Sensors and Novel Applications
Session Chairs
Arokia Nathan
Jeffrey Yang
Friday AM, April 13, 2007
Salon Level (Marriott)
9:00 PM - A19.1
Study of a Fabrication Process and Characterization of One Dimensional Array of Un-cooled Micro-bolometers Based on Germanium films deposited by Plasma
Mario Moreno 1 , Andrey Kosarev 1 , Alfonso Torres 1
1 Electronics, INAOE, Puebla, Puebla, Mexico
Show AbstractIn our previous works we have studied the fabrication process and characterization of single cell micro-bolometers based on germanium thin films deposited by low frequency (LF) PE CVD technique at low temperature and fully compatible with the IC fabrication technology. We have demonstrated promising properties of those devices for further development of IR imaging systems [1-2].In this work we report the study of a fabrication process and characterization of one dimensional array of 32 un-cooled micro-bolometers. We have used surface micro-machining techniques for the array fabrication onto a silicon wafer. The micro-bolometers in the array have a “bridge type” configuration, in which a SiNx supporting film is suspended 2.5 µm from the substrate by two legs forming the bridge in order to provide sufficient thermo-isolation for the a-Ge:H thermo-sensing layer, which is deposited by LF plasma over it. The a-Ge:H film used in this devices showed high activation energy Ea= 0.34 eV, providing high thermal coefficient of resistance, TCR=α=0.043 K-1. Metal contacts to the thermo-sensing layer were in the form of stripes (“planar” configuration) or sandwiched the thermo-sensing layer (“sandwich” configuration). The active area of the cells in the array is Ab=70x66 µm2 and the area of the array including interconnection lines and pads is AA=1600x3120 µm2.We studied the key issues in the fabrication of the arrays that influence on uniformity and reliability of the cells performance characteristics and also on the yield at the end of the fabrication process.The temperature dependence of conductivity σ(T), current-voltage characteristics I(U) and spectral noise density have been measured in the micro-bolometers in the array in order to characterize and compare their performance characteristics, such as responsivity and detectivity. Cross talk signals and noise characteristics measured for different read-out options are also discussed.[1]A. Torres, A. Kosarev, M. L. García Cruz, R. Ambrosio, J. Non-cryst. Solids, 329, 179 - 183 (2003).[2]A.Kosarev,M.Moreno,A.Torres,A.Ambrosio, in Amorphous and Polycrystalline Thin-Film Silicon Science and Technology--2006, edited by H.A. Atwater, Jr., V. Chu, S. Wagner, K. Yamamoto, H-W. Zan (Mater. Res. Soc. Symp. Proc. 910, Warrendale, PA, 2006), A17-05.
9:00 PM - A19.2
Preliminary Results on Large Area X-ray a-SiC:H Multilayer Detectors with Optically Addressed Readout.
Manuela Vieira 1 , Yury Vygranenko 1 2 , Miguel Fernandes 1 , Pedro Sanguino 1 , Alessandro Fantoni 1 , Paula Louro 1 , Reinhard Schwarz 3 1
1 Electronics Telecommunication and Computer , ISEL, Lisbon Portugal, 2 Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, 3 Physics, IST, Lisbon Portugal
Show AbstractThe need to obtain images from major anatomical part of the body and the lack of the practical means to focus X-rays necessitates the use of a large area sensing device. In this paper a large area image sensor with an optically addressed readout, that can be used for medical X-ray diagnostic imaging, with will be developed and characterized. The detector comprises a converter layer, a large area a-Si panel and external readout electronics. Basically two concepts have to be implemented: intermediate conversion of the X-rays image into an optical image by a scintillator and the conversion of the optical image into an electric one by a large area Laser Scanned Photodiode (LSP). An optical scanner is used for charge readout. The analysis of the device characteristics through: sensitivity measurements, spectral response, transfer functions, response time, cut-off frequency, dynamic range, resolution and linearity tests will be performed. The scanning technique for image acquisition will be improved to meet the specific requirements of radiographic imaging. To obtain high spatial resolution and contrast at the lowest possible dose, the scan time, spot size, laser beam intensity, design and performance of readout electronics will be optimized. The search and analysis of appropriate scintillator materials such as Gd2O2S:Tb or CsI:Tl and associated integration issues will be explored too.A series of large area transducers in the assembly glass/ZnO:Al/p (SixC1-x:H)/i(Si:H) /n(SixC1-x:H)/ i(Si:H)/ p(SixC1-x:H)/a-SiNx/ITO will be produced as a basis of the back plane. The main emphasis will be put on: role of doped (doping level, carbon content, homogeneity, resistivity, thickness) and active (thickness, photosensitivity) layers and contact design on the device performance (transfer functions, sensitivity, dynamic range, resolution, linearity, noise, response time and bandwidth).The thicknesses of both absorption layers in the tandem cells will be optimized by numerical modeling to achieve so-called photocurrent matching between top and bottom cells, in order to get the maximum of the signal-to-noise ratio. The experimental optical and electrical data will be used as input parameters for the semiconductor device simulator ASCA in order to determine the optimal design of the double junction. The current matching condition is examined by measuring the spectral response of the device as a function of different bias light illumination. Beside the sample characterization this objective includes a numerical modeling of carrier transport into device under different illumination and biasing conditions.
9:00 PM - A19.3
Non linear Photocurrent Dependence on the Light Flux: A Requirement in the Laser Scanned Photodiode Technique.
Miguel Fernandes 1 , Manuela Vieira 1 , Rodrigo Martins 2
1 Electronics Telecommunications and Computer, ISEL, Lisbon Portugal, 2 DCM, FCT/UNL, Lisboa Portugal
Show AbstractThe Laser Scanned Photodiode (LSP) concept enables the fabrication of large area image sensors with application in fields where low cost, and design simplicity are of major importance.The device is a large area p-i-n amorphous silicon based structure deposited over a glass substrate by a PECVD technique with two semitransparent electrical contacts. In order to decrease the conductivity of the doped layers methane is introduced in the reactor during the growth of the n and p layers. This step is of major importance since the lateral currents in the doped layers degrade the sensor performance. The LSP technique relies on the fact that the photocurrent of the device does not change linearly with the light intensity, and thus the local illumination conditions over the active area of the structure can be evaluated by measuring the current generated by a low power light beam.In order to extract the image information the low power modulated light beam scans the active area of the device, in raster mode, and the photocurrent generated in each position is measured at the electrical contacts by a lock-in amplifier. By recording the photocurrent measured on each point of the sensor an image of the light pattern captured by the sensor is obtained without the need of any additional signal processing. The devices analyzed in this work present an S-shape J-V characteristic when illuminated. By changing the light flux a non linear dependence of the photocurrent with illumination is observed. Thus a low intensity light beam can be used to probe the local illumination conditions, since a relationship exists between the probe beam photocurrent and the steady state illumination.Numerical simulation studies showed that the origin of this S-shape lies in a reduced electric field across the intrinsic region, which causes an increase in the recombination losses. Based on this, we present a model for the device consisting of a modulated barrier recombination junction in addition to the p-i-n junction. The simulated results are in good agreement with the experimental data. Using the presented model a good estimative of the LSP signal under different illumination conditions can be obtained, thus simplifying the development of applications using the LSP as an image sensor, with advantages over the existing imaging systems in the large area sensor fields with the low cost associated to the amorphous silicon technology.
9:00 PM - A19.4
Temperature Dependence of Leakage Current in Segmented a–Si:H n–i–p Photodiodes.
Jeff Hsin Chang 1 , Tsu Chiang Chuang 1 , Yuri Vygranenko 1 , Kyung Ho Kim 1 , Denis Striakhilev 1 , Arokia Nathan 2 , Gregory Heiler 3 , Timothy Treadwell 3
1 Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, 2 , London Centre for Nanotechnology, London United Kingdom, 3 , Eastman Kodak Research Laboratories, Rochester, New York, United States
Show AbstractDark current level of hydrogenated amorphous silicon (a–Si:H) n–i–p photodiodes is one of the key parameters in achieving high sensitivity and high spatial resolution flat-panel imagers (FPIs) for medical diagnostic applications. While a major portion of the total leakage current in large area n–i–p photodiodes may be attributed to central leakage, the peripheral component, affected by the details of the sensor structure and fabrication process, may dominate the total leakage current level in small area photodiodes; therefore, limits the practical dimensions of such device. In this work, the central and peripheral components of the leakage current in state-of-the-art segmented a–Si:H n–i–p photodiodes were systematically characterized and modelled. Photodiodes of various sizes with intrinsic layer (i-layer) thickness of 500nm and 1µm were fabricated via plasma-enhanced chemical vapour deposition (PECVD) technique. The structure of the fabricated devices closely resembles the sensing element of the pixels used in large-area FPIs. Leakage current level of <35pA/cm2 were consistently achieved for 126×126µm2 a–Si:H n–i–p photodiodes with 500nm thick i-layer at reverse bias of –3V, in room temperature. Dark current-voltage (IV) characteristics of the test devices with sizes ranging from 50µm to 2mm were measured at ambient temperatures between 20°C and 80°C. The behaviours of the leakage components with respect to bias and temperature were analyzed and the activation energies at various reverse bias voltages were extracted. An empirical model that describes the dependence of the leakage current on the photodiode geometry, bias, and temperature was formulated and implemented in Verilog-A hardware description language (HDL).
9:00 PM - A19.5
High Performance Hydrogenated Amorphous Silicon n-i-p Photo-diodes on Glass and Plastic Substrates by Low-temperature Fabrication Process.
Kyung Ho Kim 1 , Yuriy Vygranenko 1 , Jeff Chang 1 , Tsu Chuang 1 , Denis Striakhilev 1 , Arokia Nathan 2 , Gregory Heiler 3 , Mark Bedzyk 3 , Timothy Tredwell 3
1 Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, 2 London Centre for Nanotechnology, University College London, London United Kingdom, 3 , Eastman Kodak Research Laboratories, Rochester, New York, United States
Show AbstractHydrogenated amorphous silicon (a-Si) thin-film n-i-p photodiode technology is very efficient in imaging arrays for medical applications, document scanning, machine vision and other applications [1-3] due to very low dark current of the photo-sensor, high quantum efficiency in visible spectral range and fast response time under reverse bias. At present, there is a strong demand in the development of a-Si n-i-p photodiodes on plastic substrates. This would enable lighter weight, mechanically flexible and more robust imaging devices. However, most of plastic substrate materials would require lower process temperatures, between 100 ~ 200 oC, whereas there is a concern about the quality of thin-film semiconductor materials and devices formed at these reduced temperatures. We fabricated a-Si materials and n-i-p photodiodes using plasma-enhanced chemical vapor deposition (PECVD) and hydrogen dilution of silane for all n-, i-, and p-layers on glass and PEN substrates at 150 oC. The effect of hydrogen dilution ratio on the opto-electronic properties, the mechanical stress in intrinsic a-Si:H layer and electrical characteristics of n-i-p photodiodes were systematically studied. It was observed that, an increase in hydrogen dilution ratio caused deposition rate and dark conductivity to decrease, while optical bandgap and stress of i-a-Si film increased. Fabricated a-Si n-i-p photodiodes incorporated 500 nm-thick i-a-Si layer. Device area ranged from 0.025 to 4 mm2. Optimized a-Si:H n-i-p photo-diodes on glass and PEN substrates demonstrated low leakage current density of 45 pA/cm2 and ~300 pA/cm2, respectively, as it was measured on 500 x 500 um2 diodes at reverse bias of -3V. The effect of the substrate properties on the reverse current of photodiodes will be discussed in the paper. Quantum efficiency of the photodiodes was 70%. The achieved level of reverse leakage current of n-i-p diodes on glass fabricated at 150 oC corresponds to state-of-the-art devices fabricated at 200-300 oC. The performance of the photodiodes on PEN substrates is comparable to that on glass and complies with the requirements for several medical imaging applications. To our knowledge, this is the first ever report on successful fabrication of high-performance a-Si:H n-i-p photodiodes on plastic substrates.Reference[1] M. J. Yaffe and J. A. Rowlands, Phys. Med. Biol. 43, 1 (1997).[2] J. A. Theil, Mat. Res. Soc. Symp. Proc., 762, A21.4.1 (2003).[3] J. H. Chang, Yu. Vygranenko, and A. Nathan, J. Vac. Sci. Technol. A, 22, 971 (2004).
9:00 PM - A19.6
Investigation of the Performance of HgI2-Coated Direct Detection Flat Panel Imagers for Fluoroscopy and Radiography
Hong Du 1 , Larry Antonuk 1 , Youcef El-Mohri 1 , Qihua Zhao 1 , Yi Wang 1 , Mahdokht Behravan 1
1 Radiation Oncology, University of Michigan, Ann Arbor, Michigan, United States
Show AbstractActive-matrix flat panel imagers (AMFPIs) have been successfully incorporated in numerous diagnostic and therapeutic applications. However, significant performance improvement is required for clinical applications that involve low exposure per image frame and/or high spatial resolution. Detailed analysis of such imaging systems based on cascaded systems modeling indicates that performance can be improved by increasing x-ray signal sensitivity relative to intrinsic pixel noise. Motivated by these findings, we have undertaken studies of direct detection AMFPIs, in which x-rays are converted by photoconductors directly into imaging signal, and made comparisons with high-performance, prototype indirect detection AMFPIs, in which x-rays are converted by phosphor screens into visible light that is in turn detected by photodiodes. Direct detection AMFPIs offer several potential advantages over conventional indirect detection AMFPIs, including higher fill factor, and better spatial resolution. In particular, the polycrystalline form of mercuric iodide (HgI2), presently under investigation by several groups, exhibits various favorable properties compared to amorphous selenium (a-Se), which is currently used in clinically-practical direct detection AMFPIs. In the present investigations, thin film, polycrystalline HgI2 photoconductor was deposited on direct detection AMFPIs using two approaches, physical vapor deposition and particle-in-binder, with thickness ranging from 200 to 300 µm. Prototypes of two direct detection AMFPI array designs, with pixel formats of 768x768 and 1024x1024 at a pixel pitch of 127 µm, were employed. These prototype imagers demonstrated favorable properties under diagnostic x-ray imaging conditions. High sensitivity values were achieved at electric field strengths across the photoconductor of less than 1 V/µm (compared to ~10 V/µm typically used for a-Se). This simplifies the design of the acquisition electronics and helps reduce dark current and noise. For example, at a field strength of 0.54 V/µm, effective ionization energies as low as 7.5 eV were achieved, which are much lower than that of a-Se (typically ~50 eV at 10 V/µm). Modulation Transfer Functions (MTFs) measured from these imagers in some cases exceeded those measured from very high quality indirect detection AMFPIs with comparable pixel pitch and approached the theoretical limit defined by the pixel pitch. In this presentation, fundamental properties of the prototype imagers including dark current, dark current drift, uniformity, x-ray sensitivity, effective ionization energy, charge trapping, lag, MTF, and DQE are reported. The results are compared against those of indirect detection AMFPIs, properties that require further significant improvement are identified, and specific strategies for realizing such improvements are discussed.
9:00 PM - A19.7
Nanoscale Thermal Analysis of Multilayer Thin Films for Packaging using the New Mode of Heated Tip-AFM.
Nico Gotzen 3 1 , Kevin Kjoller 1 , Guy Van Assche 3 1 , William King 2 1 , Roshan Shetty 1
3 Dept of Polymer Chemistry, Vrije Universitaet, Brussels Belgium, 1 , Anasys Instruments, Santa Barbara, California, United States, 2 Woodruff School of Mechanical Engg, Georgia Tech, Atlanta, Georgia, United States
Show AbstractA20: Poster Session: Electronics and Flexible Substrates
Session Chairs
Arokia Nathan
Jeffrey Yang
Friday AM, April 13, 2007
Salon Level (Marriott)
9:00 PM - A20.1
Mechnical Strains in Flexible a-Si:H TFT Electronics.
Helena Gleskova 1 , Sigurd Wagner 1 , Zhigang Suo 2
1 Department of Electrical Engineering and Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey, United States, 2 Division of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, United States
Show AbstractWhen layers of materials are deposited on different substrates, the thermal misfit between the film grown at elevated temperature and the substrate, and the built-in stress of the film, will cause the workpiece to strain, i.e., change its dimensions. Big, thin, or soft substrates amplify the strain. The strain may range from < 1 ppm in silicon integrated circuits (where it is becoming important in the alignment of sub-100-nm devices), to tens of ppm for thin-film electronics fabricated on steel foil, to hundreds of ppm when inorganic devices are fabricated on plastic foil. When thin film circuits are fabricated on rigid, thick substrates like silicon wafers or glass plates, the coefficient of thermal expansion of the substrate controls the strain in the workpiece throughout the fabrication. As a result, the substrate is nearly free of stress and most of the stress is taken up by the film. When the in-plane stress becomes too large, the film peels from the substrate. When amorphous silicon thin-film transistors are grown on plastic foils, the in-plane strain in the workpiece is affected by the thermo-mechanical properties of substrate and film. As a result, both the film and the substrate experience mechanical stresses throughout the fabrication. When the stress becomes too large, films and/or substrate may fracture. To quantitatively describe the strains in the film and the substrate that undergo thermal cycling during a-Si:H TFT fabrication, we adapted the theory of a bimetallic strip to calculate the strains in the TFT films and the substrate during film growth and after cooling to room temperature. By controlling these strains one can design fracture-free TFT fabrication processes. This work is supported by the US Display Consortium and E.I. DuPont de Nemours.
9:00 PM - A20.2
Multilayer Permeation Barrier for Flexible Displays Grown by Plasma-enhanced Chemical Vapor Deposition in a Single Chamber.
Prashant Mandlik 1 , I-Chun Cheng 1 , Sigurd Wagner 1 , Teddy Zhou 2 , Michael Hack 2
1 Electrical Engineering and PRISM, Princeton University, Princeton, New Jersey, United States, 2 , Universal Display Corp., Ewing, New Jersey, United States
Show AbstractWe report experiments and initial results about a novel technique for the fabrication of a permeation barrier for flexible displays. The barrier is a multilayer stack of alternating inorganic and polymeric films. All films are grown in a single-chamber plasma-enhanced chemical vapor deposition system from inexpensive precursor gases. We describe the deposition of single films and of multilayer stacks. The films are characterized for growth rate, etch rate, wetting contact angle and built-in stress, and are inspected by optical microscopy, surface scan, scanning electron microscopy, and atomic force microscopy. Barrier properties are tested by measuring the life of organic light-emitting diodes that have been coated with single-layer or multilayer films. We will report the chemistry, fabrication, characterization and performance of the component films and of multilayer barriers made of the films.
9:00 PM - A20.3
Direct Deposition of Polycrystalline Silicon Films on Plastic substrates at a Room Temperature Range using Catalytic CVD Technique.
Wan-Shick Hong 1 , Chul-Lae Cho 2 3 , Dae-Hyun Lee 2 , Tae-Hwan Kim 1 , Kyung-Bae Park 3 , Jisim Jung 3 , Sang-Yoon Lee 3 , Jang-Yeon Kwon 3
1 Dept. of Nano Science and Technology, University of Seoul, Seoul Korea (the Republic of), 2 Dept. of Electronics Engineering, Sejong University, Seoul Korea (the Republic of), 3 , Samsung Advanced Institute of Technology, Kyunggi-do Korea (the Republic of)
Show AbstractPolycrystalline silicon films were directly deposited on polyethersulfone (PES) substrates, initially held at room temperature, by using the catalytic chemical vapor deposition (Cat-CVD) technique. The influence of various process parameters for the as-deposited polycrystalline silicon was investigated. Temperature of the tungsten catalyst and the concentration of hydrogen in the source gas were determined to be two major parameters that influence the crystallinity of the as-deposited film. The radiation from the filament heated up the substrate, but the temperature of the substrate surface was controlled below 190°C, so as not to damage the PES substrates. Raman scattering spectroscopy and UV reflectance spectroscopy showed that the characteristic peak intensity for the crystalline phase was greater than 50% of that of a single-crystal wafer. X-ray diffraction and transmission electron microscopy analysis showed that crystallites have a columnar structure with a preferred orientation of (111). The as-deposited films also have a low hydrogen content (<1.5 atomic %) and a high deposition rate (~30Å/sec). The polysilicon films that were prepared directly by the Cat-CVD could dispense with the additional crystallization process, and could be a good candidate for thin film transistor materials of flexible active matrix display devices.
9:00 PM - A20.4
Hot-wire Deposited Nanocrystalline silicon TFTs on Plastic Substrates.
Farhad Taghibakhsh 1 , Michael Adachi 1 , Karim Karim 1
1 Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada
Show AbstractPlastic sheets can provide lightweight inexpensive substrates for large area thin film display and hot-wire chemical vapor deposition (HWCVD) is known to be an economical technology for depositing high quality materials because of its efficient use of source gases, and its simple and inexpensive setup which is easily scaleable for large area applications [1]. However, adapting hotwire for deposition on plastic substrates is a challenge due to the low temperature requirement of plastic substrates. Compared to state-of-the-art hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs), nanocrystalline silicon TFTs offer superior threshold voltage stability, as well as higher carrier mobility for both electrons and holes [1], providing the possibility of realizing system on plastic using thin film complementary metal oxide semiconductor (CMOS) transistors.We previously reported high quality TFTs by hot-wire deposition of amorphous silicon on plastic substrates at a filament temperature of 1500°C [2]. In this research, we improve device performances by substituting amorphous silicon with nanocrystalline silicon directly deposited using hot-wire deposition at a filament temperature of 1900°C on thin plastic substrates. In addition to minimizing thermal damage to thin plastic substrates due to high radiation from the filament, other challenges such as deposition of device quality nanocrystalline silicon, minimizing mechanical stress of the film, and keeping the deposition at a relatively high rate exist. The structure of the transistors is another important factor in fabrication of high quality devices. Performance of top gate staggered and top gate coplanar thin film transistors will be compared and analysed. A top-gate TFT configuration is employed with a optimum intrinsic nc-Si:H film thickness deposited by HWCVD of a tantalum filament at 1850°C. PECVD is used for the uc-n+ Si source and drain contact layers as well as the double layer a-SiNx:H gate insulator. Aluminium metallization is used for both gate and drain/source contacts. Measurements in preliminary experiments show a sub-pA normalized leakage current, and a switching current ratio of ~ 10^7 for hotwire deposited nanocrystalline TFTs on plastic with geometric aspect ratio of 10. Threshold voltage and field effect mobility were measured to be 4 V and 0.62 cm^2/V.s respectively. Enhancement of device performance by optimization of the process is under investigation. We will present details of the fabrication process, device characterization and optimization, and results of the gate bias stress analysis. References:1. R. E. I. Schropp, “Thin Film Transistors with High Mobility and High Threshold Voltage Stability Made Using Hot Wire Chemical Vapor Deposition”, Japanese Journal of Applied Physics Vol. 45, No. 5B, 2006, pp.4309-4312.2. F. Taghibakhsh and K. S. Karim, “Hot-wire deposited a-Si:H TFTs on plastic substrates”, MRS, spring meeting 2006.
A21: Poster Session: Electronic Properties and Metastability
Session Chairs
Arokia Nathan
Jeffrey Yang
Friday AM, April 13, 2007
Salon Level (Marriott)
9:00 PM - A21.3
Computer Modelling of Atmospheric Effects on the Conductivity of Silicon Thin Films.
Vladimir Smirnov 1 , Steve Reynolds 1 2 , Charlie Main 1 , Friedhelm Finger 2 , Reinhard Carius 2
1 Division of Electronic Engineering and Physics, University of Dundee, Dundee United Kingdom, 2 IPV, Forschungszentrum Juelich, Juelich Germany
Show AbstractRecently, the effects of ambient atmosphere on the electronic properties of amorphous and microcrystalline silicon films have been studied in some detail [1-3]. In order to gain a better appreciation and understanding of these phenomena we have developed a computer simulation, in which the effect of the adsorbate on conductivity is modelled as a charge sheet placed some distance into the film. This artifice is intended to take into account the electrostatic effect of the adsorbate, assuming varying degrees of penetration into the film depending on its microstructure. The carrier continuity equations and Poisson's equation are solved for the system, which includes exponential band tails and a Gaussian distribution of dangling bond defects. By a reasonable choice of material parameters and penetration depths we show that it is possible to account for observed behavior in both undoped and boron-doped microcrystalline silicon films.[1]F. Finger, R. Carius et al, IEE Proc. CDS 150 (2003) 300.[2]V. Smirnov, S. Reynolds et al, J. Non-Cryst. Solids 338-340 (2004) 421.[3]R. Brueggemann, MRS Symp. Proc. 862 (2005) A5.1
9:00 PM - A21.4
Hole Mobility and Transport in Microcrystalline Silicon pin Junctions.
Steve Reynolds 1 2 , Reinhard Carius 2 , Friedhelm Finger 2 , Rudi Brüggemann 3
1 Division of Electronic Engineering and Physics, University of Dundee, Dundee, Angus, United Kingdom, 2 Institute of Photovoltaics, Forschungszentrum Jülich, Jülich, NRW, Germany, 3 Fachbereich Physik, Carl von Ossietzky Universität Oldenburg, Oldenburg, Niedersachsen, Germany
Show AbstractIn previous studies we have reported measurements of hole mobility in thick microcrystalline silicon pin junctions measured by the time-of-flight (TOF) technique, exceeding 1 cm2/(Vs) at room temperature in highly-crystalline samples [1]. Also for lower crystalline volume fractions (as low as 10%) significant enhancements of the hole mobility were observed [2]. Here we report on an extension of this work which includes a wider range of samples, and explores the correlation with solar cell open-circuit voltage. The short-circuit current under blue illumination is found to mirror the variation in TOF hole mobility. Computer simulations are performed using the program SC-Simul [3] in order to understand the relationship between hole mobility and solar-cell parameters. We will show which transport and recombination processes lead to the observed behaviour.[1] T. Dylla, F. Finger, E.A. Schiff, Appl. Phys. Lett. 87, 032103 (2005).[2] T. Dylla, S. Reynolds, R. Carius, F. Finger, J. Non-Cryst. Sol. 352, 1093 (2006).[3] M. Rösch, Ph.D. Thesis, Universität Oldenburg, 2003.
9:00 PM - A21.6
Electronic Proeprties of Nanocrystalline Si Films and Devices.
Vikram Dalal 1 , Kamal Muthukrishnan 1
1 Elec. and Computer Engr., Iowa State University, Ames, Iowa, United States
Show AbstractNano-crystalline Si:H is an important material for solar cells and photo-detectors. In this paper, we study the dependence of fundamental material properties such as defect density, diffusion length, carrier mobility and minority carrier lifetimes on deposition conditions of nano-crystalline Si:H. Nano-crystalline Si films and devices were deposited using a remote hot wire CVD technique where the filament was 11 cm away from the substrate, thereby avoiding deleterious effects of heating. The films and devices were deposited under varying filament temperatures ( between 1675 and 1900 C), under varying (pd) product conditions achieved by varying the pressure from 2 mT to 30 mT, and under varying ratios of hydrogen to silane. The structure of the films and devices was measured using Raman and x-ray diffraction techniques. It was found that the lowest defect densities and the highest minority carrier diffusion lengths were achieved when the Raman crystallinity ratio between amorphous and crystalline phases was between 2-2.5, and the pd product was in the range of 50-100 mTorr-cm. For such cases, the diffusion lengths could be several micrometer and the defect densities could be as low as a few 1015/cm3. The minority carrier lifetimes for such films were in the range of 500 nsec. Both very high and very low crystallnity ratios led to poorer diffusion lengths and higher defect densities. Very high pd products also led to lower diffusion lengths. The electron mobility depended mostly on the grain size, varying from ~ 1cm2/Vs to 5 cm2/Vs.
9:00 PM - A21.7
Evolution of Structural and Electronic Properties in Boron-doped Nanocrystalline Silicon Thin Films.
Hyun Jung Lee 1 , Andrei Sazonov 1 , Arokia Nathan 2
1 Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, 2 London Centre for Nanotechnology, University College London, London United Kingdom
Show AbstractWe performed a study of structural and electronic properties in nanocrystalline silicon (nc-Si:H) thin films and their evolution with controlled boron doping. The aim of this research is: i) to be able to produce p-type ohmic contacts between metals and intrinsic nc-Si:H films for p-channel nc-Si:H thin film transistors (TFTs); ii) to investigate n-type dopant compensation in nc-Si:H by p-type doping to reduce the dark conductivity (σd) and hence the leakage current in nc-Si:H, which is critical for the high performance of TFTs. The films were deposited on Corning 1737 glass substrates using conventional (13.56 MHz) plasma enhanced chemical vapor deposition (PECVD) at a substrate temperature of 260 °C. The structural and electronic properties of the doped films were studied as a function of a trimethylboron-to-silane ratio ([TMB]/[SiH4]), which was gradually varied from 0.1 to 2 %. The growth rate (≥ 3.45 nm/min) of the doped films, which increases with increasing [TMB]/[SiH4], was noticeably higher than the undoped counterparts (~ 2.7 nm/min). The crystallinity (Xc) and grain size (dgrain) over 70 %, and 8 nm, respectively, for ~ 50-nm-thick films were also the highest at low [TMB]/[SiH4] level (≤ 0.4 %). However, Raman and XRD spectra show that the films were amorphized at high [TMB]/[SiH4]. We observed a nanocrystalline-to-amorphous phase transition at [TMB]/[SiH4] ~ 1%. σd measurements at room temperature show that at low [TMB]/[SiH4] (≤ 0.2 %), boron compensates the nc-Si:H material which is known to be intrinsically n-type due to oxygen impurities incorporated during deposition. σd was reduced to ~ 10-8 S/cm compared to that of undoped films (~ 10-7 S/cm). Up to [TMB]/[SiH4] ~ 0.4 %, the films are p-type doped and form good ohmic contact with maximum σd ~ 0.1 S/cm. At high [TMB]/[SiH4], however, ohmic contacts showed low σd (≤ 0.01 S/cm) due to the amorphization of nc-Si:H films.
A22: Poster Session: Structural Properties
Session Chairs
Arokia Nathan
Jeffrey Yang
Friday AM, April 13, 2007
Salon Level (Marriott)
9:00 PM - A22.1
Elastic Properties of Several Silicon Nitride Films.
Xiao Liu 1 , Thomas Metcalf 1 , Qi Wang 2 , Douglas Photiadis 1
1 , Naval Research Laboratory, Washington, District of Columbia, United States, 2 , National Renewable Energy Laboratory, Golden, Colorado, United States
Show AbstractWe have measured the internal friction and speed of sound from T = 0.5K to room temperature of amorphous silicon nitride films prepared by a variety of methods, including low-pressure chemical vapor deposition (LPCVD), hot-wire chemical vapor deposition (HWCVD), and plasma enhanced chemical vapor deposition (PECVD). The measurements are made by depositing the films onto extremely high-Q silicon double paddle oscillator substrates with a resonant frequency of 5500 Hz. We find the elastic properties of these amorphous silicon nitride films resemble those of amorphous silicon, demonstrating considerable variation, depending on the film growth methods and post deposition annealing. The internal friction of all films below approximately T = 30K shows a broad temperature-independent plateau, characteristic of amorphous solids. The values of the internal friction, however, vary from film to film in this plateau region by an order of magnitude. This is typical for tetrehedrally bonded amorphous thin films, like a-Si, a-Ge, and a-C. The PECVD films have an internal friction at the bottom of the “glassy range,” just like e-beam a-Si. The LPCVD films have an internal friction one order of magnitude lower, while the internal friction of HWCVD film is in between. All the films shows a reduction of internal friction after annealing at various temperatures, even for the LPCVD films which were prepared at 850 C. This can be viewed as a reduction of structural disorder and internal stress. In this temperature range, the speed of sound of the PECVD films shows a linear decrease with temperature, also characteristic of amorphous solids, while no such effect is observed in LPCVD films.
9:00 PM - A22.2
New Fundamental Insights in the Infrared Spectroscopy on the Bulk Hydride Dipole Vibrations in Hydrogenated Silicon.
Arno Smets 1 , Richard van de Sanden 2
1 Research Center for Photovoltaics, National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki, Japan, 2 Department of Applied Physics, Eindhoven University of Technology, Eindhoven Netherlands
Show AbstractHydrogen plays a crucial role in the formation and the properties of a Si:H network. Examples are the light induced distribution of a very small fraction of the bulk hydrides in a-Si:H, which is considered to be linked with the Staebler-Wronski effect and the insertion of hydrogen into a strained Si-Si bond during the growth of μc-Si:H, which is believed to be the mechanism of the local lattice crystallization.The most widely applied technique to study the bonding configurations of hydrogen is by means of infrared (IR) absorption spectroscopy. IR spectroscopy can detect the wagging, bending and stretching modes (SM) of hydrides in the material. The SM’s are especially interesting, as they have detailed signatures related with the microstructure of the films. However, although the infrared technique is widely used to study thin Si:H films, the literature on infrared analyses contains in our view some fundamental controversies and unrevealed questions: 1) A wide range of empirical proportionality constants, which links the integrated absorption strength of an absorption mode to the hydrogen density of that absorption mode have been reported. 2) Various assignments of hydrogen incorporation configurations to the various hydride stretching modes have been given. 3) No satisfactory explanation of the origin of the exact frequency position of the SM’s of hydrogen incorporated in the Si:H bulk has been given. 4) What is the exact description of the screening of a hydride dipole due to its bulk-environment.In this contribution we present a model for the Si:H solid, based upon a multiple Lorentz-Lorenz dielectric approach which enables us to describe the film mass density. We have extended this to describe the SM frequency position. If the hydrides are considered as a cavity with a different dielectric embedded in the silicon matrix, we can describe the frequency position of the bulk hydrides depending on their incorporation configuration in to the bulk. We have applied this model on an unique large number (>100) of a-Si:H samples having a wide range of different microstructures by varying the deposition rate, deposition temperature and ion induced film modifications. We find a nice agreement for the assignments of hydrogen incorporation configurations to the SM’s as deduced from the density and frequency analyses, respectively. Furthermore, the effective charge of the hydride dipole in the bulk found is in excellent agreement, with the value deduced from the oscillator strength of the stretching modes using the conventional Smakula description, independent of the assumed screenings approach. By comparison the effective charge with that of hydrides vibrations in mono- or polysilane molecules, the correct screenings description of a vibrating dipole in a solid matrix can be identified. We will discuss that all the above mentioned controversies and questions can be explained and revealed consistently with the model introduced.
9:00 PM - A22.3
Structural Analysis of Nanocrystalline Silicon Prepared by Hot-wire Chemical Vapor Deposition on Polymer Substrates
Michael Adachi 1 , Farhad Taghibakhsh 1 , Karen Kavanagh 2 , Karim Karim 1
1 School of Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada, 2 Department of Physics, Simon Fraser University, Burnaby, British Columbia, Canada
Show AbstractNanocrystalline silicon (nc-Si:H) deposited by the hot-wire chemical vapor deposition (HWCVD) technique has gained considerable attention in recent years due to potential of high deposition rates and upscaling. In addition, a roll-to-roll deposition process on flexible substrates is of interest to reduce manufacturing costs. This study examines the properties of intrinsic nc-Si:H films prepared by HWCVD deposited directly on flexible Kapton E polyimide and Teflon PFA substrates. The advantage of Kapton E is its high thermal stability but also has an amber color resulting in absorption in the blue. In comparison, Teflon PFA is clear making it suitable for use in p-i-n structure solar cells but is less dimensionally stable at high temperatures.Dark electrical conductivity of films varied between 5 x 10-10 and 2 x 10-6 S/cm with varying silane concentrations (SC) diluted in hydrogen between 1-5%. Rise in dark conductivity indicated a transition between amorphous to nanocrystalline silicon between 2% and 2.5% SC when grown on glass and between 1.5% and 2% SC when grown on Kapton E. nc-Si:H growth below this transition point was confirmed by Raman spectroscopy. Photo-conductivites varied between 1 x 10-5 to 8 x 10-5 S/cm for films deposited onto glass over the interval of 1-5% silane concentration. Measurements show that conductivities of films grown on glass and Kapton E are very similar. On the other hand, films grown on Teflon PFA show lower photo conductivity, possibly due to stress in the film. Structural properties are also studied by cross-sectional Transmission Electron Spectroscopy (TEM) and X-Ray diffraction (XRD).Although known for its non-stick properties, preliminary results show that adhesion to Teflon PFA substrates was not found to be a problem if depositions were done at high substrate temperatures. Adhesion of films was also not found to be a problem for Kapton E substrates.
9:00 PM - A22.4
Manupilating the Hydrogen-Bonding Configuration in ETP-CVD a-Si:H.
M. Wank 1 , R. van Swaaij 1 , M. van de Sanden 2
1 DIMES-ECTM, Delft University of Technology, Delft Netherlands, 2 Department of Applied Physics, Eindhoven University of Technology, Eindhoven Netherlands
Show AbstractHydrogenated amorphous silicon (a-Si:H) suitable for application in solar cells can be deposited with the Expanding Thermal Plasma-CVD (ETP CVD) method at high growth rates (up to 10 nm/s) [1]. An important property of a-Si:H is the hydrogen bonding configuration in the silicon network, mostly found as monohydrides (Si-H) or dihydrides (Si-H2). These configurations can be investigated with FTIR measurements, which allows distinguishing between hydrogen bonds associated with vacancies and those associated with void surfaces [2]. The microstructure parameter R* relates these two bonding configurations to each other and is a good measure for the structure of the a-Si:H material.It has been shown that an increased substrate temperature leads to lower R* values. It was concluded that material with R* > 0.5 is void-dominated, whereas material with R* < 0.5 is vacancy-dominated [2]. The hydrogen concentration where R* = 0.5 is called the critical hydrogen concentration, ccrit. It was found that in vacancy-dominated material the defect density is independent of R*, while in void-dominated material it increases with increasing R* [3]. Furthermore, a decrease of ccrit with increasing reactor pressure was observed. These observations are possibly related to the contribution of cluster ions to the growth flux. Cationic clusters account for ~6% of the growth flux for most deposition conditions [4]. At high substrate temperatures these clusters can be incorporated very well into the film and vacancy-dominated material is obtained. However, insufficient heating results in incorporation of voids and defects into the film. The aim of this work is to gain further insight into the relation between growth flux, deposition pressure, and substrate temperature on one hand, and hydrogen-bonding structure on the other hand. Preliminary results show that ccrit increases with decreasing growth flux at constant pressure. A decrease in growth flux affects the competition between the radical surface migration and radical arrival rate at the surface, resulting in a decreased incorporation of voids and consequently resulting in an increase of ccrit. Furthermore, the influence of RF biasing of the substrate holder on this relation will be investigated. Ion bombardment resulting from biasing is expected to supply additional energy to the growing film and/or to break up ionic clusters upon impact. We except that RF biasing will shift ccrit to higher hydrogen concentrations, thus extending the region in which vacancy dominated material is obtained.[1] W. M. M. Kessels et al., J. Appl. Phys. 89, 2404 (2001).[2] A. H. M. Smets et al., Appl. Phys. Lett. 82, 1547 (2003).[3] A. M. H. N. Petit, Ph. D. Thesis, Delft University of Technology (2006).[4] W. M. M. Kessels et al. J. Appl. Phys. 86, 4029 (1999).
9:00 PM - A22.5
Galvanic Corrosion of Polysilcon Thin Films
Collin Becker 1 , David Miller 1 , Conrad Stoldt 1
1 Mechanical Engineering, University of Colorado at Boulder, Boulder, Colorado, United States
Show AbstractMaterial defects in microstructural components can affect both mechanical and electrical properties of highly miniaturized devices. Recently, it has been observed that galvanic corrosion of polycrystalline silicon (polySi) during chemical post-processing results in highly detrimental mechanical and electrical effects. Since Micro-Electro-Mechanical Systems (MEMS) technology is currently being commercialized, a systematic and in-depth study of the effects of galvanic corrosion on polySi is necessary. In this work, we will ascertain if observed MEMS reliability problems such as fatigue, mechanical wear, and failure are linked to wet chemical post-processing of polySi by aqueous hydrofluoric acid (HF).Studies examining the post-processing of MEMS devices have noted changes in surface roughness, film morphology, residual stress, mechanical modulus, fracture strength, fracture morphology, and fatigue life. Prior research from our group utilized micromachined test structures consisting of phosphorous doped polysilicon in contact with a gold metallization layer. An autonomous galvanic cell forms when these test structures are immersed in an electrolytic solution. PolySi and gold have different electrochemical potentials, and once they are placed in an HF solution that acts as an electrolytic solution, a galvanic cell forms. In fact, the literature, as well as our own studies, shows that porous silicon (PS) formation is possible by using an autonomous galvanic cell method. In this study, we analyze the Poly-0 and Poly-1 films produced with the multiuser MEMS process (MUMPs). Larger wafers are diced into 1cm^2 dies and then using an evaporation process they are masked and coated with 20 nm of Cr and 500 nm of Au. The dies are then immersed in 48% HF solution for time periods. Free polySi surfaces are visibly discolored or “stained” after the HF immersion. Field emission scanning electron microscopy (FE-SEM) was utilized to characterize the surface morphology, where grain boundary attack and pitting was observed. Results from micro-Raman spectroscopy, x-ray diffraction (XRD), and photoluminescence (PL) will be presented that reveal the extent of the corrosion damage. For example, micro-Raman spectroscopy is useful in determining residual stress and the structure within the polySi film. The photoluminescence measurements offer a comparison of our polySi films to PS generated using an autonomous galvanic cell. The XRD results elucidate the changes in crystal structure of the polysilicon. Lastly, we make a thorough comparison of corroded polySi films to PS specimens that are created with conventional external anodization. The results of this study serve to more broadly generalize our prior research of mechanical and electrical properties of actual MEMS devices pre- and post-corrosion. This research will help to validate prior investigations and provide a complete picture of polySi corrosion during MEMS production.
A23: Poster Session: Nanocrystals, Nanoclusters and Nanowires
Session Chairs
Arokia Nathan
Jeffrey Yang
Friday AM, April 13, 2007
Salon Level (Marriott)
9:00 PM - A23.1
Tailored Deposition by LPCVD of Non-stoichiometric Si Oxides and their Application in the Formation of Si Nanocrystals Embedded in SiO2 by Thermal Annealing.
Bruno Morana 1 , Juan Carlos Gonzalez de Sande 2 , Andres Rodriguez 1 , Jesus Sangrador 1 , Tomas Rodriguez 1 , Manuel Avella 3 , Antonio Carmelo Prieto 3 , Juan Jimenez 3
1 Tecnología Electrónica, ETSI de Telecomunicación, Universidad Politécnica de Madrid, Madrid, Madrid, Spain, 2 Ingeniería de Circuitos y Sistemas, EUIT de Telecomunicación, Universidad Politécnica de Madrid, Madrid, Madrid, Spain, 3 Física de la Materia Condensada, ETSI Industriales, Universidad de Valladolid, Valladolid, Valladolid, Spain
Show Abstract9:00 PM - A23.2
Optical Properties of Porous Silicon Nanoclusters Encapsulated in Silica Gel Microfilms.
Y. Posada 1 , L. Fonseca 2
1 Derpartment of Physical Sciences, University of Puerto Rico, San Juan, Puerto Rico, United States, 2 Department of Physics, University of Puerto Rico, San Juan, Puerto Rico, United States
Show Abstract9:00 PM - A23.3
Silicon Nanowires Growth Studies Using Pulsed PECVD.
John Cornish 1 , David Parlevliet 1
1 Physics and Energy Studies, Murdoch University, Murdoch, Western Australia, Australia
Show Abstract