Symposium Organizers
Scott Thompson University of Florida
Faran Nouri Applied Materials Inc.
Wilman Tsai Intel Corporation
Wen-Chin Lee TSMC
Symposium Support
Taiwan Semiconductor Manufacturing Co., Ltd.
D1: SOI, FDSOI, SGOI, GOI, Multi-Gate and Schottky SD Technologies
Session Chairs
Wen-Chin Lee
Scott Thompson
Tuesday PM, April 18, 2006
Room 3006 (Moscone West)
9:00 AM - **D1.1
Amorphization/templated Recrystallization (ATR) Method for Hybrid Orientation Substrates.
K. L. Saenger 1 , J.P. de Souza 1 , K. E. Fogel 1 , J. A. Ott 1 , A. Reznicek 1 , C. Y. Sung 1 , D. K. Sadana 1 , H. Yin 2
1 Research Div. / T.J. Watson Research Ctr., IBM Semiconductor Research & Development Center, Yorktown Heights, New York, United States, 2 Microelectronic Division, IBM Semiconductor Research & Development Center, Hopewell Junction, New York, United States
Show AbstractHybrid orientation substrates make it possible to have a CMOS technology in which nFETs are on (100) Si (the Si orientation in which electron mobility is the highest) and pFETs are on (110)-oriented Si (the Si orientation in which hole mobility is the highest). This talk will describe a new amorphization/templated recrystallization (ATR) method for fabricating bulk hybrid orientation substrates. In a preferred version of this method, a silicon layer with a (110) orientation is directly bonded to a Si base substrate with a (100) orientation. Si regions selected for an orientation change are amorphized by ion implantation and then recrystallized to the (100) orientation of the base substrate. After an overview of the ATR technique and its various implementations, we will describe some of the scientifically interesting materials and integration challenges encountered while reducing it to practice.
9:30 AM - D1.2
Systematic Characterization of Pseudomorphic (110) Intrinsic SiGe Epitaxial Films for Hybrid Orientation Technology with Embedded SiGe Source/Drain.
Christine Ouyang 1 2 , Anita Madan 2 , Nancy Klymko 2 , Jinghong Li 2 , Richard Murphy 2 , Horatio Wildman 2 , Robert Davis 2 , Conal Murray 1 2 , Judson Holt 2 , Siddhartha Panda 2 , Meikei Ieong 1 2 , Chun-Yung Sung 1 2
1 , IBM TJ Watson Research Center, Yorktown Heights, New York, United States, 2 , IBM SRDC, Systems and Technology Group, Hopewell Junction, New York, United States
Show AbstractEpitaxial embedded SiGe on (110) Si crystalline planes for the hybrid orientation technology (HOT) showed significant improvement in device performance compared to conventional SOI CMOS. Drive current in pFETs was 30% higher and ring oscillators on the HOT wafers were 23% faster for Ge concentration of 15%. The 60 nm thick (110) SiGe had to be deposited on epitaxially grown (110) Si. It was challenging because the critical thickness for pseudomorphic SiGe on (110) Si substrates is much smaller compared to that on (100) Si wafers. In order to study the epi quality and strain, both blanket and patterned films (10% and 15% intrinsic SiGe) with various thicknesses were deposited in an LPCVD system. Epitaxial growth rate on (110) substrates was 30% lower than on (100) substrate and 30% higher on patterned wafers compared to blanket wafers. Films were characterized using High Resolution XRD (%Ge, strain and thickness), UV Raman microprobe (strain), AFM (surface morphology), Auger (Ge content) and TEM (epi quality). There was an excellent agreement between the Ge content as determined by Auger and XRD. The amount of strain extracted from the Raman measurements also agreed with the amount determined by XRD on both blanket and patterned wafers. Micro-Raman measurements showed that the strain in the SiGe films on blanket (110) and blanket (100) substrates with various thicknesses were approximately the same (0.6%), and it was also the same between blanket and patterned wafers. Furthermore, the strain in the long and narrow epi stripe regions with different widths and along <110> or <100> direction on the (110) samples was all very similar (0.63~0.67%). It was also similar to that for the blanket wafers, corresponding to fully strained films. AFM measurements showed much higher RMS (0.6 nm vs. 0.08 nm) and RMAX (3.7 nm vs. 0.4 nm) for pseudomorphic SiGe growth on (110) substrates compared to (100) substrates. PTEM and XTEM showed high crystalline quality with very low defect count in the SiGe source/drain regions and Si channel regions.
9:45 AM - D1.3
Source/Drain Stressor Device Development on SOI Substrate.
Da Zhang 1 , Bich-Yen Nguyen 1 , Brian Goolsby 1 , John Hackenberg 1 , veer dhandapani 1 , jill hildreth 1 , ross noble 1 , mo jahanbani 1 , stan filipiak 1 , ted white 1 , michael mendicino 1 , amr haggag 1 , melissa zavala 1 , patrick montgomery 1 , david theodore 1 , sharon murphy 1 , raghaw rai 1 , jack jiang 1 , kiwoon kim 1 , david sieloff 1 , nigel cave 1 , venkat kolagunta 1 , jon cheek 1 , suresh venkatesan 1 , joe mogab 1
1 Technology Solutions Organization, Freescale Semiconductor, Austin, Texas, United States
Show Abstract Embedded Source/Drain stressor has been applied as a major device enhancement approach for sub-90 nm node CMOS technology. In this technology, a layer of semiconductor material is epitaxially grown on the surface of pre-recessed source/drain regions of CMOS devices, and the difference in natural state lattice constants between the epitaxial layer and the source/drain substrate induces a preferential uniaxial stress to the channel area to enhance carrier mobility. For PMOS, this is achieved by growing embedded SiGe (eSiGe) in recessed Si source/drain to provide compressive stress to the channel.While eSiGe has been developed for bulk devices to a reasonable maturity, its application on SOI substrate encounters much higher challenges. The finite source/drain thickness on SOI puts an intrinsic limit on the amount of stressor material that can be incorporated, and this challenges integration optimization for achieving appreciable channel strain. The source/drain Si thickness after source/drain recessing is extremely small, therefore special attention is needed to minimize/mitigate silicon migration for maintaining epitaxy integrity. In this paper, eSiGe development on SOI substrate is presented. Various integration approaches are described, and electrical performance is compared. Optimizations of critical process elements, such as etch, clean, and epitaxy, and their impact on device performance are depicted. It is shown that enhanced isotropic recessing is achieved on the SOI device to maximize stressor incorporation. With careful process/integration tuning, defect-free epitaxial growth of stressor in recessed source/drain is obtained. The integration of eSiGe on SOI is able to provide >20% PMOS drive current enhancement.
10:00 AM - D1.4
Schottky Source/Drain Transistor on thin SiGe on Insulator integrated with HfO2/TaN gate stack.
Fei Gao 1 2 , Sungjoo Lee 1 , Rui Li 1 , S. Balakumar 2 , Chin-Hang Tung 2 , Dong-Zhi Chi 3 , Dim-Lee Kwong 2
1 , Silicon Nano Device Lab, Department of ECE, National University of Singaproe , Singapore Singapore, 2 , Institute of Microelectronics Engineering, Singapore, Singapore Singapore, 3 , Institute of Materials Research Engineering, Singaproe , Singapore Singapore
Show AbstractContinuous scaling of the Si based MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has aroused interests in finding alternative substrates to Si. Among them, thin body SGOI (SiGe-On-Insulator) with high percentage Ge concentration has many attractive properties. However, the significant increase of series resistance is one of the problems of thin body transistor, which results in the reduction of drive current. Schottky S/D (Source/Drain) technology has been considered as an alternative to heavily doped S/D, and promising results have recently been reported. In this paper, we report Si0.35Ge0.65 on Insulator p-channel MOSFET using Ni-germanosilicide Schottky source/drain and HfO2/TaN gate stack integrated with conventional self-aligned top gate process.Single crystalline (001) Si0.35Ge0.65-on-insulator is realized by novel approach of oxidizing amorphous SiGe film deposited on silicon-on-insulator substrates by a co-sputtering technique. After multi-step dry oxidation process, single crystal Si0.35Ge0.65-on-insulator (body thickness= 20nm) with uniform Ge concentration has been achieved. During the MOSFET fabrication process, thin Si passivation technique was used to suppress the GeO2 formation. And Ni-germanosilicide on the S/D was formed at 400°C.HfO2 film on single crystal Si0.35Ge0.65 channel remained amorphous after the whole transistor fabrication process. Peak inversion capacitance corresponds to an equivalent oxide thickness of 2.2 nm. A gate leakage of 2x 10-4A/cm2 at a gate bias of -1V is achieved. MOSFETs made on Ge or SiGe (with high percentage of Ge) substrates usually suffer from high gate leakage at elevated temperature, due to the formation of poor quality Ge oxide interfacial layer, or the diffusion of Hf into the interfacial oxide/Ge-substrate, or diffusion of Ge into the HfO2 film. Obtained low leakage current of Schottky S/D MOSFETs also demonstrates merits of its low temperature process for integration of high-k/metal gate stack with thin body SGOI transistor. In addition, the clear smooth interface between Si0.35Ge0.65 channel and Ni-germanosilicide is observed at S/D region. The sufficient overlap of Ni-germanosilicide S/D with gate electrode may be explained by the fact that Ni is the main diffusing species during solid-state reaction of Ni with Si and Ge.Well-behaved drain and source current of thin body SGOI Schottky S/D PMOSFET was demonstrated. Observed excellent agreement between drain and source current of fabricated SGOI Schottky S/D transistor indicates good interface at Schottky contacts and low junction leakage using thin body structure. Hole mobility extracted using split C-V is ~ 120 cm2/V-s at low electric field, which is comparable with hole mobility from conventional bulk Ge p-MOSFET with HfO2/TaN gate stack.
10:15 AM - D1.5
Large Optimisation of Source/Drain Architecture in Double Gate CMOS using Combined Static and Transient Analysis.
Christophe Krzeminski 1 , Dubois Emmanuel 2
1 ISEN, IEMN, Villeneuve d'Ascq France, 2 ISEN, IEMN, Villeneuve d'Ascq France
Show AbstractDouble Gate MOSFET's, based on thin-film body raise the difficult problem of source-drain resistance optimization to fully take advantage of the multi-channel structure. Numerous studies have tackled the optimization of the source/drain resistance (S/D) in bulk, SOI or multigated structures. Most of them focused on one particular aspect without considering the complete problem. Furthermore, the updated 2004 ITRS ROADMAP still based their specifications of lateral abruptness through short channel effects considerations [1]. This scaling rule given by Taur et al. recommends a lateral abruptness equal to 0.11 times the physical gate length [2]. The validity of this empirical rule is restricted to conventional bulk structures and to the 65nm technology node. No estimation can be given for more advanced architectures such as thin-film channels and multi-gated configurations. To improve this situation, an intensive simulation has been undertaken in order to optimize the S/D abruptness, S/D offset and contact resistivity for a sub-20 nm double-gate planar MOSFET architecture. The reference MOSFET is a double gate planar structure that match the dimensions expected in the 45nm technology nodes in its high performance flavour. Simulations have been carried out using a standard drift-diffusion transport model. Important conclusions can be raised with the analysis of several figures of merits ) Ion-Ioff figures ii) static voltage transfer characteristics of inverters iii) CVdd/Ion metrics and iv) real inverter delays under dynamic load in function of many parameters (S/D offset, lateral abruptness, contact resistivity). We show that the optimal S/D lateral profile can be easily obtained by determining the optimum current drive or the inverter delays as a function of the S/D offset for a given abruptness and an off-state current. Moreover, it is found that that the S/D extension must be sufficiently offset from the gate edge and that an unique offset is obtained for each abruptness. Both static and dynamic simulations confirms that the optimal S/D abruptness and offsets correspond to an underlap configuration. A marginal improvement in current drive and inverter delay is obtained for an abruptness steeper than 2nm/dec. To conclude, we stress that many optimisation studies of deeply scaled devices do not operate at an optimal S/D offset and abruptness. This may result in misleading conclusions especially when dynamic properties are considered. [1]SIA Semiconductor Industry Association, ``The international Technology Roadmap for Semiconductors-ITRS 2004''.[2] Y. Taur et al., IEDM Tech. Dig., p.789-p.792, 1998.
10:30 AM - **D1.6
Perspective on Emerging Devices and their Impact on Scaling Technologies.
Thomas Hoffmann 1 , Malgorzata Jurczak 1 , Serge Biesemans 1
1 , IMEC, Leuven Belgium
Show Abstract11:15 AM - D1.7
Schottky-barrier height tuning using dopant segregation in Schottky-barrier MOSFETs on fully-depleted SOI
Joachim Knoch 1 , Min Zhang 1 , Qing-Tai Zhao 1 , Siegfried Mantl 1
1 Institute of Thin Films and Interfaces, ISG1, Forschungszentrum Juelich, Juelich Germany
Show AbstractSchottky-barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) have recently attracted a renewed interest. This interest stems from the fact that SB-MOSFETs offer solutions for aggressively scaled devices related to the source and drain contacts: Due to metallic contacts directly attached to the channel, SB-MOSFETs exhibit low extrinsic parasitic resistances, offer easy processing and allow for well-defined device geometries down to smallest dimensions. However, at a metal-semiconductor contact a SB always builds up. A high barrier in turn results in low on-currents and causes poor subthreshold behavior. Therefore, intensive research has been devoted to the investigation of low SB silicides. Recently, dopant segregation during silicidation has been successfully used in n-type bulk SB-MOSFETs and a significant reduction of the effective Schottky-barrier height and hence a strong improvement of the electrical characteristics of SB-MOSFETs could be achieved. Here we will show that arsenic as well as boron segregation during silicidation can be used to strongly improve the electrical characteristics of both, n-type as well as p-type SB-MOSFETs on fully depleted SOI. To this end, SB-MOSFETs were fabricated on 25nm thick SOI. After mesa isolation an approximately 3.5nm thick gate oxide was grown using a low temperature wet thermal oxidation step. Subsequently, poly-silicon is deposited and patterned. Afterwards, the contact areas are implanted with arsenic (5keV, 5E14 per ccm) or boron (5keV, 1E15 per ccm), respectively, and the entire contact area is nickel silicided. An almost ideal off-state could be realized in the arsenic as well as in the boron case. In addition, in the on-state the devices show approximately an order of magnitude higher on-currents. The reason for this improvement is a highly doped, thin (on the order of a few nanometers) layer that forms at the contact-channel interfaces which in turn results in very thin Schottky-barriers with a strong increase of the tunneling probability through the barrier. While in case of arsenic segregation the dopant concentration in the segregation layer is large enough to ensure a linear increase of current for small drain-source bias (typical of conventional MOSFETs) in case of boron the device still exhibits a sub-linear increase of current. This is a clear signature of a still existing, significant Schottky-barrier. Low-temperature measurements of devices with arsenic segregation confirm that the effective is reduced from 0.64eV to about 0.1eV. Furthermore, with simulations, based on a one-dimensional model of the electrostatics and the non-equilibrium Green’s function formalism, we show that using dopant segregation in ultrathin body SOI SB-MOSFETs with ultrathin gate oxides leads to an even stronger improvement rendering the performance of the devices comparable to conventional MOSFETs.
11:30 AM - D1.8
Self-Aligned, Self-Organized Epitaxial Metal Source/Drain for Advanced SOI-MOSFETs.
Nobuyuki Mise 1 , Yukimune Watanabe 1 , Shinji Migita 2 , Toshihide Nabatame 1 , Hideki Satake 1 , Akira Toriumi 2 3
1 , MIRAI-ASET, Tsukuba, Ibaraki, Japan, 2 , MIRAI-ASRC, Tsukuba, Ibaraki, Japan, 3 , The University of Tokyo, Bunkyo-ku, Tokyo, Japan
Show AbstractGate length (Lg) variations, short channel effects (SCE), and parasitic source and drain (S/D) resistances (RS/D) are getting more serious in scaled MOSFETs. The ITRS requirements for the above challenges, however, cannot be satisfied only by ultra-shallow junction technology [1]. Particularly, the Lg variations are not easily solved by the present patterning technologies. This paper reports a new junction technology, which includes a self-aligned, self-organized epitaxial NiSi2 S/D formation associated with the dopant segregation at the metallurgical junction edges. The proposed S/D structure is composed of epitaxially grown NiSi2 in contact with the Si(111) facet whose lattice mismatch is 0.5%. The initial S/D edge is defined by an offset spacer in a self-aligned way to the gate. The silicidation front becomes atomically flat in a self-organized way by keeping NiSi2/Si(111) boundary unchanged because the silicidation along <111> is much slower than that along <100>. This means that the S/D edges are not directly determined by the offset spacer edge shape along the gate line and the LER immune effective channel length (Leff) could be achieved. This Si(111) facetted NiSi2 S/D on thin SOI helps to solve most of junction problems. First, it is expected that a significant suppression of the Leff variations caused by the patterned profile along the gate is achieved by the self-organized formation of the metallurgical junction edge. Second, SCE is suppressed due to the very shallow junction with an abrupt dopant profile on the metal S/D edge, which is spontaneously obtained by taking advantage of dopant segregation and activation [2, 3] at the NiSi2/Si interface by 600°C annealing [4]. Finally, RS/D is significantly reduced by the low-resistive metal S/D. The sheet resistance of 10 nm-thick NiSi2 was 50 Ω/sq, which is about 20 times smaller than that of highly doped Si (1×1020 cm-3) with the same thickness. This work was supported by NEDO.[1] http://public.itrs.net.[2] F. C. Shone et al., IEDM Tech. Dig., p.407 (1985).[3] N. Mise et al., Silicon Nanoelectronics Workshop Abst., p.20 (2005).[4] Y. Watanabe et al., Device Research Conference Dig., p.197 (2005).
11:45 AM - D1.9
Visualisation of Ge Condensation in SOI
Kristel Fobelets 1 , Benjamin Vincent 1 3 , Anthimos Christofi 2 , Munir Ahmad 1 , David McPhail 2 , Jing Zhang 1
1 Electrical and Electronic Engineering, Imperial College London, London United Kingdom, 3 , LETI, Grenoble France, 2 Materials, Imperial College London, London United Kingdom
Show AbstractCABOOM or Characterisation of Alloy concentration via Bevelling, Oxidation and Optical Microscopy has been proposed as a way to visualise the Ge condensation process. In this technique, the sample under investigation is first bevelled using chemical-mechanical polishing to present the structure in the depth of the wafer on the surface, followed by low temperature steam oxidisation. The dependency of the steam oxidation rate on the Ge concentration in the layer gives an oxide thickness variation proportional to the alloy composition that is visualised by optical interference using white light.In this study we have used the CABOOM technique in conjunction with SIMS and XRD to investigate the Ge diffusion process as a function of oxidation time and temperature.A commercial SOI wafer with a top Si thickness of 60 nm and a buried oxide layer thickness of 370 nm has been used as starting substrate. A SiGe alloy with a Ge concentration of 8% and a thickness of 100 nm has been grown by CVD on the SOI layer.Dry thermal oxidation was done in a tube furnace flushed with oxygen during the temperature ramp-up, oxidation and ramp-down time in order to condense the Ge between the top oxide and the buried oxide of the SOI.Two different processes where investigated: a one step process using one temperature setting only and a two step process using two temperature settings consecutively. The temperature range was chosen between 1050C and 1200C, whilst the oxidation time between 1 and 8 hours.The shift of the top surface and homogeneity of the Ge concentration sandwiched between the oxide layers is well visualised in the CABOOM picture, giving a clear indication of where the Ge concentration inhomogeneities occur in the remaining layer. SIMS profiles are consistent with the CABOOM results but give less information on the homogeneity in the thin layer than CABOOM. XRD measurements confirm the Ge concentration estimated from the CABOOM measurements.For the one step condensation process, CABOOM visualises that at low temperatures a Ge spike appears between the Si SOI layer and the SiGe CVD layer. This spike disappears for longer oxidation times. In the two step process using first a low temperature in order to form a top oxide whilst preventing Ge out-diffusion, followed by a high temperature step to enhance diffusion, CABOOM shows that the low temperature spike does not disappear by the short high temperature step, indicating the the low temperature step should be limited in time to avoid excessive spiking.These results show that CABOOM is a usefull technique to visualise the diffusion processes that happen during Ge condensation in SOI.
12:00 PM - D1.10
Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation
Yawei Jin 1 , Lei Ma 1 , Chang Zeng 1 , Doug barlage 1
1 Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina, United States
Show Abstract According to most recent 2004 International Technology Roadmap for Semiconductor (2004 ITRS), the high performance (HP) MOSFET physical gate length will be scaled to 9nm (22nm technology node) in 2016. We investigate the manufacturability of this sub-10nm gate length fully depleted SOI MOSFET by TCAD simulation. The commercial device simulator ISE TCAD is used. While currently impractical for experiments this study can be used to project performance goals for aggressively scaled devices. In this paper, we will optimize different structure and process parameters at this gate length, such as body thickness, oxide thickness, spacer width, source/drain doping concentration, source/drain doping abruptness, channel doping concentration etc. The sensitivity of device electrical parameters, such as Ion, Ioff, DIBL, Sub-threshold Swing, threshold voltage, trans-conductance etc, to physical variations will be considered. The main objective of this study is to identify the key design issues for sub-10nm gate length Silicon based fully depleted MOSFET at the end of the ITRS. The paper will give the optimized device structure finally and optimized performance will be reported.
12:15 PM - D1.11
Schottky Barrier Height of CVD TiSiN, PVD TiN, and ALD TiN on p-Si (100).
Kaveri Mathur 1 , Daniel Pham 1 2 , Barry Sassman 1 , Lisa Widodo 1 , George Brown 1 , Peter Zeitzoff 1 , Howard Huff 1 , Larry Larson 1
1 , SEMATECH, Austin, Texas, United States, 2 , Freescale Semiconductor, Austin, Texas, United States
Show Abstract With CMOS scaling approaching its limit during the next decade or so, the study of the metallic-silicon contact becomes more significant. We have accordingly studied several aspects of the Schottky barrier characteristics of chemical vapor deposition (CVD) TiSiN, physical vapor deposition (PVD) TiN, and atomic layer deposition (ALD) TiN on p-Si. The effect of deposition method and also of metal thickness on barrier height was evaluated. TiN is a very promising material due to its low electrical resistivity, high thermal stability, good adhesion, and high CMOS process compatibility. This study is particularly useful for the various semiconductor applications of TiN such as diffusion barriers, metal gate electrode and also for novel devices like Schottky Barrier MOSFETs. TiSi2 was also evaluated for more complete characterization of Ti-based compounds. In this work, p-Si(100) doped to 2E15/cm3 was used as the substrate. The diode test structures were circular openings of various areas (5E-5 to 5E-4 cm2) on 150Å SiO2 and a 1500Å Si3N4 hardmask. An HF clean was performed immediately before the metal deposition to remove native oxide. Approximately 200 Å of TiSiN (CVD) and TiN (ALD and PVD) were deposited. Mean barrier height was estimated for better accuracy. Thicker ALD and PVD TiN films (~400 Å) were also evaluated. Al was used for the backside ohmic contact.A forming gas anneal was performed at 480°C for 30 minutes in a H2/N2 ambient. Schottky barrier heights were evaluated using room temperature forward-biased current-voltage (I-V) measurements. Since the diode series resistance can lead to inaccurate extraction of the barrier height and ideality factor using the I-V method, a correction for the series resistance was implemented. The barrier heights obtained for different deposition methods and thicknesses were compared with the respective measured workfunctions. A correlation was observed between the two parameters, and the barrier heights were found to follow the trends observed in the workfunctions. The actual value of the barrier height is different from the ideal value (metal workfunction - semiconductor electron affinity) due to the effect of interface states. An increase in the barrier height was observed for the 400 Å PVD and ALD TiN compared to the 200 Å value. This appears to be due to donor-like trap generation at the interface resulting from excess N in the thicker film, which was confirmed with SIMS analysis.The scope of this work can be extended to alternate materials and substrates.The results are summarized in the table below.
12:30 PM - **D1.12
CMOS Scaling Challenges and Performance Enhancers.
Witek Maszara 1 , Zoran Krivokapic 1
1 , AMD, Sunnyvale, California, United States
Show AbstractCMOS transistor scaling experiences a slow-down, for the first time in history. Gate oxide thickness stopped scaling from 90 to 65nm technology node, due to excessive gate current concerns, and remains around EOT=12A. This puts some constrains on further scaling of transistor gate length. A demand for uninterrupted scaling of transistor performance increased efforts in novel enablers of better electrostatics and of higher channel transport. The former include metal gate electrode, high k dielectric and fully depleted device architectures (single and multigate), the latter – mobility improvements by stress imposed on the device’s channel and alternative channel materials. Multiple challenges in introducing those performance enhancers ranging from understanding what kind of metal work function we have available without pinning the Fermi level for PMOS devices to stability and reliability of the gate stack, and potential interaction of applied strain with soft phonons in the gate dielectric, to statistical fluctuations in channel doping and line edge roughness effects need to be met and overcome. We will discuss some of the potential solutions including fully depleted devices and address difficulties they face in large scale manufacturing, like channel thickness control, statistical doping fluctuations in extensions, large parasitic resistance, etc.
D2: Process and Substrate-Induced Strained-Si Development
Session Chairs
Wen-Chin Lee
Scott Thompson
Tuesday PM, April 18, 2006
Room 3006 (Moscone West)
2:30 PM - D2.1
A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing.
Y.W. Teh 1 , J. Sudijono 1 , S. Thirupapuliyur 2 , S. Venkataraman 2 , Alok Jain 2
1 , Chartered Semiconductor, Hopewell Jn., New York, United States, 2 , Applied Materials, Sunnyvale, California, United States
Show AbstractAbstract:This work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film is deposited at low temperature to meet the requirements of NiSi integration while maintaining void-free gap fill. A manufacturable and highly reliable oxide film has been demonstrated through both device data and TCAD simulation showing ~6% NMOS Ion-Ioff improvement; with no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the Impact on out-of-plane stress effect on device drive current performance improvement.Device Fabrication and Process Integration:Transistor drive current enhancement from stressed Si3N4 liners has been shown separately for NMOS and PMOS devices [1]. Shallow Trench Isolation (STI), poly-silicon gate and Nickel silicide layers were formed using a conventional CMOS process. Following these steps a novel dielectric HARP (High aspect ratio process) film using a new O3/TEOS based fill process, with film property shown in table 1, was deposited followed by CMP, contact etch and W CMP.In order to understand the effect of strain on the CMOS device, we made reference to early work by C.S. Smith on the piezoresistance effect of semiconductors. The fractional change in silicon resistivity is given by:δρ/ρ = XΠi,j --------------------------------------(1)where ρ is the Si resistivity, X is the applied stress and Πi,j is the piezoresistance coefficient for different crystallographic orientations i,jThe change in Si resistance is strongly dependent on the piezoresistance coefficient. For a [001] Si surface and notch along <110> wafer,a positive coefficient with a corresponding compressive strain will produce lower Si resistivity.The NMOS performance gain seen on HARP as compared to HDP is partly due to the strong tensile Ez orientation strain. This thick HARP PMD film induces a strong pulling/lifting strain (tensile) on the Poly and Si substrate interface. Thus creating a high compressive residue strain on the Si channel in the Ez orientation. This compressive strain in the channel will significantly boost the NMOS performance as per the piezoresistance coefficient. At the same time, this PMD will also induce a compressive strain in the PMOS. But from the Piezoresistance coefficient data it shows that the PMOS is insensitive to the Ez strain effect. Therefore the PMOS performance remains unchanged.References:1. S. Ito et al., IEDM 2000, p. 247.
2:45 PM - D2.2
Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features.
Claude Ortolland 1 , Pierre Morin 2 , Franck Arnaud 2 , Stephane Orain 1 , Chandra Reddy 3 , Catherine Chaton 4 , Peter Stolk 1
1 , Philips Semiconductors, Crolles France, 2 , ST Microelectronics, Crolles France, 3 , Freescale, Crolles France, 4 , CEA-LETI, Crolles France
Show Abstract3:00 PM - **D2.3
Strain-Si Technologies for Nano-CMOS Devices.
Ken-Ichi Goto 1
1 , TSMC, Hsinchu Taiwan
Show Abstract3:30 PM - D2.4
Process-Induced Strained P-MOSFET Featuring Nickel-Platinum Silicided Source/Drain.
Rinus Lee 1 , Tsung-Yang Liow 1 2 , Kian-Ming Tan 1 , Kah-Wee Ang 1 2 , King-Jien Chui 1 , G.-Q. Lo 2 , D.-Z. Chi 3 , Yee-Chia Yeo 1
1 Silicon Nano Device Lab, Electrical and Computer Engineering, National University of Singapore, Singapore Singapore, 2 , Institute of Microelectronics, Singapore Singapore, 3 , Institute of Materials Research and Engineering, Singapore Singapore
Show AbstractStrained silicon technology has recently been actively explored for the improvement of carrier mobility in metal-oxide-semiconductor (MOS) transistors. One of the most cost-effective and manufacturable options of introducing strain in the transistor channel is through the expoitation of Process-Induced Strain. Strain can be introduced at various process steps during transistor fabrication, e.g. formation of shallow-trench isolation, contact-etch-stop layer, and metal-silicide. In this paper, we explore the use of nickel-platinum (NiPt) silicide as the source/drain stressors to induce beneficial strain in the channel region of a p-channel MOS transistor for improved hole mobility and drive current performance. We observed an appreciable drive current enhancement of 13% with the use of NiPtSi, in comparision with a device with nickel-silicided source/drain. A transistor with nickel-silicided source/drain has a tensile strain in the [110] channel direction. The introduction of Pt in NiSi reduces the tensile strain induced in the channel, due to the smaller lattice mismatch in the [110] direction and the lower volume of contraction during the silicidation process. This study also explores the effect of a varying amount of Pt in the NiSi on the device performance. Material analysis performed include X-ray diffraction and secondary ion mass spectroscopy. The integration of NiPtSi as the source/drain silicide material is therefore a viable and cost-effective process-induced strain technique to further optimize the drive current of p-channel MOS transistors.
3:45 PM - D2.5
Thermal Stability of Thin Virtual Substrates for High Performance Devices.
Sarah Olsen 1 , Steve Bull 1 , Peter Dobrosz 1 , Enrique Escobedo-Cousin 1 , Anthony O'Neill 1 , Howard Coulson 2 , Cor Claeys 3 , Roger Loo 3 , Romain Delhougne 3 , Matty Caymax 3
1 , University of Newcastle, Newcastle upon Tyne United Kingdom, 2 , Atmel North Tyneside, Newcastle upon Tyne United Kingdom, 3 , IMEC, Leuven Belgium
Show Abstract4:30 PM - **D2.6
Strain Engineering and Body Biasing for Optimization of Sub-45nm CMOS Performance
Kyoungsub Shin 1 , Sriram Balasubramanian 1 , Xin Sun 1 2 , Tsu-Jae King 2 1
1 Electrical Engineering and Computer Sciences Dept., University of California, Berkeley, California, United States, 2 Advanced Technology Group, Synopsys, Inc., Mountain View, California, United States
Show AbstractProcess-induced strain is already being used to enhance the performance of bulk-Si MOSFETs in state-of-the-art CMOS products today, and it is expected to continue to provide enhancements as the lateral dimensions of transistors are scaled down into the sub-45nm regime. Non-classical transistor structures, such as the planar fully depleted silicon-on-insulator (FDSOI) FET and the vertical double-gate FinFET, provide superior control of short channel effects and will likely be needed to meet performance requirements for low-power applications in this regime. In addition, active body-biasing can provide further reduction in static power consumption and also reduce the impact of process variations. Therefore, it will be desirable to apply process-induced strain as well as active body-biasing to non-classical transistor structures in order to maximize the benefits of transistor scaling. In this paper, the impact of strain on thin-body (planar and vertical) SOI vs. bulk-Si transistor structures is considered in order to provide guidance for optimization of the three-dimensional (3-D) channel strain profile and crystalline orientation to maximize CMOS performance. Simulated 3-D channel stress profiles are then used to compare the effectiveness of various approaches to inducing strain for the different device structures. Classic piezoresistance coefficients are used to gauge the relative mobility enhancement factors. The benefits of body-biasing are quantified for optimized device designs via 3-D device simulations.
5:00 PM - D2.7
Impact of In-situ C Doping on Implant Damage and Strain Relaxation in Epitaxial SiGe Layers on Si
Jinping Liu 1 , Anthony Domenicucci 2 , Anita Madan 2 , Jinghong Li 2 , Judson Holt 2 , Richard Murphy 2 , Andrew Turansky 2 , Robert Davis 2 , Lindsay Burns 2 , John Sudijono 1
1 Technology Development, Chartered Semiconductor Manufacturing Ltd., Hopewell Junction, New York, United States, 2 , IBM Systems and Technology Group, Hopewell Junction, New York, United States
Show AbstractStress engineering has become an industry standard means for enhancing Si device performance. Epitaxial SiGe grown in p-MOS source/drain areas has been used to introduce stress in the transistor channel areas which results in device performance enhancement. Integration of epi SiGe with Si device manufacturing processes is however not trivial. It is well-known that ion implantation processes, widely used in Si CMOS device fabrications, can cause damage to Si as well as strain relaxation in epitaxial SiGe. Such strain relaxation is not desirable for embedded SiGe in S/D areas . Substitional C is known to act as a Si interstitial sink and has been studied for implant damage removal. In this work, implant damage and strain relaxation in epitaxial SiGe layers on Si (001) and the effects of in-situ C doping on defectivity in epitaxial SiGe have been studied. Films were characterized using HRXRD for strain relaxation and Ge concentration, AFM for surface morphology, SIMS for dopant profiling, AES for Ge compositional profiling and TEM for implant damage and strain relaxation. For a 65 nm SiGe layer with~25% Ge, conventional p-MOS S/D, halo and extension implants led to significant implant damage and strain relaxation. Two defect bands were observed: one close to the surface and another one at SiGe/Si interface. In-situ C doping (1019-20 /cm3) of SiGe was found to eliminate the implant damage close to SiGe/Si interface area and prevent significant strain relaxation. Studies are now underway to further characterize the effects of composition and film thickness.
5:15 PM - D2.8
Optimization of Device Parameters for Strained Silicon on Insulator MOSFETs
Yan Du 1 , Saurabh Chopra 1 , Nivedita Biswas 1 , Veena Misra 1 , M.C. Ozturk 1
1 ECE Department, North Carolina State University, Raleigh, North Carolina, United States
Show AbstractPrevious work on bulk p-channel MOSFETs with SiGe source/drain junctions has shown that the uniaxial compressive strain induced in the channel can provide more than 50% improvement in current drive. Recently, the same concept was extended to a partially depleted SOI-MOSFET structure. In this work, we present results from a simulation study on the impact of structural parameters on the strain induced in a fully depleted channel with a gate length of sub 50nm. Simulations were carried out using ISE-TCAD (version 10 with FLOOPS-ISE TM). The critical parameters include the Si body thickness, source/drain recess depth, SiGe thickness and Ge content. The results indicate that the body thickness has a profound impact on the magnitude of the induced strain and results in a much larger increase of strain compared to bulk MOSFET. It is shown that the strain steadily increases with decreasing body thickness for the same recess and SiGe depth. The Ge concentration and recess depth also provide similar knobs for increasing the total strain in the channel. In addition, the impact of silicidation on the net strain was also explored. Finally, a discussion of the advantages and tradeoffs of the various stressors will be provided.
5:30 PM - D2.9
The Importance of Grain Orientation in Process Induced Strain.
Cristina Torregiani 2 1 , Alessandro Benedetti 1 , Hugo Bender 1 , Karen Maex 2 1
2 Electrical Engineering, KULeuven, Leuven Belgium, 1 spdt, IMEC, Leuven Belgium
Show AbstractThe growing interest in the presence of strain fields in a transistor channel demands for an attentive study of all the sources that contribute to create it. Together with the strain intentionally induced by different methods (e.g. by introducing a SiGe alloy in the source/drain regions), a big importance should be attributed to the process induced strain that is always present in any transistor structure: whenever dissimilar materials are put in contact and patterned, in fact, strain arises in the contact areas. The thermomechanical properties of these materials play a fundamental role in determining the resulting stress/strain field in adjacent regions. Among those properties, the Coefficient of Thermal Expansion (CTE) is of particular importance for the case of silicides because of the mismatch in their CTE values with respect to silicon. In specific, nickel monosilicide (NiSi) is characterized by a strongly anisotropic CTE, therefore it is expected that the orientation of its grains in a given structure will affect the strain field build up.This study analyzes the role that NiSi lines have in the build up of strain in silicon, with special focus on the impact of the silicide morphology and orientation. The structures analyzed are composed of an array of 40 nm thick NiSi stripes spaced by silicon oxide/silicon nitride dummy gates. The silicide length is kept constant at 120 nm while the “gate” length is varied; the two cases of 480 nm and 240 nm long gates are presented. Quantitative strain level determination through the Convergent Beam Electron Diffraction (CBED) technique shows a significant asymmetry in the strain field distribution around the NiSi lines; the asymmetry is attributed to the silicide grains orientation. This supposition is supported by High Resolution Transmission Electron Microscopy (HRTEM) analysis, which displays the presence of different orientations for different NiSi lines.
5:45 PM - D2.10
Impact of Heavy Boron Doping and Nickel Germanosilicide Contacts on Biaxial Compressive Strain in Pseudomorphic Silicon-Germanium Alloys on Silicon.
Saurabh Chopra 1 , Mehmet Ozturk 1 , Veena Misra 1 , Kristopher McGuire 2 , Laurie McNeil 2
1 Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 Department of Physics and Astronomy, University of North Carolina, Chapel Hill, North Carolina, United States
Show AbstractIn recent years, the semiconductor industry has increasingly relied on strain as a performance enhancer for both n and p-MOSFETs. For p-MOSFETs, selectively grown Si1-xGex alloys in recessed source/ drain regions are used to induce uniaxial compressive strain in the channel. In order to induce compressive strain effectively using this technology, a number of parameters including recess depth, Si1-xGex thickness (junction thickness), sidewall thickness, dopant density, dislocation density, and contact materials have to be optimized. In this work, we have studied the effects of heavy boron doping and self-aligned germanosilicide formation on local strain. Raman spectroscopy has been used to study the impact of heavy boron doping on compressive stress in Si1-xGex films. Strain energy calculations have been performed based on Vegard’s law for ternary alloys and the effect of boron on strain in Si1-x-yGexBy alloys has been modeled quantitatively. It will be shown that, owing to the smaller size of a boron atom, one substitutional boron atom compensates the strain due to 6.9 germanium atoms in the Si1-x-yGexBy film grown pseudomorphically on silicon. The critical thickness of Si1-x-yGexBy has been calculated for the first time based on kinetically limited critical thickness calculations for metastable Si1-xGex films. It will be shown that the critical thickness of the alloy increases as the boron content in the alloy is increased, making boron concentration an additional parameter for optimizing strain in the MOSFET. Based on these conclusions, boron concentration can be used to preserve the strain for thicker Si1-x-yGexBy films (compared to Si1-xGex films) while keeping the dislocation density low. Furthermore, we show that NiGeSi contacts can have a profound impact on the Si1-xGex strain. Our results indicate that NiGeSi introduces additional stress in the underlying Si1-x-yGexBy, which further affects the strain induced in the channel.
D3: Poster Session
Session Chairs
Wednesday AM, April 19, 2006
Salons 8-15 (Marriott)
9:00 PM - D3.1
Raman Spectroscopy Based All Stress Tensor Component In-line Metrology for SOI and SiGe Device Manufacturing.
Wojciech Walecki 1 , Talal Azfar 1 , Alexander Pravdivtsev 1 , Manuel Santos 1 , Jae-sok Ryu 1 , Tim Wong 1 , Aiguo Feng 1 , Ann Koo 1
1 , FSM, San Jose, California, United States
Show AbstractMicro-Raman spectroscopy has been established as an effective laboratory tool for characterization of chemical composition and stress in SiGe and SOI based structures ([1] and references within). In most commonly encountered applications accuracy of results of the measurements is limited by relatively low spectral resolution of the system. In our paper we present results of measurements suing dual wavelength (excitation wavelengths of 363.8 nm and 488.0 nm), allowing us to obtain resolution and stability of the system of the order of 0.02 cm-1 (which corresponds to stress below 10 MPa in Si). We also discuss in detail advantages of using resonant UV Ar excitation at 363.8 nm versus commonly used HeCd lasers (325 nm).Most of experimental systems provide stress information about chemical composition of the material, and limited information about stress related to only one independently measured scalar – stress induced change of Stokes shift of LO phonon. In cubic crystal stress tensor has six independent values. This means that these simple measurements do not provide directly values of remaining five independent stress tensor components, and depend on symmetry based assumptions. Polarization dependent micro-Raman measurements described by Bonera et al. [2] offered partial solution to this problem by showing that by controlling polarization and by suing high numerical aperture micro-Raman tool one can determine independently, up to three components of out of six independent stress components in silicon. Furthermore, Loechelt et al. [3] demonstrated that by using off axis configuration it is possible to determine all six independent components of a stress tensor, with lateral resolution of the order of 50 um. In this paper we propose new solution, which does not suffer from limitation of the mentioned above techniques [2], [3]. We describe concept, discuss theory, and fundamental limitations of novel optical probe allowing full characterization of all six components stress tensor, while preserving high spatial resolution (< 1 um). [1] R. Loo, R. Delhougne, P. Meunier-Beillard, M. Caymax, P. Verheyen, G. Eneman, I. De Wolf, T. Janssens, A. Benedetti, K. De Meyer, W. Vandervorst, and M. Heyns, in High-Mobility Group-IV Materials and Devices, edited by Matty Caymax, Ken Rim, Shigeaki Zaima, Erich Kasper, and Paulo F.P. Fichtner (Mater. Res. Soc. Symp. Proc. 809, Warrendale, PA , 2004), B1.2[2] E. Bonera, M. Fanciulli, and D. N. Batchelder, J. Appl. Phys., Vol. 94, No. 4, 15 August 2003[3] G.H. Loechelt, N.G. Cave, and J. Menéndez, J. of Applied Physics, 86, 6164-80 (1999).
9:00 PM - D3.10
A Single Nanoparticle Transistor
Stephen Campbell 1 , Yongping Ding 1 , Ying Dong 1 , Ameya Bapat 2 , Julia Deneen 3 , C. Carter 3 , Uwe Kortshagen 2
1 ECE, University of Minnesota, Minneapolis, Minnesota, United States, 2 mechanical Engineering, University of Minnesota, Minneapolis, Minnesota, United States, 3 Chemical Engineering / Materials Science, University of Minnesota, Minneapolis, Minnesota, United States
Show Abstract9:00 PM - D3.11
Sub-aF resolution C-V characterization of small-scale MOSFETs
Ali Gokirmak 1 , Sandip Tiwari 1
1 Electrical and Computer Engineering, Cornell University, Ithaca, New York, United States
Show AbstractCarrier mobility and effective device dimensions are important parameters in CMOS design. Modern deep submicron FET structures exhibit significant edge and stress related effects, and non-uniform distribution of carriers due to complicated electric field pattern. Due to these effects, which vary with device dimensions, parameters such as carrier distribution and mobilities, effective device width (Weff) and length (Leff) can only be extracted using C-V measurements performed on the specific small scale devices. In recent years high carrier mobilities are reported for nanowire and carbon nanotube FETs. However the values for the carrier mobilities have been estimated using theoretically calculated values for the device capacitance due to difficulties in measuring C-V characteristics of these devices, amounting to inversion layer capacitances in the sub-fF regime. Techniques for small capacitance measurements are needed to quantify the carrier mobilities reported for small scale CMOS and nanowire transistors. We have developed a technique for measurement of change in capacitance as a function of gate bias utilizing the ambient noise in the system in order to achieve sub aF resolution through large number of repeated measurements. The measurements are performed in ambient atmosphere at room temperature using a commercial RLC meter with 1 MHz AC signal and a DC probe setup. The measured capacitance information has an arbitrary offset determined by the errors in the calibration. However gate to source/drain capacitance change as a function of the gate voltage has two characteristic slope changes, one at the onset of inversion and a second as the channel is inverted. Using this non-linearity of the gate to source/drain capacitance information, inversion layer capacitance is accurately extracted for very small scale transistors, down to 50 aF of inversion layer capacitance.Making use of noise in order to achieve high level of signal sensitivity is known as ‘Stochastic Resonance’. There is an optimum level of noise in order to detect signals detection below the resolution limit of a threshold system. Making use of noise allows use commercial RLC meters and standard DC wafer characterization setups to achieve ultra-high resolution C-V measurements required by small scale MOSFETs and nano-wire transistors.The utility of this technique is demonstrated on bulk Si narrow channel transistors with side-gates, with sub-100 nm channel width and sub-70 nm physical gate length with inversion layer capacitances in the order of 50 aF. The details of the C-V measurement technique will be summarized along with the extracted carrier mobilities and the effect of side-gate bias on the carrier mobility in small scale devices. fA resolution current measurements using a commercial parameter analyzer using this technique is also going to be demonstrated.
9:00 PM - D3.12
BCl3/N2 Plasma for Advanced non-Si Gate Patterning
Denis Shamiryan 1 , Vasile Paraschiv 1 , Salvador Eslava-Fernandez 1 , Marc Demand 1 , Mikhail Baklanov 1 , Werner Boullart 1
1 , IMEC, Leuven, Flemis Brabant, Belgium
Show Abstract9:00 PM - D3.13
Layer Transfer of Hydrogen-implanted Silicon Wafers by Thermal-Microwave Co-Activation.
T. -H. Lee 1 2 , Y. Y. Yang 2 , C. -H. Huang 2 , Y. K. Hsu 2 , S. Lee 2 , Q. Gan 3 , C. S. Chu 4
1 Institute of Materials Science and Engineering, National Central University, Chung-Li City Taiwan, 2 Mechanical Engineering, National Central University, Chug-Li City Taiwan, 3 , United SOI Corporation, Berkeley, California, United States, 4 , Shenyang SOI Corporation, Shenyang China
Show Abstract9:00 PM - D3.2
Evidence of Reduced Self Heating with Partially Depleted SOI MOSFET Scaling.
Mikael Casse 1 , Georges Guegan 1 , Romain Gwoziecki 1 , Olivier Gonnard 2 , Gilles Gouget 2 , Christine Raynaud 1 , Simon Deleonibus 1
1 , CEA/DRT-LETI, Grenoble France, 2 , ST Microelectronics, Crolles France
Show Abstract9:00 PM - D3.3
Quantum Well Nanopillar Transistors.
Shu-Fen Hu 1
1 , National Nano Device Laboratories, Hsinchu Taiwan
Show AbstractWe have fabricated vertical single-electron transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. A part of surrounding gate arranges source, gate and drain vertically. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.
9:00 PM - D3.4
Effect of Spacer Scaling on MOS Transistors.
Wai Shing Lau 1
1 School of EEE, Nanyang Technological University, Singapore Singapore
Show Abstract9:00 PM - D3.5
Growth of InGaAs on Nanometer-scale Patterned Si substrates by Metalorganic Vapor Phase Epitaxy
Robyn Woo 1 , Dick Cheng 1 , Robert Hicks 1
1 Chemical Engineering, UCLA, Los Angeles, California, United States
Show AbstractIndium gallium arsenide is a promising material for high speed, low power devices in next generation integrated circuits. This III/V semiconductor exhibits high mobility, reduced phonon scattering, and a large ballistic mean-free path. However, a major challenge in integrating this material into existing Si technology is the epitaxial growth of InGaAs on silicon wafers. The lattice mismatch of >4% generates strain, which produces dislocations in bulk thin films. In order to minimize misfit dislocations in the material, a thick buffer layer, typically, a few microns is required. In this report, we present an alternative approach for epitaxial growth of defect-free InGaAs on Si (100) using nano-scale patterned Si substrates. At the meeting, we will discuss the key fabrication variables such as the substrate orientation, the pattern structure and dimensions, and the buffer layer growth and their relationship to dislocation density and surface smoothness.
9:00 PM - D3.6
Selective Oxidation Of Sige Alloys To Make Ge-On-Insulator Structures.
Nevran Ozguven 1 , Paul McIntyre 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States
Show AbstractThe kinetics of direct oxidation of a reduced-pressure chemical vapor deposition grown Si1-xGex layer on a SOI (100) substrate, and the strain state and crystalline perfection of the resulting high-Ge content layers were explored. Thermal oxidation was carried out at temperatures below the melting temperature of Si1-xGex. This is a means of preparing high mobility Ge-rich semiconductor channels on insulator for future high performance transistors. During oxidation Ge atoms were rejected from the SiO2 layers and their out-diffusion was suppressed by the top and buried oxides. As a result, the thickness of the SiGe layer decreased and the Ge concentration increased during oxidation. The oxidation temperature and thickness of the initial Si1-xGex layer were varied to control the strain in the SiGe layer. We found it is possible to retain almost all of the strain initially-present in Ge-rich layers for the compositions we have studied, for example with an initial Ge composition of 15% resulting in a final Ge composition of more than 40%. Transmission electron microscopy was used to measure the film thickness and to probe for crystallographic defects in the layers. The Ge fraction and the strain in the SiGe layer as a function of oxidizing conditions were determined using x-ray diffraction. Secondary Ion Mass Spectrometry was used to observe Ge depth profiles.
9:00 PM - D3.7
Quantitative X-ray Probes for Strain in Silicon Nanostructures.
Rebecca Sichel 1 , P. Evans 1 , M. Roberts 1 , D. Tinberg 1 , M. Lagally 1 , Z. Cai 2
1 Materials Science Program, University of Wisconsin, Madison, Madison, Wisconsin, United States, 2 , Argonne National Laboratory, Argonne, Illinois, United States
Show AbstractThe small scale of silicon devices is placing great demands on the structural characterization methods used during the development process. Until recently, conventional x-ray diffraction or Raman spectroscopy had proved to be adequate for structural determination. However, neither of these methods is capable of measuring a small enough area to differentiate between nanostructures and their surrounding environments. The wavelengths of light used in Raman spectroscopy are too long to allow for the necessary focusing. The x-rays produced by laboratory sources are also unable to achieve small enough spot sizes. Synchrotron x-ray microdiffraction techniques provide a high resolution alternative to other structural techniques. The focused beam allows for accurate, quantitative measurements of strain at the 100 nm scale. We have used this to determine the local strains caused by germanium hut nanostressors on freestanding silicon. Germanium huts (typically 50 nm across) were grown on a 30 nm thick silicon membrane. The huts induced radii of curvature in the silicon membrane as small as 6µm, which corresponds to a difference of .5% in strain between the top and bottom of the membrane. The deflection and strains in larger scale silicon bridges have also been measured quantitatively using the same technique. Silicon bridges bowed upwards in response to a tensile strain by thin silicon nitride layers at the ends of the bridge. By measuring the broadening of the Si (220) reflection in 2θ, the inplane strain could be directly measured. It was determined that a .1% difference existed between the strains of the top and bottommost planes of the beam. We were also able to measure the tilt of the planes of silicon using the shifting of the (004) reflection at different points along the bridge, thus determining the actual deflection profile along its length.
9:00 PM - D3.8
High Quality Low Temperature Silicon Dioxide.
Hood Chatham 1 , Yoshi Okuyama 1 , Karl Williams 1 , Martin Mogaard 1 , Helmuth Treichel 1
1 , Aviza Technology, Inc., Scotts Valley, California, United States
Show AbstractAlthough much effort has been expended toward developing alternate dielectrics for use in fabricating ULSI circuits, there is still a need for high quality SiO2 films. In particular, process temperature restrictions have increased the demand for high quality, low temperature SiO2 films. Such films have multiple applications in microelectronics, including use as passivation coatings, interlevel dielectrics, gate dielectrics in metal oxide semiconductor field effect transistors (MOSFETs), thin film transistors, and in devices using dual spacers. Advanced devices at the 65-nm node and beyond are typically fabricated with nickel silicided electrodes—which enable lower junction silicon consumption, lower sheet resistance, and reduced agglomeration, but require subsequent process temperatures to be below 550°C. Also, to prevent movement of the ultra shallow junctions (USJ) during a subsequent thermal cycle, the temperatures for process steps after USJ formation must be kept below 600°C. To meet these needs, a low temperature (<500°C) SiO2 process has been developed that results in excellent dielectric quality. This paper presents results on high quality SiO2 films deposited at temperatures from 250°C to 450°C using a novel proprietary and versatile silicon precursor using oxygen, oxygen + ozone, or nitrous oxide as the oxidizer. Process results from flexible batch and single wafer platforms are compared. Composition, electrical properties (leakage current density), film stress, deposition rate and step coverage results are presented.References1. H. Chatham, K. Williams, T. Lazerand, J. Owyang and H. Treichel, 22nd International VLSI/ULSI Multilevel Interconnection Conference, Fremont, Calif., Oct. 2005.
9:00 PM - D3.9
Strain Relaxation and Solid Phase Epitaxial Regrowth in Ion-Implanted Strained Silicon on Relaxed SiGe
Michelle Phen 1 , Kevin Jones 1 , Valentin Craciun 1
1 , University of Florida, Gainesville, Florida, United States
Show AbstractThe relaxation process of strained silicon films on silicon-rich relaxed SiGe alloys has been studied. Experimental structures were generated via Molecular Beam Epitaxial (MBE) growth techniques and contain a strained silicon capping layer of approximately 50 nm on top of relaxed SiGe. The relaxed SiGe alloy compositions range from 0 to 30 atomic % germanium. A 12 keV Si+ implant at a dose of 1x10^15 atoms/cm^2 was used to generate an amorphous layer ~250Å thick thus is confined within the strained Si cap. Upon annealing, it was found that the solid phase regrowth process broke down for higher strain levels and the regrowth related defects were observed using cross-sectional transmission electron microscopy (XTEM). The crystalline quality of the Si cap layer was assessed by HRXRD. Omega-2theta rocking curves and reciprocal space maps were acquired for (004), (113), and (224) peaks and modeled to obtain the thickness and lattice parameters of the layers. X-ray reflectivity and diffuse scattering investigations were used to monitor changes in Si cap thickness and surface and interface roughness. In addition, high-resolution X-Ray diffraction rocking curves and reciprocal space map results indicate a reduction in strain for the silicon capping layer. From asymmetrical reciprocal space maps like those for (224) and (113) it was possible to observe that the relaxation process was not homogeneous, with the regions that remained fully strained and others that were completely relaxed. This study addresses the critical strain regime necessary for the breakdown of solid phase epitaxial recrystallization in silicon.
Symposium Organizers
Scott Thompson University of Florida
Faran Nouri Applied Materials Inc.
Wilman Tsai Intel Corporation
Wen-Chin Lee TSMC
Symposium Support
Taiwan Semiconductor Manufacturing Co., Ltd.
D4: Characterization and Methods of New Materials and Structures
Session Chairs
Wednesday AM, April 19, 2006
Room 3006 (Moscone West)
9:30 AM - D4.1
Introduction of Airgap Deeptrench Isolation in STI Module for High Speed SiGe : C BiCMOS Technology.
Eddy Kunnen 1 , Li Jen Choi 2 , Stefaan Van Huylenbroeck 2 , Andreas Piontec 2 , Frank Vleugels 2 , Tania Dupont 1 , Katia Devriendt 3 , Xiaoping Shi 4 , Serge Vanhaelemeersch 5 , Stefaan Decoutere 2
1 Etch, IMEC, Heverlee Belgium, 2 BiCMOS Integration, Imec, Heverlee Belgium, 3 CMP, Imec, Heverlee Belgium, 4 Thin Films, Imec, Heverlee Belgium, 5 AMPS, Imec, Heverlee Belgium
Show AbstractThe impact of capacitive coupling effects increases with scaling down the dimensions and towards higher performances. For bipolar technologies, the introduction of deep trench isolation gives a substantial reduction in the collector substrate capacitance. In this paper a method for the formation of airgap deep trenches (with 1µm – depth 6 µm) is presented. The method is fully compatible with standard CMOS Shallow Trench Isolation (STI) and does not require additional masking steps. The approach is based on a partial removal of the poly-Si filling in the trench. Subsequently, inside D-shape oxide spacers are formed narrowing the opening of the trench down. An SF6 plasma is used to convert the nearly completely incorporated poly-Si to volatile SiF4, such that it desorbs through the opening. In the following steps the opening is sealed by depositing SiO2 resulting in the formation of an airgap (patent pending). The normal module for STI formation continues without any adaptation of the process steps. In total four standard additional process steps are needed. The absence of the common oxide/poly filling in the deep trench decreases the peripheral collector substrate capacitance with an order of magnitude to a value of 0.02fF/µm. As a consequence the low power available bandwidth is improved with 90%.
9:45 AM - **D4.2
Si and SiGe Epitaxy: Defining the Transistor Roadmap.
Arkadii Samoilov 1
1 , Maxim Integrated Products, San Jose, California, United States
Show Abstract10:15 AM - D4.3
Ultra-High Growth Rate of Epitaxial Silicon by Chemical Vapor Deposition at Low Temperature with Novel Precursor.
Keith Chung 1 , Nan Yao 1 , James Sturm 1 , Kaushal Singh 2 , David Carlson 2 , Satheesh Kuppurao 2
1 Princeton Institute of Science and Technology of Materials (PRISM) and Department of Electrical Engineering, Princeton University, Princeton, New Jersey, United States, 2 , Applied Materials, Santa Clara, California, United States
Show AbstractGrowth temperatures under 700C are required for the integration of novel front-end processes in VSLI structures to avoid any dopant diffusion. In this work, we report record growth rates of high-quality epitaxial silicon grown by thermal chemical vapor deposition from 600 to 700C. The work was enabled by a novel silicon precursor, a high-order silane. Growth rates of epitaxial silicon on <100> silicon substrates were 215nm/min, 130nm/min, and 54nm/min were achieved at 700C, 650C, 600C respectively in a hydrogen carrier environment. Compared to rates of 20nm/min and 5nm/min at 630C and 600C previously reported using a source of trisilane [1], our work represents a factor of 10X increase at 600C and 2.5X increase at 650C (Extrapolated at 650C). These growth rates are also significantly higher than the growth rates reported with UHV-CVD of 6nm/min and 1.2nm.min at 650C and 600C[2]. This is significant because high growth rates are desired for throughput and cost-of-ownership issues in modern single-wafer processing tools. Because of the low temperatures, high growth rates and concerns about gas-phase nucleation, the layers were evaluated by a wide range of characterization techniques. High resolution cross section transmission electron microscopy on an atomic levels showed no stacking faults, interface defects, or other features, with sharp diffraction patterns. Full electrical dopant activation with in-situ boron doping (by diborane) was achieved at a boron level of 1 x 1020 cm-3. Photoluminescence in Si/SiGe/Si quantum wells was observed from both the Si (grown at 600C) and SiGe, showing a high minority carrier lifetime in the silicon layers. Silicon layers on oxide were also deposited, with similar growth rates to the polycrystalline layers. For gate electrode applications, amorphous material is preferred over a polycrystalline structure, because of the ease of etching narrow gates. However, at temperatures over 600C polycrystalline layers normally result from thermal CVD [3]. In this work, the deposited layers were amorphous even at 700C. This can be attributed to high deposition rates as compared to surface diffusion length at these temperatures.In summary, record growth rates of silicon epitaxy by thermal CVD at temperatures from 600C to 700C are reported. Excellent quality of epitaxy was achieved at these temperatures based on a wide range of characterization techniques. This work at Princeton was supported by Applied Materials, Inc.[1] M.A. Todd et al, Applied Surface Science 224, 41-45 (2004)[2] N. Sugiyama, Journal of Crystal Growth 172, 376-380 (1997)[3] T.I. Kamins, J. Electrochemical. Soc. 127, 686 (1980)
10:30 AM - D4.4
A Side-gated MOSFET: Electrostatic Suppression of Short-channel and Edge Effects for sub-70 nm Gate Length CMOS Technology.
Ali Gokirmak 1 , Sandip Tiwari 1
1 Electrical and Computer Engineering, Cornell University, Ithaca, New York, United States
Show AbstractA device architecture with an independently controlled side-gate, surrounding the active area, is developed to suppress the edge related leakage currents and short channel effects, allowing further scaling of the channel width and gate length. The side-gated devices are fabricated on bulk Si substrates with 1-3e17/cm3 body doping level as nFET prototypes using thermally grown silicon dioxide top-gate insulator, silicon nitride side-gate insulator and silicon nitride shallow trench isolation (STI). The side-gated structure resembles a finFET structure where the top-gate and the side-gates are independently controlled. The device operation is achieved on the top surface while the side-gates are negatively biased in order to suppress leakage currents.Application of a large negative side-gate bias accumulates the interfaces with holes in the body of an nMOSFET. This results in significant reduction in drain to substrate leakage and source to drain leakage through the side interfaces of the device. In the narrow devices, accumulation of the side interfaces significantly reduces the depletion regions of the source/drain junctions facing each other, turning off the body of the device. Reconstruction of the potential barrier between the source and the drain increases the current confinement to the top-gate controlled Si-SiO2 interface on the top surface. This, in turn results in significant reduction in source-drain leakage currents for sub-100 nm channel devices due to punch-through and drain induced barrier lowering (DIBL).The leakage currents are suppressed below 50 fA for devices with sub-70 nm gate length and approximately 80 nm physical channel width with the application of a side-gate bias of -3 V. Subthreshold slope of devices with these dimensions are less than 100 mV/dec for drain biases of 1 V or smaller and Ion/Ioff ratio exceeds 1e9. The drive currents are as high as 1.5 mA / μm of effective device width, as extracted from C-V measurements performed on the specific devices.Narrower channel devices with 150 nm gate length show DIBL of 2 mV/V and subthreshold slope of approximately 80 mV/dec. The fabrication process for the side-gated structure is significantly simpler compared to double-gate and finFET structures, and can be built on bulk Si substrate, eliminating floating body effects. With these performance parameters and processing advantages, side-gated device geometry is a promising candidate for future generation low-power, and higher performance ULSI circuits.Details of the fabrication process and the device performance characteristics are going to be presented.
10:45 AM - D4.5
Low Temperature Selective Si and Si-Based Alloy Epitaxy For Advanced Transistor Applications.
Yihwan Kim 1 , Ali Zojaji 1 , Errol Sanchez 1 , Zhiyuan Ye 1 , Andrew Lam 1 , Nicholas Dalida 1 , Satheesh Kuppurao 1
1 Epi KPU, Applied Materials, Sunnyvale, California, United States
Show AbstractWe present development results of low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (≤ 700 oC), we have demonstrated elevated source/drain formation on ultra-thin (<5 nm) body SOI transistors without Si agglomerations, minimized Si migration on recessed source/drain, smooth morphology of selective SiGe epitaxy with high Ge (>30 %) and B (>2E20 cm-3) concentrations, and selective Si:C epitaxy with high substitutional C concentration (>1.5 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters with adapting non-conventional deposition method.
11:00 AM - D4: CHAR
BREAK
11:30 AM - D4.6
Electrical Properties of Silicon Nanoparticles Deposited by Low Pressure Chemical Vapor Deposition
Deepthi Gopireddy 1 , Christos Takoudis 1 , Dan Gamota 2 , Jie Zhang 2 , Paul Brazis 2
1 Chemical Engineering, University of Illinois - Chicago, Chicago, Illinois, United States, 2 Motorola Advanced Technology Center, Motorola, Shaumburg, Illinois, United States
Show AbstractAs the trend towards scaling down of electronic device size increases, the ‘traditional’ processing technologies will soon encounter significant limitations. A great deal of research activity is currently focused on identifying alternative highly integrated nano-devices. One promising approach to overcome these challenges is the use of nanoparticles as building blocks for virtually any kind of device or functional system. In an effort to assess their potential for future nanoelectronic devices, we have fabricated silicon nanoparticle Field Effect Transistors (FETs) using the nanoparticles as the channel. The nanoparticles of 10-20 nm diameters are grown on a 200 nm gate oxide film on a highly p-doped silicon wafer, which is used as a back gate substrate. Source and drain contacts were then fabricated using conventional lithography techniques. The nanoparticles used in this study were deposited on silicon dioxide substrate by thermal decomposition of silane using Low Pressure Chemical Vapor Deposition (LPCVD). This route offers an excellent control over particle size and size distribution and particle density by varying the deposition time, temperature and partial pressure of silane. This approach, also allows the fabrication of both n-type as well as p-type devices by doping the nanoparticles during deposition. The goal of this study is to show the semiconducting nature of the nanoparticles and to characterize the performance of nanoparticle transistors. The source-drain current through the devices is measured at room temperature as a function of the bias voltage and the gate voltage. The electrical characteristic measurements of the silicon nanoparticle-FETs show that changing the voltage applied to the gate can vary the amount of current flowing through the nanoparticle channel. The source-drain current decreases with increasing gate voltage, which demonstrates that the device operates as p-channel field-effect transistor. Based on the transfer characteristics obtained for different source-drain voltages, the carrier density and the mobility of the charge carries in these devices are also calculated.We will present the electrical characteristics of crystalline silicon nanoparticles as a function of their density and size. The devices fabricated show good performance characteristics indicating potential for future applications in nanoelectronics.
11:45 AM - D4.7
Nano-scale MOSFET Devices Fabricated Using a Novel Carbon-Nanotube-based Lithography.
Jaber Derakhshandeh 1 , Yaser Abdi 1 , Shamsoddin Mohajerzadeh 1 , Mohammad Beikahmadi 1 , M Robertson 2 , J Bennett 2
1 electrical, thin film lab, tehran, tehran, Iran (the Islamic Republic of), 2 Physics, Acadia University, Wolfville, NS, Quebec, Canada
Show AbstractWe report a novel nanoscale lithography technique based on the growth of vertically aligned CNTs on Si substrates. This technique is capable of drawing narrow lines suitable for fabricating Nano-scale MOSFETs. The growth of CNTs on Si substrates was achieved using DC-PECVD with a mixture of C2H2 and H2 at a pressure of 1.8torr and at 650oC. Ni with a thickness of 10nm was used to initiate CNT growth. Vertical growth was ensured using a DC plasma where the power density ranged between 4.5 and 5.5W/cm2. TEM and SEM analyses confirm a tip-growth mechanism with well-aligned structures. Control of the electron emission from the CNT tips was achieved by a self-defined gated structure. The fabrication steps for this structure were: vertical growth of CNTs, CVD-deposition of an insulating film (TiO2) and evaporation of a metal layer (Cr or Ag). The structure was then polished to reveal the buried CNT, and an oxygen plasma treatment was conducted to clean the surface and to recess the exposed CNTs. By applying a proper voltage between the anode and the cathode, emission of electrons from the cathode (CNT) towards the anode occurred and a current measured. A novel iterative process was used to progress from clusters of nanotubes at the micrometer scale to the goal of single, isolated nanotubes. This procedure required several steps of CNT growth, encapsulation and plasma ashing followed by developing the desired patterns by electron emission of such encapsulated CNTs onto another resist-coated substrate. Using such isolated CNTs we have drawn lines with widths varying between 42 and 120nm.This method was used to form the gate of the transistors. Once the gate is defined, the metal gate is used to define the source and drain regions. Doping was achieved by a Ge/Sb alloy deposition leading to a layer with a sheet-resistance of 2 KΩ/square. The gate SiO2 was 5 nm thick and was grown thermally with an inversion Cox of 0.7µF/cm2.The gate length ranged between 100 and 250nm.The I-V characteristics of the device have been measured using a Keithley parameter analyzer. The short-channel effects have been minimized by dipping the structure in an oxide chemical etching solution just prior to the doping step in order to recess the sidewall of the gate oxide. This modification in the fabrication process lead to a lowering of the electric field in the area close to the drain, thereby alleviating the short channel effect in place of a LDD configuration. The device shows a sub-threshold slope of 100mV/decade and a threshold voltage of 50 mV. An effective mobility of 350cm2/V-s and a drive current of 312 µA/µm were extracted for this small geometry transistor. In addition, a DIBL was measured to be 150mV/V. These results suggest that the device has a controllable short channel effect, with a peak “gm” equal to 2200 mS/mm. Improvements in the lithography process, fabrication of MOS transistors with 60nm length and continued study of the MOSFET transistors are underway.
12:00 PM - D4.8
Electron Thermal Transport Properties of a Quantum Dot.
Xanthippi Zianni 1
1 Dept. of Applied Sciences, Technological Educational Institute of Chalkida, Chalkida Greece
Show Abstract12:15 PM - **D4.9
CMOS Performance Enhancement from a Combination of NiSi Metal Gate (FUSI) and Uniaxial Strained Silicon Channels
Kelin Kuhn 1 , Chris Auth 1 , Tahir Ghani 1 , Pushkar Ranade 1
1 , Intel Corporation, Hillsboro, Oregon, United States
Show AbstractI. IntroductionTwo types of performance enhancement are of great interest past the 65nm generation. The first is the continued use of strain techniques first introduced in the 90nm and 65nm generations. The second is the use of metal gate. Although a variety of metal gate technologies have been explored, NiSi metal gate is one of the most attractive potential replacements for conventional poly-Si gates to mitigate the gate depletion effect and enhance transistor performance beyond the 65nm node. II. Performance enhancements past 65nmThis paper illustrates the feasibility of performance enhancements past the 65nm generation by demonstrating integrated NiSi gates with state-of-the-art uniaxial strained Si CMOS technology. There are two reported process options to implement Ni FUSI. In one option, Ni can be deposited on the wafers after poly-Si and SD junction activation. By carefully optimizing the poly-Si and Ni film thickness and the silicide thermal budget, full silicidation of the poly-Si gates is accomplished while preventing the formation of excess NiSi in the junctions. Alternatively, the SD silicide and gate silicide formation steps can be decoupled by using a damascene process to selectively expose the surface of the poly-Si gates after the SD junctions have already been silicided. The latter approach enables independent control of Ni thickness for SD and poly-silicide. The use of a metal gate is expected to eliminate poly-Si gate depletion and enhance inversion charge density. A 20% gain in inversion charge density and a corresponding 20% IDSAT and IDLIN gain is observed on FUSI devices. Note performance gain in FUSI devices can be attributed to a combination of higher inversion charge density and improved carrier mobility (due to lower channel doping concentration). Linear drive current comparisons for FUSI and control wafers at│VDS│=50mV suggest that both components are contributing to the performance improvement. III. ConclusionThese results demonstrate the compatibility of the FUSI metal gate approach (enhanced inversion charge density) and the uniaxial strained silicon approach (enhanced carrier mobility). This illustrates that enhancements can be combined with traditional scaling methodologies to support significantly higher performance devices for advanced technology generations.
D5: Modeling and Metrology
Session Chairs
Wednesday PM, April 19, 2006
Room 3006 (Moscone West)
2:30 PM - D5.1
Using Quantitative TEM Analysis of Implant Damage to Study Surface Recombination Velocity in Silicon.
Sophia Morghem 1 , Jennifer Gasky 1 , K. Jones 1
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractIn order to model advanced microelectronic devices, an accurate understanding of interstitial recombination at the surface in necessary. The goal of the experiment was to use the evolution of end of range damage in patterned silicon to develop a better understanding of the strength of surface recombination. Silicon wafers with shallow trench isolation structures 3700Å deep were self-implanted with silicon at 40keV and a dose of 1E15/cm2. This produced an amorphous layer 875Å deep. The samples were subsequently annealed at temperatures ranging from 750 deg C to 900 deg C. The excess interstitials can recombine at the “surface” created by the proximity to the trench sidewall. Plan-view and cross-section TEM was used to quantify the dislocation distribution as a function of distance from the trench sidewall. It was found that relatively weak recombination of interstitials at the surface is observed. This is surprising given most of the TCAD models assume a very fast surface recombination velocity. In subsequent experiments, the trench was etched prior to annealing to remove the oxide present in the trench. This had little effect on the surface recombination of interstitials. The TCAD process simulator was used to model the dislocation distribution as a function of surface recombination velocity. The results of these simulations will also be presented. This approach allows one for the first time to study the depth dependence of surface recombination without varying the implant conditions or having an amorphous layer present between the surface and the damage layer during the initial stages of annealing.
2:45 PM - D5.2
Diffraction from Periodic Arrays of Oxide-filled Trenches in Silicon: Investigation of Local Strains.
Michel Eberlein 1 2 , Stephanie Escoubas 1 , Olivier Thomas 1 , Pascal Rohr 2 , Romain Coppard 2
1 TECSEN CNRS , Universite Paul Cezanne, MARSEILLE France, 2 , ATMEL Rousset, Rousset France
Show Abstract3:00 PM - D5.3
Stress and Strain Measurements in Semiconductor Device Channel Areas by Convergent Beam Electron Diffraction
Jinghong Li 1 , Anthony Domenicucci 1 , Dureseti Chidambarrao 1 , Brian Greene 1 , Nivo Rovedo 1 , Judson Holt 1 , Derren Dunn 1 , Hung Ng 1 , Ken Rim 1
1 STG Division, IBM, Hopewell Junction, New York, United States
Show AbstractWith traditional scaling for semiconductor devices becoming increasingly difficult, device performance enhancement by strain/stress engineering has become popular. The mobility of devices has been improved by introducing strain/stress in CMOS channel area. PFET‘s performance has been improved by applying compressive stress to the channel region, while NFET’s performance is improved by applying tensile stress. Accordingly the measurement of stress and strain with high special resolution on a nanoscale has recently received much attention. Convergent electron beam diffraction (CBED) has proved to be very powerful technique for detecting small variations in lattice parameters with very high accuracy by examining the displacement of higher order Laue zone (HOLZ) lines. But strain measurements in CMOS channel area using CBED has not been well established, due to the difference between theoretical simulation and experimental results. In this paper, we report our work on measuring strain by CBED in devices from the 65nm technology node which employs embedded SiGe in the source/drain regions to enhance device performance. Reliable strain measurements were obtained using commercially available fitting software by controlling sample thickness and energy filtering the experimental CBED patterns to improve sharpness of HOLZ lines. Comparison of strain values obtained by CBED to those obtained from simulation will also be described.
3:15 PM - D5.4
A Physically Based Quantum Correction Model for DG MOSFETs
Markus Karner 1 , Martin Wagner 1 , Tibor Grasser 2 , Hans Kosina 1
1 Institute for Microelectronics, TU Wien, Vienna Austria, 2 Christian Doppler Laboratory for Microelectronics, TU Wien, Vienna Austria
Show AbstractDue to the strong impact of quantum mechanical effects on the characteristics of todays semiconductor devices, classical device simulation without quantum correction is not sufficient to provide proper results. Besides tunneling, the effect of quantum confinement strongly affects the characteristics of bulk, silicon-on-insulator (SOI), and double gate (DG) MOSFETs under inversion conditions. Due to quantum confinement, which affects the local density of states, the carrier concentration near the gate oxide decreases while classical simulation predicts an exponential growth near the gate oxide.Schrödinger Poisson (SP) solvers, which deliver a self consistent solution of a quantum mechanically calculated carrier concentration and the Poisson equation, provide accurate results. However, since the evaluation of the quantum mechanical electron density is based on the calculation of the eigenstates of a Hamiltonian, which is computationally very demanding, the application of SP solvers is impractical.In order to obtain proper simulation results at greatly reduced CPU time, several quantum correction models for classical simulation have been proposed. They extend the range of validity of classical transport models to highly scaled devices in the deca nanometer regime. The most advanced model, the Improved Modified Local Density Approximation (IMLDA) model (C. Nguyen et al., Proc. NSTI-Nanotech, 2005, vol. 3, pp. 33-36), relies on the solution of the Schroedinger equation for a single step-like potential profile and is calibrated for bulk MOS structures. For these structures, this approach delivers good agreement for CV-characteristics. However, this model is not intentioned to be used for DG MOSFET structures, which demand a different approach. To our best knowledge, the usability of several present available quantum correction models for highly scaled DG MOSFET devices is very limited.In this work, we present a specific approach for state-of-the-art DG MOSFET devices. The strong quantization in perpendicular direction results in a two-dimensional electron gas which can be well approximated with an infinite square well potential. The eigenstates are estimated with the according analytical approach. This assumption allows to determine a quantum correction potential which modifies the band edge energy in a way to reproduce the quantum mechanical carrier concentration. We implemented this model in our general purpose device simulator MinimosNT. The carrier concentration calculated from the new model shows very good agreement with the self consistent Schrödinger Poisson solution. Since the derived CV-characteristics are based on the accurate carrier concentration, no further fitting is necessary.
3:30 PM - **D5.5
TCAD Modeling of Strain-Engineered MOSFETs.
Lee Smith 1
1 , Synopsys, Inc., Mountain View, California, United States
Show AbstractThe rapid rise of standby power consumption in nanoscale MOSFETs is slowing classical scaling and threatening to derail continued improvements in MOSFET performance. Several technology boosters have been proposed to enable incremental performance improvements at similar off-state leakage. Strain-enhancement of carrier transport in the MOSFET channel has emerged as a particularly effective and relatively easy-to-integrate approach. In this talk we review the major impacts of strain on device fabrication and device characteristics, and we describe how these are addressed in TCAD simulations. Within the context of process simulation, one of the key modeling challenges is the calculation of the mechanical strain itself during various process steps such as etch, deposition, and thermal cycling. As will be shown by example, the resulting stress and strain fields are often counter-intuitive. We also review how the introduction of strain in the process flow can influence subsquent process steps such as diffusion. Strain impacts device characteristics through changes in the band structure. We review how subsequent changes in carrier repopulation, effective mass, and scattering enhance, or degrade, the mobility and shift the threshold voltage for various stress configurations. In this context, optimizing the enhancement of the low-field mobility can be viewed as an exercise in band structure engineering. For high-field transport, we use Monte Carlo device simulation to investigate the impact of strain on velocity overshoot and drive current. Due to the large interaction range of stress in CMOS materials, ~2 um, the modeling of isolated devices is not sufficient to predict final circuit behavior. We also review some recent simulation studies we have performed to investigate the impact of circuit layout on channel stress and circuit performance.
4:30 PM - D5.6
Fundamental Modeling of Group V Dopant Diffusivity and Clustering in Strained Si and SiGe Alloys.
Mohit Haran 1 , James Catherwood 1 , Paulette Clancy 1
1 Chemical and Biomolecular Engineering, Cornell University, Ithaca, New York, United States
Show AbstractMOSFETs with strained Si/SiGe alloys are of great technological importance due to their greater electron and hole mobility, and easier process integration with current technology. Strain-induced gains in mobility in strained Si and SiGe are offset by increased dopant diffusivity caused by the increasing lattice strain as the Ge content increases. Enhanced diffusivity, along with electrical deactivation of implanted dopants, poses great challenges in the fabrication of ultrashallow junctions in deep submicron devices. We have used a combination of small-scale ab initio Density Functional Theory calculations and larger scale Molecular Dynamics (MD) simulations to decouple the influence of strain and the chemical effect of germanium on both the diffusivity of intrinsic defects and that of group V dopants (P, As and Sb) in strained Si and SiGe materials. MD calculations of the behavior of intrinsic defects in SiGe alloys suggested that vacancy diffusivities increase linearly with increasing germanium content. In contrast, interstitial diffusivities remain roughly constant until the germanium content reaches 15% and then decreases with further increase in germanium concentration. The change in apparent activation energy with strain was found to be related to atomic size/induced stress of a dopant within dopants of the same group only, and not the often assumed strain compensation based on dopant size. For group V dopants, the migration barrier for interstitial-assisted dopants was found to be independent of strain. The imposition of tensile strain causes an increase in interstitial-assisted dopant diffusivity and a decrease in vacancy-assisted diffusivity. The inherent nature (or chemical effect) of Ge reduces interstitial diffusivity in a manner controlled by dopant size, while assisting vacancy diffusivity by lowering formation energies by ~0.2 eV. These effects were investigated for group V alloys (P and As) in relaxed Si0.75 Ge0.25 alloys also. At low germanium concentration, chemical effect of germanium had negligible effect on energetics of charged defects. The activation barrier for diffusion of vacancy clusters like As2V, which are a precursor to immobile deactivating clusters, increased with increases in germanium concentration.
4:45 PM - D5.7
Predictive Model for Diffusion in Strained SiGe Based on Atomistic Calculations.
Chihak Ahn 1 , Jakyoung Song 2 , Scott Dunham 1 2
1 Physics, University of Washington, Seattle, Washington, United States, 2 Electrical Engineering, University of Washington, Seattle, Washington, United States
Show Abstract5:00 PM - D5.8
3D Modelling of the Novel nanoscale Screen-Grid FET.
Pei Ding 1 , Kristel Fobelets 1 , Jesus Velazquez Perez 2
1 Electrical and Electronic Engineering, Imperial College London, London United Kingdom, 2 Fisica Aplicada, University of Salamanca, Salamanca Spain
Show AbstractA novel 3D Field Effect Transistor on SOI – called the screen grid FET (SGFET) – is proposed. 3D TCAD analysis, using Taurus (Synopsis), of the device is presented. The results indicate that this novel geometry is ultimately suitable for ultra-low power applications.The SGFET structure is basically the following: source and drain are defined in the plane of the wafer, the gating configuration however is perpendicular to this plane. The gates are metal cylinders standing into the channel plane and offer a radial gating action thus acting both perpendicular and parallel to the current flow between source and drain. More than one gating cylinder can be used, resulting in better performance of the SGFET or in higher functionality. The originality of the idea lies in the definition of the multiple gate fingers perpendicular to the current flow, similar to a permeable base transistor, but with a fabrication concept that is basically CMOS compatible. This 3D multiple gate geometry leads to the breakdown of the traditional intimate relationship between gate length and source-drain distance, allowing flexible downscaling whilst avoiding short channel effects. Moreover, arranging the gate cylinders in two rows results in drastically reduced drain induced barrier lowering (DIBL) as the 2nd row protects the source potential from the drain voltage, similar to the tetrode in vacuum tube technology. This is illustrated in the table where DIBL, determined via 3D Taurus simulations, is given for different source-drain distances and for 1 and 2 rows of gate cylinders.In order to evaluate the DC performance of the novel devices, we investigated the influence of different geometrical parameters on the characteristics. Interesting results are that device operation for low power applications improves with reduced channel doping and reduced source-drain distance as reflected in near ideal sub-threshold slopes, low DIBL, high gm/IDS and low leakage currents.Other parameters such as the influence of the distance between the gating cylinders, the oxide thickness, gate diameter have also been modelled showing some non-traditional behaviour for the SGFET as compared to the classical MOSFET.Finally a comparison between a bulk MOSFET, SOI MOSFET and SGFET has been made, showing that the non-optimised SGFET has slightly better sub-threshold characteristics than the SOI MOSFET whilst showing a much improved output conductance.
5:15 PM - D5.9
TCAD Modeling and Simulation of Sub-100nm Gate Length Silicon and GaN based SOI MOSFETs
Lei Ma 1 , Yawei Jin 1 , Chang Zeng 1 , Doug Barlage 1
1 ECE, North Carolina State University, Raleigh, North Carolina, United States
Show AbstractSub-100nm gate length Silicon and GaN based SOI MOSFETs are modeled and simulated using ISE-TCAD. Several SOI structures such as planar fully depleted SOI, FinFET, Tri-Gate MOFET, Cylindrical channel and Triangular channel have been studied to compare the structure dependence of the device performance. Silicon and GaN are also compared for these different SOI structures for projecting the device performance for very short channel SOI MOSFETs. Our study shows that the for sub-100nm gate length, GaN based transistors and Silicon based transistors have comparable performance; however for sub 20nm gate length, GaN based transistors show lower off state leakage current, less short channel effect than Silicon based transistors. The TCAD study shows that GaN could become a promising candidate for making very short channel device as the GaN processing technology is advancing.
5:30 PM - D5.10
Direct Measurements of Nanoscale Local Lattice Strains in Si CMOS Devices by TEM/CBED.
Jiang Huang 1 , D.K. Cha 1 , P.R. Chidambaram 2 , R.B. Irwin 2 , P.J. Jones 2 , M.J. Kim 1
1 Electrical Engineering, The University of Texas at Dallas, Richardson, Texas, United States, 2 , Texas Instruments, Dallas, Texas, United States
Show AbstractStrained Si has recently emerged as one of the non-classical CMOS techniques to meet the ITRS challenge. By introducing mechanical strain in the Si channel region, the carrier mobility can be enhanced which leads to the improvement of the transistor drive current. To date, strain has been adopted at the 90nm node and will continue to be used for future generations. In order to understand and engineer the strain incorporated in the nanoscale channel region better, local strain characterization with both high spatial resolution and high sensitivity becomes more critical and more difficult as the devices continue to shrink. Conventional strain measurement techniques, such as micro-Raman spectroscopy (μRS) and x-ray diffraction (XRD), are no longer suitable due to the lack of spatial resolution. Currently, advanced TEM techniques, such as high resolution phase contrast imaging (HRTEM) and convergent beam electron diffraction (CBED), are the only strain analysis methods that have enough resolution and sensitivity for direct lattice strain measurement in nanoscale Si CMOS devices. While HRTEM imaging techniques provide geometric information of the device structure down to the atomic scale, the CBED technique provides strain-sensitive three-dimensional structural information with a spatial resolution down to approximately 1 nm. In particular, strain of the order of 0.01% can be detected by CBED, using the strain induced shift of High Order Laue Zone (HOLZ) lines. We report the results of direct local strain analysis in both PMOS and NMOS Si devices from which compressive and tensile strains are observed, respectively. To date, the smallest device analyzed has the gate length of 37nm. The experimental procedure for obtaining high quality CBED patterns and the accuracy of the strain measurements are described.