Symposium Organizers
Kevin S. Jones University of Florida
Masami Hane NEC Corporation
Susan B. Felch Applied Materials Inc.
Bartek J. Pawlak Philips Research Leuven
C1: Co-Implantation and Other Spike Anneal Solutions
Session Chairs
Tuesday PM, April 18, 2006
Room 3000 (Moscone West)
9:30 AM - **C1.1
Millisecond Annealing: Past, Present and Future.
Paul Timans 1 , Jeff Gelpey 2 , Steve McCoy 2 , Wilfried Lerch 3 , Silke Paul 3
1 , Mattson Technology Inc., Fremont, California, United States, 2 , Mattson Technology Canada Inc., Vancouver, British Columbia, Canada, 3 , Mattson Thermal Products GmbH, Dornstadt Germany
Show AbstractMillisecond annealing has recently emerged as the leading candidate for activating ion-implanted dopants in silicon for advanced CMOS device fabrication. The critical applications are for the formation of ultra-shallow junctions (USJ) and for increasing the charge carrier density in polycrystalline silicon gate electrodes. Although the potential benefits of millisecond-duration heating cycles with peak temperatures just below the melting point of silicon were identified well over 20 years ago, the need to restrict dopant diffusion at the nanometre length scale is only now driving the adoption of this approach in volume manufacturing. However, many fundamental questions concerning both the materials science and the physical processes associated with millisecond annealing have yet to be answered. This paper will explore the interaction of dopant activation, diffusion and defect annealing processes during USJ formation. The paper will also examine the physical phenomena that affect how millisecond annealing performs in the manufacturing environment, where process repeatability and uniformity are of paramount importance. Special attention will be given to flash lamp and laser heating approaches and to the associated issues in the absorption of optical energy, heat transfer effects and temperature measurement. Finally, the paper will suggest areas where further research is necessary and where new opportunities for millisecond processing are expected to arise.
10:00 AM - C1.2
Ultra Shallow Junctions Optimization with Non Doping Species Co-implantation.
Nathalie Cagnat 1 , Cyrille Laviron 3 , Daniel Mathiot 4 , Blandine Duriez 2 , Julien Singer 2 , Romain Gwoziecki 3 , Marc Juhel 1 , Marco Hopstacken 2 , Frederic Salvetti 2 , Davy Villanueva 2 , Benjamin Dumont 1 , Arnaud Pouydebasque 2
1 , STMICROELECTRONICS, Crolles France, 3 LETI, CEA, Grenoble France, 4 , InESS, Strasbourg France, 2 , PHILIPS, Crolles France
Show Abstract10:15 AM - C1.3
The Carbon Co-implant with Spike RTA Solution for Boron Extension.
Bartek Pawlak 1 , Emmanuel Augendre 2 , Simone Severi 2 , Wilfried Vandervorst 2 , Tom Janssens 2 , Philippe Absil 2 , Erik Collart 3 , Susan Felch 3 , Ray Duffy 1 , Annelies Falepin 2 , Robert Schreutelkamp 3
1 , Philips Research Leuven, Leuven Belgium, 2 , IMEC, Leuven Belgium, 3 , Applied Materials Inc., Horsham United Kingdom
Show Abstract10:30 AM - C1.4
Activation and Deactivation Studies of Spike and Sub-millisecond Annealed Carbon Co-implanted Junctions.
Houda Graoui 1 , Vijay Parihar 1 , Martin Tran 1 , Majeed Foad 1 , Enrico Napolitani 2 , Di Marino Marco 2 , Alberto Carnera 2 , Salvo Mirabella 3 , Giuliana Impellizzeri 3 , Francesco Priolo 3
1 FEP, Applied Materials, Sunnyvale, California, United States, 2 MATIS-CNR-INFM and Dipartimento di Fisica, Universita di Padova, Padova Italy, 3 MATIS-CNR-INFM and Dipartimento di Fisica e Astronomia, Universita di Catania, Catania Italy
Show Abstract10:45 AM - C1.5
Germanium & Carbon Co-implantation for Enhanced Short Channel Effect Control in PMOS Devices.
Benjamin Dumont 1 , Arnaud Pouydebasque 2 , Bartek Pawlak 3 , Benjamin Oudet 1 , Dominique Delille 2 , Frederic Milesi 5 , Marie-Pierre Samson 4 , Thomas Skotnicki 1
1 , STMicroelectronics, Crolles France, 2 , Philips Semiconductors, Crolles France, 3 , Philips Research, Leuven Belgium, 5 , Ion Beam Services, Peynier France, 4 , CEA-LETI, Grenoble France
Show AbstractIn PMOS devices, parasitic phenomena like Short Channel Effects (SCE) and Source/Drain Extension (SDE) resistances become critical parameters for the 65/45nm node due to the Boron Transient Enhanced Diffusion (TED). Fundamental studies have shown that Carbon acts as a trap for Si self-interstitials that suppresses the Boron TED. In this work we demonstrate the usefulness of Germanium PreAmorphization Implantation (PAI) and Carbon co-implantation with a standard spike anneal to control Boron TED with a high activation ratio in order to improve SCE in PMOS device while maintaining excellent drive current performances.Device integration is based on a standard 65nm CMOS flow chart including a nitrided oxide (13Å EOT) and gate length down to 35nm. Co-implantation for SDE is realized by 3 successive implantations with Germanium, Carbon and Boron. The activation of dopants is achieved with a conventional spike RTP (1055°C). The Ge and C profiles were chosen in order to be situated beyond the junction such as the maximum C concentration is located near to the EOR (End-Of-Range) region induced by the PAI.For Ge+C+B devices at Lg=50nm, performance is Ion=380µA/µm at Ioff=100nA/µm at 1.0V supply voltage. The saturated threshold voltage as a function of gate length is highly improved for Ge+B split and especially for Ge+C+B split. The effect of PAI with Ge can be understood as a suppression of channelling for Boron during implantation that decreases the “as-implanted” junction depth. Drain Induced Barrier Lowering and sub-threshold slope are also improved for Ge+C+B split compared to Boron only (divided by a factor of 4 and -60% respectively) for a 50nm gate length. The MASTAR model was used to fit the data and to estimate that the junction depth is reduced from 40nm for Boron only split to 22nm for Ge+C+B split and the lateral diffusion by side is divided by a factor of 4. This demonstrates that the lateral boron TED is slowed down by Ge and in an increasing degree by the Ge+C couple. The SDE resistances are decreased by 10% for Ge+B split and by 24% for Ge+C+B split compared to B reference. However, the Carbon implantation dramatically increases the extension junction leakage. This can be explained by the combination of a natural increase of the leakage due to a steeper and more activated junction and a defect induced leakage associated to the presence of Carbon. On the other hand, no area leakage degradation is observed on surface diode that is explained by the fact that Carbon is situated inside the deep S/D region.In this work we have demonstrated a very simple, low cost solution to control the Boron TED. By using Germanium and Carbon co-implantation we are able to increase SCE control and keep state-of-the-art Ion/Ioff performances. This approach can be easily introduced in 65/45nm nodes to keep SCE/DIBL under control and thus provides a cost effective Bulk CMOS platform.
11:30 AM - C1.6
The Carbon Co-implant with Spike RTA Solution for Phosphorus Extension.
Bartek Pawlak 1 , Emmanuel Augendre 2 , Simone Severi 2 , Wilfried Vandervorst 2 , Tom Janssens 2 , Philippe Absil 2 , Susan Felch 3 , Erik Collart 3 , Ray Duffy 1 , Annelies Falepin 2 , Robert Schreutelkamp 3
1 , Philips Research Leuven, Leuven Belgium, 2 , IMEC, Leuven Belgium, 3 Front End Products Group, Applied Materials Inc., Sunnyvale, California, United States
Show AbstractWe investigate the possibility of application of phosphorus for junction extension in planar CMOS transistor. Up till now only arsenic doping offered good activation combined with shallow profile. In this paper we demonstrate that typical difficulties with phosphorus, related to its rapid interstitial-mediated diffusion, can be engineered, offering box-like profile with activation exceeding arsenic doping.Here we demonstrate that by Si amorphization and carbon co-implantation followed by conventional spike RTA we are able to shape the phosphorus extension in order to get almost box-like profile. Phosphorus junctions can be as shallow as 21 nm (at 5x1018 at./cm3) with Rs = 320 Ohms/sq., and ultra-abrupt tail, around 3 nm/decade. The activated junction has a flat ‘shoulder’, at the very high concentration level of 4x1020 at./cm3, which translates to very low Rs, better than arsenic extensions. The benefit related to carbon co-implantation is present only in combination with pre-amorphization, suggesting that the dominant role in trapping of Si interstitials is given by the substitutional fraction of carbon. Amorphization of silicon leads to carbon clustering at the end-of-range site. The position of carbon clusters is then directly linked to the initial amorphous depth. Junctions performed in that way offer excellent thermal stability.Phosphorus extensions have been implemented in the manufacturing of diodes and in planar CMOS transistors. Thermal dependent leakage studies reveal a leakage, measured at 1 V, activation energy of Ea = 0.53 eV. The leakage mechanism is concluded to have the trap assisted tunneling character. The diode leakage is directly related to the amorphization and mediated by the presence of carbon clusters. Shallow amorphization and shallow carbon co-implantation may offer diode leakages as low as the arsenic reference junction. The same co-implant conditions offer improvement in the transistor performance with respect to its arsenic reference.The carbon co-implant with conventional RTA is considered as the straightforward n-type extension solution for the 45 nm technology node.
11:45 AM - C1.7
Enhanced Activation of Standard and Cocktail Spike Annealed Junctions with Additional Sub-melt Laser Anneal.
Simone Severi 1 , Annelis Falepin 1 , Emmanuel Augendre 1 , Bartek Pawlak 2 , Susan Felch 3 , Robert Schreutelkamp 3 , Faran Nouri 3 , Philippe Absil 1 , Kristin De Meyer 1
1 , IMEC, Leuven Belgium, 2 , Philips, Leuven Belgium, 3 , Applied Materials, Sunnyvale, California, United States
Show AbstractThe ITRS road map requirement indicates the necessity to scale the junction depth while increasing the doping activation beyond the solid solubility limits imposed by the conventional spike anneal process. Simultaneous improvements on the devices scalability and performance should be achieved. Lately, the use of sub-millisecond anneals have been shown to reach both the diffusion-less and high doping activation targets. Despite these achievements, the extensive use of these advanced anneals has been prevented by the presence of defects under the junctions. The compatibility of diffusion-less junctions with post anneals is limited by the emission of Si interstitials by defects, causing significant diffusion and de-activation of the junction doping. Moreover these defects increase the junction leakage up to two orders of magnitude, preventing the use of these junctions for low stand-by power applications. Both these problems can be overcome by the use of a conventional spike anneal with reduced temperature and an additional sub-melt laser anneal. The first one anneals out the defects while limiting the doping diffusion. The second one improves the doping activation.A 1D experiment with n+ As or p+ B + F implanted and spike annealed junctions, with temperature ranging up to 1050oC and additional laser anneal, with peak temperatures as high as 1300oC, has been carried out. With the same junction implantations and anneal conditions, CMOS transistors with poly-silicon gate have been processed. SIMS profiles reveal that the n+ and p+ junction depths can be reduced by lowering the spike temperature, while the additional laser anneal produces only marginal variations of them. Atom clusters in the high concentration part of the junction profile can be partially dissolved during the high temperature sub-melt laser anneal, lowering the junction sheet resistance. From electrical transistor characterization, a decrease in S/D resistance has been observed for the highest laser peak temperature. The decrease of the junction depth improves the SCE of both nMOS and pMOS transistors, while the decrease of junction sheet resistance produces a benefit only on the NMOS performance. The residual defects under the junction profile have been characterized looking at the stability of the junctions as a function of post-annealing temperature. In addition, similar 1D and 2 D study has been performed on p+, Ge+F+B, and n+, Ge+F+P, cocktail junctions. The Ge and F implantations reduce the junction depths of both the shallow and the deep junction profiles. An optimization of the deep junction profile, as a function of the Ge implantation, is particularly important to highlight the benefit of the cocktail over the conventional junction approaches.
12:00 PM - C1.8
Simulation of Fluorine Diffusion and Boron-Fluorine Cointeraction
Robert Robison 1 , Mark Law 1
1 Electrical and Computer Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractWe have developed a model which describes both the diffusion behavior of implanted fluorine in silicon and the boron-fluorine cointeraction present in samples implanted with both impurities. The model was developed and calibrated using experimental data of Czochralski-grown Si wafers implanted with Si+ at 70keV energy and 1×1015 dose to create a continuous amorphous layer ~1200Å deep. The samples were then implanted with 16 keV fluorine at either 2×1014 or 2×1015 dose, and then 5keV boron at either 3×1013 or 1×1015 dose, for a total of four implant conditions. Samples were then annealed using a conventional furnace or RTA with an N2 ambient for various times at temperatures of 550-1050°C. SIMS was used for depth profiling of impurities, and TEM was used to observe the formation of extended defects and confirm the amorphous layer depth. An additional sample implanted with 1e15 dose boron 1.1keV energy and 2×1015 dose fluorine with 9keV energy was used in calibration. The fluorine model used in our previous work was extended to describe the observed effect on boron diffusion when fluorine is also present in a sample. We found that the fluorine-vacancy complexes present in the model are capable of reproducing the effect on fluorine effect boron diffusion almost entirely. The fluorine-vacancy complexes capture silicon self-interstitials and reduce the overall concentration of silicon self-interstitials in the sample, thus reducing overall boron diffusion. We found that when properly calibrated, the model is capable of producing second order effects such as enhanced boron activation which is sometimes demonstrated in fluorine co-implanted samples. We have calibrated the model over a range of temperatures and conditions and found that it models the data well.
12:15 PM - **C1.9
Defect-free Ultrashallow Junctions by Vacancy Engineering: the Route to Future CMOS?
Nick Cowern 1 , Andy Smith 1 , Benjamin Colombeau 2 , Russell Gwilliam 1 , Erik Collart 3 , Brian Sealy 1
1 , Surrey University, Guildford United Kingdom, 2 , Chartered Semiconductor Manufacturing Ltd., Woodlands Singapore, 3 , Applied Materials UK, Horsham United Kingdom
Show AbstractCurrent approaches to the formation of highly activated ultrashallow junctions use amorphisation and solid phase epitaxy, combined increasingly with ‘cocktail’ implants and flash or sub-melt-laser annealing. These implantation schemes generate excess interstitial defects beyond the amorphisation depth, increasing electrical junction leakage, transient enhanced diffusion of B, P or As dopants, and deactivation of B. Much current research focuses on a search for solutions to these problems. However, at present it is an open question whether such solutions will satisfy industry requirements for future CMOS over a wide enough range of applications.Recent studies [1, 2] have shown that highly activated (> 5×10^20/cm^3), ‘diffusionless’ p-type ultrashallow junctions can be formed by introducing vacancies into crystalline (non-amorphised) silicon, using medium dose, medium energy vacancy engineering implants (VEI). The approach is especially successful in applications, such as SOI devices, where a material boundary can be used to exclude deeper penetrating interstitials from the device. It offers ideal junction scaling properties, as active doping levels and junction steepness both increase with a reduction in source-drain implant energy. This talk presents new results demonstrating the formation of defect-free junctions after VEI and ultra-low thermal budget annealing. Our approach is ideally suited to low-temperature conventional annealing, or to low thermal-budget sub-second annealing, since junctions are robust against deactivation during subsequent low-temperature processing steps. We also demonstrate how VEI can be integrated with low thermal budget n-channel processing, retaining robustness against deactivation in both p- and n-channel devices. The talk will review the physics and technology of vacancy ‘implantation’, vacancy-impurity interactions and the ‘reverse’ solid-phase epitaxy (RSPER) method, which together enable the engineering of these defect-free, diffusionless, highly activated junctions. Finally, a brief overview of VEI process integration issues for future nanoscale CMOS will be provided.[1] A.J. Smith et al., Mat. Sci. Eng. B (2005), in press.[2] N. E. B. Cowern, A.J. Smith, B. Colombeau, R. Gwilliam, B.J. Sealy, and E.J.H. Collart, IEDM Technical Digest (2005, in press)
12:45 PM - C1.10
Optimization of Preamorphization Conditions to Improve Dopant Activation and Diffusion in Si and SOI.
Justin Hamilton 1 , E Collart 2 , M Bersani 3 , D Giubertoni 3 , B Colombeau 4 , J Sharp 1 , N Cowern 1 , K Kirkby 1
1 Advanced Technology Institute, University of Surrey, Guildford, Surrey, GU2 7XH, United Kingdom, 2 Parametric and Conductive Implant Division, Applied Materials UK Ltd, Foundry Lane, Horsham, West Sussex, RH13 5PX, United Kingdom, 3 ITC-irst, Centro per la Ricerca Scientifica e Tecnologia, Povo, Trento, Italy, 4 , Chartered Semiconductor Manufacturing Ltd, Industrial Park D, Street 2, 738406 Singapore
Show AbstractC2: SPER and Strained Silicon
Session Chairs
Akio Shima
Wilfried Vandervorst
Tuesday PM, April 18, 2006
Room 3000 (Moscone West)
2:30 PM - C2.1
Room Temperature Boron Diffusion in Amorphous Silicon.
Jeannette Jacques 1 , Kevin Jones 1 , Mark Law 2 , Lance Robertson 3 , Leonard Rubin 4 , Enrico Napolitani 5
1 Materials Science & Engineering, University of Florida, Gainesville, Florida, United States, 2 Department of Electrical and Computer Engineering, University of Florida, Gainesville, Florida, United States, 3 , Texas Instruments, Inc., Dallas, Texas, United States, 4 , Axcelis Technologies, Beverly, Massachusetts, United States, 5 Dipartimento di Fisica, INFM-MATIS, Padova Italy
Show AbstractAs millisecond annealing becomes more popular, the as-implanted profile dominates the final dopant distribution. Investigations were conducted to characterize boron diffusion in amorphous silicon prior to post implantation annealing. Silicon wafers were preamorphized with either 60 keV Ge+ or 15 keV and 70 keV Si+ at a dose of 1x1015 atoms/cm2. Fluorine, germanium, and silicon dopants were then implanted at energies of 6 keV, 14 keV, and 9 keV, respectively. These species were introduced at doses ranging from 1x1014 atoms/cm2 to 5x1015 atoms/cm2, followed by 11B+ implants at 500 eV, 1x1015 atoms/cm2. Secondary Ion Mass Spectrometry confirmed that fluorine and germanium enhance boron motion in amorphous materials prior to annealing. The magnitude of boron diffusion in germanium amorphized silicon scales with increasing fluorine dose. Boron atoms are mobile under these conditions at concentrations approaching 1x1019 atoms/cm3. It appears that defects inherent to the structure of amorphous silicon can trap and immobilize boron atoms at room temperature. Chemical reactions between silicon and fluorine, as well as silicon and germanium, are believed to result in the elimination of potential trapping sites. The use of sequential germanium and fluorine implants results in 80% more boron motion, as compared to silicon and fluorine implants into silicon. The mobile boron dose and the concentration of trapping sites were shown to change as a function of the fluorine dose according to power law relationships. As the fluorine implant dose increases, the trapping site population decreases and the mobile boron dose increases. Boron exhibits a solubility limit at room temperature in amorphous silicon generated via germanium implantation, with maximum mobile boron doses on the order of approximately 1x1012 atoms/cm2. The reduction of the trap density can result in an increase in the as-implanted “junction depth” by as much as 75% at a boron concentration of 1x1018 atoms/cm3 for samples implanted with 500 eV, 1x1015 atoms/cm2 boron.
2:45 PM - C2.2
Diffusion of Ion Implanted Dopants in Amorphous SiGe during Solid Phase Epitaxial Recrystallization
Leah Edelman 1 , Jeannette Jacques 1 , Judy Hoyt 2 , Rob Elliman 3 , Kevin Jones 1
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States, 2 Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 3 Electronic Materials Engineering, The Australian National University, Canberra, Australian Capital Territory, Australia
Show AbstractDuring high temperature microsecond annealing it has been shown that the total diffusion of dopants can be dominated by diffusion in the amorphous phase during solid phase epitaxial recrystallization (SPER). The diffusivity of boron has been found to be approximately 5 orders of magnitude higher than in crystalline Si. In this study, 1-micron thick relaxed layers of Si0.8G0.2 were grown on Si. After growth the layers were implanted with arsenic, boron, or phosphorus at a dose of 1x1014/cm2 and the energy was adjusted so the projected range was approximately 220Å. Next a high energy, Si implant was used to amorphize the SiGe to a depth of 0.8-microns. The amorphous SiGe was recrystallized at 550°C and the diffusion during SPER was studied using secondary ion mass spectrometry (SIMS). Surprisingly boron showed no measurable motion during recrystallization. The reason for the lack of motion will be further explored and discussed. Arsenic also showed no measurable motion. Phosphorous however exhibited unusual motion during SPER. The tail of the profile moved deeper into the crystal while the peak appears to have been displaced toward the surface, possibly by segregation during SPER. Transmission electron microscopy studies will also be reported. A possible correlation exists between regrowth related extended defect formation during SPER and the diffusion characteristics observed.
3:00 PM - C2.3
Enhanced Sb Activation for Ultra-Shallow Junctions in Strained Silicon.
Nick Bennett 1 , A. Smith 1 , C. Beer 2 , L. Li 1 , G. Dilliway 3 1 , R. Gwilliam 1 , B. Colombeau 4 , H. Radamson 5 , N. Cowern 1 , B. Sealy 1
1 Advanced Technology Institute, University of Surrey, Guildford, GU2 7XH, United Kingdom, 2 Department of Physics, University of Warwick, Coventry, CV4 7AL, United Kingdom, 3 IMEC, Kapeldreef 75, 5001, Leuven Belgium, 4 Chartered Semiconductor Manufacturing Ltd., Industrial Park D, Street 2, 738406, Singapore, 5 KTH, IMIT, Electrum 229, SE-16440, Kista Sweden
Show AbstractIn order to improve the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) the use of new materials has emerged as an alternative to aggressive scaling of device dimensions. The use of strained Si in the channel is one such initiative to bring about carrier mobility (µ) enhancement. In addition, ultra-shallow junctions (USJs) with high dopant activation, low sheet resistance (Rs), thermal stability and good lateral abruptness are required for source/drain extensions (SDEs). Arsenic is the favoured n-type dopant species however previous studies on bulk-Si have shown implanted Sb a capable alternative due to improvements in junction steepness and high levels of activation.At present little is known about the effect of strain on dopant activation for the SDE regions. Literature discussing As implants in strained layers have shown Rs reduction as a direct result of µ enhancement but with no improvement on activation.In this paper we discuss experiments performed on both biaxially tensile-strained Si layers grown on a p-Si0.8Ge0.2 strain-relaxed buffer layer and conventional p-type Si. Low energy (2keV, 4x1014cm-2) As and Sb implants were used to create junctions to ~15nm and ~12nm respectively. Dopant activation was achieved using a low thermal-budget isochronal rapid-thermal annealing scheme. Additional experiments were done using preamorphised-Si prior to Sb implant in order to determine the role of defects in activation. An innovative differential Hall profiling technique was used to measure active carrier concentration (Ns) and Hall mobility and the profiles are compared with atomic profiles measured by secondary-ion mass spectroscopy. Raman spectroscopy and cross-sectional transmission electron microscopy are employed to look at the strained layer quality and defect evolution during processing.We present results outlining Rs improvements for As and Sb doped layers produced in strained Si. Comparisons re-emphasise that the Rs reduction for As comes purely as a result of mobility improvements. Conversely for Sb, a larger, factor of two lowering is observed from a combined improvement in both µ and Ns. For the first time strain is shown to enhance the activation of dopant atoms with the active carrier concentration seen to be much higher than Sb solid-solubility in bulk-Si. Our results propose Sb as a viable alternative to As for producing highly activated and low resistive ultra-shallow junctions for use in the strain regime of n-type complementary-MOS (CMOS) devices.
3:15 PM - C2.4
Ge out-diffusion and its Effect on Electrical Performance in s-Si/SiGe Devices.
Suresh Uppal 1 , Rimoon Agaiby 1 , Sarah Olsen 1 , Sanatan Chattopadhyay 1 , Anthony O'Neil 1 , Steve Bull 2
1 , School of EE&CE, Newcastle upon Tyne United Kingdom, 2 , School of Chemical Engineering and Advanced Material, Newcastle upont Tyne United Kingdom
Show AbstractStraining Si has emerged as an innovative material approach to achieve performance enhancement without aggressive scaling. Although a performance enhancement on s-Si/SiGe based devices has been clearly demonstrated, the devices fabricated so far are not free from concerns. There are three crucial factors affecting the device performance from materials perspective, namely, strained Si thickness, Ge content in the VS, and amount of strain in the channel. In this paper, we report about quantification of Ge out-diffusion on strained Si NMOS devices with varying Ge content (i.e. strain in channel) and strained layer thicknesses. The devices were fabricated on strained Si/SiGe structures with 10, 15, 20, 25 and 30% Ge content and utilised a high temperature fabrication process. The Ge content was measured using SIMS and analysed using TCAD simulator taking into account all thermal budgets. TEM and C-V and I-V measurements were also carried out for material and electrical characterisation. It is found that with increasing Ge content in VS (and strain), the diffusivity of Ge into strained Si increases. The pre-exponential factor follows an exponential behaviour while the activation energy varies linearly with the Ge content in the SiGe layers. Moreover, it is found that interface trap charge density (Dit) and fixed oxide charge (Qf) increase with increase in Ge content. Both, Dit and Qf, decrease with increase in strained layer thickness from 3.7 to 6nm. Quantification of the effect of Ge out-diffusion on the increase in Dit and Qf values is being performed. From the calculations it is clear that transconductance (and hence mobility) of the electrons decreases as the strained-Si layer thickness reduces and this is attributed to increased Ge along the channel due to out-diffusion from SiGe. Additionally, in our devices the enhancement of mobility due to strain started to degrade beyond 25% Ge content due to alloy scattering. The results show that for a given Ge content, a combination of strained layer thickness and thermal budget should be optimised to achieve best device results.
3:30 PM - C2.5
Effect of He-induced Nanovoids on B Diffusion and Electrical Activation in Si.
Elena Bruno 1 , Salvatore Mirabella 1 , Giuliana Impellizzeri 1 , Francesco Priolo 1 , Filippo Giannazzo 2 , Vito Raineri 2 , Enrico Napolitani 3
1 , MATIS-CNR-INFM and Department of Physics and Astronomy, University of Catania, Via S. Sofia 64, I-95123 Catania (Italy), Catania Italy, 2 , CNR-IMM, Section of Catania, Stradale Primosole 50, I-95121 Catania (Italy), Catania Italy, 3 , MATIS-CNR-INFM and Department ofi Physics, University of Padova, Via Marzolo 8, I-35131 Padova (Italy), Padova Italy
Show Abstract3:45 PM - C2.6
Interaction Between Low Temperatures Spacers and Source Drain Extensions and Pockets for Both NMOS and PMOS of the 65 nm Node Technology
Nathalie Cagnat 1 , Cyrille Laviron 3 , Daniel Mathiot 4 , Pierre Morin 1 , Frederic Salvetti 2 , Davy Villanueva 2 , Marc Juhel 1 , Marco Hopstaken 2 , Francois Wacquant 1
1 , STMICROELECTRONICS, Crolles France, 3 , LETI (CEA), Grenoble France, 4 , InESS, Strasbourg France, 2 , PHILIPS, Crolles France
Show AbstractThe necessary precise tuning of dopant profiles for ultra shallow junctions requires both an accurate control of the ion implantation processes and of the various interactions possibly occurring between the dopant species and all the materials in contact with them during the integrated circuits fabrication process. In this work, we focus on the interaction between the spacer stack (oxide + nitride) and the underlying implanted silicon. Indeed, during the MOS transistors fabrication process, the source-drain extension areas are directly in contact with the oxide liner of the spacers stack. In previous works [1,2,3] it has been established that boron can diffuse from the source-drain extensions into the spacer oxide liner during the subsequent annealing steps, and that the amount of boron loss depends on the hydrogen content in the oxide, because of the enhancement of B diffusivity in SiO2 by the presence of hydrogen. However, the overall hydrogen content of the oxide layer does not depend only on the oxide characteristics itself, but also of the overlying nitride layer. Indeed, the nitride act as a capping layer preventing H to diffuse out of the underlying oxide, and thus affecting the resulting H content in the oxide.In order to characterize and quantify the above phenomena, we performed test experiments on full sheet samples, which mimic either BF2 source-drain extensions over arsenic pockets implants, or BF2 pockets under arsenic or phosphorus source-drain extensions implants. Following the corresponding implants, the wafers were covered with different spacer stacks (oxide + nitride) deposited either by LPCVD, or PECVD. After appropriate activation annealing steps, SIMS measurements were used to characterize the profiles of the various dopants, and the corresponding dose loss was evaluated for each species. Other measurements as Rs, thermawave, spectroscopic ellipsometry and XPS analyses were used to complete our study.Our experimental results clearly evidence that LPCVD or PECVD spacer stacks have different influences on the boron profiles. On the other hand, the other dopant profiles are unaffected. It is also shown that boron out-diffuses not only from the B doped source-drain extension in direct contact with the oxide layer, but also from the "buried" B pockets lying under n-doped source drain extension areas. All these results will be discussed in term of the possible relevant mechanism and of their technological importance with the support of TCAD modeling.[1] : « Modeling B diffusion in thin-oxide p+ Si gate technology » R.B. Fair - IEEE Electron Device Letters, Vol. 17, No 11, p. 497-499, 1996 [2] : « Modeling the effect of source/drain sidewall spacer process on Boron USJ » S. Chakravarthi, P. Kohli, P.R. Chidambaram, H. Bu, A. Jain, B. Hornung & C.F. Machala – IEEE 2003[3] : « Influence of the spacer dielectric processes on PMOS junction properties » P. Morin, F. Wacquant, M. Juhel, C. Laviron, D. Lenoble – E-MRS 2005
4:30 PM - **C2.7
Integration of Solid Phase Epitaxial Re-Growth, Flash and Sub-Melt Laser Annealing for S/D Junctions in CMOS Digital Technology
Simone Severi 1 2
1 , IMEC, Leuven Belgium, 2 , K.U.Leuven, Leuven Belgium
Show AbstractDuring the last few years an increasing effort in scaling the junction depth profiles, minimizing the doping diffusion, while maximizing the doping activation has been carried out. Promising results have been shown with sub-millisecond annealing techniques, as flash or sub-melt laser, and also with the low temperature process Solid Phase Epitaxial Re-growth (SPER). Furthermore a pre-amorphization step reduces the channeling during the implantation with an additional improvement of the doping activation. The 1D diffusion-less junction properties clearly improve if compared to the ones obtained with conventional anneals. However the integration of these junctions on planar CMOS technologies demonstrates that the transistor properties of the conventional annealing techniques still remain unbeaten. An electrical analysis of the 2D doping profile reveals that lateral junction profile shrinks as well as the vertical junction profile. The scalability of devices with junction activated with advanced annealing can be improved due to a longer effective gate length Leff for the same physical gate length. However the overlap capacitance decreases too, inducing an increase of the S/D resistance. The trade off between Leff and Rsd is found to be strongly dependent on the extension junction energy. Even though an optimum point for advanced annealed junctions can be found, the transistor performance does not overcome the one obtained from conventional RTA anneal. An investigation on the carrier mobility in the channel, as a possible source of current degradation, as a function of the annealing techniques and of the peak temperature has been carried out. The presence of defects in the gate oxide as well as the stress induced on the wafer during the annealing has been analysed. Furthermore the defects introduced by the implantation in the gate oxide at the edges of the gate are not completely removed after the anneal enhancing the off-state gate leakage. This effect is dependent on the size of the atoms of the implanted doping, having a different impact on NMOS and PMOS devices. Ultimately the impact of these advanced annealing techniques has been investigated on high-k and metal gate stack.
5:00 PM - **C2.8
Extended Defects and Dopant Diffusion/Activation Anomalies in Ultra-Shallow Junctions.
Fuccio Cristiano 1 , Younes Lamrani 1 , Fabrice Severac 1 , Mathieu Gavelle 1 , Simona Boninelli 2 , Nikolay Cherkashin 2 , Alain Claverie 2 , Wilfried Lerch 3 , Silke Paul 3
1 , LAAS/CNRS, Toulouse France, 2 , CEMES/CNRS, Toulouse France, 3 , Mattson Thermal Products, Dornstadt Germany
Show AbstractTo continue scaling down CMOS devices, ultra-shallow and extremely highly doped p+/n junctions must be fabricated. While novel methods of shallow junction formation are being investigated (pre-amorphisation, plasma doping, millisecond Flash or laser anneals…), it is expected that the conventional “ion implantation + RTA” procedure will still be used (and pushed to its limits) for the next future. As it is known, the major problem related to this technique, is the formation of extended defects resulting from the precipitation of the large amounts of interstitials and vacancies generated during the implantation process. Indeed, the interactions between the defects and the implanted dopants are at the origin of the diffusion and activation anomalies that are among the major obstacles to the realisation of ultra-shallow junctions satisfying the ITRS requirements.The work presented in this paper will address some of the crucial issues related to two of the currently investigated novel fabrication processes: (i) the dopant implantation into pre-amorphised silicon followed by Solid Phase Epitaxial Growth (SPEG) at low temperature (<700°C) and (ii) the use of millisecond Flash anneals at very high temperature (up to ~1300°C) in order to achieve virtually “diffusionless” junctions.In the first part, we will present a detailed study showing the role of the extended defects in determining the thermal stability of activated junctions formed by SPEG. Indeed, this technique allows very high activation levels (above equilibrium solid solubility) with minimum dopant diffusion (due to the very low thermal budget). However, the activation levels achieved by SPEG appear to be metastable with respect to the subsequent “post-annealing” steps that follow the junction formation in a typical CMOS process flow, resulting in unattended increase/decrease of the junction sheet resistance (“deactivation/reactivation” cycles). In particular, we will show how the dissolution of the preamorphisatsion defects (EORs) controls the deactivation mechanism, while the reactivation is controlled by the Boron-Interstitial Clusters (BICs) dissolution. In addition, we will report on the role of Fluorine co-implantation in stopping the junction deactivation during a post-annealing step. In this case, we will show how this result can be achieved by either the formation of Fluorine-Vacancy clusters or by a “stabilisation” of the EOR defects.In the second part, we will present some recent results on the formation of extended defects in activated junctions formed by a millisecond Flash anneal (both in cristalline and preamorphised substrates). In particular, we will study the impact of the Flash process conditions in order to achieve a full dissolution of the EOR defects. As for the case of non-preamorphised structures, we will focus our attention on the B peak region, where we will show that extended defects (BICs) can form despite the very high annealing temperatures involved.
5:30 PM - C2.9
Effect of Uniaxial Stress on Solid Phase Epitaxial Regrowth and Mask Edge Defect Formation in Two-Dimensional Amorphized Si.
N. Rudawski 1 , K. Siebein 1 , K. Jones 1 , J. Liu 2
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States, 2 , Varian Semiconductor Equipment Associates, Gloucester, Massachusetts, United States
Show AbstractIt has been shown that flash annealing deep pre-amorphizing implants can result in shallower, more active junctions. However, deep pre-amorphizing implants in patterned wafers can result in the formation of mask edge defects. These defects form at the interface of two different regrowing amorphous/crystalline interfaces. Stress can influence the formation of these defects. This study investigated approaches to controlling the evolution of defects by applying an external uniaxial stress. Si3N4 trench structures were used to create two-dimensional amorphous layers. Si+ implantation at energies of 20 and 60 keV with doses of 1×1015 cm-2 produced amorphous layers ~1400 Å deep with rounded corners beneath the mask edges. Samples were annealed under stress at temperatures between 500 and 700 °C. Stress was applied perpendicular or parallel to the <110> lateral regrowth front. Defects formed under no stress or when stress was applied parallel to the regrowth front. However, defects were not observed when a tensile stress of ~125 MPa was applied perpendicular to the regrowing interface. Using cross-sectional and plan-view transmission electron microscopy, the effect of stress on solid phase regrowth velocity and defect formation was studied. The effect of stress on the lateral regrowth velocity will be presented.
5:45 PM - C2.10
Role of Silicon Interstitials in Transient Enhanced Diffusion of N-type Dopants.
Scott Harrison 1 , Thomas Edgar 1 , Gyeong Hwang 1
1 Chemical Engineering, University of Texas at Austin, Austin, Texas, United States
Show AbstractAs device dimensions scale down, the formation of ultrashallow junctions (< 20 nm in depth) is required to avoid short-channel effects. At present, these junctions are widely synthesized by using low energy ion implantation to introduce dopants followed by thermal annealing to repair substrate damage and electrically activate implanted dopants. During annealing, the dopants often exhibit significant transient enhanced diffusion (TED) which limits the junction depth which can be realized. It is therefore necessary to understanding the underlying mechanism of dopant TED, and in turn find a means to minimize the TED while maximizing the electrical activity of injected dopant impurities. Recent experimental studies [1-3] have suggested the importance of Si interstitials (Sii) in n-type dopant TED during ultrashallow junction formation in silicon. In this presentation, we use density functional theory (DFT) calculations within the generalized gradient approximation (GGA) to examine the formation of n-type dopant-silicon interstitial pairs. Under highly extrinsic conditions, we find that the n-type dopants can form a negatively charged dopant-interstitial pair in which the dopant atom bridges two lattice silicon atoms [4]. While under intrinsic conditions, dopant-interstitial complexes in several charge states can contribute to interstitial driven TED. For the neutral P-Sii, As-Sii, and Sb-Sii pairs, we determine binding energies of 0.90 eV, 0.60 eV, and 0.04 eV with respect to their neutral substitutional dopants and the neutral split-(110) Sii. The insignificant binding energy of Sb with an interstitial indicates the pair will remain unbound which is consistent with experimental that show negligible interstitial-driven Sb diffusion [1]. For the neutral P-Sii and As-Sii pairs, we find acceptor levels of 0.49 eV and 0.23 eV (for a computed GGA band gap of 0.63 eV), indicating P-Sii- and As-Sii- will become the most stable dopant-interstitial pairs at highly n-type extrinsic conditions. For P-Sii- and As-Sii-, we determine migration barriers of 0.42 eV and 0.44 eV, suggesting that P-Sii- and As-Sii- pairs will be the major component of interstitial mediated TED under highly n-type extrinsic conditions. Our results are consistent with experimental results that have shown that interstitials can mediate P and As TED [1]. The detailied understanding we present here will greatly contribute to developing improved physical models for the formation of highly n-type doped ultrashallow junctions. References[1]A. Ural, P.B. Griffin, and J.D. Plummer, J. Appl. Phys. 85, 6440 (1999).[2]R. Kim, T. Hirose, T. Shano, H. Tsuji, and K. Taniguchi, Jpn. J. Appl. Phys. 41, 227 (2002).[3]S. Solmi, M. Ferri, M. Bersani, D. Giubertoni, and V. Soncini, J. Appl. Phys. 94, 4950 (2003).[4]S.A. Harrison, T.F. Edgar, and G.S. Hwang, Appl. Phys. Lett., in press (2005).
C3: Poster Session
Session Chairs
Wednesday AM, April 19, 2006
Salons 8-15 (Marriott)
9:00 PM - C3.1
Codoping Strategies In Heavily N-Doped Silicon.
Dominik Mueller 1 , Wolfgang Fichtner 1
1 Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich, Zurich, Switzerland
Show AbstractCodoping has been successfully applied in experiment for the fabrication of ultrashallow p-type junctions in silicon for the future device down scaling. The main challenge is to control the concentration of excess interstitials that mediate boron diffusion. In the n-type case, however, it is the excess vacancies which are predominantly responsible for both the dopant diffusion (As and Sb) and the electrical deactivation of the donors.It is therefore of utmost importance to control and minimize the vacancy concentration in n-type junctions. We have studied the donor deactivation and diffusion mechanisms by means of extensive ab initio calculations. Excess vacancies in heavily n-doped areas result from implant damage and, at high Fermi levels, from Frenkel pair generation as well as in-diffusion from the surface due to the abundantly present donor atoms. Vacancies act as powerful electron sinks at high Fermi levels, and they can deactivate up to four donors each when forming donor-vacancy clusters. Moreover, the vacancies experience low energetic barriers when traveling between donor atoms in the Si crystal, mediating therefore the very quick dopant diffusion observed in such samples.With a clear picture of these atomic scale processes at hand, we could devise strategies for the forestalling of both the deactivation and diffusion processes. Our atomistic simulations were performed with Density Functional Theory. We focused on the properties that a codopant atom must have in order to act as a powerful vacancy compensator. First, the codopant should exhibit a high vacancy trapping energy, meaning that the energy gain from the interstitial to substitutional (formerly vacant) lattice position should be large. This energy gain must be positive even if the vacancy is surrounded by as many as four large donor atoms. Second, the codopant should be small enough to be able todiffuse through the Si lattice channels without the needof intrinsic defects and without appreciable latticedistortion. Third, the isolated codopant itselfshould preferably not act as electron acceptor in anylattice position. Fourth, the codopant should fill up the unwanted empty vacancy electron acceptor states when annihilating a vacancy by assuming the substitutional position, transforming the donor-vacancy clusters from electron acceptors back into electron donors.We found that generally, light alkali and alkaline earth metals fulfill most of these prerequisites. The best suited codopant candidates for As and Sb, possibly also for P, however, are the double donors Beryllium and Magnesium. Depending on the donor concentration and the ratio of dopants/codopants introduced, a reactivation of up to 50% can be expected.
9:00 PM - C3.10
Control of Phosphorus Profile using Gas Phase Doping (GPD) for Ultra Shallow Junction Formation
Takuya Konno 1 , Nobuaki Makino 1 , Tetsuya Kai 2 , Takashi Suzuki 2 , Nobutoshi Aoki 2 , Ichiro Mizushima 2
1 Corporate Manufacturing Engineering Center, Toshiba Corporation, Yokohama Japan, 2 Semiconductor Company, Toshiba Corporation, Yokohama Japan
Show AbstractGas phase doping (GPD) is one of the methods to introduce the dopant into the surface region of the three dimensional structure which is one of the promising candidates for next generation devices. However, it is difficult to form a shallow junction with a high surface concentration using this technique. In the previous report for n-type doping by GPD using PH3, the surface concentration was less than 1×1020 atoms/cm3 [1]. In this report, a new model for impurity doping using GPD is proposed according to the systematic experimental results. Junction with high surface concentration of phosphorus (P) of more than 1×1020 atoms/cm3, the profile of which can be controlled precisely, was obtained using the process sequence based on the proposed model. GPD of P was performed using p-type Si (100) wafers. Prior to GPD, native oxide on the Si surface was removed, or the chemical oxide was formed. GPD was performed at 850°C, under the PH3 partial pressure of 0.08-20 Torr, for 10-120 min. Some wafers were in-situ H2 annealed in the same chamber before GPD. The depth profiles of P were measured by SIMS. The surface states of Si were analyzed by XPS. Sheet resistivities were measured by four-point-probe method.It was revealed from the experiments that the peak concentration was strongly affected by the partial pressure of PH3. Peak concentration of P was over 1×1020 atoms/cm3 at 20 Torr by combining with appropriate surface wet-cleaning before GPD. Highest P concentration at the surface was obtained with the sample that was in-situ H2 annealed in the chamber prior to GPD. With sufficient in-situ H2 annealing, wet-cleaning condition did not have any influence on the P concentration regardless of the wet cleaning condition.The detailed measurement of the profile of P near the surface revealed that highly activated P regions were formed in the 5 nm layer beneath the surface. Active P profile was calculated by the repetition of the etching of 1 nm-Si-layer and the measurement of sheet resistivity. XPS analyses for the as-GPD sample and 5-times-etched-sample supported the accuracy of P profile.From above results and the results obtained in the previous paper [1], a new model for P doping from gas phase into Si is proposed. PH3 is thermally decomposed to P and H. In case that PH3 partial pressure is low, absorbed P atoms on Si surface diffused into Si immediately. On the other hand, in case of high PH3 pressure, a large amount of P atoms absorb on the Si surface. High P concentration layer is formed just beneath the surface of Si, where the P concentration is in equilibrium with the amount of absorbed P. Since this high P concentration layer acts as the diffusion source of P, depth profile of P in Si can be controlled precisely by the condition of GPD and the post-annealing process.Ref. [1] T. Sato et al., Jpn. J. Appl. Phys., 37, 1162 (1998).
9:00 PM - C3.11
PN Junction Formation for High-Performance Insulated Gate Bipolar Transistors; Double-Pulsed Green Laser Annealing Technique
Toshio Kudo 1
1 R & D Center, Sumitomo Heavy Industries, Ltd., Yokosuka-shi, Kanagawa, Japan
Show Abstract Reflecting the efficiency-increasing trend of insulated gate bipolar transistors (IGBTs) of thin Si wafer type, low thermal budget activation process is demanded for forming PN junction on the back of the Si wafer (at a collector electrode) without heating the front of the Si wafer which has an emitter electrode made of aluminum with the low-melting point. Laser annealing technique is suitable for the low thermal budget activation process because of very short irradiation time. A boron (B) implant into n-type Si wafers was performed at an energy of 40keV to a dose of 1E+15/cm2, and a phosphorus (P) implant into p-type Si wafers at an energy of 400keV to a dose of 1E+13/cm2. The B or P implanted wafers were activated with the double-pulsed laser annealing system in which diode pumped solid state (DPSS) green lasers were equipped as light sources. Adjusting widely the annealing time through a delay time between laser pulses of pulse width ~100ns, the double-pulse method can control the depth of activation in the low thermal budget process. The green wavelength has the optical penetration depth of about 1μm and is of advantage to the activation of deep PN junction. The effect of laser annealing parameters on activation was investigated with the energy density of pulse lasers, the delay time, and the overlap ratio of line-beam scanning. The B or P dopant distribution in depth was determined from analyses of secondary ion mass spectroscopy (SIMS), and the carrier concentration distribution in depth from analyses of spreading resistance profiles (SRP). The activation ratio of B or P dopants was estimated making a comparison of two analytical results: the total implanted dopants from SIMS and the total carriers from SRP. The delay time, one of the annealing parameters was proved to be most effective for the activation of the deep PN junction in IGBTs. Increasing the delay time from 0ns to 500ns under the same annealing conditions: the first & second pulse energy density of 1.8J/cm2 and the overlap ration of 67%, the implanted B dopants were activated to approximately 100% because of being melted to the depth of ~0.5µm, and the carrier concentration profiles of P dopants became deeper from 1µm to 1.7µm at 1E+14 carrier/cm3 and the activation ration was improved from 40% to 70%. And the overlap ratio increase of 67% to 90% and the pulse energy density increase of 1.8J/cm2 to 2.0j/cm2 produced a minor improvement of activation. The double-pulsed green laser annealing is expected to be a key process in fabricating high-performance IGBTs.
9:00 PM - C3.2
Boron Migration Length In Silicon : Molecular Dynamics Versus Experiments.
Valerie Cuny 1 , Evelyne Lampin 1 , Fabrizio Cleri 2 , Christophe Krzeminski 1
1 ISEN, IEMN, Villeneuve d'Ascq France, 2 , ENEA, ROMA Italy
Show AbstractWe present molecular dynamics simulations of the migration of boron in silicon aimed at enriching the continuum-level models of dopant diffusion. The boron atom, initially put in an interstitial site of the silicon lattice, evolves at constant temperature in the energy landscape of the atomic interactions calculated in the Stillinger-Weber scheme. The first event in this atomic system is the kick-in of the boron atom in a substitutionnal site accompanied by the release of a silicon self-intersitital. The silicon interstitial afterwards diffuses in the simulation cell and causes a succession of migrations and immobilities of the boron atom. The atomic positions are analysed to check whether the kick-out or the interstialcy mechanism is responsible of the motion of the boron atom. The displacement of boron is subsequently used to calculate its migration length. The results averaged on a wide amount of diffusing events are in excellent agreement with the parameter of a continuum model of the boron diffusion fitted on the measured spreading of boron delta layers. This agreement not only provides a confirmation of the migration lenth of boron but also a promising method to calculate this parameter for other dopants or materials.
9:00 PM - C3.3
Atomistic Simulation of Solid Phase Epitaxy of Amorphous Silicon: Influence of the Interatomic Potential on the Recrystallisation Velocity.
Christophe Krzeminski 1 , Valerie Cuny 1 , Emmanuel Lecat 1 , Evelyne Lampin 1 , Ardechir Pakfar 2 , Clement Tavernier 2 , Herve Jaouen 2
1 ISEN, IEMN, Villeneuve d'Ascq France, 2 , ST-Microelectronics, Crolles France
Show AbstractIn the race for the downscaling of electronic devices, the ITRS ROADMAP 2004 enforces sharp requirements in terms of source/drain sheet resistance, junction depth, lateral abruptness ...[1] The formation of an amorphous layer by ion implantation subsequently annealed to rebuild its cristalline arrangement is the main alternative to meet these objectives. The simulation of this specific process is a mandatory problem for the microelectronic industry since a realistic dopant profile is necessary to calculate the electrical characteristics of these non-classical MOSFETs. While the solid phase epitaxy (SPE) of amorphous silicon (a-Si) is well understood in intrinsic silicon [2], complex effects take place in the presence of dopants. Only molecular dynamics (MD) simulations are expected to be able to face this issue. Several groups have already presented simulations of the recristallisation process with molecular dynamics [3]. Nevertheless, the exploitation of such simulations has never been pursued and it is still a question whether such methods would be able to correctly predict the velocity of the epitaxy. In the present work, we have investigated the recrystallization of an amorphous layer at the interface with crystalline silicon using the MD technique. The amorphous cluster has been generated using the WWW algorithm [4]. This approach generates amorphous silicon with realistic structural properties. The silicon/amorphous interface is further fabricated by gluing together the two clusters along the [100] plane. The annealing is then simulated by MD using one of the Stillinger-Weber, EDIP or Tersoff potential. Afterwards, a systematic analysis of the recrystallisation process is carried out by calculating the structure factor perpendicular to the amorphous crystalline interface, and using it to obtain the velocity of the solid phase epitaxy. A temperature plot of the velocity is performed in order to extract the activation energy. Preliminary results show clear differences between velocities predicted by the three atomic potentials. The ultimate choice of atomic potential will not only depend on the intrinsic SPE velocity but also on their ability to describe the interaction with the standard dopants.[1] SIA Semiconductor Industry Association, ``The International Technology Roadmap for Semiconductors-ITRS '', (2004).[2] G. Olson et al.,``Kinetics of Solid Phase recrystallisation in amorphous silicon'', Mater. Sci. Rep. 3, 1 (1998).[3] A. Mattoni et al., ``Boron ripening during solid-phase epitaxy of amorphous silicon'', Phys. Rev. B 69, 045204 (2004).[4] Wooten et al., ``Computer Generation of structural Models of Amorphous Si and Ge'', Phys. Rev. Lett. 54, 1392 (1985).
9:00 PM - C3.4
Modeling and Simulation of the Influence of SOI Structure on Damage Evolution and Ultra-shallow Junction Formed by Ge Pre-amorphization Implants and Solid Phase Epitaxial Regrowth.
K. R. C. Mok 1 , B. Colombeau 2 , M. Jaraiz 3 , P. Castrillo 3 , J. E. Rubio 3 , R. Pinacho 3 , I. Martin-Bragado 4 , M. P. Srinivasan 1 , F. Benistant 2 , J. J. Hamilton 5
1 Department of Chemical and Biomolecular Engineering, National University of Singapore, Singapore Singapore, 2 , Chartered Semiconductor Manufacturing, Singapore Singapore, 3 Departamento de E. y Electronica, Universidad de Valladolid, Valladolid Spain, 4 , Synopsys, Mountain View, California, United States, 5 , Advanced Technology Institute, Guildford, Surrey, United Kingdom
Show Abstract9:00 PM - C3.6
Short and Long Pulsed Excimer Laser Processing of Silicon: Numerical and Experimental Investigation.
Stephane Coutanson 1 , Eric Fogarassy 1 , Julien Venturini 2
1 , InESS(CNRS), STRASBOURG Cedex 2 France, 2 , SOPRA-SA, Bois-Colombes France
Show Abstract9:00 PM - C3.7
Evaluating Dopant Diffusion and Clustering Parameters with Ab Initio Molecular Dynamics
Beat Sahli 1 , Wolfgang Fichtner 1
1 , ETH Zurich, Zurich Switzerland
Show AbstractThe increasingly complex physics-based models used for the simulation of dopant diffusion and activation with the kinetic Monte Carlo method contain numerous physical parameters. Many parameters prove inaccessible to experiment, but can be evaluated by ab initio molecular dynamics simulation. In addition to an accurate ab initio potential, reliable methods to extract the desired information from the molecular dynamics trajectories are necessary to obtain correct results. For this purpose, we have developed an extendable framework of trajectory data analysis methods. We used these methods to assess the diffusion coefficient, the defect configuration and the migration mechanism of the self-interstitial and the vacancy in silicon. Because sufficient ab initio molecular dynamics data was previously not available, we performed extensive simulations at our laboratory, using around one hundred CPU years of idle time on personal workstations. We present the analysis methods as well as the results obtained. Especially notable is the fact that the self-interstitial has many different migration mechanisms of similar importance. This means that it is very difficult to find all relevant mechanisms with the static approach of searching for stable states and the transition states in-between them instead of using molecular dynamics. The analysis methods are not only applicable to the vacancy and the self-interstitial, but can be used for dopants and for clusters of dopants and intrinsic defects as well. Moreover, the methods can be used for both unstrained and strained silicon.
9:00 PM - C3.8
Ab-initio Study of Boron Diffusion Retardation in Si1-xGex.
Yonghyun Kim 1 , Taras Kirichenko 2 , Gyeong Hwang 3 , Sanjay Banerjee 1
1 Microelectronics Research Center, The University of Texas at Austin, Austin, Texas, United States, 2 , Freescale Semiconductor, Austin, Texas, United States, 3 Department of Chemical Engineering, The University of Texas at Austin, Austin, Texas, United States
Show AbstractStress and defect engineering using Si1-xGex layers has been employed extensively in high-performance metal-oxide-semiconductor field-effect transistor (MOSFET) due to attractive material properties of SiGe and ease of integration with conventional silicon processing. Precise control of dopant redistribution and activation has become crucial for fabrication of deep sub-micron MOSFET devices with ultra-shallow junctions. Suppression of transient enhanced diffusion (TED) of boron is one of the major challenges for sub-100nm transistors, highlighting the need to better understand the underlying mechanism of defect-dopant diffusion in Si1-xGex. Understanding and control of defect and dopant dynamics at Si/Si1-xGex interface are especially important for MOSFETs with SiGe source/drain extensions. Although several experimental and theoretical studies have been undertaken to understand the fundamentals of dopant and defect behavior in Si1-xGex, clear and detailed description of underlying mechanisms is still lacking. In this talk we will present our density functional theory (DFT) calculation results on charged and neutral boron-interstitial (BI) pairs in Si1-xGex and decouple the effect of local strain induced by Ge from the chemical effect of Ge. In contrast to previous studies we show that retardation of BI diffusivity is determined not only by change of BI migration barrier on the presence of germanium but also by several other factors such as change in binding and formation energy of B-SiI, B-GeI as well as change in stability of Si and Ge interstitials. We find that the binding energy of B-GeI is 0.2 eV smaller than that of B-SiI in the both neutral and charged state. We also show that the diffusion BI pair exhibits a directional (with respect to Ge atom) anisotropy in presence of Ge. Along with structure and energetics of interstitials and BI pairs we provide a detailed analysis of changes in band-structure, local density of states (LDOS) as well as changes in bonding mechanisms (based electron density and electron localization function topologies) in Si1-xGex and Si/ Si1-xGex systems. The fundamental understanding and data are indispensable in developing a comprehensive model for p-type dopant diffusion in Si1-xGex, which will contribute greatly to improving current process technologies.
Symposium Organizers
Kevin S. Jones University of Florida
Masami Hane NEC Corporation
Susan B. Felch Applied Materials Inc.
Bartek J. Pawlak Philips Research Leuven
C4: Millisecond Annealing
Session Chairs
John Borland
Simone Severi
Wednesday AM, April 19, 2006
Room 3000 (Moscone West)
9:30 AM - **C4.1
Impurity Solubility and Redistribution Due to Recrystallization of Preamorphized Silicon.
Ray Duffy 1
1 , Philips Research Leuven, Leuven Belgium
Show AbstractThe use of silicon substrate preamorphization in ultrashallow junction formation has increased in recent years. The reduction of channeling during impurity implantation, coupled with higher-than-equilibrium metastable solubility levels, produces scaled junctions with low resistances. However, a number of physical phenomena arise that must be considered for proper impurity profile and device optimization. With respect to impurity solubility advanced annealing techniques such as solid-phase-epitaxial-regrowth (SPER), flash, and laser annealing, can place impurity atoms on substitutional sites in the Si lattice to extremely high concentrations when combined with preamorphization. Moreover, there is a relationship between the equilibrium distribution coefficient and metastable solubility. The distribution coefficient is defined as the relative tendency of various impurities to dissolve in solid silicon. The implication is that the long-established equilibrium distribution coefficient of an impurity, extracted in the liquid to solid phase transformation, can make a prediction of metastable solubility after transformation of amorphous silicon into crystalline silicon during SPER, flash and laser annealing.With respect to impurity redistribution the significant effects can be split into 3 categories, namely before, during, and after recrystallization. Before recrystallization impurity diffusion in the amorphous region may occur. Boron is particularly susceptible to this effect, which is very significant for the formation of p-type junctions. During recrystallization many impurities move ahead of the amorphous-crystalline interface and relocate closer to the surface. In general redistribution is more likely at high impurity concentrations. For the low-temperature SPER case there is a direct correlation between the magnitude of this redistribution effect and the impurity metastable solubility. After recrystallization, with SPER, flash, and laser annealing commonly leaving residual damage in the silicon substrate, interstitial-diffusers are especially vulnerable to preferential diffusion toward the surface, where impurity atoms may be trapped, ultimately leading to a more shallow profile. Residual defects also affect the stability of the junction activation upon subsequent thermal processing. These effects will be discussed in the context of silicon device optimization.
10:00 AM - C4.2
Varying the Regrowth Conditions of Amorphous Silicon with Laser Spike Annealing
Daniel Zeenberg 1 , Kevin Jones 1
1 Materials Science & Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractAs the fabrication for the CMOS technology trends to decreasing the size of transistors for the benefit of increased performance and device density, the implant and annealing process technologies are being forced to meet increasingly challenging demands for ultra-shallow junctions. As the current annealing preferences shift from rapid thermal annealing toward sub-second fabrication technologies such as flash and laser annealing, the dynamics of micro-structural evolution on the order of milliseconds and microseconds become of increasing importance. To investigate the kinetics in this ultra-fast annealing regime, this study investigated the effect of varying the temperature and time of amorphous silicon regrowth during the microsecond and millisecond timeframe. Amorphous layers were created in silicon wafers using a 30keV silicon implant at a dose of 1x1015 ions/cm3. These wafers were then processed using a scanning 10.6 µm CW CO2 laser at varying power densities and scan rates in order to vary the dwell time of each condition. A mixture of sheet resistance, optical interferometry, and cross-sectional transmission microscopy were used in order to investigate the regrowth rate and defect evolution in the partially-regrown and fully-regrown layers. The regrowth temperature across all samples showed a positive correlation to the sheet resistance; trending to lower values as power increased. Ramp rate, however, showed an inverse effect as the small thermal budget of the highest ramp rates did not allow for proper solid phase epitaxial regrowth to occur. The processing range for regrowth also trended to lower powers and smaller overall power ranges with increasing anneal times.
10:15 AM - C4.3
Defect Evolution During Laser Annealing.
Susan Felch 1 , Abhilash Mayur 1 , Vijay Parihar 1 , Faran Nouri 1
1 Front End Products, Applied Materials, Sunnyvale, California, United States
Show Abstract10:30 AM - **C4.4
The Behavior of Ion Implanted Silicon During Ultra-High Temperature Annealing
Amitabh Jain 1
1 Silicon Technology Development, Texas Instruments Inc., Dallas, Texas, United States
Show AbstractUltra-high temperature annealing has emerged as a promising technique for annealing ion implanted layers with a view to maximizing electrical activation while minimizing dopant diffusion. In order to ensure successful implementation, several materials-related problems have been under study. Since the time scale of the process is short, diffusion in the amorphous phase dominates the final profile as recrystallization persists late into the annealing cycle. We show that it is possible to preserve the steepness of the implanted profile as a result of the nature of this diffusion. In general, the residual disorder after anneal is seen to be higher than with current anneal processes. However, the short time scale of the process curtails the opportunity for movement of dislocations into regions where the electrical behavior of a device would be affected. An additional effect of the limited time scale is the ability of silicon to viscoelastically support the high strain-rates that may arise during the anneal. In this paper we review results from short time scale experiments that demonstrate these effects. We show that a physical understanding of these effects is forming the basis for viable process technologies.
11:30 AM - **C4.5
Pattern Density Effects In Millisecond Annealing
Yun Wang 1 , Shaoyin Chen 1 , Xiaoru Wang 1 , Michael Thompson 2
1 , Ultratech Inc., San Jose, California, United States, 2 Material Science, Cornell University, Ithaca, New York, United States
Show AbstractProper device scaling requires junction depth to shrink proportionally to the gate length while maintaining adequate sheet resistance in order to suppress short channel effects and keep device performance on track of the ITRS roadmap. This has historically been achieved by moving from isothermal anneals to spike RTA with increasingly high peak temperatures and heating/cooling ramp rates. These methods have become increasingly difficult as the thermal budget approaches fundamental limits established by the radiative heat transfer. Meeting these challenges today requires yet another shift to sub-millisecond annealing technologies such as non-melt laser spike annealing (LSA).In LSA, a surface layer is locally heated to temperature near silicon melt by means of a scanning line laser source. Heating a local region only, temperature ramp rates are established by the laser source while the substrate acts as a heat sink to rapidly quench the surface temperature, limited primarily by the silicon thermal conductivity. The coupled high peak temperature and low total thermal budget yields highly activated junctions with almost no diffusion, as mandated by scaling requirements.However, when applied to real circuits, such ultra-fast annealing faces new challenges. One key issue is within die temperature non-uniformity which arises from various pattern density effects including non-uniform optical absorption and inhomogeneous thermal properties. While these effects are known to exist in conventional lamp-based RTA, their magnitudes are exacerbated during millisecond annealing because of the short thermal diffusion length. In LSA, a contrast reduction technique is developed to suppress pattern density effects. As a result, uniform peak temperatures and impurity activation can be achieved across a wide range of film stacks. In this talk, we will discuss the origin and magnitude of these pattern density effects, and factors that may impact them. Quantitative methods to characterize the effects will be discussed, along with potential solutions to minimize the impact. Both theoretical models and experimental results will be presented.
12:00 PM - **C4.6
Issues and Optimization of Millisecond Anneal Process for 45 nm node and beyond
Kanna Adachi 1 , Kazuya Ohuchi 1 , Nobutoshi Aoki 1 , Hideji Tsujii 1 , Takayuki Ito 2 , Hiroshi Itokawa 2 , Koji Matsuo 2 , Kyoichi Suguro 2 , Yoshinori Honguh 3 , Naoki Tamaoki 3 , Kazunari Ishimaru 1 , Hidemi Ishiuchi 1
1 SoC Research & Development Center, Toshiba Corporation Semiconductor Company, Yokohama Japan, 2 Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company, Yokohama Japan, 3 Corporate R & D Center, Toshiba Corporation, Kawasaki Japan
Show AbstractUltra shallow junction is an inevitable component for high performance CMOSFETs. However, it has been revealed that it’s quite difficult to achieve the ITRS target for 45-nm node by conventional anneal technologies. To achieve this target, we have investigated millisecond anneal (MSA), such as Laser Spike Annealing (LSA) and Flash Lamp Annealing (FLA) and have found that there are three crucial issues from device integration and CMOSFETS performance viewpoint. In this report, we discuss these issues and also mention how to cope with them.The first issue is the junction leakage current increased by MSA associated with insufficient damage recovery. This junction leakage is dominated by high electric field of high impurity concentration by halo rather than the residual damage unrecovered by MSA. Process opimization method to decrease the junction leakage current is shown. The second one is the gate leakage current due to the damage introduced by high temperature MSA. In the case of either FLA or LSA, high temperature anneal improves the drain current for pMOSFET while it causes increase of the gate leakage current for nMOSFET. Therefore, optimization of anneal condition is required from the viewpoint of process integration. Furthermore, we must avoid a crystallization of high-k dielectrics materials by using MSA beyond 45-nm node. The third issue is the pattern dependence of light interference of FLA originated in its white light spectra. To clarify this issue, we investigated junction depth profiles with different pattern annealed by both FLA and LSA. Optical simulation is also carried out to analyze this phenomenon. Through the avobe analysis, we discuss the chanllenges of anneal technology for 45-nm node and beyond.
12:30 PM - C4.7
Deactivation of Ultra Shallow B and BF2 Profiles After Non-melt Laser Annealing.
Jim Sharp 1 , Karen Kirkby 1 , Nick Cowern 1 , Majeed Foad 2 , Massimo Bersani 3 , Damiano Giubertoni 3
1 Ion Beam Centre, University of Surrey, Guildford, Surrey, United Kingdom, 2 Front End Products Group, Applied Materials Inc., Sunnyvale, California, United States, 3 Centro per la Ricerca Scientifica e Tecnologia, ITC-irst, Povo, Trento, Italy
Show AbstractThe continued aggressive scaling down of source and drain extension regions for CMOS devices requires ultra shallow and abrupt profiles that have a low sheet resistance [1]. Boron implanted at very low energies (sub 1 keV) in conjunction with pre-amorphising implants can obtain the required junction depths for the PMOS source/drain extension regions. Conventional rapid thermal annealing used to activate the boron results in enhanced diffusion of the profile due to the damage introduced by the implantation steps. Subsequent thermal processes used for source/drain contact formation can lead to deactivation and eventual reactivation of the boron due to dissolution of both end of range defects and boron interstitial clusters [2]. This deactivation/reactivation occurs co-incidentally with substantial diffusion of the profile. A promising way to obtain highly active boron profiles with minimal diffusion is to use high temperature non-melt millisecond annealing, for example using a scanning laser, to anneal the ultra shallow boron implants [3]. The results presented here show a high initial activation in 500eV, 1x1015 cm-2 boron and 2.2keV, 1x1015 cm-2 BF2 implants in germanium pre-amorphised (100) silicon from non-melt laser annealing, and show their thermal stability during further thermal processes. The presence of fluorine when superimposed over the boron profile degrades the electrical properties of the initial fabricated junction, even after the laser anneal, and a difference in deactivation and reactivation behaviour between the two types of implant is seen.In addition, a novel differential Hall profiling technique is used to measure the level of carriers and the mobility in the first few nanometres of the boron profile. The effect of the non-melt laser annealing on this surface region will be discussed using results from these Hall profiling measurements.1.International Technology Roadmap for Semiconductors. 2004.2.F.Cristiano, N.C., P.Calvo, Y.Lamrani, X.Hebras, A.Claverie, W.Lerch and S.Paul, Thermal stability of boron electrical activation in preamorphised ultra-shallow junctions. Materials Science and Engineering B, 2004. 114-115: p. 174.3.Felch, S.B., et al. Optimization of pre-amorphization and dopant implant conditions for advanced annealing. in Ion Implantation Technology Proceedings of the 15th International Conference on Ion Implantation Technology ITT 2004, Oct 25-27 2004. 2005: Elsevier, Amsterdam, 1000 AE, Netherlands.
12:45 PM - C4.8
Thermally Induced Deformation and Stresses During Millisecond Flash Lamp Annealing.
Mark Smith 1 , K Seffen 1 , R McMahon 1 , W Skorupa 2
1 , Department of Engineering, University of Cambridge, Cambridge United Kingdom, 2 , Forschungszentrum Rossendorf, Dresden Germany
Show AbstractC5: Laser Annealing, Modeling, and USJ Metrology
Session Chairs
Bartek Pawlak
Paul Timans
Wednesday PM, April 19, 2006
Room 3000 (Moscone West)
2:30 PM - C5.1
Long Pulse Laser Thermal Processing: A Compromise in the Annealing Duration for Efficient, Damage-Free and Localized Hot Semiconductors Processes.
Julien Venturini 1
1 Laser Division, Sopra, Gennevilliers France
Show Abstract2:45 PM - C5.2
Electrical Characterization of Residual Implantation-Induced Defects in the Vicinity of Laser-Annealed Implanted Ultrashallow Junctions.
V. Gonda 1 , S. Liu 1 , T.L.M. Scholtes 1 , L.K. Nanver 1
1 DIMES-ECTM, Delft University of Technology, Delft Netherlands
Show Abstract3:00 PM - **C5.3
Ultra-shallow Junction Formation and Dopant Profile Engineering in CMOS Devices Formed by Non-melt Laser Spike Annealing.
Akio Shima 1 , Atsushi Hiraiwa 2 , Toshiyuki Mine 1 , Kazuyoshi Torii 1
1 Central Research Laboratory , Hitachi. Ltd., Kokubunji, , Tokyo, Japan, 2 Micro Device Devision, Hitachi, Ltd., Ome, Tokyo, Japan
Show Abstract With continual reductions in CMOS devices, ultra-shallow, abrupt, and low resistive junctions are playing an important role to suppress the short channel effect and obtain better device performance. However, the conventional rapid thermal annealing (RTA) can not meet the 65-nm-node requirements due to thermal diffusion and solid solubility limitation. To solve this problem, such technologies as flash lamp annealing (FLA) and laser annealing have been investigated. In visible and near IR wavelength range, thin film interference due to multiple reflections leads to large reflectance variations in different device structures. Non-uniform heating is inevitable in lamp illumination with continuous wavelength systems such as FLA and RTA. It degrades the reproducibility and causes wafer deformation or breakage. Problem becomes severer for ultra short time scale annealing because of insufficient heat diffusion. Laser annealing is not suffered from this problem and can provide uniform heating. We fabricated CMOSFETs by simply replacing RTA for source/drain(S/D) activation in the conventional production flow by non-melt laser spike annealing (LSA). When using the sub-millisecond annealing of LSA, the optimization of the overlap length between the gate and S/D extensions was important due to the minimal lateral diffusion. The LSA-devices without offset spacers had better performance, angled extension implantation gives better results in NMOS, and normal implantation does in PMOS. The CMOS devices thus formed had better Vth roll-offs and larger drain currents compared to those by RTA. Since the ultra low thermal budget of LSA keeps dopant profile almost the same as that of as-implanted and abrupt, engineering of profiles of halo and counter doping are also important to further enhance the device performance. In the case of LSA, the dopant concentration at silicidation edges is smaller than that of RTA and the contact resistance increases. Thus halo implantation with lower energy and smaller tilt angle is preferable. Counter doping depth should be adjusted in conjunction with halo profile to avoid increasing the well concentration at the junction edges and increasing the junction capacitance. The devices optimized in these points achieved 10%- and 20%-better performances compared to those by the LSA that had only the optimized gate-S/D extension overlap structure and RTA, respectively. The larger junction field in LSA-formed device causes severer hot carrier (HC) degradation. This problem can be solved by shifting the HC injection point to outside the gate oxide region by halo profile engineering leading to reduce the number of HC's that are injected into the gate oxide. In summary, we have shown that LSA is the most promising technique to fabricate ultra-shallow junction for the 65-nm-node and beyond, and dopant profiles engineering taking into account the minimal diffusion length of LSA is required to bring out the best device performances.
3:30 PM - **C5.4
Performance Improvement using Laser Annealing Technology in sub-40nm CMOS Devices.
Tomonari Yamamoto 1 , Tomohiro Kubo 2 , Takae Sukegawa 2 , Ken-ichi Okabe 2 , Lucia Feng 3 , Yun Wang 3 , Masataka Kase 2
1 DEVICE DEVELOPMENT DEPT., Fujitsu Ltd., Akiruno, Tokyo, Japan, 2 PROCESS DEVELOPMENT DEPT., Fujitsu Ltd., Akiruno, Tokyo, Japan, 3 , Ultratech Inc., San Jose, California, United States
Show Abstract4:30 PM - **C5.5
Physical Modeling of Defects, Dopant Activation and Diffusion in Aggressively Scaled Si, SiGe, and SOI Devices: Atomistic and Continuum Approaches.
Victor Moroz 1
1 , Synopsys, Inc, Mountain View, California, United States
Show AbstractThe upcoming technology nodes face a fundamental dilemma: while it is necessary to apply a substantial thermal budget to dissolve the extended defects induced by implant damage, such a thermal budget leads to unacceptably deep source/drain junctions. Only through the careful engineering of defects and stress can this dilemma be resolved. Some potential approaches include the use of co-implants such as germanium, carbon, nitrogen, and fluorine. The annealing technique itself will likely switch from the state-of-the-art spike anneal to a millisecond anneal or a combination of the two depending on specific implants and device design. Moving from bulk devices to FDSOI MOSFETs and FinFETs resolves most of these problems, but brings a set of new issues. Aggressively scaled bulk and SOI devices exhibit layout-sensitive dopant activation and defect dissolution due to the stress and proximity of Si/SiO2 interfaces. In this paper we review the use of advanced atomistic and continuum implant, diffusion, and defect ripening models to analyze the tradeoffs of different junction engineering approaches and to help optimize the process conditions for different device types. In addition to the nominal doping profiles we also investigate statistical variations introduced by the channel doping and source/drain doping and discuss possible approaches to reduce such variations.
5:00 PM - C5.6
Modeling and Experiments of Boron Diffusion during sub-millisecond Non-melt Laser Annealing in Silicon
Taiji Noda 1 2 , Susan Felch 3 , Vijay Parihar 3 , Christa Vrancken 4 , Tom Janssens 4 , Wilfried Vandervorst 4
1 , Matsushita Electric Industrial Co., Ltd., Leuven Belgium, 2 , Matsushita assignee at IMEC, Leuven Belgium, 3 , Appiled Materials, Sunnyvale, California, United States, 4 , IMEC, Leuven Belgium
Show Abstract Achievement of diffusion-less annealing is a challenging topic for sub-45nm technology node. For the formation of highly activated and ultra-shallow p-type junctions, there are two approaches, (1) low temperature SPER or (2) ultra-fast sub-millisecond annealing. F or C co-implantation with spike anneal is also a promising technology. In this work, modeling and experiments of non-melt Laser annealing are shown. An atomistic diffusion model for defect evolution during laser annealing is also presented. The wafers were implanted with Ge at energies of 5, 8, and 30 keV at a dose of 1×1015/cm2. Then boron was implanted at an energy of 0.5 keV, 1×1015/cm2. The depth of original amorphous/crystalline interface is determined by Ge PAI condition. Non-melt laser annealing was done at temperatures ranging from 1000 C to 1300 C. For the defect study, the influences of laser scan speed and combination annealing (for example, SPER + Laser, spike RTA + Laser) are also investigated. Anomalous boron diffusivity enhancement in amorphous-Si is observed. This enhanced boron diffusion in amorphous-Si increases as a function of amorphous layer depth. The sheet resistance as a function of Ge implant energy reveals that deep PAI produces the higher boron activation. In the case of deep PAI, boron atoms receive SPER for a longer time than shallow PAI. Therefore larger enhanced boron diffusion in amorphous-Si is observed in deep Ge PAI than shallow Ge PAI. The laser peak temperature affects defect evolution in end-of-range damage region and boron diffusion behavior. Boron diffusion behavior during non-melt laser annealing is shown in this paper. The residual defect distribution and boron diffusion/activation are influenced by the Ge PAI condition. These results indicate that the control of EOR defects is quite important, and a non-melt laser annealing technique with optimized Ge PAI is a promising candidate for sub-45nm CMOS technologies.
5:15 PM - C5.7
Accurate Sheet Resistance Measurement on Ultra-Shallow Profiles.
Trudo Clarysse 1 , Danielle Vanhaeren 1 , Alain Moussa 1 , Roger Loo 1 , Wilfried Vandervorst 1 , Vladimir Faifer 2 , Michael Current 2 , Robert Hillard 3 , Rong Lin 4
1 SPDT/MCA, IMEC, Leuven Belgium, 2 , Frontier Semiconductor, Inc., San Jose, California, United States, 3 , Solid State Measurements, Inc., Pittsburgh, Pennsylvania, United States, 4 , Capres A/S, Kongens Lyngby Denmark
Show Abstract5:30 PM - C5.8
Analysis and Optimisation of New Implantation and Activation Mechanisms in Ultra Shallow Junction Implants using Scanning Spreading Resistance Microscopy (SSRM).
Pierre Eyben 1 , Simone Severi 1 , Ray Duffy 2 , Bartek Pawlak 2 , Wilfried Vandervorst 1 3
1 SPDT/MCA, IMEC, Leuven Belgium, 2 , Philips Research Leuven, Leuven Belgium, 3 Electrical Engineering Dept., INSYS, K.U.Leuven, Leuven Belgium
Show Abstract5:45 PM - C5.9
Developing Local Electrode Atom Probe as a Method of Characterizing Semiconductors.
J.S. Moore 1 , K. S. Jones 1 , K. Thompson 2
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States, 2 , Imago Scientific Instruments Corporation, Madison, Wisconsin, United States
Show AbstractAs semiconductor devices and related structures continue to be scaled downward, so too must the characterization methods that are employed to evaluate them. Local Electron Atom Probe (LEAP), has recently been developed with the potential to create the desired 3D atomic maps. The LEAP point projection microscope uses a pulsed voltage or laser to analyze needle-shaped sample tips by utilizing time-of-flight mass spectrometry. Two methods, deep reactive ion etching (DRIE) and in-situ focused ion beam (FIB) liftout, were used to prepare LEAP samples from a CVD grown Si/SiGe superlattice. Once prepared, the samples were analyzed using pulsed laser LEAP and the results compared to TEM and SIMS analysis of the same samples. LEAP was able to resolve interface abruptness at a 4nm/decade resolution, superior to SIMS results for the same sample, and showed a drastic decrease in surface roughening effects. Differences between the two sample preparation methods, samples comprised of a Si/SiGe layered structure with variable levels of bulk-doped boron, and samples comprised of implanted phosphorus will also be discussed.