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2006 MRS Spring Meeting & Exhibit

April 17-21, 2006 | San Francisco
Meeting Chairs: J. Charles Barbour, Paul S. Drzaic, Gregg S. Higashi, Viola Vogel

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Symposium B : Silicon Carbide---Materials, Processing, and Devices

2006-04-18 Show All Abstracts

Symposium Organizers

Michael A. Capano Purdue University

Michael Dudley State University of New York-Stony Brook

Tsunenobu Kimoto Kyoto University-Katsura

Adrian R. Powell Cree Inc.

Shaoping Wang Fairfield Crystal Technology

B1: Bulk Growth I

Session Chairs

Adrian Powell

Tuesday PM, April 18, 2006

Room 3004 (Moscone West)

9:15 AM - **B1.1

Recent Progress in the Growth and Polishing of 75mm and 100 mm SiC Substrates for RF and High Power Electronic Applications.

T. Anderson ¹, J. Chen ¹, E. Emorhokpor ¹, A. Gupta ¹, C. Martin ¹, P. Wu ¹, M. Yoganathan ¹, Andrew Souzis ¹, I. Zwieback ¹
¹, II-VI Incorporated, Pine Brook, New Jersey, United States

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9:45 AM - B1.2

Effect of Radiation in Solid during SiC Sublimation Growth.

Shin-ichi Nishizawa ¹, Shin-ichi Nakashima ¹, Tomohisa Kato ¹
¹, National Institute of Advanced Industrial Science and Technology, Tsukuba Japan

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Sublimation is the most commonly used technique to grow SiC bulk single crystal. In this technique, source powder and seed crystal are set inside a closed carbon crucible, and heated up over 2000 K. It is well-known that radiation heat transfer is very important under such high temperature condition. So, the radiation heat transfer in gas phase is usually considered in the modeling of SiC sublimation. However, Silicon carbide single crystal is semi-transparent. In this case, radiation heat transfer not only in gas phases but also in a growing crystal might be very important. From this point of view, the effect of infrared absorption on temperature field during SiC sublimation growth was numerically investigated. There is few report on infrared absorption coefficient of SiC single crystal. In this study, the infrared absorption coefficient was estimated by following way. At first, the dielectric function ε(ω) was considered with a concentration of free electrons. This leads that ε(ω) depends on the doping concentration and wave length. From ε(ω), the optical index of reflection and the extinction coefficient were calculated. Then, the absorption coefficient of SiC single crystal was estimated from these coefficients with functions of doping concentration and wave length. With taking account of estimated absorption coefficient, the heat transfer inside a furnace was numerically analyzed with commercially available software (CFD-ACE+). Radiation heat transfer was analyzed by the Discrete Ordinates Method. In order to make clear the effect of absorption in solid, simple cylindrical crucible design was used in this study. The numerical simulation was carried out with varying the doping concentration, and also grown crystal length. At the initial stage with thin seed crystal, the temperature distribution inside a crucible was not affected by the radiation in solid. After the crystal growth, however, the temperature distribution inside a growing crystal strongly depended on the absorption coefficient. Under the same growth conditions (ex., same induction current, or same observed temperature), as increasing the absorption coefficient, the temperature gradient along the growing-axis at the growing surface increased. This is because the infrared radiation was absorbed near the surface with large absorption coefficient. This means that temperature distribution and also thermal stress inside a growing crystal strongly depend on the doping concentration. In other words, the growth condition should be determined with taking account of doping concentration.

10:00 AM - B1.3

High Carrier Lifetime Bulk-Grown 4H-SiC Substrates for Power Applications.

David Malta ¹, Jason Jenny ¹, Valeri Tsvetkov ¹, Mrinal Das ¹, Don Hobgood ¹, Calvin Carter ¹
¹, Cree, Inc., Durham, North Carolina, United States

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10:15 AM - B1.4

Growth and Characterization of Nitrogen Doped 4H SiC Boules by Halide Chemical Vapor Deposition.

Mark Fanton ¹, Alexander Polyakov ², Sung Wook Huh ², Paul Klein ³, Marek Skowronski ², David Snyder ¹, Brian Weiland ¹
¹Electro-Optics Center, Penn State University, Freeport, Pennsylvania, United States, ²Materials Science & Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States, ³, Naval Research Laboratory, Washington, District of Columbia, United States

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10:30 AM - **B1.5

Investigation Of Dislocation Behavior During Bulk Crystal Growth Of SiC.

Noboru Ohtani ¹, M Katsuno ¹, H Tsuge ¹, M Nakabayashi ¹, T Fujimoto ¹, H Yashiro ¹, M Sawamura ¹, T Aigo ¹, T Hoshino ¹
¹Advanced Technology Research Laboratories, Nippon Steel Corporation, Chiba Japan

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11:00 AM - B1: Bulk I

BREAK

B2: Epitaxial Growth I

Session Chairs

M. Dudley

Tuesday PM, April 18, 2006

Room 3004 (Moscone West)

11:30 AM - B2.1

High Growth Rate Process in a SiC Horizontal Reactor with the Addition of HCl: Structural and Electrical Characterization.

Francesco La Via ¹, Giuseppa Galvagno ¹, Andrea Firrincieli ¹, Salvatore Di Franco ¹, Andrea Severino ¹, Marco Mauceri ³, Stefano Leone ³, Giuseppe Abbondanza ³, Ferdinando Portuese ³, Lucia Calcagno ², Gaetano Foti ²
¹, CNR-IMM, Catania Italy, ³, Epitaxial Technology Center, Catania Italy, ²Physics Department, Catania University, Catania Italy

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A new process that overcomes the limitation of the low growth rate, typical of the silicon carbide epitaxy, will be presented in this work. The introduction of HCl avoid the homogeneous nucleation in the gas phase of silicon precipitate and gives the possibility of increasing the Si/H₂ ratio to 0.6% with a consequent increase of the growth rate up to 112 μm/h. In this work, we have characterized the epitaxial layers grown with the addition of HCl by electrical, optical and structural analyses. A comparison with an optimized process without the addition of HCl is reported too. The epitaxial layers were optimized, in a first step, by optical microscopy, low temperature photoluminescence, KOH etch, atomic force microscopy, and transmission electron microscopy in plan view. The effects of the deposition parameters on the surface roughness and the defects density have been studied in detail. From this preliminary study it has been observed that, increasing the Si/H₂ ratio, it is necessary to increase the deposition temperature and to decrease the C/Si ratio. Then, several Schottky diodes with different contact areas have been realized with boron implanted edge termination and using a nickel silicide (Ni₂Si) as Schottky barrier, on these optimized epitaxial layers. These diodes were characterized by current-voltage (I-V) and capacitance-voltage (C-V) maps of the entire wafer to obtain statistical information, over more than 400 diodes, of the spatial distribution of defects and doping uniformity. The effect of several deposition parameters (Si/H₂ ratio, Cl/Si ratio, Si/C ratio and deposition temperature) on the electrical characteristics of Schottky diodes has been studied too. From this study an optimized process has been obtained that gives Schottky diodes electrical characteristics comparable with the standard epitaxial process with the great advantage of an epitaxial growth rate a factor fourteen higher. This high growth rate gives the possibility to grow very thick layers (about 100 μm) with a good quality and at low cost. These thick layers are needed for power devices with breakdown voltage of about 10 KV.

11:45 AM - B2.2

Growth Rate, Morphology Control, and Dopant Incorporation in Low-temperature Epitaxial Growth of 4H-SiC Using CH₃Cl Growth Precursor.

Yaroslav Koshka ¹, Huang-De Lin ¹
¹, Mississippi State University, Mississippi State, Mississippi, United States

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In our previous work, a possibility of good-quality homoepitaxial growth of 4H-SiC at temperatures below 1300⁰C was demonstrated. In this paper, the mechanism of the growth at reduced temperatures using halo-carbon growth precursor chloromethane is further investigated. The trend of the growth rate saturation at high flow rates of the silicon growth precursor is explained using the model of silicon vapor condensation. A possibility to suppress silicon condensation and increase evaporation/etching of silicon clusters in order to increase the growth rate is explored. Strong dependence of the growth morphology on the Si/C ratio is established. It is demonstrated that identification of the window of Si/C ratio favorable for good epilayer morphology is critical for achieving higher growth rates without facing the morphology degradation. It should be noted, however, that the effective Si/C ratio above the growth surface may be very different from the input ratio, with the difference drastically increased when the epitaxial growth is conducted at low temperatures. The higher difference at lower temperatures can be explained by gas phase reactions taking place farther from thermodynamic equilibrium than at higher temperatures. No less important factor is the depletion of the silicon growth precursor due to silicon vapor condensation, which can significantly reduce the magnitude of the effective Si/C ratio.The temperature dependence of the growth rate is used to extract the activation energy of the growth process and identify the factors limiting the growth rate. Comparison of the activation energy of the growth rate with that of the fitting parameter of the growth rate dependence on silane flow allowed one to identify mechanisms determining the growth rate and its dependence on precursor flows and temperature.A pronounced dependence of dopant incorporation on the growth temperature was observed during the low-temperature epitaxial growth. Almost an order of magnitude variation in the net donor concentration was caused by less than 50⁰C variation in the temperature at the growth surface. Unless the temperature distribution inside the susceptor is carefully optimized, the identified trends may result in significant doping non-homogeneity across the wafer surface. On the other hand, strong sensitivity of impurity incorporation to the growth temperature provides additional control over the epilayer doping and a possibility to vary doping in a wide range.

12:00 PM - **B2.3

Growth of Crystalline Silicon Carbide by CVD Using Chlorosilane Gases

Mark Loboda ¹, M. MacMillan ¹, J. Wan ¹, G. Chung ¹, E. Carlson ¹, Y. Makarov ², A. Galyukov ², M. Molnar ³
¹, Dow Corning Corporation, Midland, Michigan, United States, ², Semiconductor Technology Research, Inc., Richmond, Virginia, United States, ³, Hemlock Semiconductor Corporation, Hemlock, Michigan, United States

Show Abstract

Chemical vapor deposition (CVD) processes for silicon carbide epitaxy in semiconductor applications have traditionally implemented processes based on monosilane (SiH4) and bydrocarbon (CxHy) chemistry. This trend is interesting as it is in contrast to chlorosilane (H[4-x]SiClx) chemistry established in mass production processes in silicon epitaxy [1] and also high temperature CVD processes for high reliability/purity SiC coating on monolithic graphite which use organochlorosilane ((CH3)ySiClx) chemistry.Recently, research in the epitaxial growth of SiC has started to study processes which include incorporation of chlorine containing precursors (e.g. HCl, MeCl) [2,3]. Semiconductor grade chlorosilane precursors have properties that are very suitable for use in the SiC epitaxy at high temperatures (1100 C≦T≦2500 C). A particularly desirable feature is that compared to SiH4, chlorosilanes have a reduced tendency towards homogeneous reactions in the gas phase which can result in defects in the deposited epilayer material [1]. Reduced homogeneous reaction tendency can extend the process space to allow adjustment other process parameters such as to increase SiC growth rates and/or improve material quality. This paper will review the basic chemistry of the reactions of several known approaches employed to grow SiC from chlorine containing gas mixtures by CVD. At Dow Corning, chlorosilane-based chemistries have been successfully implemented to deposit high quality (thickness variations <2%, background doping <1E14/cm3, contact layer doping >1E20/cm3) SiC epilayers in both R&D and production epitaxy equipment [4]. To further industry insight on the evolution of Cl-based SiC growth approaches, experimental and modeling results from efforts on chlorosilane SiC growth at the Dow Corning Compound Semiconductor laboratory will be presented and include growth kinetics, n and p type doping trends, carrier lifetime and defect evolution. References[1] Wolf, S., and Tauber, R., Silicon Processing for the VLSI Era; Vol. 1, Lattice Press, 1986[2] Myers, R., Kordina, O., Sishkin, Z., Rao, S., Everly, R., Saddow, S.D., Mat. Sci. Forum Vols. 483-485 (2005),p.73-6[3] Koshka, Y., Lin, H., Melnychuk, G., Mazzola, M., Wyatt, J., Mat. Sci. Forum Vols. 483-485 (2005),p.81-84[4] MacMillan, M., Loboda , M.J.; Chung, G., Carlson, E.; Wan, J. to be published in Silicon Carbide and Related Materials 2005, Trans Tech Publications 2006.

12:30 PM - B2.4

Epitaxial Growth of 4H-SiC with Ge-incorporated 4H-SiC Buffer Layer.

Akinori Seki ¹, Akira Manabe ¹, Yukari Ishikawa ², Noriyoshi Shibata ²
¹Higashifuji Technical Center, Toyota Motor Corporation, Susono, Shizuoka, Japan, ²R & D , Japan Fine Ceramics Center, Nagoya, Aichi, Japan

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12:45 PM - B2.5

HCl Induced 4H-SiC Growth Rate Increases and Morphology Issues in a Vertical Cold Wall Reactor

Chris Thomas ¹, MVS Chandrashekhar ¹, Yuri Makarov ², Michael Spencer ¹
¹Electrical and Computer Engineering, Cornell University, Ithaca, New York, United States, ², Widetronix, Inc, Ithaca, New York, United States

Show Abstract

B3: Dislocations in Epitaxy

Session Chairs

S. Nishizawa

Tuesday PM, April 18, 2006

Room 3004 (Moscone West)

2:30 PM - B3.1

Growth of Low Basal Plane Density SiC Epilayers with Minimized Surface Depressions.

Zehong Zhang ¹, Tangali Sudarshan ¹
¹, Univ. of South Carolina, Columbia, South Carolina, United States

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2:45 PM - B3.2

Decrease in the Defect Density of Homoepitaxial Film by Surface Pretreatment of 4H-SiC Substrate.

Yukari Ishikawa ¹, Noriyoshi Shibata ¹, Akinori Seki ², Akira Manabe ²
¹R &D , Japan Fine Ceramics Center, Nagoya, Aichi, Japan, ²Higashifuji Technical Center, Toyota Motor Co., Susono, Shizuoka, Japan

Show Abstract

3:00 PM - B3.3

Non-Destructive Electro- and Photo-Luminescence Imaging of Dislocations in SiC Epitaxy.

Kendrick Liu ¹, Robert Stahlbush ¹, Karl Hobart ¹, Joseph Sumakeris ², F. J. Kub ¹
¹, Naval Research Laboratory, Washington, District of Columbia, United States, ², Cree, Inc, Durham, North Carolina, United States

Show Abstract

The development of bipolar SiC power devices is currently hampered by the capability to grow high quality epilayers containing low basal plane dislocations (BPDs). Non-destructive characterization techniques are needed to assist in developing and monitoring low-defect epitaxial growth processes. Electroluminescence (EL) imaging in the forward bias requiring little post-growth processing has been used successfully to examine BPDs in thick n- epitaxy drift layers [1]. Aluminum deposited at room temperature and lithographically patterned provides contact to a p+ anode layer. Because the Al layer is un-sintered, it causes minimal damage to the SiC surface and can be removed before devices on the wafer are fabricated. However, EL imaging requires the epi-growth of the anode layer, which may be undesirable in some cases. Photoluminescence (PL) imaging is a non-contact technique that does not require electrical biasing. Therefore, for PL imaging, the p+ anode layer is optional. PL mapping techniques have been previously demonstrated to reveal structural defects in SiC epitaxy layers using a UV-Ar+ laser excitation source [2-5]. We present and compare non-destructive EL and PL imaging techniques. Various epitaxy drift layers were examined with and without a p+ anode layer. For samples with the anode layer, a gridded Al metal film was deposited. Open areas in the grid allowed for imaging of the dislocation luminescence using a liquid nitrogen cooled CCD camera attached to a probe station. Electrical current is isolated by using guard rings patterned in the Al layer. For the PL imaging, a compact and portable UV-LED excitation source (365nm central wavelength and 10nm spectral half width) was used. The final lens-tube assembly of the UV-LED was only about 9 inches in length and a few ounces in weight. PL imaging was performed on both epilayers with and without an anode layer. Comparisons of the PL and EL images of Al patterned samples showed that the dislocation luminescence corresponded quite well with the EL technique revealing better dislocation-background contrast. In summary, we have reported non-destructive EL and PL imaging techniques to examine dislocations in n- epitaxy drift layers. For the EL technique, a simple Al pattern was used to forward bias the samples having an anode layer on top of a drift layer. For the PL technique, a low-cost, compact and portable UV-LED source was used. The PL technique can be totally non-contact. We have also shown that the PL technique correlated well with the EL technique. However, unlike the EL technique, the PL technique does not require an anode layer for the metal contact.[1] K. X. Liu, et al., Proceedings of the International Conference on Silicon Carbide and Related Materials, Pittsburgh, September 18-23, 2005.[2] M. Tajima, et al., Ibid.[3] T. Miyanagi, et al., Ibid.[4] I. Kamata, et al., Ibid.[5] J. M. Bluet, et al., Materials Science and Engineering, vol. B102, p. 277, 2003.

3:15 PM - B3.4

Prismatic Faults In 4H-Sic Pin Diodes.

Mark Twigg ¹, Nabil Bassim ¹, Robert Stahlbush ¹, Paul Losee ², Canhua Lee ², Ishwara Bhat ², T. Chow ²
¹Electronics Science and Technology Division, Naval Research Laboratory, Washington, District of Columbia, United States, ²Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States

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3:30 PM - B3.5

Electrical and Lifetime Characterization of In-Grown Stacking Faults in 4H-SiC

Joshua Caldwell ¹, Paul Klein ¹, Robert Stahlbush ¹, Orest Glembocki ¹, Karl Hobart ¹, Fritz Kub ¹
¹Power Electronics, Naval Research Lab, Washington , District of Columbia, United States

Show Abstract

In-grown stacking faults (IGSFs) within 4H-SiC epilayers and diodes have recently come under increased scrutiny. Three different types have been identified a triple SF,¹ the carrot defect² and an 8H-SiC planar inclusion.^3,4 However, electrical characterization has been limited to forward IV⁴ and Ballistic Electron Emission Microscopy.⁵We present optical beam induced current (OBIC) imaging of two types of IGSFs showing these defects may act as either a shunt allowing current leakage or as a semi-insulating region. OBIC provides non-destructive, spatial characterization of the electrical activity of defects within devices, giving images of dominant leakage paths. Here, in the absence of an applied bias, these two IGSFs appeared as triangular areas of either bright (high current) or dark (low current) contrast, respectively. Reverse IV measurements support the OBIC observations, as the leakage current in the diodes with high current IGSFs was significantly higher than in diodes from the same wafer without IGSFs. This effect was most dramatic at low voltage. OBIC, under increasing reverse bias, showed these IGSFs to diminish in intensity in comparison to the surrounding diode. This indicates that while these defects act as leakage paths, the current capacity relegates the effect to low biases only. At no point did the dark IGSFs contribute to the leakage.Electroluminescence (EL) measurements of the IGSFs were similar, with a bright luminescence line at the surface with a dark triangular area extending below. Electrical stressing did not affect the IGSFs. However, the EL from the low current IGSF under 50X magnification appeared to be made of at least two lines, as opposed to the single line observed for the high current IGSFs. Carrier lifetimes were measured via the decay of the 391nm bandedge PL. The lifetimes did not appear to be dramatically affected by the IGSFs, as the decays, measured within and outside the faulted regions were similar. Because in OBIC the light absorption determines the carrier injection, it is sensitive to the band gap of the absorbing material. The presence of a larger OBIC current in the defect and carrier lifetimes similar to the surrounding region suggests the defect may be composed of a lower band gap polytype, such as 3C, 6H or 8H. Samples provided by Cree, Inc.; ONR contract N00014-02-C-0302, monitored by Dr. H. Dietrich.¹ M. E. Twigg, R. E. Stahlbush, P. A. Losee, et al., presented at ICSCRM, (Pittsburgh, PA, 2005).² M. Benamara, X. Zhang, M. Skowronski, et al., Applied Physics Letters 86, 021905 (2005).³ S. Izumi, H. Tsuchida, I. Kamata, et al., Applied Physics Letters 86, 202108 (2005).⁴ H. Fujiwara, T. Kimoto, T. Tojo, et al., Applied Physics Letters 87, 051912 (2005).⁵ K.-B. Park, Y. Ding, J. P. Pelz, et al., presented at ICSCRM, (Pittsburgh, PA, 2005).

3:45 PM - **B3.6

Do You Really Expect To Grow Epilayers On That? A Rationale For Growing Epilayers On Roughened Surfaces.

Joseph Sumakeris ¹, Brett Hull ¹, Michael O'Loughlin ¹, S. Ha ², Marek Skowronski ², John Palmour ¹, Calvin Carter, Jr. ¹
¹, Cree, Inc, Durham, North Carolina, United States, ², Carnegie Mellon University, Pittsburgh, Pennsylvania, United States

Show Abstract

4:15 PM - B3: Epi Disloc

BREAK

B4: Bulk Growth II

Session Chairs

S. Wang

Tuesday PM, April 18, 2006

Room 3004 (Moscone West)

4:30 PM - B4.1

Electrical Properties of Undoped 4H-SiC Crystals Grown by Halide Chemical Vapor Deposition.

H.J. Chung ¹, S. Nigam ¹, S.W. Huh ¹, A.Y. Polyakov ¹, M. Skowronski ¹, E.R. Glaser ², J.A. Freitas,Jr. ², M.A. Fanton ³
¹Materials Science and Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States, ², Naval Research Laboratory, Washington, District of Columbia, United States, ³, Penn State University Electro-Optics Center, Freeport, Pennsylvania, United States

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4:45 PM - **B4.2

Silicon Carbide Growth: Evaluation and Modeling.

Michel Pons ¹, Peter Wellmann ², Schin-Ichi Nishizawa ³, Elisabeth Blanquet ¹, Jean-Marc Dedulle ¹, Didier Chaussende ¹
¹LTPCM, INPGrenoble, Saint Martin D'Heres France, ²Material Science, University of Erlangen, Erlangen Germany, ³, AIST, Tsukuba Japan

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5:15 PM - B4.3

Lifetime Killer Defect in Undoped 6H-SiC Bulk Crystals Grown by Halide Chemical Vapor Deposition.

Saurav Nigam ¹, Sung Huh ¹, Hun Chung ¹, Alexander Polyakov ¹, Marek Skowronski ¹
¹Department of Materials Science and Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States

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5:30 PM - B4.4

Effects of Annealing on Deep Centers in HCVD-grown n-type 6H-SiC.

S.W. Huh ¹, H.J. Chung ¹, S. Nigam ¹, A. Polyakov ¹, M. Skowronski ¹, E. Glaser ², N. Garces ², W. Carlos ²
¹MSE, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States, ², Naval Research Laboratory, Washington, D.C., District of Columbia, United States

Show Abstract

Annealing experiments were performed on HCVD (Halide Chemical Vapor Deposition)-grown bulk n-type 6H-SiC. The annealing was done at 1600oC for 30 minutes to investigate the stability of deep centers. DLTS (Deep Level Transient Spectroscopy) measurements before and after annealing showed an increase in concentration of the 1.0 eV electron trap by almost one order of magnitude after annealing and a slight decrease in the concentration of 0.65 eV electron trap (Z1/Z2). The concentration of other electron traps did not show any change after annealing. Hole traps in the sample were measured by MCTS (Minority Carrier Transient Spectroscopy) before and after annealing, but there was virtually no change observed in hole traps concentration after annealing.PICTS (Photo-induced Current Transient Spectroscopy) measurements on a high resistive sample also showed the increase in the concentration of the 1.0 eV electron trap after annealing. In agreement with this, the activation energy determined by Temperature-dependent Hall effect measurement on the highly resistive sample changed from 0.65 eV from valence band before annealing to 1.0 eV from conduction band after annealing. LTPL (Low Temperature Photoluminescence) from 0.7-3.1 eV and EPR (Electron Paramagnetic Resonance) at 9 GHz were also performed on the same samples to look for changes in the concentrations of various deep centers (such as the carbon vacancy and the defects responsible for the so-called UD1 and D1 PL bands), after the high temperature anneal. For example, EPR on a highly resistive sample before and after the high temperature anneal showed a marked decrease in the concentration of carbon vacancies, Vc, as observed earlier by others1. Also, the concentration of the defect commonly referred to as SI-5 (in a recent report2, Son et. al., have unambiguously identified this defect as the carbon vacancy-carbon antisite pair defect, VC- CSi, ), was monitored with EPR before and after the anneal. The paramagnetic state of this signal was attained by illumination of the samples at temperatures close to 80 K with near bandedge light from a xenon lamp. We found very little change (within factors of 2) in the total integrated area, i.e., concentration of the SI-5 EPR signal. Possible correlations with the traps observed in the DLTS measurements will also be discussed.The work at NRL was supported by the Office of Naval Research.1 see, for example, D. Alvarez et. al., Journal of Electronic Materials, Vol. 32, No. 5, 2003.2 N.T. Son et. al., 2005 International Conference on Defects in Semiconductors, Materials Science Forum, in press.

B5: Poster Session: SiC Materials Posters

Session Chairs

J. Sumakeris

Wednesday AM, April 19, 2006

Salons 8-15 (Marriott)

9:00 PM - B5.1

The Formation of Smooth, Defect-free, Stoichiometric Silicon Carbide Films from a Polymeric Precursor.

Michael Pitcher ¹, Patricia Bianconi ²
¹Chemistry, METU, Ankara Turkey, ²Chemistry, University of Massachusetts at Amherst, Amherst, Massachusetts, United States

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9:00 PM - B5.10

Preparation of Al₂O₃ Thin Films on SiC by Metal Organic Chemical Vapor Deposition.

Tomohiro Hatayama ¹, Shiro Hino ¹, Shiho Hagiwara ¹, Eisuke Tokumitsu ¹
¹, Tokyo Institute of Technology, Yokohama Japan

Show Abstract

Silicon carbide (SiC) is promising for next generation power device applications because it's outstanding properties such as high breakdown voltage, high electron mobility and thermal conductivity. Although many groups have challenged to develop SiC metal-oxide-semiconductor field-effect-transistors (MOSFETs), there is still an obstacle to the practical use. The main problem in SiC MOSFETs is poor interface properties of thermally grown SiO₂/SiC, which result in low channel mobility and large on-resistance of SiC MOSFETs. One of the alternative ways to obtain good interface quality is deposition of the gate-insulator films without oxidizing the SiC substrates during the deposition process. To suppress the oxidation of the SiC substrates, low deposition temperature of the gate-insulator films is desirable.In this work, we have deposited Al₂O₃ gate insulator on 4H-SiC (0001) and HF-etched Si (100) by metal organic chemical vapor deposition (MOCVD). We chose Al₂O₃ as a gate-insulator material, because Al precursors used in MOCVD easily react with oxidants, which enables us to deposit Al₂O₃ films with low-defect density even at low temperatures. In addition, a large conduction band discontinuity (ΔE_C) is expected for Al₂O₃/SiC. In this work, Al₂O₃ films were deposited by source-gas-pulse-introduced MOCVD using Al(C₂H₅)₃ (TEA) and H₂O. The deposition temperature is 190 ^oC to suppress the oxidation of the SiC substrates. The top electrodes of the MOS capacitors were fabricated by vacuum evaporation of Al through a shadow mask. Ni was used for the backside electrodes, which was sintered at 850 ^oC for 3 min in N₂ ambient, before the deposition of Al₂O₃ films on SiC. Al₂O₃ thickness was between 15 and 20 nm.We evaluated the capacitance-voltage (C-V) and leak current density versus electric field (J-E) characteristics of the Al₂O₃/SiC MOS capacitors and calculated interface state density (D_it) with high-low C-V measurement. The C-V curve of the Al₂O₃/SiC exhibits typical MOS characteristics. However, we have observed large flat-band shift of about 7V for the Al₂O₃ deposited at 190 ^oC, which is presumably due to the fixed charge at the interface. The breakdown electric field of Al₂O₃ was around 7MV/cm and the leakage current density is in the order of 10^-8 A/cm², which is much smaller than the HfO₂ films deposited at the same temperature. It is worth noting that the D_it of the Al₂O₃/SiC was estimated to be 10¹² eV^-1cm^-2, which is lower than that of the thermally grown SiO₂/SiC.

9:00 PM - B5.11

High-Resolution X-ray Topography of Dislocations in 4H-SiC Epilayers

Isaho Kamata ¹, Hidekazu Tsuchida ¹, William Vetter ², Michael Dudley ²
¹, Central research institute of electric power industry, Yokosuka, Kanagawa, Japan, ², State university of New York, Stony Brook, New York, United States

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Silicon carbide (SiC) substrates and epilayers contain many crystal defects, such as micropipes, screw dislocations, threading edge dislocations (TEDs), basal plane dislocations (BPDs) and stacking faults. To investigate these defects, synchrotron radiation topography is frequently carried out. When the monochromatic synchrotron X-ray topography is taken by the grazing-incidence reflection geometry using 11-28 reflection, screw dislocations, TEDs and BPDs are simultaneously seen and shown as different topographic images [1]. Many studies of dislocations were reported using 11-28 reflections in 4H-SiC [1,2]. Topographic images of the dislocations have been analyzed by the ray-tracing method of computer simulation [3]. However, experimental images of dislocations were not fully matched to the fine structure of simulation images, because of a lack of resolution in recording media: conventional films and nuclear emulsion plates [3]. This time, we report obtaining high-resolution topographic images using a new recording medium, and compare results between the experiment and the computer simulation. Synchrotron topography in 11-28 reflection was carried out at SPring8 applying holography films as high-resolution recording media. The TED images are distinguished as four types, which have ribbon-like features with different rotating angles, through the use of the films. The four different TED images agree well with the computer simulated images which have been reported by Vetter et.al. taking into account of the different Burgers vector directions [3]. By comparing the three topographic images taken at g=-12-18, 11-28 and 2-1-18, we confirmed experimentally that the four types of TED images originated from the difference of Burgers vector directions. We also investigated high-resolution topographic images of elementary screw dislocations, micropipes, and BPDs in 4H-SiC epilayers. The experimental image of screw dislocation fairly matched with simulated image. The fine features in the experimental topographic images of micropipes and BPDs are also compared with the simulated images in detail. [1] T. Ohno, H. Yamaguchi, S. Kuroda, K. Kojima, T. Suzuki, K. Arai: J. cryst. Growth. Vol. 260 (2004) 209. [2] H. Tsuchida, T. Miyanagi, I. Kamata, T. Nakamura, R. Ishii, K. Nakayama and Y.Sugawara: Jpn. J. Appl. Phys. Vol. 25, (2005), L806-808. [3] W. Vetter, H. Tsuchida, I. Kamata, M. Dudley: J. Appl. Cryst. Vol. 38, (2005), 442-447.

9:00 PM - B5.12

Perchlorosilanes and Perchlorocarbosilanes as Precursors to Silicon Carbide.

Roman Pavelko ¹, Vladimir Sevastyanov ¹, Yurij Ezhov ¹, Nikolaj Kuznetsov ¹
¹, Kurnakov Institute of General and Inorganic Chemistryof Russian Academy of Sciences, Moscow Russian Federation

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9:00 PM - B5.13

Measurement of the Electon-hole Pair Ionization Energy in a 4H SiC Betavoltaic cell.

MVS Chandrashekhar ¹, Christopher Thomas ¹, Michael Spencer ¹
¹Electrical Computer Engineering, Cornell University, Ithaca, New York, United States

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9:00 PM - B5.14

Effects of Hydrogen on the Physical Vapor Transport Growth and Properties of Nitrogen Doped 4H SiC

Mark Fanton ¹, Alexander Polyakov ², Sung Wook Huh ², Marek Skowronski ², Randal Cavalero ¹, Rodney Ray ¹
¹Electro-Optics Center, Penn State University, Freeport, Pennsylvania, United States, ²Materials Science & Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States

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9:00 PM - B5.15

Deep Traps Spectra in n-type and p-type 4H-SiC Films Grown by Chlorosilane Epitaxy.

S.W. Huh ¹, S. Nigam ¹, A. Polyakov ¹, M. Skowronski ¹, G. Chung ², M. MacMillan ², J. Wan ², M. Laboda ²
¹MSE, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States, ², Dow Corning Compound Semiconductor Solutions, Midland, Michigan, United States

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9:00 PM - B5.17

Toward Particulate-Free Thin Films of SiC and TiC by Plasma Discharge Assisted Pulsed Laser Deposition.

Robert Combs ¹, Xiaodong Zhang ¹, Brent Koplitz ¹
¹Chemistry, Tulane University, New Orleans, Louisiana, United States

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The thin film characterization and plasma diagnostics of laser ablated plumes of SiC and TiC using both femtosecond (exp-15 s, fs) and nanosecond (exp-9 s, ns) laser pulse durations are investigated. The purpose of this work is to determine the role of the laser pulse interaction with the ablated vapor, as this serves as an important factor in the deposition of particulate-free films. Since the vaporization event takes place in the picosecond (exp-12 s) timescale, the ns pulses heat the expanding vapor through the duration of the pulse, whereas the high energy fs pulses are completed before any interaction with the vapor is possible. Thus, it is necessary to determine whether continued heating of the plasma is critical for a more complete vaporization or if an initial high energy interaction is more important. From film analysis, it is clear that the interactions are very different with respect to the thickness of the films and size distribution of deposited particulates. The general trend indicates that fs pulses produce a high number of particulates ca. 1 µm average diameter, with the majority of the film comprised of particles < 200 nm. However, in the case of the ns films, there were much fewer 1 µm particles and the major film components were << 200 nm. Therefore, the longer pulses heat the plasma during the expansion and enhance film quality. By incorporating high repetition rates, the ablation plume has a number density capable of facilitating a discharge at high electric field strength (1500 V/cm) between two parallel plates. This provides enough energy to digest most of the particulates to be deposited. Without electric fields, the observed trend is an increase in particulates deposited due to the increase of ablated material. At sufficiently high field strength, the reverse is observed, the number of particulates decreases as laser repetition rate is increased. The films vary in thickness according to measurement relative to the ablation cone. For example, using fs pulses (0.5 mJ/pulse, 1 kHz), film thickness measurements provide a minimum of 84 nm (3 cm from ablation axis) and a maximum of 286 nm (0.5 cm from ablation axis). However, with electric fields present, the minimum thickness was 58 nm and a maximum thickness of 101 nm. Therefore, a more uniform film was deposited by creating a discharge across the plume.Plasma characterization was performed with quadrupole mass spectrometry and with ion probes. Mass spectra were acquired along the ablation axis. Charge accumulation measurements were made with a cylindrical (0.25 mm diameter, 1 cm long) probe oriented 5 cm from the ablation source. These studies lend themselves to the production of particulate-free thin films of hard materials for use in tribological applications.

9:00 PM - B5.18

Passivation of Dangling Bonds at Hexagonal SiC Surfaces.

Gary Pennington ¹, C Ashman ², N Goldsman ¹, P Lenahan ³, A Lelis ⁴
¹, University of Maryland, College Park, Maryland, United States, ², HPTi, Reston, Virginia, United States, ³, Penn State University, University Park, Pennsylvania, United States, ⁴, Army Research Lab, Adelphi, Maryland, United States

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9:00 PM - B5.19

Halide Chemical Vapor Deposition of Thick AlN Films on SiC.

Timothy Bogart ¹, Mark Fanton ¹, Xiaojun Weng ², Ed Oslosky ¹, Brian Weiland ¹, Rodney Ray ¹, Adam Dilts ¹, David Snyder ¹
¹, Penn State Electro-Optics Center, Freeport, Pennsylvania, United States, ²Materials Science & Engineering, Pennsylvania State University, University Park, Pennsylvania, United States

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9:00 PM - B5.2

Surface Dynamics in Alloys Growth: Simulation of the Effect of Multi-species Deposition on Unstable Vicinal Surfaces.

Ajmi BHadj-Hamouda ¹, Alberto Pimpinelli ¹, Florin Nita ^{2 3}
¹LASMEA, Universite Blaise Pasca l, 6602 du CNRS, 63177, AUBIERE France, ² Institute of physical chemistry, IG Murgulescu" of Romanian Academy, Spl. Independentei 202, Bucharest Romania, ³Dipartimento di Fisica, INFM and IMEM/CNR, Via Dodecaneso 33, Genova, I1614 Italy

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9:00 PM - B5.20

Characterization of SiC Materials and Devices by SIMS

Yupu Li ¹, Yumin Gao ¹
¹, Applied Microanalysis Labs, Santa Clara, California, United States

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9:00 PM - B5.21

Defects in 4H-SiC MOSFETs: Processing Dependent Defect Densities

Morgen Dautrich ¹, Patrick Lenahan ¹, Aivars Lelis ²
¹, Penn State University, University Park, Pennsylvania, United States, ², Army Research Labs, Adelphi, Maryland, United States

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A major problem faced in SiC metal oxide semiconductor field-effect transistor (MOSFET) technology is the existence of interface trap defects at the SiC/gate oxide interface. The large concentration of interface trap defects leads to shifts in threshold voltage and low channel mobility. Until recently, virtually nothing was known with certainty about the atomic scale structure of the defects responsible for these interface traps. Electron spin resonance (ESR) has been widely utilized to study electrically active defects in electronic materials. The electrically detected ESR technique called spin dependent recombination allows ESR measurements to e made in fully processed semiconductor devices, as it is many orders of magnitude more sensitive than conventional ESR, and is exceptionally well suited to characterize interface defects in fully-processed semiconductor devices.In several earlier studies, we have reported on SDR studies of both 4H and 6H-SiC MOSFETs with both thermally grown and deposited oxides. In those studies, we identified an intrinsic dangling bond defect as well as a likely near-interface vacancy center. Also, we noted that the studied 4H-SiC MOSFETs with thermal gate oxides contain a concentration of vacancy-like centers at the SiC/SiO2 interface, which extend significantly into the SiC bulk. In this study, we report on SDR measurements of variously processed thermal oxide 4H- SiC MOSFETs fabricated by Cree Inc. We find very large differences in SDR defect spectra as a function of processing variations. Comparisons of SDR measurements and conventional MOS electronic measurements of interface trap density clearly indicates a strong correlation between the SDR amplitudes and interface trap densities. Our studies have primarily involved the effects of various post-oxidation nitridation anneals. Versus samples with no nitridatin, we observe a large (order of magnitude) decrease in both SDR amplitude and interface trap densities with the introduction of various nitridation anneals. We also observe smaller differences in SDR amplitude and interface traps as a function of nitridation anneal parameters. We believe that these results strongly support the idea that the defects observed via SDR are primarily responsible for the interface trap density in technologically relevant 4H-SiC MOSFET technology.

9:00 PM - B5.22

Dislocation-Related Etch Protrusions Formed On 4H-Sic (000-1) Surface By Molten KOH Etching.

Masahide Gotoh ¹, Takeshi Tawara ¹, Shun-ichi Nakamura ¹, Tae Tamori ¹, Yoshiyuki Kuboki ¹, Yoshiyuki Yonezawa ¹, Masaharu Nishiura ¹
¹, Fuji Electric Advanced Technology Co., Ltd., Matsumoto, Nagano, Japan

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9:00 PM - B5.23

PECVD A-Sic:H Encapsulation For Chronically Implanted Neural Recording Devices.

Jui-Mei Hsu ², Prashant Tathireddy ¹, Loren Rieth ^{2 1}, Sascha Kammer ³, Klaus Peter Koch ³, A. Richard Normann ⁴, Florian Solzbacher ^{1 2 4}
²Department of Material Science and Engineering, University of Utah, Salt Lake City, Utah, United States, ¹Department of Electrical Engineering, University of Utah, Salt Lake City, Utah, United States, ³Department of Medical Technology and Neuroprosthetics, Fraunhofer Institute for Biomedical Engineering, St. Ingbert Germany, ⁴Department of Bioengineering, University of Utah, Salt Lake City, Utah, United States

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Fully integrated neural recording devices for chronic implants require a stable biocompatible encapsulation layer at the interface between the recording device and the brain neural tissue to maintain long term recording characteristics. Amorphous silicon carbide (a-SiC:H) was investigated as an insulating, hermetic, and biocompatible encapsulation for such devices. We focused on low temperature deposition process to avoid degrading the integrated device during the encapsulation process.A plasma-enhanced chemical vapor deposition (PECVD) system was used to deposit a-SiC:H films. The deposition conditions included a pressure of 0.4Torr and substrate temperature 150-275C. SiH4 and CH4 were the precursor gases diluted in hydrogen during deposition. The dilution ratio (precursor/total gas) ranged from 6 to 65%. Deposited-film properties were investigated by Fourier transform infrared spectroscopy (FTIR), ellipsometry, transmission electron microscopy (TEM), dissolution, and adhesion tests. AC (impedance spectroscopy) and DC electrical measurements were used to evaluate film degradation, delamination, and dissolution.Films of thickness 0.3–0.8μm were deposited on oxidized silicon and quartz substrates containing Ti/Pt (50/330nm) interdigitated electrodes. These test chips were placed in Ringer’s solution (NaCl 6gm, KCl 0.075gm, CaCl2 0.1gm, NaHCO3 0.1gm in 1L DI water) at 37C for impedance spectroscopy and leakage current tests. Silicon substrates deposited with a-SiC:H films were placed in phosphate buffered saline solution at 90C for dissolution tests. As observed by ellipsometry, there was no dissolution of SiC films in four weeks. However, when films had poor adhesion or pinholes, etching of silicon substrate was observed. The etching of silicon in preferential etching planes generates square defects that are proportional to the etching time during dissolution test. The thickness of films increased up to 20% during dissolution tests. The lower refractive index of the surface layer compared to that of bulk a-SiC:H suggests surface oxidation during the dissolution test. Analysis of TEM/EDX cross sections was performed to measure the atomic composition and porosity of these a-SiC:H layers.Our study also suggests that a higher hydrogen dilution ratio and silane starving (17% silane in precursor) deposition condition can deposit films of higher silicon-carbon bonding density as measured by FTIR and higher refractive index measured by ellipsometry. Films deposited at lower temperatures exhibit lower refractive index, lower silicon-carbon bonding density, and higher defect density. Higher silicon-carbon bonding density films have higher stress, which may lead to micro cracks. Within the range of deposition conditions investigated, it was found that about 36% hydrogen dilution and 200C during deposition produce the best a-SiC:H films for good encapsulation of chronically implanted devices.

9:00 PM - B5.24

The Formation Mechanism of Carrot Defects in SiC Epifilms.

Xiaoting Jia ¹, Juan Zhou ¹, Jie Bai ¹, Michael Dudley ¹
¹Materials Science & Engineering, Stony Brook University, Stony Brook, New York, United States

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9:00 PM - B5.25

Seedless Coalescence of Pendeo-epitaxial 3C SiC grown on High Aspect Ratio Micromachined Si Posts.

MVS Chandrashekhar ¹, Christopher Thomas ¹, Brian Noel ², Michael Spencer ¹
¹Electrical Computer Engineering, Cornell University, Ithaca, New York, United States, ²Electrical Computer Engineering, Virginia Commonwealth University, Richmond, Virginia, United States

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It is desirable to grow SiC on Si for cost reasons. However, due to the significant lattice mismatch between the 2 materials, the grown material is highly defective, as the strain is relieved through dislocations. Pendeo-epitaxial techniques have proven to be somewhat effective in improving the quality of the material, but rely on patterning a previously grown 3C-SiC seed layer. This patterned wafer is then regrown to produce the pendeo-epitaxial material.In this work, we investigate the possibility of using a pre-patterned Si-wafer, without the use of a seed SiC layer. This eliminates one of the growth stages, greatly simplifying the process and reducing cost. Furthermore, the high aspect ratio of the Si pillars provides that some of the strain from the lattice mismatch may be relieved through Si-post buckle rather than through dislocations in the 3C SiC. These posts also provide a facile-release layer for the 3C SiC for MEMS applications owing to their high surface area.A square array of Si posts 1 um wide and 7 um deep at a period of 2 um were fabricated using photolithography and the Bosch etch process. This etch ensured the slight undercut required for effective coalescence of the grown layer. CVD growth of 3C SiC was then carried out in a vertical cold wall style reactor using a hydrogen-silane-propane chemistry. A buffer layer was formed in the usual manner and the layer grown at a nominal growth rate of 3 um/hr. Growths of various times were performed. The growth was not optimized.The grown material was characterized by X-ray diffraction (XRD) and was determined to be poly-crystalline 3C-SiC, although there was some preferred orientation to the substrate orientation. It is believed that through effective optimization of the growth, single crystal 3C SiC can be obtained.It was observed that after 1 hour of growth, coalescence of the grown layer took place. This will be demonstrated through a scanning electron microscopy (SEM) investigation. Deposition on the sidewalls was observed, but was cut-off as the grown layer coalesced. In addition, due to the close proximity of the posts to one another, the coalesced layer was rather flat (~80nm RMS roughness determined by AFM), despite the lack of a seed layer. It is possible to effectively wafer-bond such a surface through the use of a glue-layer such as spin-on glass.In summary, a seed-free method for producing a continuous 3C SiC layer on pre-pattened Si was demonstrated. The grown SiC layer showed a RMS roughness of ~80nm after 1 hour of growth.

9:00 PM - B5.26

Crystal face and C/Si ratio Dependence of Phosphorus Doping by SiC Epitaxial Growth.

Takeshi Tawara ¹, Yuko Ueki ¹, Shun-ichi Nakamura ¹, Masahide Gotoh ¹, Yoshiyuki Yonezawa ¹, Masaharu Nishiura ¹
¹, Fujielectric Advanced Technology Co., Nagano Japan

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9:00 PM - B5.27

Growth and Mechanism in Halide Chemical Vapor Deposition of Silicon Carbide.

Yi Chen ¹, Govindhan Dhanaraj ¹, Hui Chen ¹, Hui Zhang ², Michael Dudley ¹
¹Materials Science and Engineering, Stony Brook University, Stony Brook, New York, United States, ²Mechanical Engineering, Stony Brook University, Stony Brook, New York, United States

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9:00 PM - B5.28

Development of PECVD SiC for MEMS Using 3MS as the Precursor

Jiangang Du ¹, Neha Singh ¹, Christian Zorman ¹
¹Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio, United States

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SiC is an attractive material for MEMS applications due to its outstanding mechanical, chemical and electrical properties. The preponderance of work in the development of SiC MEMS has focused on SiC thin films deposited by APCVD and LPCVD at high substrate temperatures (800C to 1350C). Recently, however, interest in fabricating SiC-based devices on temperature-sensitive substrates has motivated the development of PECVD-based processes for hydrogen-terminated, amorphous SiC (a-SiC:H) with properties suitable for MEMS. The PECVD approach has permitted the lowering of substrate temperatures to below 400C, thus enabling the incorporation of buried metal electrode structures, the use of non-conventional sacrificial layers (i.e., polyimide) and furthering the development of SiC micromechanical structures with on-chip Si microelectronics. This paper reports our effort to develop a PECVD process for a-SiC:H films specifically designed for MEMS applications using trimethylsilane (3MS) as the precursor. Trimethylsilane is an attractive precursor since it is currently being used in advanced Si microelectronics to produce low-k dielectric, diffusion barrier SiC thin films. In our work, SiC films were deposited in a GSI Ultradep PECVD system using Dow Corning Z3MS metalorganic precursor diluted in He. Films were deposited to thicknesses between 100 nm and 2 μm at a substrate temperature of 350C. The deposition pressure, 3MS/He flow rate, and electrode power were varied to explore the effect of processing parameters on the residual stress and chemical durability of the films. In all cases, the as-deposited films exhibited compressive residual stresses as determined using the wafer curvature measurement technique. Films with residual stresses below -100MPa would, upon a short 10 min anneal at 450C, exhibit modest tensile stresses (<100MPa), which in some cases could be reduced to nearly zero. 100 nm-thick films annealed at 1100C retained their insulating properties, suggesting that any unintentional dopants are not activated upon high temperature exposure. Chemical resistance to acids and bases commonly used in Si micromachining as well as the mechanical stability of the films exhibiting moderate tensile stresses were evaluated using bulk micromachined membranes and surface micromachined structures. Free-standing, 2 μm-thick, membranes with a nominal surface area of 1 x 1 mm2 and fabricated by Si anisotropic etching in a KOH/H2O solution at 55C could be pressurized to about 100 PSI without breakage or delamination. Cantilever beams and bridges surface micromachined using a SF6/CHF3-based plasma to pattern the films and an HNA-based isotropic Si etch to release the structures could be fabricated and used to confirm the residual stress data. The extended paper will detail the recipe development and film characterization efforts as well as the use of these films as mechanical membranes in SiC-based micromachined pressure sensors and fluidic filters.

9:00 PM - B5.29

Microwave Photoconductivity Decay Mapping and Investigation of Lifetimes in 4H-SiC Epitaxial Layers

Joshua Caldwell ¹, Aron Pap ², Amitesh Shrivastava ³, Zehong Zhang ³, Paul Klein ¹, Tibor Pavelka ², Tangali Sudarshan ³, Orest Glembocki ¹, Karl Hobart ¹, Fritz Kub ¹
¹Power Electronics, Naval Research Lab, Washington , District of Columbia, United States, ²Semiconductor Physics Laboratory, Semilab Inc., Budapest Hungary, ³Electrical Engineering Dept., University of South Carolina, Columbia, South Carolina, United States

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In order to capitalize on the superior material properties of SiC, high quality epitaxial layers with long minority carrier lifetimes are required. One technique to investigate lifetime is microwave photoconductivity decay (μ-PCD) that measures both the non-radiative and radiative recombination mechanisms. In this work, two dimensional maps of the carrier lifetime created via μ-PCD were obtained for four 4H-SiC epitaxial layers varying in thickness from 15 to 160 μm. The measurements were performed using the 355nm pulsed laser line of a 3X Nd:YAG incorporated into a WT-2000 lifetime scanner created by Semilab Inc. The wide band gap of SiC requires λ≤384nm, thus lifetime measurements are difficult as the penetration depth of the laser is limited (~48 μm at 355 nm). Furthermore, the growth of epilayers upon highly conductive substrates allows for the creation of a ground plane for the microwaves when measuring thin epilayers, thereby making baseline conductivity measurements extremely difficult. The ability to acquire full maps using μ-PCD has to this point been unsuccessful and the majority of measurements reported utilized wavelengths in the 266 nm range, where the penetration depth limits the measurement to the surface dominated regime. Measurement of thin (<30μm) epilayers require improvements in sensitivity, which is accomplished using the epitest antenna attachment that comes in contact with the surface of the epilayer. The measurements on the 100 and 160μm thick epilayers found relatively homogeneous lifetimes in the 700ns range across the majority of the sample, with significant drops at the edges. However, various anomalies in the lifetime maps were observed with long thin lines as well as small points of lifetime reduction present. The cause for these anomalies is currently unknown. In comparison, the measurements on the 15 and 35μm thick epilayers yielded lifetimes of 1.5 and 2.1μs. These longer lifetimes in comparison to the thicker samples is quite surprising, however, an exponential decrease in the lifetime of 5-15% was observed when the sample was illuminated continuously with white light during the measurement. Such decreases were not observed in the thick epilayers. This decrease appears to be due to a saturation of one or more effective recombination traps found in the middle of the band gap. It is possible that the white light is photo-ionizating the Z1/Z2¹ and/or the EH6/7² defects prevalent in SiC that have been determined to effectively influence the carrier lifetimes. ¹ P. B. Klein, B. V. Shanabrook, S. W. Huh, et al., Applied Physics Letters Submitted (2005).² N. T. Son, E. Sorman, W. M. Chen, et al., in Int. Symp. Compound. Semicond. (IOP Publishing Ltd., San Diego, CA, 1994), Vol. 141: Chapter 4, p. 405.

9:00 PM - B5.3

Surface Cleaning and Etching of 4H-SiC(0001) using Atmospheric Pressure Hydrogen Plasma.

Heiji Watanabe ¹, Shigenari Okada ¹, Hiromasa Ohmi ¹, Hiroaki Kakiuchi ¹, Kiyoshi Yasutake ¹
¹Department of Precision Science and Technology, Osaka University, Suita, Osaka, Japan

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Silicon carbide (SiC) is a promising candidate material for high-power, high-frequency, and high-temperature electronic devices. An essential step in fabricating such devices is the preparation of atomically flat and clean SiC surfaces. However, achieving an ideal SiC surface is difficult due to the mechanical hardness and chemical inertness of SiC. Hydrogen annealing is widely used for cleaning SiC surfaces, but the procedure requires high temperatures over 1400C. In addition, a low-damage, high-rate method for etching SiC surfaces has not been established yet. In this study, we used atmospheric pressure (AP) hydrogen plasma for cleaning and etching 4H-SiC(0001) surfaces. The AP plasma was generated using a very high frequency (VHF) 150-MHz power supply and a gas mixture containing hydrogen and helium. Localized AP plasma in a typical 0.3-0.6 mm gap between the electrode and substrate can supply high-density hydrogen radials and prevent ion-induced damage to the SiC surface. Surface treatment of wet-etched 4H-SiC(0001) was conducted at room temperature. The residual fluorine atoms originating from the HF solution were removed and the scratches on the as-received SiC substrates had disappeared completely after the AP hydrogen plasma treatment. Surface characterization using the low energy electron diffraction (LEED) technique also revealed that the damaged layers on the SiC surfaces, which were introduced by the slicing and polishing processes, were effectively removed using the AP hydrogen plasma treatment even at room temperature. We used a cylindrical rotary electrode to supply high VHF power to the AP plasma and obtained a high etching rate over 1000 nm/min. Moreover, we developed a porous carbon electrode for cleaning the surface of SiC wafers. The porous electrode can be used to treat the whole wafer and we obtained a moderate etching rate of around 100 nm/min. These results demonstrated the effectiveness of using our AP hydrogen plasma treatment for etching as-received polished SiC wafers and cleaning epitaxial SiC surfaces.

9:00 PM - B5.5

Spectral Characterization of Persistent Photo Conductance in SiC.

Steven Smith ^{2 1}, Andrew Evwaraye ², William Mitchel ²
²Materials Directorate, Air Force Research Laboratory, Wright-Patterson Air Force Base, Ohio, United States, ¹, University of Dayton Research Institute, Dayton, Ohio, United States

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9:00 PM - B5.6

Electrical Measurement of the Vanadium Acceptor Level in 4H- and 6H-SiC.

William Mitchel ¹, William Mitchell ¹, H. Smith ¹, G. Landis ¹, Mary Zvanut ², Wonwoo Lee ²
¹Materials and Manufacturing Directorate, Air Force Research Laboratory, Wright-Patterson AFB, Ohio, United States, ²Physics Department, University of Alabama at Birmingham, Birmingham, Alabama, United States

Show Abstract

Transition metal doping is a common method for producing the high resistivity in semi-insulating (s.i.) semiconductors and vanadium doping is presently being used to make s.i. SiC. The vanadium deep levels compensate residual nitrogen and boron impurities and pin the Fermi level at the deep level. Since vanadium is amphoteric in SiC, either its donor level, V^4+/5+, or its acceptor level, V^3+/4+, can pin the Fermi level depending on the relative concentration of the shallow donors and acceptors. The donor level is widely accepted to be located around E_C – 1.5 eV in both 6H and 4H SiC. However, there are conflicting reports on the location of the acceptor level. Temperature dependent Hall effect (TDH) and resistivity measurements, and electron paramagnetic resonance (EPR) studies have been performed on both 6H and 4H vanadium doped semi-insulating SiC samples grown by the physical vapor transport technique. Nitrogen and boron concentrations have been measured in some samples by secondary ion mass spectrometry (SIMS). Unlike undoped s.i. SiC, where several different thermal ionization energies have been observed, the ionization energies for all of the vanadium doped s.i. samples studied here were found to cluster around only two values for the two polytypes, E_C – 0.86 eV and E_C – 1.42 eV for 6H and E_C – 1.08 eV and E_C – 1.52 eV for 4H. SIMS measurements indicate that the nitrogen concentration exceeds the boron concentration in samples with the shallower of two values while the opposite is true for the deeper level samples. EPR detected both V³⁺ and V⁴⁺ in shallower level samples while only V⁴⁺ was detected in the deeper level samples. These results indicate that the vanadium acceptor level, V^3+/4+, is located at E_C – 0.86 eV in 6H-SiC and E_C – 1.08 eV in 4H-SiC. However, some EPR results do show a small, unexpected asymmetry in the angular dependence of the V⁴⁺ signal, most noticeably in the 4H samples. This suggests that at least some of the vanadium related levels might be complexed with another defect or be under higher local strain than expected.

9:00 PM - B5.7

Intrinsic Defects in High Purity Semi-insulating 6H SiC.

D. Savchenko ², E. Kalabukhova ², S. Lukin ², T. Sudarshan ³, Y. Khlebnikov ⁴, William Mitchel ¹
²Institute of Semiconductor Physics, NASU, Kiev Ukraine, ³Department of Electrical Engineering, University of South Carolina, Columbia, South Carolina, United States, ⁴, Intrinsic, Semiconductor Corp., Dulles, Virginia, United States, ¹Materials and Manufacturing Directorate, Air Force Research Laboratory, Wright-Patterson AFB, Ohio, United States

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9:00 PM - B5.8

SIMS Analysis of Nitrogen in Silicon Carbide Using Raster Change Technique.

Larry Wang ¹, Byoung-Suk Park ¹
¹, Evans Analytical Group, Sunnyvale, California, United States

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9:00 PM - B5.9

Increase Growth Rate by Powder Geometry Design in SiC Sublimation Growth

Xiaolin Wang ¹, Dang Cai ¹, Hui Zhang ¹
¹Mechanical Engineering, Stony Brook University, Stony Brook, New York, United States

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2006-04-19 Show All Abstracts

Symposium Organizers

Michael A. Capano Purdue University

Michael Dudley State University of New York-Stony Brook

Tsunenobu Kimoto Kyoto University-Katsura

Adrian R. Powell Cree Inc.

Shaoping Wang Fairfield Crystal Technology

B6: Semi Insulating SiC

Session Chairs

Mark Laboda

Wednesday AM, April 19, 2006

Room 3004 (Moscone West)

9:15 AM - **B6.1

Deep Levels in 4H Silicon Carbide Epilayers Induced by Neutron-Irradiation up to 10¹⁶ n/cm².

Anna Cavallini ¹, Antonio Castaldini ¹, Filippo Fabbri ¹, Paolo Errani ¹, Filippo Nava ¹, Vladimir Cindro ¹
¹Department of Physics, University of Bologna, Bologna Italy

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9:45 AM - B6.2

Deep Levels and Compensation in High Purity Semi-Insulating 4H-SiC.

William Mitchel ¹, W. Mitchell ¹, H. Smith ¹, W. Carlos ², E. Glaser ²
¹Materials and Manufacturing Directorate, Air Force Research Laboratory, Wright-Patterson AFB, Ohio, United States, ², Naval Research Laboratory, Washington, District of Columbia, United States

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The compensation mechanisms producing the high resistivity in high purity semi-insulating (HPSI) SiC are still not fully understood. Several defects have been identified by electron paramagnetic resonance (EPR) including vacancies and more complex defects such as the divacancy and the carbon vacancy-carbon antisite pair. It has been suggested that some of these defects are responsible for compensation in HPSI SiC. Several photo-EPR experiments suggest that some of these defects have states in the lower half of the bandgap. However, Hall effect measurements on similar material indicates that the Fermi level is in the upper half of the bandgap. In addition, the defect concentrations from EPR measurements appear to be too low to compensate boron and nitrogen impurities known to be in the 10¹⁵ to 10¹⁶ cm^-3 range. To help clarify these questions we report here the results of a study of temperature dependent Hall effect (TDH), EPR, photoluminescence (PL) and secondary ion mass spectrometry (SIMS) measurements on samples from several HPSI 4H-SiC crystals grown by the physical vapor transport technique. Thermal activation energies from TDH varied from a low of 0.55 eV to a high of 1.5 eV. All samples studied showed n-type conduction with the Fermi level in the upper half of the band gap. Carrier concentration measurements indicated the deep levels had to be present in concentrations in the 10¹⁵ to 10¹⁶ cm^-3 range. Several defects were detected by EPR including the carbon vacancy and the carbon-silicon divacancy. PL measurements in the near IR showed the presence of the UD-1, UD-2 and UD-3 emission lines that have been found in HPSI material, along with those from vanadium and chromium, all with varying intensities. No correlation between the relative intensities of the PL lines and the TDH activation energy was observed. SIMS measurements on nitrogen, boron and other common impurities can assist in establishing the type of the compensating deep levels by establishing whether a donor-like or acceptor-like deep level is needed to compensate the shallow levels. This information can be used to help correlate specific defects with deep levels when the charge state of the defect and its photo-response are determined by EPR.

10:00 AM - **B6.3

Characterization of Semi-insulating SiC.

Nguyen Son ¹, Patrik Carlsson ¹, B Magnusson ^{1 2}, Erik Janzen ¹
¹Dept of Physics, Chemistry and Biology, Linkoeping University, Linkoeping Sweden, ², Norstel AB, Linkoeping Sweden

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10:30 AM - B6.4

Deep Levels in As-Grown and Electron-Irradiated P-type 4H-SiC

Katsunori Danno ¹, Tsunenobu Kimoto ¹
¹Department of Electronic Science and Engineering, Kyoto University, Kyoto Japan

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Deep levels detected in p-type SiC epilayers work as minority carrier (hole) traps in most bipolar devices. Little knowledge is, however, available on deep hole traps in SiC. In this work, we have detected deep hole traps in as-grown p-type 4H-SiC epilayers by deep level transient spectroscopy (DLTS).Samples used in this study were Al- or B-doped p-type 4H-SiC epilayers grown by chemical vapor deposition. The net acceptor concentration was 0.5 -1.5 × 10¹⁶ cm^-3 for Al-doped epilayers and 9.0 × 10¹⁵ cm^-3 for a B-doped epilayer, respectively. Titanium was employed as a Schottky metal, because high barrier height (about 2.1 eV) could be obtained on p-type 4H-SiC, by which leakage current was suppressed even at very high temperature of 700K. From DLTS measurements from 350K to 700K for Al- or B-doped p-type epilayers, three deep levels (named HK2, HK3 and HK4) could be obtained at 400K, 560K and 630K irrespective of dopant species. The trap concentrations in the Al-doped epilayer were 2.9 × 10¹² cm^-3, 2.6 × 10¹² cm^-3 and 1.0 × 10¹² cm^-3 for HK2, HK3 and HK4, respectively. From the Arrhenius plots of emission-time constants assuming temperature-independent capture cross section for the Al-doped epilayer, the traps were revealed to be energetically located at E_V + 0.86 eV (HK2), E_V + 1.27 eV (HK3) and E_V + 1.44 eV (HK4). DLTS measurements were performed under various electric field to study the charge state of the hole traps. If the trap has negative charge (acceptor-like), the emission time constants should be decreased by increasing the applied electric field. The emission-time constants of each trap were, however, almost unchanged irrespective of applied electric field. These results indicate the absence of Poole-Frenkel effect, therefore the deep hole traps might have a neutral charge state after hole emission, being donor-like (+/0) traps. Thermal stability of these traps was investigated. The thermal annealing was performed in the temperature range from 1000°C to 1550°C for 30 min. Trap concentration of the HK2, HK3 and HK4 in the as-grown epilayer used in this measurement was in the low 10¹² cm^-3. The concentrations of HK3 and HK4 were reduced to below the detection limit (1-2 × 10¹¹ cm^-3) by annealing at 1350°C. The trap HK2 was thermally more stable than HK3 and HK4, and become lower than the detection limit by annealing at 1550°C. To investigate the origins of deep hole traps, we performed low-energy electron irradiation (energy: 160 keV, fluence: 1 × 10¹⁸ cm^-2). With this irradiation energy of 160 keV, only carbon displacement like generation of carbon vacancies and carbon interstitials can take place. By the irradiation, the trap concentrations of the HK3 and HK4 were significantly increased (HK3: below detection limit (<1-2 × 10¹¹ cm^-3) to 1.3 × 10¹² cm^-3, HK4: 5.5 × 10¹¹ cm^-3 to 4.1 × 10¹² cm^-3). This result indicates that the HK3 and HK4 may be related with carbon displacement. As for HK2, no significant change was observed.

10:45 AM - B6.5

A Study of V3+/4+ Level in Semi-insulating 4H and 6H-SiC Using Optical Admittance Spectroscopy and Electron Paramagnetic Resonance.

Wonwoo Lee ¹, Mary Zvanut ¹
¹Physics, Univeristy of Alabama at Birmingham, Birmingham, Alabama, United States

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11:00 AM - B6: SI SIC

BREAK

B7: SiC Materials Issues

Session Chairs

B. Mitchel

Wednesday PM, April 19, 2006

Room 3004 (Moscone West)

11:30 AM - **B7.1

Atomic Structure of SiC Surfaces: Hydrogen Etching, Non-Basal-Plane Orientations and Metal Ad-Layers

Ulrich Starke ¹
¹, Max-Planck-Institut fuer Festkoerperforschung, Stuttgart Germany

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The importance of the detailed atomic structures of SiC surfaces for device related processes has been recognized more and more in recent years. While the structure of the basal-plane surfaces, i.e. SiC(0001) and SiC(000-1) are well known by now, other important issues, such as non-polar orientations, pore surfaces, the metallization of SiC surfaces and even more the surface modifications upon ex situ hydrogen etching are only beginning to be investigated. The present paper reviews recent advances in the structural characterization of surfaces after hydrogen etching or metal deposition and presents new results on different surface orientations of SiC. The surfaces are investigated using atomic force microscopy (AFM), scanning tunneling microscopy (STM), low-energy electron diffraction (LEED), Auger electron spectroscopy (AES) and X-ray photoelectron spectroscopy (XPS).First, the significant influence of process parameters for hydrogen etching of SiC(0001) is demonstrated, both with respect to the sample morphology as well as for the atomic structure of the surface. Too aggressive etching methods lead to step bunching and the extension of surface defects as shown by AFM. Surface passivation by hydrogen or by oxide monolayers is determined by LEED and AES.Second, the deposition of ultra-thin metallic layers on SiC is discussed. Adsorption and thermal reaction of noble and reactive metals with SiC(0001) are demonstrated by STM, LEED and AES. Ag interacts very little with the surface. Ti on the other hand reacts strongly and forms silicide and carbide bonds depending on the preparation parameters. Several different surface reconstruction phases can be found.Finally, several non-basal plane SiC surface orientations are introduced with different aspects towards future applications. Lying parallel to the c-axis SiC(11-20) promises new growth perspectives for defect free material. In addition to the effect of hydrogen etching, the development of several surface phases with different Si-C compositions, yet the same surface periodicity will be shown. From the development of porous 4H-SiC, another interesting surface orientation has made itself known. The surfaces of a plane oriented diagonal in the bulk unit cell, namely SiC(-110-2) and SiC(1-102) contain one-dimensional chains of different dangling bond configurations. For both surfaces, the morphology and atomic structure upon hydrogen etching and in vacuum preparation are discussed based on AFM, STM, LEED, AES and XPS results.

12:00 PM - **B7.2

Process-Induced Deformations and Stacking Faults in 4H-SiC

Robert Okojie ¹, Xianrong Huang ², Michael Dudley ², Ming Zhang ³, Pirouz Pirouz ³
¹Sensors and Electronics Technology Branch, NASA Glenn Research Center, Cleveland, Ohio, United States, ²Dept. of Mater. Sci. & Eng., SUNY, Stony Brook, New York, United States, ³Dept. of Mater. Sci. & Eng., CWRU, Cleveland, Ohio, United States

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Optical(O), Transmission Electron Microscopy (TEM), and High-Resolution X-ray Diffraction (HRXRD) methods are used to obtain knowledge of the deformations and stacking faults (SFs) generated in n-type 4H-SiC wafers and epilayers when subjected to polishing and temperature. Three p-type 4H-SiC wafers with unpolished backside had 2 μm n-type epilayers grown on the Si-face. The doping levels ranged between 5.2 x 10¹⁷ and 2 x 10¹⁹ cm^-3. After treatment at 1150 ^oC and TEM analysis, SFs, were discovered along the basal plane [11-20] direction in epilayer with doping level as low as 5.2 x 10¹⁷ cm^-3. This is two orders of magnitude below the proposed threshold (3 x 10¹⁹ cm^-3) required for the onset of the generation of SFs in annealed epilayers on the basis of quantum well recombination (QWR) [1]. Because SFs cannot in principle be thermally generated via QWR at this lower doping level, this result strongly suggests the existence of an additional relief mechanism. It lends further confirmation of the existence of significant compressive shear stress in the 4H-SiC epilayers after growth on the Si-face wafers with unpolished backside and that plastic deformation occurs when some of the stress is relieved by thermal treatment [2]. The strain energy associated with such deformation is quantitatively determined to be greater than the Peierls energy barrier of the basal plane dislocation, thus allowing for the movement of the SFs. Initial curvature measurement was made on three n-type Si-face virgin wafers [(N_d = 0.636, 1.1, and 2.13) x 10¹⁹ cm^-3] by OR/HRXRD before and after backside polishing. For the double axis rocking curve, the wafers are linearly scanned along the [11-20] direction from one wafer edge to the other. The peak position shifts to the high-angle side when the beam is scanned across the wafer. The peak shift δθ increases almost linearly with position. Since the lattice constant of the wafer is homogeneous across the wafer, the increasing δθ with position indicates that the (0001) lattice planes are curved. In all three cases, the peak shift δθ increases almost linearly with position and the curvature of the Si-face changes polarity from positive to negative before and after polishing, respectively. This means that the backside polishing process introduces irreversible deformation to the wafer, which is a significant result because it indictaes that the polishing process itself is a strain relief mechanism and could have effects on the wafer microstructure similar to that obtained during thermal processing. The HRXRD measurements after the 2 μm epilayer is deposited show that the curvatures are nearly identical to that before and after epitaxy, which is in contrast to the large residual compressive stress previously reported in epilayers grown on backside unpolished wafers [2]. References[1]Thomas A. Kuhr et al, J. of Appl. Phy., 92(10), 5863-5871. (2002).[2]Robert S. Okojie and Ming Zhang, Mat. Res. Soc. Proc. Vol. 815, 2004.

12:30 PM - B7.3

Diffusion of Boron into 4H SiC from a Borosilicate Glass Source.

MVS Chandrashekhar ¹, Christopher Thomas ¹, Michael Spencer ¹
¹Electrical Computer Engineering, Cornell University, Ithaca, New York, United States

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12:45 PM - B7.4

The Role Of Surface Steps On The Glide Of Misfit Dislocations During III-N/4H-Sic Heteroepitaxial Growth.

Nabil Bassim ¹, Mark Twigg ¹, Charles Eddy ¹, Michael Mastro ¹, Philip Neudeck ², Andrew Trunek ³, J. Anthony Powell ⁴, Ronald Holm ¹, Richard Henry ¹
¹Electronics Science and Technology Division, U.S. Naval Research Laboratory, Washington, SW, District of Columbia, United States, ², NASA Glenn Research Center, Cleveland, Ohio, United States, ³, OAI, NASA Glenn, Cleveland, Ohio, United States, ⁴, Sest, Inc., NASA Glenn, Cleveland, Ohio, United States

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B8: Epitaxy of 3C SiC

Session Chairs

T. Kimoto

Wednesday PM, April 19, 2006

Room 3004 (Moscone West)

2:30 PM - **B8.1

Development of a high-growth rate 3C-SiC on Si CVD process.

Meralys Reyes-Negron ^{1 2}, Yevgeniy Shishkin ¹, Stephen Saddow ¹
¹Electrical Engineering Dept., University of South Florida, Tampa, Florida, United States, ²Chemical Engineering Dept., University of South Florida, Tampa, Florida, United States

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3:00 PM - B8.2

Preparation of Atomically Flat 3C-SiC(001) on Si Surfaces Uusing H2-etching.

Camilla Coletti ¹, Martin Hetzel ², Chariya Virojanadara ², Ulrich Starke ², Stephen Saddow ¹
¹Electrical Engineering, University of South Florida, Tampa, Florida, United States, ², Max-Planck-Institut fuer Festkoerperforschung, Stuttgart Germany

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Reproducible hydrogen etching processes to improve the surface morphology of 3C-SiC on Si(001) substrates with different original surface conditions have been developed. The effect of hydrogen etching on these surfaces has been investigated using AFM, LEED and AES. As-grown and chemical-mechanical polished (CMP) 3C-SiC(001) samples have been etched in a horizontal hot-wall CVD reactor at atmospheric pressure in a hydrogen flux (10slm flow rate) for temperatures ranging from 900 to 1300 °C. The samples were etched for 10-30 minutes and cooled down in a hydrogen flux since this has been shown to terminate surface dangling bonds with hydrogen resulting in a more stable surface. AFM has been used as the main characterization tool to develop an optimum etching process. From the first set of etching experiments the surface morphology appeared to be strongly dependent on the sample history. Thus, two optimum etching processes (e.g. different etching parameters) have been defined for the two different sets of samples. Flat, high-quality surfaces presenting defined atomic terraces and a low RMS surface roughness were obtained on substrates etched at 1100°C for as-grown and 1300°C for CMP-treated samples. In both cases, higher etching temperatures resulted in surfaces with step bunching and enlarged surface defects. Samples etched under the best conditions have been studied using LEED and AES. In an UHV analytical analysis chamber, without any intermediate treatment, the surfaces revealed a sharp (5x1) LEED pattern. A (5x1) surface reconstruction has previously not been reported on 3C-SiC(001) for UHV prepared surfaces and therefore appears to be a new structure for this material. In addition, using AES a ‘bulk-like’ SiC composition was revealed up to the near surface region, with a trace of oxygen present due to previous air exposure. This further indicates that high-quality surfaces are revealed after etching. The final goal of this research is to develop a reproducible process to prepare well-ordered, flat and homogeneous 3C-SiC surfaces for subsequent device processing and to determine the resulting surface structure.

3:15 PM - **B8.3

Recent Results From Epitaxial Growth on Step Free 4H-SiC Mesas

Philip Neudeck ¹, Andrew Trunek ², David Spry ², J. Anthony Powell ³, Hui Du ⁴, Marek Skowronski ⁴, Nabil Bassim ⁵, Michael Mastro ⁵, Mark Twigg ⁵, Ronald Holm ⁵, Richard Henry ⁵, Charles Eddy ⁵
¹, NASA Glenn Research Center, Cleveland, Ohio, United States, ², OAI, NASA Glenn, Cleveland, Ohio, United States, ³, Sest, Inc., NASA Glenn, Cleveland, Ohio, United States, ⁴Dept. of Materials Science and Engineering, Carnegie Mellon University, Pittburgh, Pennsylvania, United States, ⁵Electronics Science and Technology Div., Naval Research Laboratory, Washington, District of Columbia, United States

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The ability to produce arrays of device sized (up to 0.4 mm x 0.4 mm) 4H-SiC mesas with silicon-face (0001) top surfaces entirely free of atomic scale steps has enabled realization of unique and improved wide bandgap epitaxial films. For example, when heteroepitaxial films of 3C-SiC or 2H-GaN are properly grown on top of such step-free 4H mesa surfaces, 100-fold reductions in heterofilm dislocation density have been achieved compared with growth on conventional surfaces with steps [1,2]. Furthermore, 4H-SiC thin lateral cantilevers entirely free of dislocations have also been realized [1]. Despite these achievements, some physical limitations and mechanisms of step-free mesa growth processes remain to be more fully understood. This paper updates recent progress made in growth, characterization, and understanding of high quality homoepitaxial and heteroepitaxial films grown on step-free 4H-SiC mesas. First, we report initial achievement of step-free 4H-SiC surfaces with carbon-face surface polarity. Next, we will describe further observations of how step-free 4H-SiC thin lateral cantilever evolution is significantly impacted by crystal faceting behavior which imposes non-uniform film thickness on cantilever undersides. Finally, recent investigations of in-plane lattice constant mismatch strain relief mechanisms observed for heteroepitaxial growth of 3C-SiC as well as 2H-AlN/GaN heterofilms on step-free 4H-SiC mesas will be reviewed [3,4]. In both cases, the complete elimination of atomic heterointerface steps on the mesa structure enables uniquely well-ordered misfit dislocation arrays to form near the heterointerface with remarkable lack of dislocations threading vertically into the heteroepilayer. In the case of 3C-SiC heterofilms, it has been proposed that dislocation half-loops nucleate at mesa edges and glide laterally along the step-free 3C/4H interface [3]. In contrast, 3C-SiC and 2H-AlN/GaN heterofilms grown on 4H-SiC mesas with steps exhibit highly disordered interface misfit dislocation structure coupled with 100X greater density of dislocations threading through the thickness of the heteroepilayers. These results indicate that the presence of steps at the heteroepitaxial interface (i.e., on the initial heteroepitaxial nucleation surface) play a highly important role in the defect structure, quality, and relaxation mechanisms of single-crystal heteroepitaxial films. [1]P. G. Neudeck and J. A. Powell, in Silicon Carbide: Recent Major Advances, W. J. Choyke, H. Matsunami, and G. Pensl, Eds., Springer-Verlag: Heidelberg, Germany, pp. 179-205, 2003.[2]N. D. Bassim, et al., Applied Physics Letters, vol. 86, pp. 021902-3, 2005.[3]H. Du et al., to appear in Materials Science Forum, ICSCRM-05 Proceedings.[4]N. D. Bassim, et al., to appear in Materials Science Forum, ICSCRM-05 Proceedings.

3:45 PM - B8.4

Process Control During Liquid Phase Epitaxial Growth of 3C-SiC on Si Substrates.

Mark Smith ¹, M Voelskow ², R McMahon ¹, W Skorupa ²
¹, Department of Engineering, University of Cambridge, Cambridge United Kingdom, ², Forschungszentrum Rossendorf, Dresden Germany

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4:00 PM - B8: 3C SiC

BREAK

B9: Epitaxy II

Session Chairs

S. Saddow

Wednesday PM, April 19, 2006

Room 3004 (Moscone West)

4:30 PM - B9.1

Epitaxial Growth and Characterization of SiC on Different Orientations.

Larry Rowland ¹, Canhua Li ², Greg Dunne ¹, Jody Fronheiser ¹
¹, GE Global Research, Niskayuna, New York, United States, ², Rensselaer Polytechnic Institute, Troy, New York, United States

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4:45 PM - **B9.2

Advances in 4H-SiC Homoepitaxy for Power Devices.

Bernd Thomas ¹, Christian Hecht ¹
¹, SiCED Electronics Development GmbH & Co. KG, Erlangen Germany

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In the last 10 years the market for SiC based devices has been developed continuously. The device quality could be enhanced and the costs have been reduced by improving the quality and size of the wafer material as well as by a significant progress in epitaxial growth of active layers.The segment of power devices plays an important role within the SiC device market. Today Schottky Barrier Diodes (SBD) with blocking voltages of 300V, 600V and 1200V are available at the market. SBD’s with higher blocking voltages (e.g. 1700V) and JFET-based switches are expected to be introduced in the near future. The aimed device performance determines the specifications of the active epitaxial layers. Besides material properties like good crystal structure, purity and specular surface morphology a doping homogeneity better than 10% and a thickness homogeneity better than 2% on waferscale are required for productive process management. For the mentioned voltage classes the CVD process should guarantee a doping range of ND-NA from 4xE15 to 2xE16 cm-3 and a layer thickness between 3.5 and 15 µm. In order to achieve this reliable, the background doping level should be at least one order of magnitude lower than the active doping concentration. Furthermore, the run-to-run as well as the wafer-to-wafer reproducibility of a multi-wafer process is of significant importance for production suitability and stability.For a further market penetration of SiC power devices an effective cost reduction is necessary. One essential factor - the epitaxial cost - can be reduced by increasing the reactor capacity by the use of multi-wafer systems. To realize lower material costs, special attention must be paid to the reduced off-orientation for large area substrates which needs to evaluate new process windows. Additionally, equipment parameters, which are not directly related to the properties of epitaxial layers are of great interest to utilize a cost-effective system for large-scale production.We will present recent results of the homoepitaxial growth of 4H-SiC on 3” (0001) 8°- and 4°-off oriented wafers using multi- and single-wafer hot-wall CVD systems. The multi-wafer equipment exhibits a capacity of 7x3” wafers per run and can be upgraded to a 5x4” set-up. The single-wafer CVD allows deposition on 3x2”, 1x3” or 1x4” substrate configurations. By optimizing the process conditions epitaxial layers with excellent crystal quality, purity and homogeneity of doping and thickness were grown. The wafer-to-wafer homogeneity will be illustrated by the presentation of the doping and thickness mappings of full-loaded runs. The run-to-run reproducibility will be discussed as well as the stability and reliability of the reactor. To specify the epi-layer quality results from various characterization techniques will be presented.

5:15 PM - B9.3

High Quality Uniform Thick Epitaxy of 4H-SiC for High Power Device Applications

Jie Zhang ¹, Esteban Romano ¹, Igor Sankin ¹, Janice Mazzola ¹, Carl Hoff ¹, Yaroslav Koshka ², Janna Casady ¹, Mike Mazzola ¹, Jeff Casady ¹
¹, SemiSouth Laboratories, Inc., Starkville, Mississippi, United States, ²Electrical and Computer Engineering, Mississippi State University, Starkville, Mississippi, United States

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For high power device applications, thick 4H-SiC epilayers are required as the voltage blocking layer [1]. While thick SiC epilayers grown at growth rates greater than 20 um/h have been reported using vertical hot-wall reactors [2, 3], much recent research on the SiC thick epitaxy has been conducted with horizontal hot-wall CVD reactors. This is mainly attributed to the fact that these reactors are most commonly available and have been able to produce high quality SiC epilayers. Successful growth of thick SiC epilayers has been demonstrated in the horizontal hot-wall CVD reactors, with most of them being research tools with limited wafer handling capacity [4, 5]. In this paper, we will present the development of thick SiC epitaxy in a production horizontal hot-wall reactor. This reactor is equipped with wafer rotation and can grow three 2-in wafers at a time or single wafers up to 4-in in diameter. The feasibility for thick epitaxy in this reactor was first demonstrated using standard growth rates with prolonged growth time. Subsequently process optimization for improved surface morphology and increased growth rate is being performed. 4H-SiC substrates, either 2-in or 3-in, 8-deg. off-axis towards [11-20] direction, are used. Surface morphology is inspected using optical microscopy with Nomarski contrast. The doping is obtained by CV measurements and the thickness by either FTIR or SEM cross section inspection. With the standard process conditions, we have grown a 60-um thick epilayer on a 2-in substrate at a growth rate of 6 um/h with excellent thickness uniformity of 2.5%. The doping was 1.2x1015 cm-3 with a good uniformity of 10.8%. The system and process stability has been proven by the successful growth of a 100-um epilayer on a 3-in substrate for 20 hours with a growth rate of 5 um/h. The n-doping was 5.8x1014 cm-3 with a uniformity of 18%. The surface morphology was relatively smooth for the 60-um epilayer, whereas a certain degree of step-bunching was observed for the 100-um epi. We will show that through the optimization of the growth conditions, epilayers thicker than 100 um with good morphology and uniformity can be achieved. In addition, we will demonstrate increased growth rates through process optimization for thick epitaxial growth in this production CVD reactor. AcknowledgementsThis work is partially supported by DARPA SBIR Phase II, AFRL Contract # FA8650-05-C-7209, monitored by Dr. John Blevins.References[1] Y. Sugawara, Materials Science Forum vols. 457-460 (2004), p. 963[2] A. Ellison, J. Zhang, A. Henry and E. Janzén, J. Cryst. Growth vol. 236 (2002), p. 225[3] H. Tsuchida, I. Kamata, T. Jikimoto and K. Izumi, Materials Science Forum vols. 389-393 (2002), p. 171[4] J. Zhang, J. Mazzola, C. Hoff, Y. Koshka and J.B. Casady, Materials Science Forum vols. 483-485 (2005), p. 77 [5] R. Myers, O. Kordina, Z. Shishkin, S. Rao, R. Everly and S.E. Saddow, Materials Science Forum vols. 483-485 (2005), p. 73

5:30 PM - B9.4

Multiplication of Basal Plane Dislocation via Interaction with c-Axis Threading Dislocations in 4H-SiC.

Govindhan Dhanaraj ¹, Yi Chen ¹, William Vetter ¹, Hui Chen ¹, Jie Bai ¹, Hui Zhang ², Michael Dudley ¹
¹Materials Science and Engineering, Stony Brook University, Stony Brook, New York, United States, ²Mechanical Engineering, Stony Brook University, Stony Brook, New York, United States

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5:45 PM - B9.5

High Quality Homoepitaxy on Micropipe-Free Silicon Carbide (SiC) Substrates for Large Area Devices

Christer Hallin ¹, Yuri Khlebnikov ¹, Peter Muzykov ¹, Igor Khlebnikov ¹, Jan-Olof Svedberg ², Andrei Konstantinov ², Chris Harris ¹, Cem Basceri ¹, Cengiz Balkas ¹
¹, INTRINSIC Semiconductor, Dulles, Virginia, United States, ², INTRINSIC Semiconductor AB, Kista Sweden

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The move towards commercialization of SiC based devices places increasing demands on the quality of the substrate and epitaxy materials. Structural defects such as MPs, dislocations and stacking faults are often detrimental to device yield and/or performance, and still present in commercial materials. While the industry has steadily decreased the MP levels in commercial SiC substrates over the past years, the achievement of wafers that are entirely free of MPs marks an important milestone in commercialization of SiC based devices. We present the results of a study for controlling the nucleation and propagation of MP defects in SiC ingots grown via Physical Vapor Transport (PVT). Our studies confirm that during bulk growth of SiC, foreign polytype nucleation such as 3C-polytype occurs at the initial stages of growth (nucleation period) and/or during subsequent growth in the presence of facets. Results in this investigation suggest that polytype instability during crystal growth adversely impacts the MP density. Based on this key concept, SiC single crystal ingot growth conditions for nucleation and growth stages were optimized. These conditions were subsequently implemented in an innovative PVT growth environment to achieve a process technique with highly effective polytype control. Under continuously modulated growth conditions, MPs induced by seed material and/or formed during the growth were eliminated. 2-inch and 3-inch diameter MP-free (zero MP density) conducting 4H-SiC ingots were obtained. In addition to the crystal quality of substrates, in-situ pre-epitaxial treatments, process temperature and pressure, precursor and carrier flows, are the critical epitaxy growth parameters impacting the level of defects in epitaxial layers. In this part, we will present the results from CVD grown SiC epitaxial layers (1µm to 50µm thick) on MP-free substrates in hot-wall multi-wafer reactors. Characteristics of the epitaxial layers grown on three distinct off-axis cut SiC substrates (<1ο, 4o, and 8o off from <0001> direction) will be discussed. In addition, both Si- and C-face growth studies will be compared for differences in surface energy and growth chemistry impact on dislocation propagation. Dislocations and their arrays (e.g., along grain boundaries) are known to be one of the critical non-radiative recombination centers. The full wafer minority carrier lifetime measurements as well as etch pit density post molten KOH etch and their relation to the distribution of dislocations will be presented. It will also be discussed that possibility of forming dislocations arrays in MP-free SiC substrates and their propagation into epitaxial layers. Initial results from 700V, 100A Schottky diode shortloop test structures (6x6 mm2) on MP-free substrates with approximately 80% functional device yield will also be presented.

B10: Poster Session: SiC Device Posters

Session Chairs

M. Capano

Thursday AM, April 20, 2006

Salons 8-15 (Marriott)

9:00 PM - B10.1

Laser-Patterned Deep Green to Light Yellow Silicon Carbide Light-Emitting Diodes.

Sachin Bet ¹, Nathaniel Quick ², Aravinda Kar ¹
¹MMAE/CREOL, University of Central Florida, Orlando, Florida, United States, ², Applicote Associates, LLC, Sanford, Florida, United States

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9:00 PM - B10.11

Pr-O-N Dielectrics for MIS Stacks on Silicon and Silicon Carbide Surfaces.

Karsten Henkel ¹, Mohamed Torche ¹, Rakesh Sohal ¹, Carola Schwiertz ¹, Ioanna Paloumpa ¹, Dieter Schmeißer ¹
¹Angewandte Physik-Sensorik, BTU Cottbus, Cottbus, Brandenburg, Germany

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We combine higk-k dielectrics with high band gap semiconductors for new possibilities for high frequency and high power applications. We investigate the dielectric properties of Praseodymium based oxides and silicates by prepared MIS structures consisting of metal layer (M), Pr-Ox as a high-K insulating layer (I), and silicon (Si) or silicon carbide (SiC) as semiconductor substrates (S). Our approach uses both, electrical measurements and spectroscopic characterisation for the stability of the various interfaces within the stacks. Pr₂O₃ layers are prepared by electron beam evaporation from Pr₆O₁₁ powder and in situ controlling of interface and volume composition (XPS). Pr-Silicate layers were prepared either by metal evaporation onto a thin oxide on top of the semiconductor and following annealing steps or by a wet chemical process out of aqueous Pr(NO₃)₃ solutions.The reactivity of the metal electrodes on thin (2nm) Pr₂O₃ films is addressed for metal contacts. Al, Au, Ag layers are thermally evaporated while Ti layer was deposited by sublimation. XPS results show a strong diffusivity of Al, Ag, and Au in Pr₂O₃ upon annealing to 300°C with an alloy formation with the Si substrate. In contrast, Ti remained stable even upon annealing up to 900°C. These results demonstrate that Ti is a good diffusion barrier between Pr₂O₃ and metal contacts and we used for our further studies Ti/Al double layers as contacts. We also report on the optimisation of the preparation conditions of the dielectric films in terms of the stability of the coexisting Pr₂O₃ , Pr-silicate, and SiO₂ phases.For the electrical measurements we produced Pr₂O₃ layers in the thickness range of 16nm to 175nm. Here we used capacitance-voltages analysis and found permittivity values (DK=ε_r) of 8 to 20 depending on physical thickness. These data are consistent with the formation of a Pr-silicate layer at the interface between SiO₂ and Pr₂O₃. The thinner the layer the more significant is the contribution of the lower DK of the interfacial layer. The reported DK values result in an equivalent oxide thickness (EOT) down to 5nm. By analyzing the conductance voltage dependencies we found high interface state densities in the range of 5*10¹² to 10¹³ cm²/Vs. Current voltage characteristics deliver leakage currents at 1V above flat band in the range of 10^-2 A/cm². Attempts to reduce especially the leakage current and interface state density and of further shrinking of EOT will be shown.

9:00 PM - B10.12

Comparison of Parameter Extraction Techniques for Schottky Barrier Diode Gas Sensors

Ming Weng ¹, Alton Horsfall ¹, Cezar Dimitriu ¹, Nick Wright ¹, Konstantin Vassilevski ¹, Irina Nikitina ¹
¹, University of Newcastle upon Tyne, Newcastle upon Tyne United Kingdom

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9:00 PM - B10.13

Demonstration of Hybrid Silicon-on-Silicon Carbide Wafers and Electrical Test Structures with Improved Thermal Performance.

Steven Whipple ¹, John Torvik ², Randolph Treece ³, Jeffrey Bernacki ³
¹Physics, University of Colorado, Boulder, Colorado, United States, ²Electrical Engineering, University of Colorado, Boulder, Colorado, United States, ³, Astralux, Inc., Boulder, Colorado, United States

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SiC is a wide bandgap semiconductor with excellent material properties such as high breakdown field, saturation velocity, and adequate electron mobility as well as up to three times higher thermal conductivity compared to Si. It is expected that SiC devices may replace Si devices for certain high power and high frequency electronic application when SiC materials technology matures. For example, high power LDMOS RF transistors have severe thermal management issues when used in demanding cellular base station applications where near-CW operating conditions with high peak powers are required while still maintaining good linearity. Aggressive substrate thinning and the use of isotopically purified Si has been explored to improve thermal management. In this work, we explore making alternative hybrid Si/SiC wafers that result in Si devices with improved thermal management and electrical performance. Two-inch hybrid Si-on-SiC substrates consisting of thin film [100] Si (1.1 um) on bulk semi-insulating [0001] 6H-SiC wafers were fabricated using low-temperature (150C) wafer bonding and slicing techniques. A set of samples were prepared comparing various thicknesses of SiO2 (60, 240 and 520 nm) as an intermediate bonding layer between the two materials. A variety of test structures such as van der Pauw structures, linear transfer-length measurement arrays and resistors were fabricated in the Si layers using standard Si processing (such as lithography, B-diffusion and oxidation) in order to characterize the robustness, electrical, and thermal properties of the hybrid substrates. Bulk Si and Si-on-insulator (SOI) substrates were used for comparison. We report the Si layers of the hybrid Si-on-SiC substrates to be device-grade in terms of mobility and crystal structure, and that their device-to-device electrical isolation properties are superior to those of bulk Si and comparable to those of SOI. Furthermore, electrical test structures on hybrid Si-on-SiC substrates exhibit vastly superior heat dissipation compared to equivalent devices on bulk Si or SOI. Specifically, the temperature rise in resistors can be as much as 102C lower in resistors made on Si/SiC (Tj= 191C) compared to on bulk Si (Tj= 293C) under high-power density operation (67 kW/cm²). We will describe the effects of intermediate oxide thickness on thermal resistance.

9:00 PM - B10.14

High Power SiC MESFETs

Christopher Harris ¹, Andrei Konstantinov ², Jan-Olov Svedberg ², Ian Ray ², Christer Hallin ¹, Bengt-Olof Larsson ²
¹, Intrinsic Semiconductor, Dulles, Virginia, United States, ², Intrinsic Semiconductor AB, Kista Sweden

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9:00 PM - B10.15

Control of Trenching and Surface Roughness in Deep Reactive Ion Etched 4H and 6H SiC.

Glenn Beheim ¹, Laura Evans ¹
¹, NASA Glenn Research Center, Cleveland, Ohio, United States

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Single-crystal SiC of the 4H and 6H polytypes has very attractive characteristics for harsh-environment microelectromechanical systems (MEMS) such as high-temperature SiC pressure sensors. Fabrication of SiC MEMS often requires that SiC be etched to depths on the order of 100 μm or greater. Various groups have demonstrated deep reactive ion etching (DRIE) of SiC with a high etch rate (1 μm/min or greater), but a process has not yet been demonstrated which simultaneously provides the desired characteristics of (1) high etch rate, (2) vertical sidewalls with minimal trenching at the sidewall base, and (3) smooth etched surfaces. We report here the development of a SiC DRIE process which meets these requirements to a degree which enables economical fabrication of SiC MEMS that are largely free of performance-reducing micromachining defects. In DRIE of SiC, etching at the base of the sidewall is generally enhanced by a local increase in ion flux that causes trench formation. This defect is particularly troublesome when fabricating SiC micromechanical structures, such as diaphragms for pressure sensors, since the trench acts as a stress concentrator that weakens the structure. In addition, deep etching of SiC often results in the undesired formation of dimples and spike-like structures on horizontal surfaces (i.e., surfaces parallel to the wafer face). A series of experiments was performed to determine operating parameters that minimize these defects while maintaining acceptable etch rates. Generally, DRIE of SiC is performed using substrate cooling because the SiC etch products are volatile at room temperature. This study is believed to be the first systematic investigation of the effect of substrate temperature on SiC etch characteristics. An inductively coupled plasma etcher (ST Systems Multiplex ICP) was modified to provide control of the substrate temperature over the range of 20 to 180 °C. The other parameters investigated in this study were pressure (over a wide range, from 5 to 25 mTorr) and gas composition (using mixtures of SF₆, O₂ and Ar). Both n-type 6H and p-type 4H SiC samples were etched. The study shows that substrate temperature, pressure and gas composition all exert a strong influence on etch rate, trench depth, roughness of horizontal etched surfaces and sidewall angle. An optimized process was developed which maximized verticality of the sidewall while providing minimal trenching, smooth horizontal etched surfaces, and an acceptable etch rate (> 0.5 μm/min).

9:00 PM - B10.17

Hydrogen Incorporation In Sio₂/Sic Structures Upon Different Thermal Treatment Sequences.

Gabriel Soares ¹, Israel Baumvol ^{2 3}, Claudio Radtke ¹, Fernanda Stedile ⁴
¹, PGMICRO - UFRGS, Porto Alegre, RS, Brazil, ², CCET - Universidade de Caxias do Sul, Caxias do Sul, RS, Brazil, ³, Instituto de Fisica - UFRGS, Porto Alegre, RS, Brazil, ⁴, Instituto de Quimica - UFRGS, Porto Alegre, RS, Brazil

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SiC is a semiconductor with interesting characteristics: wide band gap, high saturation electron velocity, high thermal conductivity, and SiO₂ formation under thermal oxidation. They make it attractive in electronic devices applications that involve high-power, high-temperature, and/or high-frequency conditions. Despite many advances already achieved, improvements in the electrical characteristics of the SiO₂/SiC interface are still needed. For this reason, the understanding of the passivation of electrically active defects at the SiO₂/SiC interface plays a fundamental role in the control of the characteristics of SiC-based devices.Mechanisms of hydrogen and oxygen transport, incorporation, and removal in the samples were accessed using gases enriched in isotopes less abundant in nature and analysis by nuclear reactions. Thermal oxidations of SiC wafers were performed in O₂ ambients enriched in the ¹⁸O isotope. Before and/or after oxidations, samples were annealed in deuterium rich H₂ aiming at passivating at least some defects at the SiO₂/SiC interface. By means of nuclear reactions, the amount (areal density) of hydrogen and oxygen in the various samples as well as the isotopes profiles were obtained. The chemical composition of the sample and the distribution of the compounds in depth were probed by X-ray Photoelectron Spectroscopy (XPS) varying the detection angle of the photoelectrons. The more interesting results include a two orders of magnitude decrease in the amount of hydrogen incorporated when comparing SiC samples annealed in D₂ to similar samples submitted to an additional thermal oxidation step. This last hydrogen amount is similar to that obtained for SiC samples oxidized prior to D₂ annealing. An one order of magnitude increase in hydrogen incorporation was obtained increasing the D₂ annealing temperature from 500 to 1000°C. Finally a new contribution to the C1s region XPS spectrum from some of the samples was observed, corroborating the idea that carbon plays an important role in the oxidation/passivation process.

9:00 PM - B10.18

Theoretical Analysis of Short-Channel Si and SiC Quantum-Wire MOSFETs.

Tsunenobu Kimoto ¹
¹Department of Electronic Sci. & Eng., Kyoto University, Kyoto Japan

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Major challenges in advanced LSIs include scaling of Si MOSFETs while keeping gate control and low leakage current. In ultra-small MOSFETs, various harmful effects become significant, which hamper the further improvement of device performance. To overcome these “red bricks” faced by ultra-small (classical) FETs, a novel device concept and structure will be strongly required. In this study, a short-channel quantum-wire (QW) MOSFET is proposed. Advantages and estimation of device performance are discussed. In the short-channel QW-MOSFET, the channel consists of multiple nm-scale p-type (n-type) quantum wires, which connect n+-type (p+-type) source and drain. The QW region may be designed as precisely-doped n-type for an n-channel device. The QW is electrically isolated from the substrate by oxide or pn junction. In the nm-scale channel devices, carriers are confined in one-dimensional QW, leading to the remarkably suppressed phonon/ intervalley scattering. The device is especially attractive for semiconductors with indirect band structure, because the appropriate selection of QW orientation enables the travel of light electrons (smaller m*) to dominate. Combination of the nm-scale QW and short channel design, the coherent and ballistic transport of carriers is realized, by which the current-handling capability and transconductance will be significantly enhanced. The basic current-voltage characteristics of Si QW MOSFETs at room temperature were calculated by using the Landauer’s approach developed for ballistic FETs with conventional structure. The drain current can be expressed by the product of the carrier flux injected to the channel and the transmission coefficient. The carrier flux is mainly determined by the electronic states of subbands near the potential maximum near the source edge. The transmission coefficient can be estimated from the source and drain Fermi levels. In this tudy, a quantum wire with a cross section of 5 nm x 5 nm and a wire pitch of 10 nm was assumed. The typical thickness of gate oxide (SiO2) and channel length were 2 nm and 10 nm, respectively. For an n-channel Si(001) device, the drain current and transconductance take the maximum, when the QW is aligned along the [100] direction, taking account of the anisotropy in effective mass, degeneracy, and density of states. The maximum drain current at a gate voltage of 0.6 V (gate oxide field: 3 MV/cm) was estimated to be 2-3 mA/um, which is about one-order-of-magnitude higher than that of a classical Si MOSFET (0.1-0.2 mA/um) with the same oxide thickness and channel length at the same bias voltage. The n-channel 4H-SiC{0001} QW MOSFETs show also high drain current, about 2 mA/um. High-temperature operation of SiC devices will become a big advantage in future ULSIs. Detailed modeling, effects of QW size and orientation, and material choice will be discussed.

9:00 PM - B10.19

First-principles Calculations of Schottky Barrier Heights of oxide/SiC, metal/SiC, oxide/metal/SiC (OMS) and metal/oxide/SiC (MOS) Interfaces.

Shingo Tanaka ¹, Tomoyuki Tamura ², Kazuyuki Okazaki ¹, Shoji Ishibashi ², Masanori Kohyama ¹
¹MATSCI-UBIQEN, AIST, Ikeda, Osaka Japan, ²RICS, AIST, Tsukuba, Ibaraki Japan

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Silicon carbide (SiC) is expected as high-performance electronic devices. In order to develop the high-quality devices, it is important to understand and to design oxide/SiC, metal/SiC, oxide/metal/SiC (OMS) and metal/oxide/SiC (MOS) interfaces. In this paper, we perform the first-principles calculations using the projector augmented wave (PAW) method and estimate the interface Schottky barrier heights (SBH) of SiC interfaces [1]. Recently, we have calculated the 6H-SiC(000-1)-2x2 surface and its result is in good agreement with the experiments [2]. In the oxide/SiC interface, we treat several models of silicate adlayers in comparison with the |*rad*|3x|*rad*|3 model [3]. Specific states by Si-O-C and Si-O-Si bonds can be seen in the charge density distribution and the local density of states (LDOS). In the metal/SiC interfaces, we have dealt with the several types of metals as Al, Ti, Ni, Cu, Pt and Au, and its alloy. Obviously, the interface SBHs show the termination dependence. The calculated p-type (n-type) interface SBHs at the C-termianted interface are smaller (larger) than that at the Si-termianted one. This tendency can be understand that the interface dipole at the former interface is larger than that at the latter one. Also we obtain the metal species dependence for the interface SBHs. In a combination with the oxide and metal interface, we have calculated OMS and MOS interfaces. The results show the atom species dependencies at the interface. This work was performed as a part of National Research Grid Initiative (NAREGI) by Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan. [1] S. Tanaka and M. Kohyama, Phys. Rev. B 64, 235308 (2001); Mat. Res. Soc. Symp. 640, H5. 18 (2001); Appl. Surf. Sci. 216, 471 (2003): J. Hoekstra and M. Kohyama, Phys. Rev. B 57, 2334 (1998): M. Kohyama and J. Hoekstra, Phys. Rev. B 61, 2672 (2000). [2] Y. Hoshino, R. Fukuyama, Y. Matsubara, T. Nishimura, S. Tanaka, M. Kohyama, and Y. Kido, Phys. Rev. B 73, 195331 (2005). [3] W. Lu, P. Kr|*udieru*|ger, and J. Pollmann, Phys. Rev. B 61, 13737 (2000).

9:00 PM - B10.2

Effect of Dopant Concentration on High Voltage 4H-SiC Schottky Diodes.

Francesco La Via ¹, Giuseppa Galvagno ¹, Fabrizio Roccaforte ¹, Andrea Firrincieli ¹, Salvatore Di Franco ¹, Marco Mauceri ², Stefano Leone ², Giuseppe Abbondanza ², Ferdinando Portuese ², Lucia Calcagno ³, Gaetano Foti ³
¹, CNR-IMM, Catania Italy, ², Epitaxial Technology Center, Catania Italy, ³Physics Department, Catania University, Catania Italy

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This work shows an evident correlation between the reverse leakage current and the dopant concentration of the epitaxial layer in 4H-SiC Schottky diodes. A variation of about 30% in the doping concentration (between 1.1×10¹⁶ and 1.7 × 10¹⁶ cm^-3) generates, at room temperature, an increase of the leakage current at –600V of more than two orders of magnitude.As a high leakage current is detrimental for device performances, understanding these current effects is important to set the dopant limitations for the device drift layer and to obtain a high forward current with the minimal leakage current. In this work a detailed study of the influence of the dopant concentration on the forward and reverse I-V characteristics has been performed in a critical concentration range between 0.44 × 10¹⁶ - 1.73 × 10¹⁶ cm^-3. The epitaxial layers were nitrogen doped 4H-SiC (0001), grown on 8° off axis substrates. The n^- epitaxial layers were 6 mm thick, grown on a heavily doped n⁺ substrate with a resistivity of 0.018 Ωcm. The measured leakage current was constant over a range of dopant concentration, i.e. from 4.4 × 10¹⁵ to about 1.1 × 10¹⁶ cm^-3. At higher doping levels , the leakage current increased following a linear trend in a semi logarithmic scale as a function of epilayer dopant concentration. Forward I-V characteristics have been also analyzed to take into account the complete electrical characterization of the diodes. In these conditions, a dopant concentration of 1.1 × 10¹⁶ cm^-3 gives the best results in the reverse characteristics without a significant worsening of the forward voltage drop. Another important issue for SiC is related to the possibility to operate at high temperatures. For this reason and to study the leakage current mechanisms, the forward and reverse characteristics have been analyzed for temperature ranging from 298 K to 573 K, for three different dopant concentrations. Schottky diodes with the lower dopant concentration (1.1×10¹⁶/cm³) showed a strong temperature dependence of the reverse leakage current in all the investigated reverse voltages range. Conversely, for higher doping levels (1.5 and 1.7×10¹⁶/cm³) of the epilayer, the temperature variation of the leakage current was more significant at lower (< –300 V) than at higher reverse biases (-600 V). All the tested devices exhibited an ideal behavior in forward bias conditions. Moreover, calculated I-V characteristics using the thermoionic theory have been reported as a function of epilayer dopant concentration. Finally, the details of how high temperatures affect the properties of junctions have been carefully described to obtain further improvement in the future by proper device optimization.

9:00 PM - B10.3

Thermal Interactions of Ni on Stepped 6H-SiC Surfaces - Implications for Thin Film Microstructure.

Andrew Woodworth ^{3 1}, Charter Stinespring ¹, Srikanth Raghavan ²
³Department of Physics, West Virginia University , Morgantown, West Virginia, United States, ¹Chemical Engineering, West Virginia Univarsity, Morgantown, West Virginia, United States, ²Lane Department of Computer Science and Electrical Engineering, West Virginia University , Morgantown, West Virginia, United States

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9:00 PM - B10.4

Ohmic Contact Characteristics of 3C-SiC Using a TiWN thin-film for High Temperature MEMS Applications.

Gwiy Chung ¹
¹School of Electrical Enginnering, University of Ulsan, Ulsan Korea (the Republic of)

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9:00 PM - B10.5

Fabrication and Characterization of 5kV IGBTs on 4H-SiC.

Charlotte Jonas ¹, Qingchun Zhang ¹, Sei-Hyung Ryu ¹, Anant Agarwal ¹, John Palmour ¹
¹SiC Power Devices, Cree, Inc., Durham, North Carolina, United States

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SiC’s potential for high power, high temperature and high-speed applications have been clearly demonstrated [1]. The IGBT is a combination of a DMOSFET and a BJT. It combines the positive attributes of being a voltage-controlled device but has the switching and conduction characteristics of a BJT. In this paper, fabrication and characterization of p-channel IGBTs on 4H-SiC will be discussed. P-channel IGBTs were fabricated on 4H-SiC n-type substrates since they are more readily available than low resistivity p-type substrates. A p-type buffer layer was grown on the substrates to prevent the depletion region from punching through in the device off state. A 50 µm p-type drift layer was grown on the buffer layer for 5 kV blocking capability. It is desirable that the drift layer is as thin as possible to reduce the on-state voltage, while maintaining the 5 kV blocking capability. The selection for the doping and thickness of the drift and buffer layers were based on numerical simulations. The n-well, p+, n+, JFET region and terminations are formed by ion implantation followed by a thermal anneal at ~1600°C. A thin thermally grown SiO₂ and thick CVD oxide are deposited over the termination region as a surface passivation. A gate oxide of ~450 Å was thermally grown and anneal in Nitric Oxide followed by polysilicon deposition. Al/Ni were deposited for the emitter contacts and Ni was used to form the backside IGBT collector contact. Both contacts were annealed at ~800°C. A thick aluminum film was deposited as an overlay. Figure 1 shows the cross-section of the device.Output characteristics are shown in figure 2. Turn-on voltage is –3.1 V and the specific on-resistance is ~400 mΩ cm² at 25°C with a gate voltage of –34 V. The on-resistance decreases as the temperature increases as shown in figure 3. DC blocking was mapped and ~30% of the devices sustained a 5 kV blocking capability.We acknowledge the support of DARPA (Contract Number: N00014-05-C-0202) for the financial support.[1] Anant Agarwal, Mrinal Das, Sumithra Krishnaswami, John Palmour, James Richmond, and Sei-Hyung Ryu, "SiC Power Devices - An Overview," Mat. Res. Soc. Symp. Proc. Vol. 815, pp. 243-254, (2004) Materials research Society Symposium, San Francisco, California, U. S. A., April 14-15, 2004.

9:00 PM - B10.6

Epitaxial γ-Al₂O₃ Dielectrics for 4H-SiC MOS Devices

Carey Tanner ¹, Jun Lu ², Hans-Olof Blom ², Jane Chang ¹
¹Chemical and Biomolecular Engineering, University of California, Los Angeles, Los Angeles, California, United States, ²Angstrom Laboratory, Uppsala University, Uppsala Sweden

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The development of epitaxial high-κ dielectrics has the potential to improve the performance of SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) due to enhanced dielectric strength and chemical stability under extreme operating conditions. Alumina is well-known for its stability in several phases, and epitaxy of γ-Al₂O₃ thin films has been previously demonstrated on Si. Several other intrinsic properties of Al₂O₃ also make it a viable gate oxide material for SiC devices. The higher dielectric constant of Al₂O₃ (κ = 10) allows MOSFET operation at a higher electric field than that allowed by SiO₂. Its larger bandgap (7-8 eV) relative to that of other high-κ oxides, such as HfO₂ and La₂O₃, allows adequate band offsets to be maintained at the interface with 4H-SiC (E_g = 3.26 eV). This study represents the first reported demonstration of epitaxial dielectrics on SiC, and we evaluate the structural and electrical properties of γ-Al₂O₃ on 4H-SiC.Al₂O₃ thin films were grown on chemically mechanically polished n-type 4H-SiC (0001) by atomic layer deposition (ALD) at 200-300°C using trimethylaluminum and water vapor. The films were fully-oxidized and stoichiometric with low carbon incorporation as evaluated by in-situ X-ray photoelectron spectroscopy (XPS). The as-deposited Al₂O₃ films were determined to be amorphous by in-situ reflection high-energy electron diffraction (RHEED). Annealing in ultra-high vacuum, N₂, and O₂ environments at 600-1100°C was investigated to control the Al₂O₃ film structure. Complete crystallization to γ-Al₂O₃ was observed by RHEED, XRD, and high-resolution transmission electron microscopy (HRTEM) analysis. An abrupt interface with 4H-SiC for both amorphous and crystalline Al₂O₃ was determined by HRTEM. The lack of an interfacial layer is critical to the formation of a high-quality crystalline interface. Based on the diffraction pattern, an epitaxial relationship of γ-Al₂O₃ (111) with 4H-SiC (0001) was observed. The film crystallinity was further confirmed by X-ray diffraction (XRD). The band alignment at the Al₂O₃/4H-SiC interface was determined experimentally by XPS and photoconductivity measurements, and compared to that predicted by density functional theory (DFT) calculations.Capacitance-voltage (C-V) and current-voltage (I-V) measurements of 4H-SiC MOS capacitors fabricated with 100-500 Å thick Al₂O₃ dielectric films were performed to compare the dielectric constant, fixed charge, density of interface states, and breakdown properties of epitaxial γ-Al₂O₃ films with respect to those of amorphous Al₂O₃ as well as state-of-the-art thermal oxides.

9:00 PM - B10.7

Laser PIN Diode Fabrication and Endotaxy of Silicon Carbide

Zhaoxu Tian ¹, Nathaniel Quick ², Aravinda Kar ¹
¹College of Optics and Photonics/CREOL , University of Central Florida, Orlando, Florida, United States, ², AppliCote Associates,LLC, Sanford, Florida, United States

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9:00 PM - B10.8

Electrical Properties of SiNx/4H-SiC MIS Capacitor and MISFET.

Zhao Pan ¹, Rusli Rusli ¹, Xia Jinghua ¹, Wang Hong ¹
¹School of EEE, Nanyang Technological University, Singapore Singapore

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9:00 PM - B10.9

Schottky Contact Formation in Carbon/4H-SiC Structures.

Senthil Sambandam ¹, Warren Collins ², Weijie Lu ^{1 2}
¹Department of Chemistry, Fisk University, Nashville, Tennessee, United States, ²Department of Physics, Fisk University, Nashville, Tennessee, United States

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2006-04-20 Show All Abstracts

Symposium Organizers

Michael A. Capano Purdue University

Michael Dudley State University of New York-Stony Brook

Tsunenobu Kimoto Kyoto University-Katsura

Adrian R. Powell Cree Inc.

Shaoping Wang Fairfield Crystal Technology

B11: SiC Contacts

Session Chairs

M. Capano

Thursday AM, April 20, 2006

Room 3004 (Moscone West)

9:00 AM - B11.1

Ion Implanted p⁺/n 4H-SiC Junctions: Effect of the Heating Velocity During the Post Implantation Annealing.

Roberta Nipoti ¹, Antonella Poggi ¹, Fabio Bergamini ¹, Mara Passini ¹
¹, CNR-IMM, Bologna Italy

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In ICSCRM’05 (Pittsburgh, Sept. 18-23, 2005) ion implanted p⁺/n 4H-SiC junctions with current voltage characteristics equal to those of epitaxial p-i-n diodes were presented. In this work those implanted junctions are compared with junctions made by equal implantation process, annealing temperature and annealing time but different heating velocity. This study allowed us to highlight the importance of the transient thermal cycle that precedes the post implantation annealing process.A 4H-SiC n-type epitaxial wafer, oriented <0001> 8° off-axis, was used. The doping and thickness of the epitaxial layer were 3×10¹⁵ cm^-3 and 5 mm, respectively. A selective area Al⁺ implantation in the n-type epitaxial layer was used for the p+ emitter regions that had doping and thickness equal to, respectively, 6×10¹⁹ cm^-3 and 164 nm. Diodes with area in the range 2×10^-4 - 1×10^-3 cm² were made. Implantation temperature was 400°C. The post implantation annealing process was done in high purity Ar ambient within an inductively heated furnace at 1600°C for 30 min. Two different heating velocities were compared: 7°C/sec and 35°C/sec. Several tens of diodes for each heating velocity were measured. The slow and the fast heating rumps gave diodes with emitter sheet resistances equal to, respectively, 85 kΩ (= 1.4 Ωcm) and 50 kΩ, (= 0.8 Ωcm), and with leakage currents at 100 V reverse bias equal to, respectively, 3×10^-10 A and 2×10^-12 A. This last was our instrumental current floor. By an instrumental set up with a lower current floor, i.e. 10^-15 A, the diodes annealed with the faster heating rump had reverse current of 10^-10 A/cm² at room temperature and 500 V reverse bias. This current became higher than 10^-9 Acm^-2 only at temperatures > 70°C. All the diodes annealed by the slow heating rump had a forward characteristics with a region of ideality factor > 2 when measured at room temperature. But the majority of the diodes annealed with the fast heating rump had ideality factor < 2. Only at sample temperatures > 200°C, these latter diodes showed a forward current region with excess recombination. In conclusion, faster was the heating velocity of the post implantation annealing: lower was the sheet resistance of the implanted emitter, weaker was the diode reverse leakage current and almost ideal was the diode forward characteristic, but the sheet resistivity of the p⁺ implanted layer was higher than that expected for an epitaxial layer of equal doping value and the junction forward characteristics showed an excess recombination current heating the sample. That can be explained hypothesizing that the electrical activation and/or the damage recovery of the implanted layer need to be further improved. This study shows that damage recovery during the heating transient of the post implantation annealing process is the phenomenon on which to focus our studies to improve the quality of ion implanted SiC junction.

9:15 AM - B11.2

Impact of EBAS annealing on sheet resistance reduction for Al-implanted 4H-SiC(0001).

Masami Shibagaki ¹, Akihiro Egami ¹, Akira Kumagai ¹, Kenji Numajiri ¹, Fumio Watanabe ², Shigetaka Haga ², Kuniaki Miura ², Shingo Miyagawa ³, Naohiro Kudoh ³, Tomoyuki Suzuki ³, Masataka Satoh ³
¹Advanced Technology Development, Canon ANELVA CORPORATION, Tokyo Japan, ²Development, Sukegawa Electric Co., LTD, Takahagi Japan, ³Research Center of Ion Beam Technology, Hosei Univrsity, Tokyo Japan

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9:30 AM - B11.3

Ti/AlNi/W Ohmic Contacts to P-Type SiC.

Bang-Hung Tsao ¹, Jacob Lawson ¹, James Scofield ²
¹Metals and Ceramics, University of Dayton Reserach Institute, Dayton, Ohio, United States, ², Air Force Reserach Laboratory, WPAFB, Ohio, United States

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Improved AlNi-based ohmic contacts to p-type 4H-SiC have been achieved using low energy ion (Al+) implantation, the addition of a thin Ti layer, and a novel two-step implant activation anneal process. Resistivities of 5x10-5 ohm-cm2 were reached by doping the surface region of lightly p-doped 4H-SiC epilayers via low energy Al+ implantation. Acceptor activation was achieved by annealing the samples with a 1400+1700C two-step sequence in an Ar atmosphere, which also yielded improved surface morphology when implanted samples were capped with photo resist during the anneals. AFM average roughness values improved by over 5X compared to samples without capping. The metallurgical morphology and contact resistivity remained intact even after annealing at 1100C, indicating good thermal stability. The Ti/AlNi/W contacts on implanted layers were compared to Ni2Si intermetallics and were found to be comparable to or superior in terms of specific contact resistivity, uniformity, and thermal stability. Ni2Si contacts exhibited significant potential for further work. Ti/AlNi/Au contacts were also studied which resulted in contact resistivities in the 5x10-4 ohm-cm2 range. Even though these values are an order of magnitude higher than those of the Ti/AlNi/W system, the reduced anneal temperature (650C) implies that Ti/AlNi/Au is a promising stacking configuration. The benefits of using Ge to reduce the anneal temperature necessary for ohmic behaviors was not observed in our investigation. On the other hand, benefits of a longer 30 minute anneal time at 600 – 700C, in either vacuum or atmospheric pressure Ar ambients was observed. Namely, the 2 minute annealing cycle used for the Ti/AlNi/W and Ti/Ni2Si/W study resulted in higher anneal temperatures before ohmic characteristics were seen. This same anneal time was not sufficient for the Ti/AlNi/Au samples, whereas increasing the cycle time to 30 minutes resulted in ohmic behavior at a much lower temperature. Increasing the anneal time however, had little or no impact on reducing the required anneal temperature of the Ti/AlNi/W and Ti/Ni2Si/W samples when the experiments were repeated.

9:45 AM - B11.4

Degradation of Ion-Implanted SiC pn Diodes and Current Gain in SiC BJTs

Anant Agarwal ¹, Sumi Krishnaswami ¹, James Richmond ¹, Craig Capell ¹, Sei-Hyung Ryu ¹, John Palmour ¹, Kenneth Jones ², Charles Scozzie ²
¹SiC Power Devices, Cree Inc., Durham, North Carolina, United States, ², Army Research Laboratory, Adelphi, Maryland, United States

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The reduction in the current gain of SiC BJTs has been observed after operating the devices for as little as 15 minutes. It is accompanied by an increase in the on-resistance of the BJT. There are three possible explanations for this effect. The current gain in a SiC BJT is strongly influenced by (a) the surface recombination in the region between the emitter and the base contact due to the surface states especially along the emitter side-walls, (b) the bulk recombination in the region between the emitter and the base contact implant due to the defects induced by the ion-implantation of Al to form the p+ regions and by the ohmic contact formation, and (c) the bulk recombination in the base-emitter space charge region. The degradation in current gain can be explained by an increase in recombination by any of these three mechanisms. The increase in bulk recombination (effects b and c) can be explained on the basis of what has been previously observed in SiC pn junction diodes. Basically, an increase in the forward voltage (Vf) of SiC PiN diodes was reported. This Vf increase was explained by the growth of stacking faults from certain basal plane dislocations within the drift layer of the PiN diode. The energy for this expansion of the stacking fault comes from the electron-hole recombination in the conductivity modulated drift layer. It is speculated that a similar phenomenon may be taking place in the SiC BJT device. The base of the transistor is flooded with electron-hole pairs during operation. The recombination of electron-hole pairs in the base gives rise to stacking faults which can grow in the base and extend into the collector region. These stacking faults reduce the life-time of the minority carriers locally in the base, which in turn results in reduced current gain. Experimental evidence will be presented and an attempt will be made to distinguish between different degradation mechanisms which may be simultaneously present in the device. Additionally, the effect of dislocation induced stacking faults on the forward and reverse characteristics of an ion-implanted SiC pn diode will be studied. This is the first report of the effect of ion-implantation on the degradation of pn junctions and the effect of degradation on the reverse leakage current of the pn diode.

10:00 AM - B11.5

Simultaneous Formation of Ohmic Contacts for Both n- and p-type 4H-SiC Using NiAl-based Contact Materials.

Susumu Tsukimoto ¹, Toshitake Onishi ¹, Kazuhiro Ito ¹, Masanori Murakami ¹
¹Materials Science and Engineering, Kyoto University, Kyoto Japan

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10:15 AM - B11.6

TiW/TiWN/Pt Ohmic Contacts to n-Type 3C-SiC.

Kirk Hofeling ¹, Loren Rieth ¹, Florian Solzbacher ¹
¹Electrical and Computer Engineering, University of Utah, Salt Lake City, Utah, United States

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10:30 AM - B11.7

Carbon Related Split-interstitials in SiC - a Challenge for Density Functional Theory.

Uwe Gerstmann ^{1 2}, Eva Rauls ^{1 3}, Mauricio Pinheiro ^{1 4}, Sigmund Greulich-Weber ¹, Francesco Mauri ⁴
¹Department of Physics, University of Paderborn, Paderborn Germany, ²Laboratoire de Mineralogie-Christallographie de Paris, Universite Pierre et Marie Curie, Paris France, ³Institute of Physics and Astronomy, University of Aarhus, Aarhus Denmark, ⁴Departamento de Fisica, Universidade Federal de Minas Gerais, Belo Horizonte Brazil

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Since dopant atoms hardly diffuse into SiC, other methods like ion implantation are the preferred doping methods, but result in various radiation-induced defects, which make doping ineffective. High temperature annealing is required to reduce these unwanted by-products. Valuable information of the annealing process can be gained from the unannealed samples, which provide good insight in the conditions before the annealing process. It is common consensus, that mobile split-interstitials, either intrinsic ones like the carbon splitinterstitial (CC)c or those in connection with dopants, e.g. (NC)c, play a central role in the beginning of the annealing process but these highly important defects can still not conclusively be assigned to experimentally observed EPR spectra. In the light of the reassignment of the EI5/EI6 centers to isolated carbon vacancies, some centers in electron irradiated p-type SiC which were originally assumed to be related to carbon vacancies have been reinterpreted: the carbon split-interstitial has been suggested tentatively for the so-called EI1/EI1 (S=1/2) [1, 2] as well as for the EI3/EI3 (S=1) centers [3]. In a recent work, hyperfine (hf) splittings due to a single interstitial 13C nucleus could be resolved in unannealed irradiated n-type 6H-SiC [4]. Based on Fermi level arguments, this so-called EIn triplet center was assigned to a single carbon split-interstitial (CC)c, most probable in its twofold positive charge state. However, calculations based on the usual local density approximation (LDA) in density functional theory (DFT) predict this charge state to be diamagnetic within a symmetric D2d configuration. After using a self-consistent scissors-operator technique to cope the gap-error (inferred by the spurious selfinteraction in LDA), however, the twofold positive split-interstitial (CC)c 2+ gives rise to a paramagnetic high-spin configuration revealing possible self-interaction related deficiencies of the LDA to describe the correct geometry of carbon-related split-interstitials. In this work, this observation is confirmed by additional calculations using self-interaction corrected (SIC) potentials. Explicitely self-interaction free functionals provide a paramagnetic state with tilted geometry in C1h symmetry and the calculated hf splittings are in nice agreement with experimental data. As a consequence, plain LDA and due to their incomplete self-interaction cancelation also hybrid functionals should be used with great caution to investigate these type of defects in semiconductor physics.[1] M. Bockstedte, M. Heid, A. Mattausch, and O. Pankratov, Mat. Sci. Forum 433-436 (2003), p. 471.[2] A. Gali, P.Deak, N.T. Son, E. Janzen, H.J. von Bardeleben, and J.-L. Monge, Mat. Sci. Forum 433- 436 (2003), p. 511. [3] T.T. Petrenko, T.L. Petrenko, and V.Y. Bratus, J. Phys. C 14 (2002), p. 1433. [4] M.V.B. Pinheiro et al., Mat. Sci. Forum (Proceedings of ICSCRM Pittsburgh 2005), in production.

10:45 AM - B11: Contacts

BREAK

B12: Bipolar and Other Devices

Session Chairs

S. H. Ryu

Thursday PM, April 20, 2006

Room 3004 (Moscone West)

11:00 AM - B12.1

Dual Mode Operation of a Pd/AlN/SiC Based Hydrogen Sensor

Md Rahman ¹, L Rimai ², R Naik ³, S Ng ¹, G Auner ², G Newaz ⁴
¹Chemical Engineering & Materials Science, Wayne State University, Detroit, Michigan, United States, ²Electrical and Computer Engineering, Wayne State University, Detroit, Michigan, United States, ³Physics and Astronomy, Wayne State University, Detroit, Michigan, United States, ⁴Mechanical engineering, Wayne State University, Detroit, Michigan, United States

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11:15 AM - B12.2

1.8 kV, 10 mOhm-cm2 4H-SiC JFETs

James Scofield ¹, Sei-Hyung Ryu ², Sumi Krishnaswami ², Anant Agarwal ²
¹AFRL/PRPE, Air Force Research Laboratory, WPAFB, Ohio, United States, ², CREE, Inc, Durham, North Carolina, United States

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A 4H-SiC vertical power JFET in 4H-SiC is a very attractive device for power switching applications because it offers high blocking voltage, low specific on-resistance, and fast switching characteristics. Since its structure lacks gate oxide layers, which is problematic in 4H-SiC devices, a 4H-SiC JFET can be used in very harsh environments without compromising its performance and reliability. In this paper, we present our latest result in high voltage 4H-SiC JFET development. A 12 μm thick, 5 x 1015 cm-3 doped n-type epilayer was grown on an n+, 4H-SiC substrate as the drift layer for the device. P-wells and the floating guard rings were formed by aluminum implantation, and n+ source regions were then formed by heavy-dose nitrogen implantations. The implants were activated at 1600 oC in silicon overpressure. Then, a 0.8 μm thick n-type epilayer with a doping concentration of 1.4x1017 cm-3 was grown as the lateral channel layer. The channel epilayer was then implanted with aluminum to form top p+ gate, which is annealed at 1600oC. The p+ implanted layer and n-channel epilayers were then patterned using a dry etching technique down to n+ source and p-well implants. A 0.6 μm thick PECVD oxide layer was then deposited and densified in dry O2 as field passivation. After opening the vias, Al/Ni ohmic contacts were formed on the n+ source, the p-wells, and the p+ gates regions, while Ni was used to form backside contact. The ohmic contacts were then covered with TaSi2 or Ta-Ru-N diffusion barrier layers to prevent deterioration of ohmic behavior at elevated temperatures. A 2 μm thick Ti/Pt/Au layer was evaporated and lifted-off to form overlayer and probing pads. Finally, a 0.3 μm thick silicon nitride layer was deposited and patterned as the final passivation and protection against oxidation.An on-resistance of 0.21 Ω (Ron,sp = 10 mΩ-cm2)was measured from a 4.65x10-2 cm2 4H-SiC JFET at room temperature with gate shorted to source. A pinch-off voltage of approximately –30 V was measured. The device was capable of blocking 1.8 kV with –40 V on the gate. The ideal parallel plate E-field at this voltage is approximately 2.1 MV/cm. Static and dynamic characteristics of the devices at elevated temperatures are currently in progress, and will be presented at the conference.

11:30 AM - B12.3

Studies Of The Effect Of Different Dislocation Types On The Performance Of Devices Fabricated On 4H-Sic Homoepitaxial Layers Using Synchrotron White Beam X-Ray Topography Based Techniques.

Hui Chen ¹, Balaji Raghothamachar ¹, William Vetter ¹, Michael Dudley ¹, Yu Wang ², Brian Skromme ²
¹Materials Science and Engineering, Stony Brook University, Stony Brook, New York, United States, ²Electrical Engineering, Arizona State University, Tempe, Arizona, United States

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11:45 AM - B12.4

Deep Level Defects Which Limit Current Gain in 4H SiC Bipolar Junction Transistors.

Corey Cochrane ¹, Patrick Lenahan ¹, Aivars Lelis ²
¹, The Pennsylvania State University, University Park, Pennsylvania, United States, ², US Army Research Laboratory, Adelphi, Maryland, United States

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There is considerable interest in the development of silicon carbide bipolar junction transistors (BJT) for high power and high temperature applications. Although considerable progress has been reported recently, most SiC BJTs exhibit relatively modest current gain, primarily due to the presence of rather high density of recombination centers in the transistor base. [1] In this study, we have utilized a very sensitive electrically detected electron spin resonance (ESR) technique to detect and identify these recombination centers in fully processed 4H SiC BJTs. The electrically detected ESR technique, spin dependent recombination (SDR), allows direct detection of recombination centers via observation of spin dependent changes in recombination dominated currents. Our measurements involve 4H SiC npn power transistors with epitaxial emitters. These devices were fabricated by Cree Corporation. We observe multiple line SDR detected ESR spectra with a strong central line with a near isotropic or isotropic g ≈ 2.003 and at least four other (considerably weaker) lines. The g is a second rank tensor defined by g = hυ/βH, where h is Planck’s constant, υ is the microwave frequency, β is the Bohr magneton, and H is the magnetic field at resonance. We tentatively link the strong center line to an intrinsic defect (involving only carbon and silicon atoms) most likely a vacancy center. We link several somewhat weaker spectra (which occur at fields 50 to 100 G) away from the strong center line to paramagnetic defects involving nuclear magnetic moments (for example of 14N or 1H). We find that the SDR response is a strong function of device bias. The SDR versus device bias, for example base/collector bias provides strong evidence that the observed spectra are due to deep level centers in the base of these BJTs. Our results demonstrate that several defects play important roles in limiting the current gain in the SiC BJTs and strongly suggest that an intrinsic defect, likely a vacancy, plays a dominating role in the base recombination. Most importantly, our results clearly demonstrate by the electrically detected ESR technique of SDR has great potential in the exploration of BJT performance limiting defects in wide band gap semiconductor materials such as SiC. [1] A.K. Agarwal, S-H Ryan, J. Richmond, C. Capell, J. Palmour, S. Balachandran, T.P. Chow, ISPSD Proceedings, (2003) p.135.[2] A.K. Agarwal, S-H Ryan, J. Richmond, C. Capell, J. Palmour, S. Balachandran, T.P. Chow, B. Geil, S. Bayne, C. Scozzie, and K.A. Jones, ISPSD Proceedings, (2003) p.361.

12:00 PM - B12.5

Demonstration of a Two Dimension Electron Gas in 3C/4H-SiC Polytype Heterojunctions.

Chris Thomas ¹, MVS Chandrashekhar ¹, Michael Spencer ¹
¹Electrical and Computer Engineering, Cornell University, Ithaca, New York, United States

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12:15 PM - B12.6

Thermal Detection Mechanism Of Sic-Based Resistive Gas Sensors.

Timothy Fawcett ¹, Meralys Reyes-Natal ^{1 2}, Anita Lloyd Spetz ³, Stephen Saddow ², John Wolan ¹
¹Chemical Engineering, University of South Florida, Tampa, Florida, United States, ²Electrical Engineering, University of South Florida, Tampa, Florida, United States, ³S-SENCE and Division of Applied Physics, Linkoping University, Linkoping, Linkoping, Sweden

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Silicon carbide-based resistive gas sensors from our laboratory have been previously reported to detect hydrogen at concentrations ranging from less than 1% to 100% H₂ in Ar and at temperatures ranging from 50°C to 450°C. The gas sensing mechanism for these devices was not well understood, hindering further improvement in this technology. In this study, resistive devices built on a thin 3C-SiC epitaxial layer grown on silicon-on-insulator (SOI) were used to explore the gas sensing mechanism. A thin 150Å Si layer was wafer bonded to a polycrystalline SiC substrate using an oxide adhesion layer. The Si film was then converted to 3C-SiC using a hot-wall CVD deposition process resulting in a 3C-SiC on poly-SiC material structure. The gas sensing devices consisted of rectangular ohmic NiCr contacts with a Au overlayer measuring 0.25-2mm x 0.25-2mm with a gap of 0.25-2mm fabricated on the 3C-SiC layer. Under a constant dc bias, ranging from 0.5-10V, these sensors demonstrated an increase of current ranging from 13.5μA to 2.6mA upon the introduction of 40% H₂ in N₂ to the test gas stream with no external heating of the device. The sensor’s response to 40% H₂ in N₂ was increased to 150mA by heating the device to 500°C and applying a 10 V dc bias. The time to full response for these sensors was ~ 20 seconds. Sensor response to concentrations ranging from 2% to 100% H₂ or CO₂ in N₂ was repeatable and showed long-term stability. Insight into the gas sensing mechanism for these resistive gas sensors was achieved by monitoring the temperature of the device during H₂ sensing. Upon the introduction of 40% H₂ in N₂ to the sensing environment, the device temperature, as measured by an RTD in intimate thermal contact with the device, decreased from 0.6-100°C depending on the initial device temperature and the constant dc bias applied to the sensor. The device temperature changes upon the introduction of H₂ to the sensing environment due to the difference in thermal conductivity of H₂ (168.35 mW/(m.K)) and N₂ (24 mW/(m.K)). Details of the device performance and a model of the sensing mechanism will be discussed.

12:30 PM - **B12.7

SiC Power Devices – Progress and Impact.

Hsueh-Rong Chang ¹
¹, International Rectifier, El Segundo, California, United States

Show Abstract

B13: SiC MOS devices

Session Chairs

Mrinal Das

Thursday PM, April 20, 2006

Room 3004 (Moscone West)

2:30 PM - B13.1

Reliability of High Voltage 4H-SiC MOSFET Devices.

Sumi Krishnaswami ¹, Sei-Hyung Ryu ¹, Bradley Heath ¹, Anant Agarwal ¹, John Palmour ¹, Aivars Lelis ², Charles Scozzie ², James Scofield ³
¹, Cree, Inc., Durham, North Carolina, United States, ², Army Research Laboratory, Adelphi, Maryland, United States, ³, Air Force Research Laboratory, Dayton, Ohio, United States

Show Abstract

The development of SiC power MOSFETs in fast switching applications has come a long way. At Cree, DMOSFETs with a record low value for the specific on-resistance (8 mΩ-cm2) and superior switching performance has been recently demonstrated [1]. Device reliability and stability are now being studied. This paper presents the gate oxide reliability and device stability of 1200 V, 5 A 4H-SiC DMOSFETs. The concerns about the gate oxide reliability stem from the fact that the barrier height from the SiC conduction band (CB) to the oxide CB is only 2.7 eV as compared to 3.1 eV in a silicon MOS system. The reduced barrier results in Fowler-Nordheim tunneling of the carriers into the oxide from the CB of SiC under high electric fields and temperature [2].In 4H-SiC power MOSFET, there is concern about MOS reliability under the following two conditions: (1) on-state of the MOSFET, in which high electric field exists in the oxide overlapping the n+ source regions due to the application of high positive gate bias, and (2) off-state in which the oxide in the JFET region and in the edge-termination regions are stressed under high electric field. Therefore for a reliable operation, the power MOSFET requires a high performance MOS channel and a reliable gate dielectric. Gate oxide reliability measurements of 4H-SiC DMOSFETs were performed using the Time Dependent Dielectric Breakdown (TDDB) technique at 175C. The oxide lifetime is then plotted as a function of electric field. The results show the projected oxide lifetime to be >100 years at a operating field of ~3 MV/cm. Device reliability of packaged DMOSFETs were studied by stressing the device under three conditions: (a) Gate stress - a constant gate voltage of +15 V is applied to the gate at a temperature of 175C. The forward I-V characteristics and threshold voltage are monitored for device stability, (b) Forward current stress – devices are stressed under a constant drain current of 4 A and Vg = 20 V. The devices are allowed to self-heat to a sink temperature of 125C and the I-Vs monitored with time, and (c) High temperature reverse bias (HTRB) testing at 1200 V and 170C to study the reliability of the devices in the off-state. Our first measurements on (a) and (b) show very little variation between the pre-stress and post-stress I-V characteristics and threshold voltage up to 1000 hrs of operation at 175C, indicating excellent stability of the DMOSFETs in the on-state. The devices also seem to be very reliable with respect to HTRB stress.AcknowledgementThis research was funded through the Cooperative Agreement W911NF-04-2-0022 program supported by Army Research Laboratory and AFRL TIA # FA8650-04-2-2410 monitored by Dr. J. Scofield.References[1] S-H. Ryu, S. Krishnaswami, B. Hull, B. Heath, M. Das, J. Richmond, A. Agarwal, J. Palmour, J. Scofield, presented at ICSCRM 2005 in Pittsburgh, Sept 2005.[2] A.K. Agarwal, S. Seshadri, L.B. Roland, IEEE Elec. Dev. Letters, Vol. 18, 1997, 592-594.

2:45 PM - B13.2

4H-SiC p-channel MOSFET Development for CMOS Applications.

Brett Hull ¹, Sei-Hyung Ryu ¹, Mrinal Das ¹, Sumi Krishnaswami ¹, James Richmond ¹, Bradley Heath ¹, John Palmour ¹, James Scofield ²
¹, Cree, Inc., Durham, North Carolina, United States, ², Air Force Research Laboratory, Wright-Patterson AFB, Ohio, United States

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3:00 PM - B13.3

Large Area Vertical 3C-SiC MOSFET Devices

Adolf Schoner ¹, Mietek Bakowski ¹, Per Ericsson ¹, Helena Stromberg ¹, Hiroyuki Nagasawa ², Masayuki Abe ²
¹, Acreo AB, Kista Sweden, ², Hoya Advanced Semiconductor Technologies Co., Ltd., Sagamihara Japan

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3C-SiC is a promising material for medium power (600 V or 1200 V, 10–100 A) MOSFET devices. High channel mobility values of up to 250 cm²/Vs have been reported. The high channel mobility is attributed to a compared to 4H-SiC reduced density of charged states at the SiO₂/3C-SiC interface. A commercial advantage of 3C-SiC is the possibility to use large diameter silicon substrates for the 3C-SiC wafer manufacturing. Vertical DMOSFET devices with varying size from single cell to 3x3 mm² large devices have been processed using 3C-SiC wafers with 10 µm thick, 5e15 cm^-3 doped n-type epilayers. The devices had hexagonal and square unit cell designs with 2 µm and 4 µm channel length. The p-body was Al-implanted with a maximum doping of 1e18 cm^-3 and a box profile depth of 1 µm. The source was P-implanted with a box profile doping of 4e19 cm^-3 and a depth of 0.4 µm. The gate oxide was thermally grown during 90min at 1100 °C in dry oxygen followed by a 3 hours 950 °C post-oxidation anneal in wet oxygen. The resulting oxide thickness was about 60nm. The gate contact was formed by Al-deposition. As deposited Ti/W contacts were used for the source and drain ohmic contacts. Any thermal treatment with temperatures above 400 °C was avoided after the gate oxidation to prevent degradation of the SiO₂/3C-SiC interface. The devices were terminated by either implanted Al-doped rings (ring termination) or not contacted cells (cell termination). The investigated vertical DMOSFET devices have blocking capability of 100 V at leakage currents below 1 mA. The blocking capability deteriorates with increasing number of cells due to increasing device leakage. A correlation of increased leakage current with the number of extended crystal defects in the device area has been observed. In general, devices with ring termination gave higher blocking voltages compared to devices with the same number of active cells and cell termination. The as-deposited Ti/W metal resulted in good ohmic contacts to source and drain. The specific on-resistance was 17 mΩcm² and 34 mΩcm² for 2 µm and 4 µm channel length, respectively. The on-resistance is dominated by the channel and the contact resistance is negligible. 1x1 mm² devices can handle currents of 2 A with gate voltages of 15 to 20 V. It is expected that 3x3 mm² devices work with on-state currents above 10 A. The drain current and the leakage current scale linearly with the device size.Although the extracted interface states values are of the order of 1e13 cm^-2eV^-1, channel mobility values of around 40 cm²/Vs were observed. The channel mobility shows saturation and behaves as expected with increasing gate voltage. The linear scaling of the DMOSFET performance with the device area together with the demonstrated high current handling capability confirms the potential of 3C-SiC for the fabrication of medium power, large area MOSFET devices.

3:15 PM - **B13.4

950V, 8 mΩ-cm2 High Speed 4H-SiC Power DMOSFETs

Sei-Hyung Ryu ¹, Charlotte Jonas ¹, Bradley Heath ¹, Anant Agarwal ¹, John Palmour ¹
¹, Cree, Inc., Durham, North Carolina, United States

Show Abstract

Power MOSFETs in 4H-SiC are very attractive for power switching applications because of their low specific on-resistances, higher operating temperatures, and normally-off characteristics. It should also be noted that the device size of a 4H-SiC DMOSFET is approximately 1 % of that of a silicon device with the same blocking voltage and on-resistance because of their low specific on-resistance. As a result, a 4H-SiC DMOSFET can demonstrate extremely fast switching times and very low switching losses, making it very attractive for high frequency ( > 10 MHz) power applications. In this paper, we present our latest results in high speed 4H-SiC power DMOSFET developments.A 6 μm thick, 1.2E16 cm-3 doped n-type epilayer was grown on an n+, 4H-SiC substrate as the drift layer for the device. P-wells were formed by aluminum implantation, and n+ source regions were then formed by a heavy-dose nitrogen implantation. The MOS channel length, defined be the distance between the edges of the p-well and the n+ source implants, was approximately 0.5 μm. A cell pitch of 12 μm was used, and the MOS channel density (W/L per unit area) was around 8.3E6 cm-2. A heavy dose aluminum implantation formed p+ contacts to the p-wells as well as the floating guard rings. All the implants were activated at 1600 C in silicon overpressure. A 0.6 μm thick PECVD oxide layer was then deposited and patterned as the field oxide. A 500 A thick gate oxide layer was thermally grown at 1175 C in dry O2, then nitrided at 1175 C in NO. A degenerately doped polysilicon layer was deposited and patterned as gate electrode. The ohmic contacts to source, drain, and p+ regions were formed with annealed Ni. A 3 μm thick aluminum layer was evaporated and lifted-off to form metal overlayer and probing pads, and an 8 μm thick polyimide layer was applied as the final surface passivation layer. A peak effective channel mobility of 18 cm2/Vs, and a threshold voltage of 6 V were measured from a test MOSFET (W/L = 150 μm / 150 μm) built on a p-well adjacent to the power DMOSFET. At room temperature, a 4H-SiC DMOSFET with an active area of 0.012 cm2 showed an on-resistance of 0.66 Ω , which corresponds to a specific on-resistance of 8 mΩ-cm2 at a gate bias of 15 V (Eox = 3 MV/cm). The device showed stable avalanche characteristics at a drain bias of 950 V with the gate shorted to the source. The ideal parallel plate E-field at this voltage is approximately 2.3MV/cm. The device showed a rise time of 8.6 ns and a fall time of 58 ns in a resistive switching configuration (500 V supply voltage and 250 Ω load resistor). Characterizations at elevated temperatures and inductive load switching measurements are in progress, and the results will be presented at the conference.

3:45 PM - B13.5

Time-Dependent Bias Stress-Induced Instability of SiC MOS Devices.

Aivars Lelis ¹, D. Habersat ¹, B. Simons ¹, F. Olaniran ¹, J. McGarrity ², F. McLean ², N. Goldsman ³
¹, U.S. Army Research Lab, Adelphi, Maryland, United States, ², Berkley Associates, Springfield, Virginia, United States, ³, University of Maryland, College Park, Maryland, United States

Show Abstract

We have observed a gate-bias stress-induced instability in both the flatband capacitance of SiC MOS capacitors and in the threshold voltage of SiC MOSFETs. The magnitude of this bias stress-induced instability increases linearly with log time, with no saturation of the effect observed, even out to 10,000 seconds. A positive gate-bias stress causes a positive shift and a negative gate-bias stress causes a negative shift, consistent with charge tunneling into or out of oxide traps near the SiC / SiO2 interface as opposed to mobile ions drifting across the gate oxide. The observed instability effect involves as much as 20 percent of the total “fixed” or oxide trapped charge present—even at room temperature. For example, we have observed flatband instabilities in capacitors, with oxide thicknesses of 600 Å, of about 0.6 V at 10,000 s, which represents a change in charge of about 2E11. The total oxide trapped charge in these samples has been determined to be around 1E12. (The flatband instability in these samples after only 100 s of stressing is less than 0.3 V, which represents a change in charge of about 1E11, or 10 percent of the total trapped charge present.) The gate fields applied are relatively small (< 3 MV/cm) and the effect is repeatable. Not only do we see similar instabilities in both capacitors and MOSFETs, but similar effects have been observed in both 4H and 6H material, in both thermal and deposited oxides, on both as-grown and implanted epi, and from various manufacturers. If charge tunneling is in fact the mechanism causing this instability, then the linear increase with log time implies an even distribution of traps several nm into the oxide. This is also the range over which the presence of C and strained SiO2 has been reported. It is important to understand the cause of these instabilities because they not only affect threshold voltage but also affect both the actual mobility, due to charge scattering from traps close to the interface, and the effective mobility, by changing the number of free carriers in the channel.

4:00 PM - B13: MOS

BREAK

B14: Oxide and Other Dielectrics

Session Chairs

A. Schoner

Thursday PM, April 20, 2006

Room 3004 (Moscone West)

4:30 PM - **B14.1

The SiC-Dielectric Interface.

S. Dhar ¹, S. Choi ¹, L. Feldman ¹, K. Yellai ², S. Wang ², M Park ², J. R. Williams ²
¹Physics, Vanderbilt University, Nashville , Tennessee, United States, ²Physics, Auburn University, Auburn, Alabama, United States

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5:00 PM - B14.2

Oxygen Transport and Exchange During Dry Thermal Oxidation of 6H-SiC.

Claudio Radtke ¹, Gabriel Soares ¹, Fabiane Trombetta ¹, Israel Baumvol ^{2 3}, Fernanda Stedile ⁴
¹PGMICRO, UFRGS, Porto Alegre Brazil, ²CCET, Universidade de Caxias do Sul, Caxias do Sul Brazil, ³Instituto de Fisica, UFRGS, Porto Alegre Brazil, ⁴Instituto de Quimica, UFRGS, Porto Alegre Brazil

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5:15 PM - B14.3

Alternative Magnesium Calcium Oxide Gate Dielectric for SiC MOS Application

D. Stodilka ¹, R. Davies ¹, A. Gerger ¹, B. Gila ¹, C. Abernathy ¹, S. Pearton ¹, F. Ren ²
¹Materials Science and Engineering, University of Florida, Gainesville, Florida, United States, ²Chemical Engineering, University of Florida, Gainesville, Florida, United States

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5:30 PM - B14.4

Evaluation of HfO₂ Gate Dielectrics for 4H-SiC MOS Devices

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