Chairs
Steven Binari
Naval Research Laboratory
Code 6855
Washington, DC 20375-5320
202-404-4616
Albert Burk
ESSD
Northrop Grumman Corporation
Pittsburgh, PA 15235-5098
412-256-2061
Michael Melloch
School of Electrical & Computer Engr
Purdue University
1286 Electrical Engr Bldg
West Lafayette, IN 47907-1285
317-494-3528
Chanh Nguyen
HRL Labs
MS RL61
Malibu, CA 90265
310-317-5605
Symposium Support
*Air Force Research Laboratory
*Army Research Office
*DARPA
*ODDR&E
Proceedings published as Volume 572
of the Materials Research Society
Symposium Proceedings Series.* Invited paper
SESSION Y1: SiC DEVICES AND PROCESSING I
Chairs: Michael R. Melloch and Suresh Seshadri
Monday Morning, April 5, 1999
Golden Gate A2 (M)
8:30 AM *Y1.1
SiC POWER ELECTRONIC DEVICES, MOSFETS AND RECTIFIERS. James A. Cooper , Sei-Hyung Ryu, Yu Li, Maherin Matin, Jan Spitz, Dallas Morisette, Mrinal K. Das, Michael R. Melloch, Michael A. Capano and Jerry M. Woodall, Purdue University, School of Electrical and Computer Engineering, West Lafayette, IN.
SiC unipolar power devices such as power MOSFETs and Schottky rectifiers are strong candidates for high-frequency switching applications because they exhibit little or no reverse recovery current, leading to minimal switching energy loss. This is significant because in high-frequency switching applications, the switching energy may become the dominant loss in the system. SiC power MOSFETs have made rapid progress over the last several years. Blocking voltage has increased from about 60 V in 1992 to 2,6000 V in 1997. The figure-of-merit = BV2/R has also steadily increased, and by early 1998 the of SiC UMOSFETs was about 25x higher than the silicon theoretical limit. This improvement is a result of innovations in device structure designed to protect the gate oxide from high electric fields in the blocking state. Similar progress has also been made in SiC Schottky rectifiers, where is now about 130x higher than the silicon theoretical limit. Blocking voltage in SiC Schottky rectifiers now stands at about 1700 V, and reverse leakage in Ni Schottky diodes is less than 1 mA/cm2 out to about 1200 V reverse bias. 4H-SiC Schottky rectifiers have been tested in IGBT switching circuits driving inductive loads at 6A and 300 V, and they reduce the switching loss by a factor of four compared to silicon PiN diodes. It is expected that the first commercial application of SiC power devices will be Schottky rectifiers for electronic motor control applications. A number of materials issues remain to be resolved before commercial introduction of SiC MOSFETs or Schottky rectifiers will be economically feasible. These include activation of p-type implants without surface damage, improvement of MOS inversion layer mobility, better understanding of the role of defects and dislocations on device performance, and improvements in surface polish to eliminate irregularities that reduce breakdown voltage in Schottky diodes.
9:00 AM *Y1.2
RECENT PROGRESS IN SiC MICROWAVE MESFETS. S.T. Allen , W.L. Pribble, R.A. Sadler, T.S. Alcorn, Z. Ring and J.W. Palmour, Cree Research, Durham, NC.
Cree has recently made substantial progress in fabricating SiC microwave MESFETs for high power applications. A peak power density of 4.0 W/mm was measured with an on-wafer load pull system from a 0.84-mm device. Operating at a drain bias of 60 V, this FET had a peak power of 3.4 W, a Class A PAE of 39% and an associated power gain of 12.5 dB. A power density of over 4 W/mm was also measured from a 0.25-mm MESFET at 10 GHz, with a peak power of 1.1 W, a Class A PAE of 20% and an associated gain of 9 dB. Cree has also successfully fabricated large periphery MESFETs that were able to be operated at a 60 V bias, demonstrating the high quality of the material and the uniformity of the process. A single device with 48-mm of gate periphery was packaged in a carrier with input and output matching networks fabricated with alumina, and produced 80 watts CW at 3.1 GHz with 37% PAE. Cree has recently transitioned its MESFET process to two-inch semi-insulating SiC substrates, and is continuing to develop this technology for applications from UHF through X-band.
9:30 AM Y1.3
THE EFFECTS OF DAMAGE ON HYDROGEN-IMPLANT- INDUCED THIN-FILM SEPARATION FROM BULK SILICON CARBIDE. R.B. Gregory , T.A. Wetteroth, S.R. Wilson, Motorola Inc., Semiconductor Products Sector, Tempe, AZ; O.W. Holland, D.K. Thomas, Oak Ridge National Laboratory, Solid State Division, Oak Ridge, TN.
Exfoliation of silicon carbide by hydrogen implantation and subsequent annealing forms the basis for a thin-film separation process which, when combined with oxidation and hydrophilic wafer bonding, can be exploited to produce silicon-carbide-on-insulator, SiCOI. This material is potentially useful as a wide bandgap semiconductor for power applications. It is known that silicon carbide thin films produced by this process exhibit unacceptably high resistivity because defects generated by the hydrogen implant neutralize electrical carriers. Thin-film separation occurs because of chemical interaction of hydrogen with dangling bonds within microvoids created by the implant, and physical stresses due to gas-pressure effects during post-implant anneal. While experimental results show that exfoliation of silicon carbide is dependent upon the concentration of implanted hydrogen, the authors observe that the damage generated by the implant can, in fact, severely retard exfoliation. This behavior is attributed to excessive damage at the projected range of the implant which interferes with the physical processes associated with implant-induced cleaving. However, damage can be controlled independently of hydrogen dosage by elevating the temperature of the silicon carbide during the implant in order to promote dynamic annealing. It will be shown that high-temperature irradiation reduces the hydrogen fluence required to affect efficient separation of a thin film. The reduced hydrogen dosage, in turn, results with a thin-film containing fewer defects that passivate carriers. The greater efficacy of high-temperature implantation in achieving thin-film separation is attributed to the details of the damage morphology and concentration, which will be discussed. The effect is to increase the potential for producing SiCOI which is sufficiently free of defects and, thus, more easily electrically activated.
9:45 AM Y1.4
CHARACTERIZATION OF SiO2/SiC SAMPLES USING PHOTOELECTRON SPECTROSCOPY. L.I. Johansson , P.A. Glans and Q. Wahab, Department of Physics, Linköping University, Linköping, SWEDEN; T.M. Grehk, Th. Eickhoff and W. Drube, Hamburger Synchrotronstrahlungslabor HASYLAB am Deutschen Elektronen-Synchrotron DESY, Hamburg, GERMANY.
The defect density at the oxide/semiconductor interface is an important factor for the performance of devices. For SiO2/SiC the interface defect densities obtained to date are relatively high and one limiting factor for the formation of a high quality oxide is considered to be a carbon containing by-product at the interface. Characterizations of oxide layers thermally grown on SiC have earlier been reported (using XTM, AES and XPS) and indicated a homogeneous SiO2 layer free from carbon related compounds except for a region very close to the interface. We have utilized synchrotron radiation in efforts to investigate the SiO2/SiC interface using photoemission. Samples with oxide layers, around 50 thick, thermally grown on n-type 4H-SiC substrates were studied. Firstly, by using a high photon energy (3.0 keV) a direct and simultaneous probing of the SiC substrate, the interface and the oxide layer could be made. The probing depth was varied by changing the electron emission angle. Recorded Si 2p and C 1s core level spectra each showed two components. The relative intensity of these components were extracted and compared to calculated intensity variations assuming different models for the elemental distribution. The analysis showed that the additional graphite like C 1s component observed in recorded spectra originated from a carbon layer on top of the oxide and not at the interface. Secondly, the samples were investigated using lower photon energies, giving a much smaller probing depth. The composition in the topmost surface region was then investigated after successive Ar+ - sputtering cycles. This gave the same results, i.e. that contribution from graphite like carbon on top of the oxide but not at the SiO2/SiC interface could be identified.
10:30 AM Y1.5
ANNEALING OF ION IMPLANTATION DAMAGE IN SiC USING A GRAPHITE MASK. Chris Thomas , Crawford Taylor, James Griffen, M.G. Spencer, Materials Science Center of Excellence, Howard University, School of Engineering, Washington, DC; Kevin Kornegay, Department of Electrical Engineering, Cornell University, Ithaca, NY; Mike Capano, School of Engineering and Computer Science, Purdue University, West Lafayette, IN; S. Rendakova, TDI, Inc., Gaithersburg, MD.
High temperature annealing of SiC is required to remove damage done by ion implantation, particularly, p-type implantation using Al or Boron. There appears to be a consensus that annealing temperatures in excess of 1700 C are required to completely remove damage during p-type ion implantation. At these temperatures the surface of SiC is degraded and severe step bunching has been observed (particularly in the implanted regions). In order to prevent the degradation of the SiC surface at high temperatures a mask could possibly be used to prevent Si evaporation and atomic motion. One possible mask that has been proposed is AlN, however, this material may not be able to withstand temperatures greater than 1600 C, and there are issues concerning the auto doping of Al. Another candidate mask material is graphite. In this presentation, we will present our results using graphite as a high temperature annealing mask. A graphite mask can be formed by graphitizing photo resist material. Utilizing this technique a mask of varying thickness can be produced. We have annealed samples of virgin and implanted SiC substrates at 1700 C in a He atmosphere using these graphite masks. The mask is removed after anneal by exposure to oxygen at 800 C for about 1 hour. This oxidation temperature is low enough so that the oxidation of the underlying SiC is minimal. The material after annealing, has been examined by optical microscopy, as well as Atomic Force Microscopy (AFM), the surface showed no degradation or step bunching due to the annealing process. Preliminary electrical measurements on boron implanted into n-type 4H-SiC substrates indicated p-type activation. Details of these measurements will be presented.
10:45 AM Y1.6
EFFECT OF VARYING OXIDATION PARAMETERS ON THE GENERATION OF C-DANGLING BOND CENTERS IN OXIDIZED SiC. P.J. Macfarlane and M.E. Zvanut, University of Alabama at Birmingham, AL.
SiC is perhaps the most appropriate material to replace Si in power-metal-oxide-semiconductor-field-effect-transistors (MOSFETs), because, unlike the other wide band-gap semiconductors, SiC can be thermally oxidized similarly to Si to form a SiO2 insulating layer. In our studies of oxidized SiC, we have used electron paramagnetic resonance (EPR) to identify C-dangling bonds generated by hydrogen release from C-H bonds. While hydrogen's effect on SiC-based MOSFETs is uncertain, studies of Si-based MOSFETs indicate that it is important to minimize hydrogen in MOS structures. To examine the role of hydrogen, we have studied the effects of SiC/SiO2 fabrication on the density of C-related centers, which are made EPR active by a dry heat-treatment. We observed that the creation of C-dangling bonds is independent of the polytype used. Centers can be generated in oxidized, dry heat-treated 3C-SiC epilayers deposited on Si substrates as well as oxidized single and double side polished 4H-SiC and 6H-SiC wafers. Dry heat-treatment in an inert ambient (N2) or an oxidizing ambient (O2) produces approximately the same density of centers. The generation of centers does not depend on the oxidation time. The parameters that appear to have the greatest effect on center density are the starting and ending steps of our oxidation procedure. For example, samples that were inserted and removed from the furnace in flowing O2did not produce the center after dry heat-treatment. We will report on the details of these experiments and use our results to suggest an oxidation procedure that limits center production. This work is supported by ONR grant no. N00014-96-2-1238. P.J. Macfarlane is supported by a fellowship from the Alabama Space Grant Consortium. We thank Cree Research, Inc. and HOYA Corp. for the SiC samples.
11:00 AM Y1.7
THICK OXIDE LAYERS ON N AND P SiC WAFERS BY A DEPO-CONVERSION TECHNIQUE. Q. Zhang , I. Khlebnikov, V. Madangarli, S. Soloviev and T.S. Sudarshan, Department of Electrical Engineering, University of South Carolina, Columbia, SC.
The thickness of oxide layers on SiC wafers that can be obtained by thermal oxidation is limited due to the slow oxidation rate of SiC compared to that of Si. In this paper we present the electrical properties of thick oxide layers (upto 10,000 angstrom) on N and P-type 6H-SiC wafers obtained by a depo-conversion technique based on thermal oxidation of Si films deposited on the SiC wafers by R.F magnetron sputtering of undoped Si from single crystal Si target. Since the oxide thickness is determined by the thickness of the Si film, it is possible to obtain any desired oxide layers thickness by controlling the thickness of the deposited Si film. This minimizes the influence of the SiC substrate properties such as, polytype nature (6H vs 3C), orientation (C-axis, A-axis etc.), wafer face (Si vs C) etc. on the variations in oxide quality and thickness. Also, it is possible to grow very thick oxide layers by successive application of this depo-conversion technique. SiC MOS capacitors with different oxide thickness were fabricated and characterized to determine the quality of the grown oxide. In order to improve the oxide-semiconductor interface, a thin thermal oxide was grown on some wafers prior to the Si sputter deposition. High frequency capacitance-voltage measurements on MOS capacitors with a 2000 angstrom thick composite oxide (with a thin thermal oxide interface) indicated an effective charge density comparable to that of MOS capacitors with a 300 angstrom thick thermal oxide. The breakdown field of the depo-converted oxide obtained using a ramp response technique indicates a good quality oxide with average values in excess of 6 MV/cm. A high-voltage (1000 V) schottky diode on p-type SiC was demonstrated using an 6000 angstrom thick depo-converted oxide layer for edge termination by metal-overlap. Thus the thick oxide layer growth by depo-conversion technique shows promise for various applications in the fabrication of high power SiC devices.
11:15 AM Y1.8
BIAS-STRESS INDUCED CHANNEL MOBILITY IMPROVEMENT IN 4H-SiC MOSFETs. K. Chatty , T.P. Chow, R.J. Gutmann, Center For Integrated Electronics and Electronics Manufacturing, Rensselaer Polytechnic Institute, Troy, NY; E. Arnold, D. Alok, Philips Research, Briarcliff Manor, NY.
The electrical properties of the current state-of-the-art SiC-SiO2 interfaces are inferior to those of silicon. The densities of oxide charges and interface states are much higher than at the Si-SiO2 interface resulting in poor transconductance and inversion-layer mobility. The understanding and control of the characteristics of SiC-SiO2 interface is therefore crucial to the realization of practical SiC MOS devices. In this work, we report an investigation of a bias instability which affects the channel mobility in SiC MOSFETs. Lateral n-channel MOSFETs with different gate oxide thicknesses were fabricated on 4H-SiC. The initial field effect mobility was extracted from the IDS-VGS characteristics, and values of flat band voltage were obtained from the C-V measurements on MOS capacitors located on the same wafer. The devices (MOSFETs and capacitors) were subjected to a bias-temperature stress for 30 minutes at 150o at stress voltages corresponding to oxide fields as high as 1MV/cm. The shifts in the threshold voltage and flat band voltage were consistent with ionic drift in the oxide. Following a positive bias stress, the field effect mobility was found to increase by 2 orders of magnitude from the original value. Upon application of a negative bias stress to the MOSFET, the device characteristics were degraded compared to the unstressed device. The high mobility state could be recovered by a positive bias stress and was found to be reversible with repeated bias stressing. A possible explanation of this phenomenon in terms of changes in the interface state occupancy resulting from passivation by interfacial ions is proposed. Acknowledgements: This work is supported by Philips Research, Briarclif Manor, NY, USA and MURI of the Office of Naval Research.
11:30 AM Y1.9
FULL BAND MONTE CARLO SIMULATION OF SHORT CHANNEL MOSFETs IN 4H AND 6H-SiC. Mats Hjelm , Hans-Erik Nilsson, Ervin Dubaric, C. Sture Petersson, Department of Information Technology, Mid-Sweden Univ, Sundsvall, SWEDEN; Peter Kaeckell, Institut fuer Festkoerpertheorie und Theoretische Optik, Jena, GERMANY; Clas Persson, Department of Physics and Measurement Technology, Linkoeping Univ, Linkoeping, SWEDEN.
A full band Monte Carlo study, which compares electron transport and device performance for 4H and 6H-SiC short channel MOSFETs is presented. The objective is to give accurate estimations under ideal conditions, i.e. a good semiconductor-oxide interface and high quality epitaxial layers. Both 4H and 6H-SiC has a discontinuous energy spectrum in the conduction band along the c-axis direction, which results in limited carrier heating due to the electric field. This band structure effect can be an advantage in a short channel MOSFET, since it reduces the probability for threshold voltage degradation due to hot electrons injected into the oxide. The combination of a low mean energy and high saturation velocity is a very promising feature for both 4H and 6H-SiC. Semi-insulating substrates are commercially available for 4H, which makes it possible to design floating body devices similar to SOI MOSFETs. The low impact ionization coefficient for both electron and holes will reduce floating body induced breakdown. Furthermore, the high thermal conductivity ensures marginal lattice heating.
Preliminary results indicate that the energy is limited, even though the channel is oriented perpendicular to the c-axis direction. Our simulations show a maximum mean energy of about 0.11 eV in the channel irrespective of the channel orientation in a 0.1 m 4H-SiC n-MOSFET with V = 2.0 V and V = 2.5 V.
The physical explanation for the low energy is the strong polar optical and surface scattering combined with the anisotropic band structure and discontinuous energy spectrum in the c-axis direction. This reduces the energy that the electric field gives the carrier. The discontinuity is present in both 4H and 6H-SiC devices, but it is stronger in 6H-SiC.
SESSION Y2: SiC EPITAXIAL GROWTH AND CHARACTERIZATION
Chairs: Albert A. Burk and Olle Kordina
Monday Afternoon, April 5, 1999
Golden Gate A2 (M)
1:30 PM *Y2.1
EPITAXIAL GROWTH OF SiC IN A VERTICAL MULTI WAFER CVD SYSTEM: ALREADY SUITED AS PRODUCTION PROCESS? Roland Rupp , Christian Hecht, Arno Wiedenhofer and Dietrich Stephani, Siemens AG, Corporate Technology Department ZT EN, Erlangen, GERMANY.
Results about a new CVD system suited for epitaxial growth on six 2' SiC wafers at a time are presented. Goal of the installation of this system in our laboratory was to generate a highly reliable and cost effective (less than 150 per 10 m thickness) process for manufacturing of SiC epi layers and thereby make it suited and affordable for device production. Excellent gas flow stability is achieved for this new reactor type as shown by in situ observations of the gas flow dynamics in the reactor chamber. These experimental results agree favorably with numerical process simulation results. The epitaxial layers grown in the multi wafer system today show a by an order of magnitude higher background impurity level ( 1015 cm-3 as reported so far for layers grown in single wafer systems ( 1014 cm-3). But even this impurity level enables the use of such layers for manufacturing of devices with reverse voltage levels up to 1200 V. On the other hand, the doping homogeneity achieved until today is very encouraging. The total variation on a 2' wafer is less than 20 at about 1*1016 cm-3. The wafer to wafer variation of the average doping value both within a run and from run to run is about 10. The reproducibility of the layer thickness is even better. The surface of the epitaxial layers is very smooth with a typical growth step height of 0.5nm (4H, 8 off orientation). First measurements on Schotty diodes build on these layers show very low leakage current values indicating low point defect density in the epitaxial layers.
Further work has to be done to increase the lifetime of the consumables in the reactor (sample holder etc.) and - by that mean - meeting our cost goals mentioned above.
2:00 PM Y2.2
MULTI-WAFER VPE GROWTH OF HIGHLY UNIFORM SILICON CARBIDE EPITAXIAL LAYERS. M.J. O'Loughlin , H.D. Nordby, Jr. and A.A. Burk, Jr., Northrop Grumman Advanced Technology Laboratory, Baltimore, MD.
A multi-wafer silicon carbide vapor phase epitaxy reactor has been developed in collaboration with Aixtron, Inc. The reactor, features full planetary motion and is capable of high quality epitaxy on seven, two-inch diameter (or smaller) wafers at a time. The susceptor is potentially scalable to three-inch diameter wafers. Specular 4H-SiC epitaxial layers are commonly grown at rates exceeding 3 m/hr with unintentional n-type background doping of less than 11015 cm-3. Intentional n-type doping ranging from less than 51015 to greater than 51019 cm-3 is routinely employed. We are currently performing preproduction growths of static induction transistor (SIT) and metal semiconductor field effect transistor (MESFET) active layers. For 1 3/8-inch diameter substrates, layer uniformity is typically better than 5 (standard deviation/mean) for doping and 3 for thickness. In a multi-wafer run, interwafer uniformity is typically better than 10 for doping and 5 for thickness. Process control and repeatability will be discussed. Although the majority of our process is currently focused on 1 3/8-inch diameter substrates, we have been actively developing processes for uniform growth on 2-inch diameter substrates. We have demonstrated doping and thickness uniformity of approximately 4. Significant process parameters, and ongoing developments intended to further improve layer uniformity and run-to-run reproducibility, will also be presented.
2:15 PM Y2.3
CHARACTERIZATION OF THICK 4H-SiC HOT-WALL CVD LAYERS. M.J. Paisley , K.G. Irvine, O. Kordina, R. Singh, J.W. Palmour, and C.H. Carter, Jr., Cree Research, Inc., Durham, NC.
Epitaxial 4H-SiC layers suitable for high power devices have been grown in a hot-wall chemical-vapor deposition (CVD) system. These layers were subsequently characterized for many parameters important in device development and production. The uniformity and accuracy of both thickness and doping will be presented for n- and p-type layers, culminating with a 1.2% thickness variation across a prototype three-inch wafer. Doping trends vs. temperature and growth rate will be shown for the p-type and n-type dopants used. The n-type dopant drops in concentration with increasing temperature or increasing growth rate. In contrast, the p-type dopant increases in concentration with decreasing temperature or increasing growth rate. A simple descriptive model for this behavior will be presented.
The outcome from capacitance-voltage and SIMS measurements demonstrate that transitions from n to n-, or p to p-, and even n to p levels can be made quickly without adjustment to growth conditions. The ability to produce sharp transitions without process changes avoids degrading the resulting surface morphology or repeatability of the process. Avoiding process changes is particularly important in growth of thick layers since surface roughness tends to increase with layer thickness. Device results from diodes producing two different blocking voltages in excess of 5 kV will also be shown. The higher voltage diodes exhibited a breakdown behavior which was near the theoretical limit for the epitaxial layer thickness and doping level grown.
2:30 PM Y2.4
HOMO-EPITAXIAL AND SELECTIVE AREA GROWTH OF 4H AND 6H SILICON CARBIDE USING A RESISTIVELY HEATED VERTICAL REACTOR. Ebenezer Eshun , Crawford Taylor and Michael G. Spencer, Howard University, Materials Science Center of Excellence, Washington DC; Kevin Kornegay, Department of Electrical Engineering, Cornell University, Ithaca, NY; Ian Ferguson and Alex Gruary, EMCORE Corporation, Sommerset, NJ.
Silicon carbide technology is rapidly developing production processes. This is due to the rapid progress in the development of high quality epitaxy and substrates. We report on the development of a resistively heated vertical reactor and itís application to homo-epitaxy and selective area growth. Epitaxial growth of 4H and 6H SiC requires high temperatures (in excess of 1500 C). We have been working in conjunction with EMCORE Corporation to develop resistive heating as an alternative to RF heating technology. Resistive heating offers advantages in the area of cost, temperature uniformity, and power efficiency of heating. However, resistive heating presents severe technological challenges in terms of filament life. We have been able to develop a useable resistive heating system. With this unit we are able to obtain temperatures in excess of 1700 C. At 1700 C the power consumption is 8 kW as compared to 50 kW at 1600 C for an identical RF heated unit. Using this system, we have grown ìstate of the artî 4H and 6H SiC on its respective substrates. At 1550 C our background doping is in the 3 - 5 1015 cm-3 as measured by C-V techniques. The background doping is p-type in agreement with earlier results presented by investigators from Siemans Corp., using a similar unit. We will present details of the results obtained at 1600 C as well as data obtained at the elevated growth temperatures, which are obtainable using this system.