1997 MRS Spring Meeting & Exhibit

Chairs

Gregg Higashi, Bell Labs, Lucent Technologies
Masataka Hirose, Hirsohima Univ
Srini Raghavan, Univ of Arizona
Steven Verhaverbeke, CFM Technologies

Symposium Support

• Air Products and Chemicals, Inc.
• Ashland Chemical Company
• CFM Technologies
• DNS Electronics
• Fujikin Incorporated
• Fujitsu, Ltd.
• Hitachi, Ltd.
• Hoechst Celanese Corp.
• Lucent Technologies
• Matsushita Electric Industrial Co., Ltd.
• Millipore Corporation
• Mitsubishi Electric Corporation
• Morita Chemical Industries
• NEC Corporation
• Santa Clara Plastics
• SEMATECH, Inc.
• SEMITOOL, Inc.
• SONY Corporation
• SubMicron Systems, Inc.
• Tokyo Electron Limited
• Toshiba Corporation

Proceedings published as Volume 477
of the Materials Research Society
Symposium Proceedings Series.

In sessions below "*" indicates an invited paper.

SESSION P1: MEGASONIC CLEANING 
Tuesday Morning, April 1, 1997
Golden Gate A3

8:00 AM *P1.1 
MEGASONIC IRRADIATION INDUCED CHEMICAL REACTIONS IN SOLUTION FOR SILICON WAFER CLEANING, Tadahiro Ohmi, Tohoku Univ, Dept of Electronics, Sendai, JAPAN; Masayuki Toda, Yamagata Univ, Dept of MS&E, Yamagata, JAPAN.

To respond to mass production and further integration in the next generation of ULSI, we have already proposed a new type, highly effective, chemical vapor free and all room temperature wet cleaning process for Si substrates which consumes very little amount of chemicals and ultrapure water. Mechanisms of adsorption and desorption of contaminants on Si wafer surface were clarified, then the total room temperature wet cleaning process was realized based on these mechanisms. The new wet cleaning method that we call ''UCT Cleaning'' (UCT for Ultra Clean Technology) which feature ozonated ultrapure water, surfactants and megasonic irradiation, perfectly cleans wafer surface for a consumption of less than 1 chemicals and 10 ultrapure water compared to the RCA cleaning. While developing the UCT cleaning, we have been investigating the essence of cleaning in solution. Much radical generation in SPM (HSO+HO+HO), SC-2 (HCl+HO+HO) and FPM (HF+HO+HO) solution was observed by ESR (Electro Spin Resonance analysis) and cleaning function of OH radical and H radical in these solutions was suggested. Further more, radical generation in ultrapure water irradiated by megasonic was also confirmed. Therefore, it could be expected that the contaminants removal by megasonic irradiation in the UCT cleaning is not only mechanical (lift off of contaminants from surface) but also chemical due to the effect of the megasonic generated radicals. Chemicals consumption in the UCT cleaning can be further reduced by using megasonic irradiation combined with ultrapure water based cleaning solution which feature a very small amount of chemicals and controlled dissolved gases. We believe that the UCT cleaning based on new technologies will contribute well to the growth of the semiconductor industry in the future.

8:30 AM *P1.2 
MECHANISMS OF MEGASONIC CLEANING, R. Gouk, David B. Kittelson, T. Kuehn, Y. Wu, Univ of Minnesota, Dept of Mech Engr, Minneapolis, MN.

The overall objective of the work described is to develop a model based on first principles to predict the performance of megasonic cleaning systems. This phase of the work focuses on the physical mechanisms of cleaning, i.e., cleaning in DI water. We have shown that shear and lift forces produced by bulk fluid motion and acoustic oscillations of the fluid and pressure forces produced by acoustic oscillations are unlikely to be able to remove submicron particles from silicon wafers under the conditions used in current cleaning tanks. Thus other mechanisms are likely to be involved. We believe that some combination of forces produced by the collapsing or pulsating cavitation bubbles and microstreaming in the acoustic boundary layer near the surface of the wafer are responsible for cleaning. Our presentation will describe development and validation of a numerical model to determine the sound pressure field, the acoustic streaming body force field, and the resulting flow field. It will also describe measurements of cavitation intensities produced by megasonic pressure fields. We are still in the process of developing relationships among the sound pressure, flow, and cavitation intensity fields; and cleaning efficiency and incorporating these relationships into an overall cleaning model.

9:00 AM P1.3 
PRACTICAL CONSIDERATIONS IN MEGASONIC WAFER CLEANING, R. Mark Hall, SCP Global Technologies, Boise, ID.

As device dimensions scale to smaller values, the ability to clean the wafer surface becomes more critical. Megasonic energy has been commonly used in many semiconductor cleaning solutions as a technique for improving particle removal efficiency. There are, however, varying opinions as the effect of transducer shape, power levels, frequency, and wafers spacing on overall cleaning efficiency. In this study, we examine these important process parameters and their impact relative to particle removal, surface roughness, and back side contamination. To accomplish this testing, two commercial megasonic cleaning systems were evaluated. The first system has a curved lens for radial power distribution, and the second system has a flat ''focused beam'' transducer lens. The effect of wafer spacing was evaluated from 1.14 mm to 6.35 mm, and the megasonic energy level was varied from 0 to 100 of maximum ouput power at several frequencies. The wafer contamination consisted of nitride particles deposited on the wafer surface at levels of .12 m and above. The results of these tests showed a strong correlation to megasonic power for particle removal for each wafer gap spacing considered. In addition to this, the effects of back side contamination were more evident as the wafer gap decreased. Although both megasonic cleaning systems demonstrated the capability to remove particles at high efficiency (95), each system had advantages for cleaning efficiency and shadowing effects.

9:15 AM P1.4 
PARTICLE REMOVAL FROM SILICON SUBSTRATES IN MEGASONIC-ASSISTED DILUTE SC1 PROCESSES, Ismail I. Kashkoush, Rich E. Novak, Bob R. Grant, SubMicron Systems Corp, Allentown, PA.

The effect of megosonic energy on particle removal in dilute SCl chemistry was investigated. HF contaminated silicon wafers were used. SCl solution was used as dilute as 100:1:1. Bath temperature was changed to vary between 50 and 70C. Megasonic energy was also varied between 0 and 1600 W in pulsed mode. Results show that megasonic energy enhances the particle removal even in dilute SCl solutions. Extended bath life also resulted during these experiments. The chemical concentration control was shown to be significant factor for dilute SCl chemistry to remove particles. These techniques provide low cost of ownership of the process by using dilute chemicals and longer bath life, i.e. more environmentally sound.

9:30 AM P1.5 
SiN PARTICLE REMOVAL EFFICIENCY STUDY, Gregg S. Higashi, Bell Labs, Lucent Technologies, Orlando, FL; Carolyn Lee, Rice Univ, Houston, TX; Joseph M. Rosamilia, Tom Boone, Jane Qian Liu, Bell Labs, Lucent Technologies, Murray Hill, NJ.

Controlling particle contamination in wafer cleaning is important to reduce defect density and improve device performance and yield. In this study, a screening experiment was employed to evaluate particle removal efficiency among different cleanings, including FSI BCLN, bench rinse and dry only, bench SC1/megasonic only, bench RCA cleaning, and bench RCA based cleaning. To optimize particle removal efficiency in RCA-based cleaning, a design of experiment (DOE) has been done to investigate the impact of SC1/megasonic cleaning on SiN particle removal efficiency. Bath temperature, megasonic power, and solution chemistry of SC1 bath were evaluated. The removal efficiency in relation to particle sizes was also investigated. Our screening experiment showed that SC1/megasonic cleaning alone is not as efficient to remove particles. FSI BCLN, bench RCA or RCA-based cleanings have comparable removal efficiencies.. DOE shows that megasonic energy is the most important parameter among the three factors. For a given megasonic power, particle removal efficiency for SC1 bath 1:8:64 (NHOH:HO:HO) is slightly better than 1:1:10 ratio. Interaction between power and temperature shows that at lower temperature particle removal efficiency increases as megasonic power increases. But at the higher temperature, the megasonic power of 400 W actually had better removal efficiency than the 800 W. For larger particles the particle removal efficiency is higher and data variability is smaller than the results from smaller particle sizes.

SESSION P2: R/D COORDINATION/SCl TECHNOLOGY 
Tuesday Morning, April 1, 1997
Golden Gate A3

10:15 AM *P2.1 
COLLABORATIVE RESEARCH AND DEVELOPMENT TO BOOST SEMICONDUCTOR MANUFACTURING PRODUCTIVITY: THE ROLE OF INDUSTRY NATIONAL LABS AND UNIVERSITIES, Susan Cohen, SEMATECH Inc, Austin, TX.

SEMATECH, a consortium of 10 U.S. integrated circuit manufacturers, focuses its efforts on precompetitive research and development to support advanced semiconductor manufacturing technologies. A key feature of this industry collaboration has been the involvement of National Laboratories and Universities in the more fundamental research and supporting experimentation. This research has been closely coupled to the final end users, both the IC manufacturers and the equipment suppliers, and provides an excellent mechanism for technology transfer. In this presentation, I will highlight some excellent examples of leveraged research and development from both the National Labs and Universities and show examples of how this has impacted the industry. For example, one activity that I will highlight is the Sandia/SEMATECH Contamination Free Manufacturing (CFM) Research Center. This is an extremely successful example of a collaborative program between the National Labs, Universities and Industry that has been an integral part of the SEMATECH CFM activities. I will also discuss some of the difficult issues, such as physical distance, intellectual property, and funding, which can potentially become barriers to initiating and maintaining similar types of programs. The key role of both the equipment suppliers, the universities and the national laboratories in providing the supporting research infrastructure to keep the semiconductor industry on our historical productivity curve will be emphasized.

10:45 AM *P2.2 
ADVANCED ALKALI CLEANING SOLUTION FOR SIMPLIFICATION OF SEMICONDUCTOR CLEANING PROCESS, Hitoshi Morinaga, Mitsubishi Chemical Corp, Kitakyusyu, JAPAN; Masumi Aoki, Toshiaki Maeda, Mitsubishi Chemical Corp, Prod Dept 3, Tech Sect 3 Gr, Kitakyusyi, JAPAN; Masaya Fujisue, Hiroyuki Tanaka, Minoru Toyoda, Mitsubishi Chemical Corp, Kurosaki Dev Ctr, Kitakyusyu, JAPAN.

A new alkali cleaning solution (MC-1) is developed for the purpose of simplifying cleaning step in the semiconductor manufacturing process. The conventional NHOH/HO/HO (called SC-1 or APM) cleaning is poor at removing metallic impurity although it features outstanding particle removal efficiency. Furthermore, metals such as Al, Fe, Zn and Cu easily get adsorbed on substrate in large volume if they are contained in this cleaning solution even in trace volume. The SC-1 cleaning must be followed by such an acid cleaning step as HCl/HO/HO (called SC-2 or HPM) cleaning, therefore, in order to remove metallic impurities. MC-1 Solution has been developed in an attempt to overcome drawbacks of the conventional SC-1 cleaning and to eliminate SC-2 cleaning or other acid cleaning steps. MC-1 is mainly composed of alkali and it also contains chelating agent (carboxylic-acid-type) which is extremely effective in preventing metallic impurity from getting adsorbed onto substrate. Metal adsorption can be eliminated by performing SC-1 cleaning which employs MC-1 instead of NHOH. Al adsorption can be also eliminated although it is very hard to be suppressed by the currently proposed alkali cleaning solutions with chelating agent injected. The SC-1 cleaning using MC-1 is also able to remove metallic impurity from substrate if cleaning conditions are optimized. In short, this modified SC 1 cleaning has made it possible to simultaneously remove particle and metallic impurity. Chelate injection is found not to induce deterioration of particle removal efficiency, surface microroughness (AFM), or organic adsorption to the substrate surface (TDS-GCMS). Adoption of MC-1 makes the acid cleaning such as SC-2 cleaning unnecessary, which leads to considerable cost reduction as well as improvement of throughput in cleaning step. This cleaning solution is also applicable to post CMP cleaning.

11:15 AM P2.3 
THE ROLE OF HO2- IN SC1 CLEANING SOLUTIONS, Steven Verhaverbeke, Jennifer Parker, CFM Technologies, Dept of Process Development, West Chester, PA; Chris F. McConnell, CFM Technologies, Dept of Administration, West Chester, PA.

The RCA Standard Cean, developed by W. Kern and D. Puotinen in 1965 and disclosed in 1970 is extremely effective at removing contamination from silicon surfaces and is the defacto industry standard. The first step of the RCA Standard Clean (SC1) has proven to be the most efficient particle removing agent found to date. The hydroxide in the solution steadily etches silicon dioxide at the boundary between oxide and the aqeous solution. The hydrogen peroxide in SC1 serves to protect the surface from attack by OH- by re-growing a protective oxide directly on the silicon surface. In this paper, a quantitative model of oxide etching and oxide growth is presented. Using this model and comparing the results to oxide growth rates in neutral hydrogen peroxide solutions as well as SC1 solutions indicates that H2O2 is not the dominant oxidizing species, and that a more likely candidate is HO2-. Moreover the diffusion through the oxide layer was found to be image charge assisted diffusion.

11:30 AM P2.4 
THE ADSORPTION-DESORPTION OF CATIONS AT THE SILICA-WATER INTERFACE AND THEIR IMPLICATION IN WAFER-CLEANING EFFICACY, Whon Chee Lee, Kevin J. Torek, Micron Technology, Boise, ID.

The adsorption-desorption of various cations at the silica-water interface is discussed in terms of the surface complexion model. Competitive complex formation equilibria explain the strong dependence of cations on pH. Some experimentally determined surface equilibria constants are tabulated and compared for different valences of cations. A chemical oxide (silica) is generated on the silicon surface during the SC1 process and activated by the high pH solutions for cation adsorption. The rates of processes occurring at the silica-water interface, such as the incorporation and dissolution of cations, are addressed in order to obtain better cleaning efficacy.

11:45 AM P2.5 
IN-HOMOGENEOUS PRECIPITATION OF IRON FROM SC1 SOLUTIONS, Martin Knotter, Philips Research Laboratories, Eindhoven, NETHERLANDS; Stefan de Gendt, Paul Mertens, IMEC, UCP-VMT, Leuven, BELGIUM; Marc M. Heyns, IMEC, UCP-ASP, Leuven, BELGIUM.

Exposure of silicon wafers to metal contaminated SC-1 solutions causes local surface roughening. In order to understand this phenomenon, different models can be developed. It is a fact is that some metal ions (e.g. Fe) in SC-1 baths catalyze the hydrogen peroxide decomposition. Therefore, one model assumes that the resulting gas bubbles shield the silicon surface locally from the SC-1 etching process, thus creating local surface roughening [H. F. Schmidt et al, Jpn. J. Appl. Phys. 34 (1995) 727-31]. We however like to introduce a new model, wherein the gas bubbles act merely as a transport medium to carry catalytic active Fe-aggregates to the bath surface. Fluid dynamics make these floating Fe-aggregates to precipitate onto the surface of an immersed wafer. Adsorbed onto the surface, these Fe aggregates remain catalytically active. Thus causing local depletion of hydrogen peroxide and silicon surface roughening. Additionally, the Fe-aggregates become built-in into the chemical oxide, at the exact location of the local silicon surface roughening. In earlier models, this has lead to the conclusion that local surface roughening is causing capacitor yield degradation. Considering our new model, we tend to believe that the local presence of 'high' concentration of Fe (due to aggregate adsorption), is likely to cause the capacitor degradation rather than the locally induced surface roughness. Electrical breakdown results will be presented to confirm our model.

SESSION P3/J4: SURFACE PREPARATION AND GATE OXIDE RELIABILITY 
Chairs: Gregg S. Higashi and Kathleen S. Krisch 
Tuesday Afternoon, April 1, 1997
Salon 5/6

1:30 PM *P3.1/J4.1 
CRITICAL ISSUES IN WET CHEMICAL PROCESSING OF ULTRA-THIN GATE OXIDES, C. Robert Helms, Stanford Univ, Dept of Electrical Engr, Stanford, CA.

This paper will first review the requirements for gate insulators for use over the next 15 years. These include gate lengths of 70 nm and oxide equivalent thicknesses down below 20 . Thickness control of better than 3, electrical defect densities down to 0,001 per cm will be required, with wafer sizes 400 mm. The gate insulator must also function as a diffusion barrier to impurities in the gate contact (or contact material itself, if a metal) and exhibit stability to any subsequent higher temperature steps. The critical surface prep requirements will next be discussed. For a modern process up to 7 cleans are performed prior to gate insulator formation, in addition to 3 resist strip operations, wet or dry film etch/strip, and planarization. Numerous cleaning operations are also performed by the wafer suppliers. Critical issues for surface prep include particle deposition and removal, effects of surface prep chemistries on wafer defects (especially for polished CZ wafers), metal deposition and removal, organic and other inorganic contamination, surface roughness, and surface termination. It is clear that a lowest Cost of Ownership solution for surface prep in the future must be considered in an integrated framework including the wafer itself, the cleans, and the gate insulator formation and other processes to be performed. In addition, environmental, safety, and health factors must be considered. This is leading to nonaqueous resist strip processes and more application specific tools and chemistries. Thickness control and uniformity is viewed as a key issue. Opportunities for simplified aqueous progate surface prep will next be discussed. Integrated single water ''dry'' cleans will not likely be adopted until gate insulator formation is also performed on a single wafer basis. This may occur in the 10-15 year out time frame when 400 or 450 mm wafers will be ramping into production.

2:00 PM *P3.2/J4.2 
CRITICAL ISSUES FOR THE MEASUREMENT OF GATE OXIDE RELIABILITY, Anthony S Oates, Bell Labs, Lucent Technologies, Orlando, FL.

Aggressive transistor performance requirements for advanced IC technologies necessitate the use of ultrathin gate oxides () operating at relatively high fields. Operation of devices with these high fields present a significant reliability concern since time-dependent oxide degradation is accelerated with increasing electric fields. In this talk, we present an overview of reliability assessment of thin gate oxides using lifetime measurements. Accurate prediction of oxide reliability requires an understanding of the effect of electric field on degradation, and here we discuss the field dependence and the impact of bias conditions (accumulation and inversion) on failure times. We address the issue of calculation of the oxide field during accelerated stress tests and show that the ' 'true'' oxide field can differ substantially from that expected from the optical thickness of the oxide because band bending, poly depletion and carrier confinement effects become significant below about 100 . We show that a neglect of these effects can introduce significant errors in lifetime projections from accelerated tests.

2:30 PM *P3.3/J4.3 
SURFACE TREATMENTS WITH UV-EXCITED RADICALS FOR HIGHLY-RELIABLE GATE DIELECTRICS, Takashi Ito, Fujitsu Laboratories Ltd, Electron Devices & Materials Lab, Kanagawa, JAPAN.

The UV-excited chlorine radical treatment is well known to effectively remove trace metal contaminants from silicon surfaces. The process makes high selectivity of silicon etching and was subjected to clearly identify breakdown spots on thin gate dielectrics. After dielectric breakdown, a silicon crystallized filament as small as a few nanometers in diameter was formed which was selectively etched with chlorine radicals. Nonuniformities of silicon native oxide films were identified through the same process by selective etching of silicon surfaces through the native oxide films. Etching of a polysilicon buffer layer of the modified LOCOS structure without any damage and contamination was another application of the process. Densification of native oxide films formed after the conventional wet cleaning was possible by UV ozone treatment. Densities were quantitatively evaluated by glancing angle x ray diffraction technique. Surface treatments with UV chlorine and UV ozone produce clean and uniform silicon surfaces resulting in highly reliable gate dielectrics for ULSIs.

3:30 PM *P3.4/J4.4 
IMPACT OF METAL CONTAMINATION OF 7.0nm GATE OXIDES ON VARIOUS SUBSTRATE MATERIALS, Shuichi Saito, K. Hamada, NEC Corporation, ULSI Device Dev Labs, Kanagawa, JAPAN; David J. Eaglesham, Bell Labs, Lucent Technologies, Dept of Silicon Processing Research, Murray Hill, NJ; Y. Shiramizu, NEC Corporation, ULSI Device Dev Labs, Kanagawa, JAPAN; Janet L. Benton, Bell Labs, Lucent Technologies, Murray Hill, NJ; H. Kitajima, NEC Corporation, ULSI Device Dev Labs, Kanagawa, JAPAN; Dale C. Jacobson, Bell Labs, Lucent Technologies, Murray Hill, NJ; John M. Poate, Bell Labs, Lucent Technologies, Dept of Silicon Processing Research, Murray Hill, NJ.

As gate oxide thicknesses decrease with device size reduction, the metal contamination level must also decrease to maintain device reliability. During gate oxide formation, metal atoms may be included in the oxide from either surface or bulk contamination during the process. The contamination level which affects device performance may be different for these processes. Moreover, the influence of metal contamination on the devices strongly depends on the gettering capability of the substrate. Evaluation of MOS devices has been carried out for different contamination methods (dip method and Fe I/I) and different substrate gettering (p/p+, DZIG, NIG, Fz, and high energy implantation). Device performance was evaluated using gate oxide breakdown voltage and Qbd characteristics for gate oxide reliability and junction leakage current to clarify the influence of damage in high energy implantation. The results suggest that reduced contamination levels are required for thinner gate oxides, and that high energy implantation provides useful gettering.

4:00 PM *P3.5/J4.5 
EFFECT OF Cl IN GATE OXIDATION, Paul W. Mertens, IMEC, Leuven, BELGIUM; Michael J. McGeary, Olin Corp, Microelectronic Materials Div, Cheshire, CT; Marc Meuris, IMEC, Clean Technology Group, Leuven, BELGIUM; Marc M. Heyns, IMEC, Leuven, BELGIUM.

Metallic contamination has a detrimental effect to the electrical integrity of ultrathin gate oxides. Today ultrathin gate oxides show defect levels that are still in excess of the level required for successful ULSI application (>1 GBIT). In situ use of Cl in an oxidation furnace results in an effective metal removal. Different chemistries and process schemes for in situ Cl cleaning are compared. The experiments demonstrate that Cl appears to be the most active component. Using a process in which all Cl in the furnace ambient is present as Cl results in a significant source reduction and in a more environmentally benign process. The current study will cover the following aspects of the use of Cl: the basic chemistry of the process, metal removal, effect on gate oxides, and safety and health issues.

4:30 PM P3.6/J4.6 
ORGANIC CONTAMINATION OF SILICON WAFER IN CLEAN ROOM AIR AND ITS IMPACT TO GATE OXIDE INTEGRITY, Masataka Hirose, D. Imafuku, Seiichi Miyazaki, Hirsohima Univ, Dept of Electrical Engr, Hiroshima, JAPAN.

Silicon wafer surfaces after wet cleaning are progressively contaminated with organic molecules in clean room air. The total carbon concentration on a hydrogen-terminated Si(100) surface tends to saturate at a level of about 10 cm when the exposure time exceeds 90 min. In order to understand the influence of the surface organic contamination on the gate oxide integrity, the total carbon concentration before the oxidation was changed from nearly zero to , and 4 5 nm thick gate oxides were grown in wet atmosphere at 850C. It is found that cumulative TDDB failure rate for the MOS capacitors under constant current stress is enhanced when the initial carbon contamination is increased beyond 2x10. The slope of Weibull plot for oxides without carbon contamination is rather steep and the breakdown occurs at electron injection levels of 2-10 C/cm, while the carbon contamination of more than 4x10 causes the breakdown even at 0.1-1 C/cm. Also, the initial tunnel current is well explained by theory for oxides with and without carbon contamination, and the dielectric degradation under the constant current stress occurs through dramatic increase of the direct tunnel current component as a consequence of a localized conducting filament formation in the oxide layer near the interface. It is shown that this degradation is accelerated with the carbon contamination exceeding 2x10.

SESSION P4: CMP/CMP CLEANING 
Wednesday Morning, April 2, 1997
Golden Gate A3

8:00 AM *P4.1 
COMMON MECHANISMS IN DIELECTRIC AND METAL CMP: HYPOTHESES AND APPLICATIONS, Lee M. Cook, Rodel Inc, Newark, DE.

CMP may be viewed as a tribochemical process in which specific reactions are mediated by the environment at the point of contact between the abrasive particle and the substrate. CMP processes for a variety of materials (e.g., SiO, metal, SiN, and Si) appear to possess a set of common removal mechanisms involving the production and removal of a solvated surface layer, present either as a discrete species or as a reaction intermediate. An examination of the mechanisms proposed yield practical focus points for materials development, which have been employed in a variety of new commercial CMP products. Specific examples of recent applications of theory to dielectric, metal, and trench isolation will be reviewed within the context of working models for the CMP process.

8:30 AM P4.2 
THE INTEGRATION OF INTERLAYER DIELECTRIC DEPOSITION AND CHEMICAL MECHANICAL POLISHING, Anda McAfee, Daniel A. Koos, Stephen McArdle, Mercedes Jacobs, Robert V. Hiatt, Motorola Inc, Mesa, AZ.

This paper addresses an important process issue in the integration of chemical mechanical polishing with interlevel dielectric (ILD) deposition for advanced back end processing. Delamination has been observed at the interface between two tetraethylorthosilicate (TEOS) layers at interlevel dielectric (ILD) deposition where a dep-etch-dep (D/E/D) technique is employed prior to tungsten chemical mechanical polish (CMP). The weak interface between the TEOS layers was found to be the result of carbon and fluorine residue left from the tetraflouromethane (CF) doped etch process. Evaluation of various D/E/D interface conditions were studied using X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). Experiments were carried out to determine if the residue and subsequent flaking could be eliminated by modifying the established process. From the analysis an improved process was identified which yielded superior results based on induced film stress and shear testing. The process has been implemented into full production with no subsequent occurrence of interfacial delamination.

8:45 AM P4.3 
USE OF MALONIC ACID IN CHEMICAL MECHANICAL POLISHING (CMP) OF TUNGSTEN, Liming Zhang, Raghunath Chilkunda, Kyong-Te Le, Emil Kneer, Srini Raghavan, Univ of Arizona, Dept of MS&E, Tucson, AZ.

Chemical-mechanical polishing of tungsten films is typically carried out using acidic alumina-based slurries. In order to improve the surface cleanliness of wafers after tungsten CMP, the use of malonic acid as an additive in the polishing slurry has been explored. Malonic acid is a dicarboxylic acid with pKa values of 2.8 and 5.7. The principal objective of the work to be reported in this presentation was to delineate conditions under which alumina contamination of tungsten and silicon dioxide could be reduced through the use of malonic acid in the slurries. 
The interaction between malonic acid and alumina particles has been investigated through electrokinetic and adsorption measurements. At suitable malonic acid concentrations, tungsten and alumina surfaces develop a negative zeta potential resulting in conditions conducive to reduced particulate contamination Small scale polishing experiments have been carried out both in the presence and absence of an oxidant to relate electrokinetic results to the level of particulate contamination after polishing.

9:00 AM P4.4 
SURFACE CHARACTERISTICS, ETCHING BEHAVIORS AND CHEMICAL-MECHANICAL POLISHING OF ALUMINUM ALLOY THIN FILMS, Wei-Tsu Tseng, National Chiao Tung Univ, National Nanl Device Laboratories, Hsinchu, TAIWAN; Jun Wu, Yee-Shih Chang, Tsinghua Univ, Inst of MS&E, Hsinchu, TAIWAN.

Characteristics of surface oxide on aluminum alloy thin films play the vital role in determining the susceptibility of these thin films to erosion and corrosive attack by, for example, acidic slurry during chemical mechanical polishing (CMP) process. Surface morphologies, such as porosity and roughness, of this thin oxide have profound influences on the etching rate of these thin films. In addition, the physical and electrochemical nature of surface oxide depends strongly upon the composition of these Al alloy thin films so that the CMP removal rate is highly composition-dependent [1]. In this study, AFM and ESCA are adopted to characterize the surface features of sputter-deposited pure Al, Al-1.0 Si, Al-0.5 Cu, and Al-1.0 Si-0.5 Cu thin films. Etching tests with HO based oxidizers are performed on these thin films in order to disseminate the roles of composition and surface features on etching behaviors. Concentration and pH dependencies of etching are also examined. The results are compared with those from our previous CMP study [1] and the correlations between them are discussed.

9:15 AM P4.5 
PLANARIZATION OF GRATINGS USING MAGNETORHEOLOGICAL FINISHING, Fuqian Yang, S. D. Jacobs, D. Golini, J. J. Edwards, Univ of Rochester, Ctr for Optics Manufacturing, Rochester, NY; D. H. Raguin, Rochester Photonics Corp, Rochester, NY.

Interest in field-assisted finishing has increased greatly during the past decade. Among the various approaches, the most recently developed process is called magnetorheological finishing (MRF). In MRF a magnetorheological suspension composed of carbonyl iron particles is used to polish optical glasses and other materials. A non-uniform magnetic field is applied between the workpiece and the carrier surface to increase the flow resistance (such as apparent viscosity and yield stress) of the magnetorheological suspension and the chemo-mechanical interaction between the polishing of the workpiece surface. One of the advantages of the MRF process is that it is deterministic if the properties of magnetorheological fluid are well controlled. Surface planarization of BK7 glass gratings with periods of 130, 30, 16, 8, and 5 m was performed with the MRF process. Approximate 0.5 m of materials was removed in the experiments. Grating height decreased as a function of grating period, going from 1.03 m to 0.33 m (130 m grating period), and 0.44 to 20 (gratings with 30, 16, 8, and 5 m periods). The microroughness on the top and the bottom of the grating structures also decreased with material removal, reaching about 10 for gratings with 30 and 16 m periods.

9:30 AM P4.6 
DOUBLE-SIDE SCRUBBING OF Si WAFERS: PARTICLE PERFORMANCE AT 0.12 m, Ramin Emami, Igor J. Malik, Diane J. Hymes, Venus Noorai, Jackie Zhang, Wilbur C. Krusell, OnTrak Systems Inc, Milpitas, CA.

Consistent cleaning performance is important both for prime Si production and semiconductor manufacturing in front- and back-end cleaning applications. Current demands for prime Si wafers as well as front-end cleaning require surface particle levels to be typically <30 for defects m. Low surface particle levels must be achieved while other important surface properties (metals, organics, wetability, surface roughness) are tightly controlled. The goal of this paper is to demonstrate the cleaning capability of double- side scrubbing to meet the above-mentioned specifications and discuss the interplay of mechanical and chemical aspects of this cleaning method that make it attractive for the most demanding applications. The discussion includes recent improvements of the brush material (polyvinyl alcohol) and trends towards more dilute chemistries for both particle and metals removal. Possible directions for further improvements of double side scrubbing are outlined.

9:45 AM P4.7 
CHEMICAL-MECHANICAL CLEANING FOR POST-CMP APPLICATIONS: DEFECTS AND METALS RESULTS, Eugene Zhao, Ramin Emami, Igor J. Malik, Kamal Mishra, Wilbur C. Krusell, John M. de Larios, OnTrak Systems Inc, Milpitas, CA.

Post-CMP cleaning is an important part of the multilevel metallization scheme used in advanced integrated circuits. Double-side scrubbing using dilute alkaline solutions has become a dominant cleaning method for this application. HF etching of a thin SiO surface layer is often desirable as a part of the post-CMP clean and has been performed typically as an additional cleaning step in a wet bench. The goal of this paper is to demonstrate the post-CMP cleaning capability of chemical-mechanical cleaning in a HF-compatible double-side scrubber. We show post-cleaning defect levels after both oxide- and W-CMP. Defects levels <50 defects (m) by Tencor 6420 on post-CMP PETEOS wafers are demonstrated after 1-step CMP. Additional data presented include surface roughness and W-plug morphology by AFM, defect review by optical microscopy and SEM, and surface metals by several techniques. The discussion focuses on the complementary mechanical and chemical aspects of this cleaning method. The advantages and drawbacks of HF usage in post-CMP cleaning are reviewed.

SESSION P5: POST-ETCH PROCESSING 
Wednesday Morning, April 2, 1997
Golden Gate A3

10:30 AM *P5.1 
'BACK END' CHEMICAL CLEANING IN INTEGRATED CIRCUIT FABRICATION, Yaw S. Obeng, Raju Raghavan, Bell Labs, Lucent Technologies, Orlando, FL.

The economics of IC fabrication demands maximum device yields, especially at the ' back-end' where the device wafers are most valuable. This dictates that the processes employed must be highly manufacturable, and that we fully understand the chemicals and processes used. As with all industries, the process choices are constrained by the environmental impact of the chemicals employed, and cost. In this talk, the application of wet chemical cleaning at the 'back-end' of Integrated Circuit (IC) or Metal-Oxide Semiconductor (MOS) fabrication is reviewed from chemical, environmental and cost perspectives. The various classes of commercially available solvents will be reviewed from the perspective of process suitability, impact on device yield and waste management. Strategies for minimizing processing concerns, as well as alternatives to organic solvent based wet chemical processing will also be discussed. Bulk photoresist (PR) stripping, post metal definition-, and post window etch cleaning will be used to illustrate the discussion. We will also discuss the use of radiotracing as a diagnostic tool in understanding the mechanism for metallic contamination during solvent cleans. We will present data to show how the chemistry and solvent composition affects alkali metal (for example, sodium) contamination of dielectric- and barrier films during IC processing

11:00 AM P5.2 
POST METAL ETCH TREATMENT FOR SUBMICRON APPLICATIONS, Simon Gonzales, Gordy Grivna, Motorola Inc, New Technology Group, Mesa, AZ; Anda McAfee, Motorola Inc, Mesa, AZ.

The corrosion and passivation of post metal etch structures are critical for submicron applications and overall yield performance. This includes the requirement to minimize metal line loss, remove veil formations, and prevent post corrosion from occurring. This study focused on 0.6 micron metal line spaces and the development of a process utilizing an integrated metal etch, photoresist strip, and passivation tool. All key elements of the metal etch tool and veil removal were studied in order to implement a robust and manufacturable process. Data collected to characterize the corrosion/passivation mechanism included: veil and photoresist strip chemistries, passivation steps, time delays, subsurface material versus veil formation, and electrical and defectivity yield. A post metal etch process was tested and integrated into a manufacturing environment that has provided minimal line loss, complete removal of etch veils, robust corrosion control, and substantial reduction of intermetal shorts.

11:15 AM P5.3 
ETCHING CHARACTERISTICS DURING CLEANING OF SILICON SURFACES BY NF-ADDED HYDROGEN AND WATER-VAPOR PLASMA DOWNSTREAM TREATMENT, Miki T. Suzuki, Jun Kikuchi, Fujitsu Ltd, Process Dev Div, Kawasaki, JAPAN; Mitsuaki Nagasaka, Fujitsu Ltd, Manufacturing Tech Div, Kawasaki, JAPAN; Shuzo Fujimura, Fujitsu Ltd, Process Dev Div, Kawasaki, JAPAN.

As device size shrinks, native oxide affects electrical properties of ULSI devices. For example, native oxide on contact areas degrades the contact resistivity after forming electrode at contact holes. Therefore, it is important to remove native oxide from silicon surfaces prior to thin film formation. However, sidewall formed of B-PSG film is greatly etched during contact hole cleaning by conventional HF wet treatment. This results in expansion of hole diameter. Thus, we have developed a damageless dry cleaning process for native oxide removal. We have reported that NF added hydrogen and water vapor plasma downstream treatment removed native oxide from silicon surfaces and formed hydrogen-terminated surfaces. In the present study, we investigated etching characteristics of B-PSG films by this downstream treatment to examine adaptability to the contact hole cleaning. NF was injected into the downstream of hydrogen and water vapor microwave plasma (H:90 sccm, HO:10 sccm, NF:50 sccm, 0.8 torr, 500W). Etching depth of B-PSG films (boron 3.2wt, phosphorous 6.4wt) in this treatment was estimated by ellipsometry. We varied wafer temperature during the treatment to examine the dependence of wafer temperature on etching rate. Silicon wafer temperature was directly monitored using a pulse-modulated infrared laser interferometric thermometry. We removed the native oxide formed in SPM solution (thickness: 1.52.0 nm) using this treatment for 1 min (wafer temperature: 22C). Under the same treatment condition, the same amount of B-PSG film as that of the native oxide was etched. This result is suitable for the contact hole cleaning. By raising the wafer temperature (at 40C), the amount of B-PSG film decreased.

11:30 AM P5.4 
PHOTORESIST STRIPPING USING OZONE/DE-IONIZED WATER CHEMISTRY, Ismail I. Kashkoush, Bob Matthews, Rich E. Novak, SubMicron Systems Corp, Allentown, PA.

A novel process using de-ionized water and ozone mixtures was developed to remove photoresist from silicon wafers. The process does not use, as historically done, sulfuric acid or hydrogen peroxide and consequently there is no need for de-ionized water rinsing steps. Unlike the sulfuric/peroxide process where the resist is undercut and floats away then oxidized by the hydrogen peroxide, the ozonated water process is a direct oxidation of the resist on the wafer surface. The resist is continually thinned during reaction and the solution remains ''crystal clear'' during the entire process time. Results show that the stripping rate increases with the dissolved ozone content in de-ionized water. An etch (stripping) rate of 300-400 A/min is typically achieved on different resists using this process. Compared to the proven traditional sulfuric/peroxide process, this method provides very low cost of ownership and more environmentally sound wafer processing.

11:45 AM P5.5 
EFFECT OF GAS ADDITION ON OZONE ASHING, Kayoko Kojima, Toshiba Corp, Manufacturing Engr Res Ctr, Yokohama, JAPAN.

Damage-free ashing is required for miniaturization of devices in the field of electronic device manufacture. Ozone ashing is a method that does not cause damage to devices since no plasma is used. We investigated the effect of gas addition on ozone ashing to increase the ashing rate and decrease the ashing temperature. The ashing rate increased with the addition of alcohol or ammonia to the ozone gas. The higher the flow rate and ozone concentration, the greater was the effect of the additives on the ashing rate; however, no effect was observed when the supply of ozone gas was insufficient. An ashing-treated resist was analyzed by x-ray photoelectron spectroscopy (XPS) and Fourier transform infrared spectroscopy (FT-IR) in order to clarify the role of alcohol or ammonia in ashing. The IR spectra indicated that C-D bonds exist in the ashing-treated resist, when heavy methanol is used as an additive. In the case of alcohol addition, it is considered that hydrogen atoms of the alcohol reacted with the double bonds of the resist to generate radicals in the resist, leading to an increase in the rate of oxidative decomposition of the resist. On the other hand, in the case of ozone ashing in the presence of ammonia, the results of the analysis showed that N-H bonds were formed on the resist surface by the ashing. It is considered that the resist was decomposed oxidatively with the addition of not only hydrogen but also nitrogen of ammonia to the resist, different from the base of alcohol addition, and the ashing rate was accelerated.

SESSION P6: SURFACE MICROROUGHNESS 
Wednesday Afternoon, April 2, 1997
Golden Gate A3

1:30 PM *P6.1 
HOT WATER ETCHING OF SILICON SURFACES: NEW INSIGHTS OF MECHANISTIC UNDERSTANDING AND IMPLICATIONS TO DEVICE FABRICATION, Joseph M. Rosamilia, Tom Boone, J. Sapjeta, Krishnan Raghavachari, Gregg S. Higashi, Q. Liu, Bell Labs, Lucent Technologies, Murray Hill, NJ.

As the device features continue to decrease for future device technologies, the product yield and performance become more dependent on the wafer cleaning technology. For many years, HF-last and RCA cleaning have been the main approaches for producing an ultraclean surface. After an HF step, the silicon surface has been found to be completely hydrogen terminated [l] and has a high stability against reoxidation in air [2, 3]. However, the H-terminated surface has been shown to be readily attacked by oxidants such as OH [4]. When deionized water at elevated temperatures comes in contact with HF treated surface, dissolution of the Si substrate occurs [5] even though DI water has long been thought to be concretely benign to the Si surface. Etching by hot DI water rinsing was first reported by Higashi who found that the Si(100) surface etched anisotropically causing unwanted surface topography [5]. This surface erosion has a negative device impact. Since hot water rinsing is widely used in manufacturing, especially in conjunction with several commercial techniques for aiding in wafer drying, it is important to understand the chemistry of the Si dissolution reaction. Earlier studies [5] done in this laboratory demonstrated the impact of dissolved oxygen on device yield. That study showed a depression in the FN tunneling voltage when the dissolved oxygen in the DI rinse water was high. TEM evaluations revealed etching with a high degree of surface microroughness in the gate region. A mechanism was proposed which involved sequential back-bond attack; first by the dissolved oxygen and then by OH- on the hydrogen-terminated surface. More recent studies by IMEC showed that the etching reaction was dependent on the OH concentration [6]. The presentation will review what is currently known about this phenomenon, correlate etch rate data to rinse water conditions, and explore the implications of the current understanding to future advanced device technologies. We will examine the mechanism in greater detail by evaluation of etch rate data as a function of dissolved oxygen concentration and temperature. The evolution of the Si surface morphology will be followed using atomic force microscopy and TEM. In addition, theoretical calculations will demonstrate the validity of the mechanism.

2:00 PM P6.2 
LOW pH CHEMICAL ETCH ROUTE FOR SMOOTH H-TERMINATED SI(100) AND STUDY OF SUBSEQUENT CHEMICAL REACTIVITY, Bruce J. Hinds, Gerald Lucovsky, North Carolina State Univ, Dept of Physics, Raleigh, NC; Dave E. Aspnes, North Carolina State Univ, Dept of Physics, Raleigh, NC.

In the aim of forming atomically flat H-passivated Si(100) surfaces, wet chemical etching of thermally grown sacrificial SiO to the substrate interface has been examined. The pH of aqueous HF etching solutions is reduced to minimize oxidation of Si surface by [OH] and establish HF and HF as dominate etching species. HSO and HCl and are used as hydronium sources over a pH range of -0.32 to 1.6. Roughness, as monitored by spectroscopic ellipsometry, shows a minimal atomic roughness of 4.2 ang. rms with an optimal solution of 1:0.5:30 HF(49wt%):HSO(98wt%):HO. The study of the mechanisms for optimal smoothness shows that it is not solely related to pH, sulfate concentration, or HF etching mechanism. The use of HCl resulted in smoothness of 5.2 ang. rms over a large range of HCl concentrations. These surfaces are found to be moderately reactive to ambient conditions. This reactivity is monitored by in-situ ellipsometry during the controlled introduction of reactive gasses into an inert glove bag environment. Hydrocarbon absorption is the primary form of reactivity which is readily removed by a methanol rinse. However an irreversible initial oxygen incorporation is seen by ellipsometry and Auger analysis of H-terminated Si(100) surfaces.

2:15 PM P6.3 
INFLUENCE OF BHF TREATMENTS ON HYDROGEN-TERMINATED Si(100) SURFACES, Toshinori Osada, Y. Kawazawa, Morita Chemical Industries Co, Ltd, Osaka, JAPAN; Seiichi Miyazaki, Masataka Hirose, Hirsohima Univ, Dept of Electrical Engr, Hiroshima, JAPAN.

The hydrogen configurations on Si(100) surfaces treated with BHF (NHF/HF/HO) have been studied by Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR) Also, silicon fluorine bonds on Si(100) surfaces have been examined by x-ray photoelectron spectroscopy (XPS). ATR spectra have shown that a surface treated with lower concentration BHF is terminated by a larger amount of SiH bonds than that treated with higher concentration BHF. The Si surface terminated with the largest amount of SiH bonds has been obtained by BHF containing 10 NHF with 1.02.0 HF (pH = 4.044.2) for a treatment time of 3060 s. Thus the hydride configurations depend on not only BHF composition but also the treatment time. 
The SiH absorption intensity increases with the pH value of BHF up to 4.8 because the SiH bonds appear at (111) facets produced by Si etching with OH ions for pH values greater than 4.4. Also, XPS spectra have revealed that the concentration of Si-F bonds on Si(100) after BHF treatment depends on HF concentration in the solution. Increase in HF concentration in the solution causes an increase of SiH peak intensity. This suggests that fluorine containing ionic species such as HF react with Si at atomic defects on the terrace surfaces to produce SiH bonds. Therefore, it is important to control the pH value, total fluorine concentration in the solution and the treatment time in order to obtain the flat, hydrogen-terminated Si(100) surfaces.

2:30 PM P6.4 
MINIMIZATION OF INTERFACIAL MICROROUGHNESS FOR 13 - 60 ULTRATHIN GATE OXIDES, J. Sapjeta, Tom Boone, Joseph M. Rosamilia, Tom W. Sorsch, G. Timp, Bell Labs, Lucent Technologies, Murray Hill, NJ.

Submicron ULSI circuit performance is becoming increasingly sensitive to the quality of the silicon/gate interface as device dimensions shrink. For very thin oxides, high roughness values can result in reduction of channel mobility and charge to breakdown, and in an increase of interface trap density. Thus, it is important to understand the origin and minimize surface and interfacial roughening during processing. There are at least three processing steps that contribute to interface quality: 1) sacrificial oxide growth, 2) cleaning prior to gate oxidation, and 3) the oxidation itself. The key issues for cleans are to protect the silicon against roughening and still thoroughly remove metals, particles, and other surface contaminants prior to oxidation. Then, the interface quality must be preserved during oxidation. The present study uses atomic force microscopy to characterize cleaning and oxidation-induced microroughness. The cleaning portion of the study compares conventional wet cleans with an in-situ vapor-phase UV/Cl clean. Experiments were performed to determine the influence of SC1-HF last, SC1-SC-HF-last, and vapor-phase UV/Cl cleans on interface roughness for both epi- and bulk silicon substrates. Oxides were grown by rapid thermal oxidation at 1050C in low pressure O. For epi silicon substrates with an initial roughness of 0.7 rms, UV/Cl cleans (1.0 rms) proved to be superior to the wet cleans (1.3 rms). Interface roughness for the wet-cleaned wafers was comparable for bulk and epi substrates, but bulk substrates were pitted by the UV/Cl clean for all cleaning times examined (7-60 sec). For extremely thin (13-40 ) oxides, the thickness had a negligible effect on the resulting interface roughness. The contribution of a sacrificial oxide layer to the final gate oxide interface roughness will be discussed. Data correlating roughness with gate oxide reliability for oxide thickness in the range of 13-60 will also be presented.

2:45 PM P6.5 
MIRROR-POLISHING RESIDUAL DAMAGE CHARACTERIZATION IN THE SUBSURFACE OF Si WAFERS USING N LASER/mm-WAVE PHOTOCONDUCTIVITY AMPLITUDE TECHNIQUE, Yoh-Ichiro Ogita, Y. Hosoda, Kanagawa Inst of Technology, Dept of E&EE, Kanagawa, JAPAN; M. Miyazaki, Sumitomo Sitix Co Ltd, Saga, JAPAN.

By using the N laser/mm-wave photoconductivity amplitude technique (PCA), we have examined the residual damage characterization of the subsurface of CZ Si wafers prepared changing CMP conditions, correlating the PCA signal with the gate oxide integrity and the surface roughness measured by AFM. Several times of CMP polishing did not cause necessarily the surface microroughness with RMS value of 0.1 to 0.5 nm to be decreased, but caused the yield of the gate oxide integrity for 11 MV/cm and the PCA signal to be increased. This implies that the increase of the yield depends on removal of the subsurface damage by several times of CMP polishing. The increase of the yield did not correlate with the surface roughness, but well correlated with the PCA signal. The noncontact PCA technique has revealed the increase of the yield as removal of the subsurface damage. Thus, the technique makes it possible to characterize subsurface residual damages induced by the mirror polishing.

SESSION P7: WET CHEMICAL CLEANING AND GATE OXIDE INTEGRITY 
Wednesday Afternoon, April 2, 1997
Golden Gate A3

3:30 PM P7.1 
EFFECT OF ULTRA-DILUTE RCA CLEANS ON THE INTEGRITY OF THIN GATE OXIDES, Tushar H. Dhayagude, Weidong Chen, Laura Davis, Mohsen Shenasa, National Semiconductor Corp, Advanced Technology Group, Santa Clara, CA; David Nelms, VERTEQ Inc, R&D Div, Santa Ana, CA; Mike Oleson, VERTEQ Inc, R & DDiv, Santa Ana, CA.

As device geometries are scaled below the sub-half micron regime, pre-diffusion cleans become increasingly important. The cost of wafer cleans becomes a substantial part of the total cost. Recently dilute RCA cleans, chemical ratios around 50:1, have been used to reduce cost. In this work, we have used Ultra-dilute RCA cleans, ratios greater than 100:1, and studied their effect on the Qbd and Ebd of thin gate oxides. We have also compared the results to that obtained from dilute RCA cleans. Ultra-dilute cleans and dilute RCA cleans were performed on gate oxide integrity monitor wafers. Thin gate oxides of less than 100Å were used. Qbd and Ebd were measured on area capacitor, iso-edge intensive and herringbone structures. Metallic contamination was measured on the test wafers using TXRF and SPV. Particles were measured using a light point defect counter. Surface roughness and chemical oxide thickness were measured using AFM and ellipsometer respectively. The results of the study show that the Qbd and Ebd on wafers cleaned using ultra-dilute RCA clean was equivalent to those cleaned using dilute RCA clean. Both cleans showed equivalent particle removal efficiency and metallic contamination. Surface roughness of less than 2Å (RMS.) was obtained using both the cleans. Further ultra-dilute RCA cleans used less chemicals compared to dilute RCA cleans, leading to shorter rinse cycles. This resulted in increased throughput and lower Cost of Ownership (COO) for recipes with ultra-dilute RCA cleans. In this paper, the ultra-dilute RCA clean process will be discussed, and a comparative analysis of the data obtained from ultra-dilute and dilute RCA cleans will be presented.

3:45 PM P7.2 
RCA AND IMEC CLEAN: METALLIC IMMUNITY AND GATE-OXIDE INTEGRITY, Weidong Chen, Tushar H. Dhayagude, National Semiconductor Corp, Advanced Technology Group, Santa Clara, CA; Prasad Chaparala, Esin Demirlioglu, National Semiconductor Corp, Research Group, Santa Clara, CA; Mohsen Shenasa, National Semiconductor Corp, Advanced Technology Group, Santa Clara, CA; Twan Bearda, Sophia Arnauts, Marc Meuris, IMEC, Clean Technology Group, Leuven, BELGIUM.

RCA and IMEC pre-gate cleans have been extensively studied and evaluated for many years. It is reported that both cleans have shown good electrical performance and yield. The purpose of this work is to correlate the electrical data, Ebd and Qbd, with the metallic contamination data on monitor wafers, obtained using VPD-TXRF and SPV. RCA and IMEC cleans were performed on gate oxide integrity shortloop. Monitor wafers were processed along with shortloop wafers. Thin gate oxides of less than 100 Åwere used. Both the experimental clean splits, RCA and IMEC, were performed on two processes; Process A with surface Fe and Ca contamination of the order of 1E10 atoms per cm as measured using VPD-TXRF, and Process B with surface Fe and Ca contamination about 1 order magnitude higher than in Process A. Bulk Fe contamination was also measured on all experimental splits using SPV and was found equivalent. Qbd and Ebd were measured on area capacitors, iso-edge intensive and herringbone structures. 
Good Qbd and Ebd data was obtained for RCA and IMEC cleans in Process A, for all structures. The percentage of shorts and intermediate failures were negligible for both cleans in Process A. Lower Qbd and Ebd were obtained for both cleans in Process B than for Process A. Also, the percentage of shorts and intermediate breakdowns were much higher. In this paper, the details regarding the correlation between the nature of the metallic contamination (Surface and Bulk) and gate oxide integrity will be further discussed.

4:00 PM P7.3 
EFFECTS OF WAFER CLEANING REDUCTION ON METALS REMOVAL AND ULTRATHIN GATE OXIDE QUALITY, Stephan A. Cohen, IBM T.J. Watson Research Ctr, Yorktown Heights, NY; Mary Ann Zaitz, IBM Microelectronics, Hopewell Jct, NY; Christopher D'Emic, IBM T.J. Watson Research Ctr, Yorktown Heights, NY.

The drive to reduce chemical consumption for cost savings is high in the semiconductor industry. Recently, studies have shown that the traditional 1:1:5 ratios of the SC1, SC2 cleans can be reduced and still maintain good cleaning. The optimization of process parameters must be done in accordance with the type of cleaning tool. Processes in wet decks may be optimized differently from single chamber tools, especially if extended bath lifetimes are expected. In this study, temperature reduction and dilution of the SC1 and SC2 cleans in a wet deck are examined for their effects on metals removal efficiency from silicon surfaces as measured by TRXRF. For an HF, SC1, SC2 sequence, good metal removal can be maintained by dropping the SC1 temperature down to 35C and chemical ratio to 1:1:40. At too low a SC1 dilution and temperature, the Cu removal efficiency drops. In SC2, good metals removal remains without peroxide and a lower limit for HCl is determined. It is also found that peroxide must be reduced if HCl is reduced in SC2, otherwise metals plating out from SC1 cannot be removed effectively. To understand the impact of these reduced cleans on gate oxide integrity, the electrical properties of 30 gate oxides grown using these experimental cleans is discussed.

4:15 PM P7.4 
STUDY ON THE EFFECT OF SILICON SURFACE CLEANING PROCESSES ON GATE OXIDE INTEGRITY, Alessandro Corradi, Elio Borzoni, Piero Godio, Gabriella Borionetti, MEMC Electronic Materials, Novara, ITALY.

The extended use of MOS technology for VLSI and ULSI device applications has addressed technological and scientific efforts to the quality improvement of thin oxide dielectric integrity. Many scientific papers have been recently published (1-3) which examine the influence of crystal related defects (COPs, FPDs), surface metal impurities and microroughness on thin oxide degradation. The present paper intends to investigate the influence of silicon wafer surface cleaning processes on Gate Oxide Integrity (GOI) by treating both epitaxial and CZ P100 wafers grown with very reproducible processes in order to distinguish and keep under control crystal related defects and surface effects on GOI. Experimental design has been performed on a typical cleaning sequence largely used in IC manufacturing focusing on two crucial phases: an acid oxidizing bath for organic digestion (phase A) and a SC1 type solution for particle removal (phase B). For both phases, evaluation of the effect on GOI of process variables like chemical types and concentration, chemical bath sequence, chemical solution lifetime and wafer residence time have been performed. Oxide integrity has been evaluated by applying constant current or ramp voltage test on doped poly gate MOS devices of 0.1 cm with 200 A thermal oxide. The importance of both phases in affecting gate oxide quality will be demonstrated and discussed through the comparative analysis of GOI results, surface morphology data (by LPDs and AFM characterization), residual metallic and organic contamination analysis. Particular attention will be taken in evaluating the effect of cleaning process conditions on the GOI response of material substrates (epi or CZ) having very different starting levels of Crystal Originated Particles. In addition, a study on GOI of surface roughness ''per se'' as obtained varying wafer polishing conditions will be included.

4:30 PM P7.5 
INVESTIGATION OF THE NEED FOR ALTERNATIVE CLEANING CHEMISTRIES FOR 30ÅGATE OXIDES, Amr Bayoumi, Hewlett Packard Co, ULSI Research Lab, Palo Alto, CA; Alice Fischer-Colbrie, Hewlett Packard Co, Matls Characterization Group, Palo Alto, CA; Russ Parker, Mike Cox, Wayne Greene, Hewlett Packard Co, ULSI Research Lab, Palo Alto, CA.

A comparative study of pregate cleaning solution chemistries has been conducted, for 30 furnace oxides, in terms of oxidation rate, particle adhesion, metallic contamination from solutions, capacitance voltage (CV) characteristics, breakdown fields, and gate leakage currents. Chemistries studied included standard SC1 (w/Megasonic)/SC2, final HF, as well as room-temperature single-bath HF-based chemistries (HF only, HF+HO, HF+HCl, HF+HO+HCl, SPM+HF). Reasons for considering HF-based mixtures include: (1) for oxides 15-30 thick, the SC1/SC2 chemical oxide might constitute 50 of the final oxide, and possibly degrading the overall gate oxide integrity (GOI); (2) chemicals/DI rinse minimization; (3) emerging clustered techniques for MOS stack formation might require an initial in-situ surface treatment step (i.e., requires a H-terminated rather than an oxide passivated surface); and (4) a regular CMOS flow is likely to have a screen (or sacrificial) oxide which protects the Si-SiO interface, and an HF etch is then required anyway. This study is focused on the implications of integrating these cleans into a regular CMOS process flow, and actual cleaning equipment already existing in the fabrication line were used. Conventional and synchrotron radiation TXRF were used for monitoring of metallic contamination from the chemicals (starting wafer contamination levels were kept in the low-mid 10 cm). Particle count data wore analyzed as well. Our data indicated that standard SC1/SC2 flow gives slightly better GOI, while HF mixtures had notably lower metallic contamination levels. Oxidation rates were not sensitive to the final surface condition (as a result of using dilute HF and long rinse times, and Cl-species in the oxidation recipe). Capacitance-Voltage analysis was conducted at different frequencies to study interface and bulk traps, and there were no pronounced differences among these chemistries. In the light of these data, and given the long history of proven reliability of standard SC1/SC2 without HF-last, we have concluded that 30 furnace oxides can be reliably grown using the conventional cleaning technology. HP-based mixtures might be justified for even more aggressive gate oxide thicknesses.

4:45 PM P7.6 
COMPARISON OF REMOVAL EFFICIENCY OF METALLIC IMPURITIES OF Si(100) DEPENDING ON THE CLEANING SPLITS OF (UV/O + HF) AND (HO + HF), Hyeongtag Jeon, Baikil Choi, Hanyang Univ, Dept of Metallurgical Engr, Seoul, SOUTH KOREA.

Si surface cleaning has been studied intensively in these days. One of the major concerns is about the removal of metallic impurities on Si surface. In this study, we choose contaminant elements of Cu and Fe which show high or low electronegativity values compared to Si's. The Si wafers were cleaned using piranha (H=4:1) and HF (HF:HO=1:100) solutions to eliminate the organic impurities and native oxide. The initial Si wafers were then contaminated intentionally by dipping into the 1 ppm standard solution of Cu and Fe and cleaned by the cleaning splits of the chemical solution HF combined with UV/O3 treatment and the chemical mixture of H and HF. The initial wafers which were contaminated with the standard solutions exhibited the contamination levels of 10 10 atom/cm and removed down to levels as low as 10 atom/cm which were monitored by TXRF (Total Reflection X-ray Fluorescence). And repeated treatments of these cleaning splits improved the surface microroughness of these initial wafers which were measured by AFM (Atomic Force Microscopy). The minority carrier lifetime was measured by SPV (Surface Photovoltaic) method. The surface and interface morphologies of Cu and Fe contaminated surface were examined by SEM (Secondary Electron Microscopy) and TEM (Transmission Electron Microscopy). The contact angles after each cleaning step were monitored to investigate the hydrophobicity and hydrophilicity of the Si surface. These results will be discussed and compared depending on the cleaning splits.

5:00 PM P7.7 
STUDY ON Cu CLEANING EFFICACY DEPENDING ON INITIAL CONTAMINATION METHOD, Jong-Soo Kim, Hiroshi Morita, Jae-Dong Joo, Tadahiro Ohmi, Tohoku Univ, Dept of Electronics, Sendai, JAPAN.

We investigated the dependence of cleaning efficiency for Cu on Si surface on the methods of pre-contamination treatments with different contamination solutions and various initial metal concentrations on Si surfaces. Through this study, we found that the Cu contaminated in ultra pure water(UPW)spiked with 1ppm CuCl2 could not be removed perfectly by cleaning with solutions having strong dissolubility for Cu such as surfuric acid-hydrogen peroxide mixture(SPM),ozonized-ultra pure water(O3-UPW) and hydrochloric acid-hydrogen peroxide mixture(HPM)showing a dependence of cleaning efficiency on dipping time for contamination into UPW. In contrast, the Cu contaminated with the level of 3E+14 atoms/cm2 in diluted-hydrofluoric acid(DHF)spiked with 1ppm CuCl2 was removed below detection limit of 2E+09 atoms/cm2 by cleaning with SPM, O3-UPW and HPM without dipping time dependence. The different desorption behaviour of Cu contaminated in UPW from that of DHF can be interpreted by the fact that the Cu exists in the oxide grown during contamination in UPW due to metal-induced-oxidation (MIO)effect of metal Cu particle and then the Cu inside the oxide can not be removed by only dissolution process of SPM,O3-UPW and HPM without etching effect. The MIO effect in UPW was confirmed by x-ray photoelctron spectroscopy(XPS) analysis on the Si surface contaminated in UPW. From the XPS spectra, it was shown that the thickness of metal-induced-oxide increased with dipping time into UPW spiked with CuCl2. Therefore, we can also explain the dependence of cleaning efficiency on the initial Cu concentration which increase with dipping time by MIO effect.

5:15 PM P7.8 
SPFM PRE-CLEANING FOR FORMATION OF SILICON INTERFACES BY WAFER BONDING, Stefan Bengtsson, Chalmers Univ of Technology, Dept of Solid State Electronics, Goteborg, SWEDEN; Karin Ljungberg, Technical Univ of Denmark, Mikroelektronik Centret, Lyngby, DENMARK.

This abstract presents results on the use of H:HF (SPFM), at low HF concentrations (10 to 1000 ppm), as the cleaning procedure prior to formation of Si/Si interfaces by wafer bonding. Cleaning issues are extremely important for wafer bonding applications. The electrical properties of Si/Si junctions are strongly affected by the cleaning procedures used before the wafers are brought into contact. Furthermore, the ability of the surfaces to form successful and high-yield bonds is extremely dependent on microroughness, surface termination, and particles. The aim of this project was to investigate surface preparation procedures capable of enhancing the room temperature bondability as well as giving good electrical characteristics of bonded Si/Si junctions. The SPFM cleaning process makes it possible to achieve a hydrophilic (OH terminated) surface, thereby achieving a strong room temperature bond. Hydrophilic surfaces also have less tendency of attracting particles from air and chemicals, which decreases the particle contamination probability at the interface. By using SPFM instead of another hydrophilizating cleaning process, the interfacial oxide can be kept at a minimum, ensuring good electrical properties of the bonded Si/Si junction. Results from surface analysis using XPS and AFM after cleaning in SPFM will be presented. The SPFM cleaned surfaces exhibit very good bonding properties. The surfaces bond spontaneously and the formed interfaces show high surface energies. Electrical characterization, using IV measurements and spreading resistance, were performed on bonded Si/Si junctions. The results show that Si/Si junctions with excellent electrical properties can be formed by wafer bonding after SPFM cleaning. SIMS analyses have been used to map the presence of impurities in the vicinity of the bonded interface. A comparison with results after other cleaning procedures will be presented.

SESSION P8: POSTER SESSION 
Wednesday Evening, April 2, 1997
8:00 P.M. 
Salon 7

P8.1 
ANALYTICAL MODELS FOR RINSING PROCESSES IN AQUEOUS IMMERSION EQUIPMENT, Robert N. Walters, Paul G. Lindquist, John J. Rosato, SCP Global Technologies, Boise, ID.

The rinsing behavior of silicon wafers in aqueous immersion equipment has received a great deal of interest in recent years. The benefits of a low consumption rinse process are best seen in the reduction of capital and recurring costs associated with facilitizing aqueous equipment. Historically, several first order models were developed to predict the performance of the entire rinsing process. These prior techniques model the removal of a chemical carry-over volume from an array of silicon wafers and a rinse bath as a continuously stirred tank reactor (CSTR) system. The present work develops more detailed models that focus only on the removal of chemicals from the wafer surface. Several models are presented that predict the removal rate of chemicals from the wafer surface. These models account for the convective and diffusive aspects of mass transport during rinsing. The effect of wafer gap aspect ratio and the physical properties (viscosity, thickness, species) of the carry-over volume are also defined. This effort extends the previous analytical rinsing models to include nonlinear effects and reduces the number of assumptions used to develop these models. Empirical data is obtained from the use of a specially designed wafer gap conductivity probe and rinsing chamber. Experimental data is used to compare the accuracy and applicability of these models. By comparing the various models with the experimental results, the extent to which convection and diffusion each affect the rinsing process can be determined. The result is a useful technique to determine the optimum cleaning flow regime and the rinsing performance of real world configurations.

P8.2 
THE EFFECT OF SUBSTRATE CONDITION AND CONTAMINATION SOLUTION ON THE GROWTH OF COPPER PARTICLES, Geun-Min Choi, Hyundai Electronics Industries Co Ltd, Dept of Advanced Process, Sendai, JAPAN; Katsuyuki Seikine, Tohoku Univ, Dept of Electrical Engr, Sendai, JAPAN; Hiroshi Morita, Tadahiro Ohmi, Tohoku Univ, Dept of Electronics, Sendai, JAPAN.

Cu particle growth behavior on crystal silicon (c-Si) and amorphous silicon (a-Si) in the contamination solution (CuCl and CuF) has been investigated. This study reveals that the growth behavior of Cu particle depends on the contamination solution and the substrate condition. Contamination level is found to be insignificant in terms of Cu particle growth. When 1 ppm Cu in UPW (Ultra Pure Water) is spiked as a function of time, the amount of Cu impurity on a-Si in the early stage is 2 orders of magnitude higher than that of c-Si irrespective of contamination solution. The native oxide thickness grown on c-Si during contamination shows a dependence on the contamination solution, whereas that on a-Si is independent of contamination solution. We will present the above data in more detail and discuss the Cu particle growth behavior with contamination solution and substrate condition.

P8.3 
COMPARISON AND REPRODUCIBILITY OF H-PASSIVATION OF Si(100) WITH HF IN METHANOL, ETHANOL, ISOPROPONOL AND WATER BY IBA, AFM, AND FTIR, Vasudeva P. Atluri, Intel Corp, Chandler, AZ; Nicole Herbots, D. Dagel, H. Jacobsson, M. Johnson, Arizona State Univ, Dept of Physics & Astronomy, Tempe, AZ; R. Carpio, Burt Fowler, SEMATECH Inc, Austin, TX.

Three HF:Alcohol solutions were investigated to develop a low temperature surface cleaning method for Si. HF:Alcohol solutions can etch native SiO while passivating Si with H. H can then be desorbed at low temperatures. In this work, Si (100) wafers are etched in a solution of HF in alcohol after a modified RCA cleaning, to produce (1 x 1) H-terminated hydrophobic surfaces ordered at room temperature. Si (100) etched by either HF:Methanol, or HF:IPA, or HF:Ethanol were analyzed by Ion Beam Analysis (IBA), Atomic Force Microscope (AFM), and-Fourier Transform Infrared Spectroscopy (FTIR). Residual O and C were measured by nuclear analysis (NRA) combined with ion channeling at 3.05 MeV and 4.265 MeV, respectively. Hydrogen was detected by the elastic recoil of He at 2.8 MeV. A 60 second etch in HF:Ethanol followed by 5 minutes rinse in deionized water was more effective in removing surface carbon, whereas a 60 second etch in HF:IPA followed by dewetting in air and quick rinse in deionized water removed more surface oxygen. Si (100) etched for 60 seconds in HF:IPA followed by 5 minutes rinse in IPA exhibited the highest amount of hydrogen. Samples etched by aqueous HF during preclean processing showed more O by a factor of 1.61, whereas C levels were either more or less within a factor range of 1.12 to 0.91 and less H by a factor of 0.70 when compared to alcohol solutions. Reproducibility studies showed that variation in Si (100) surface coverages range between 1.68 x 10 to 3.35 x 10 atoms/cm for C, and 9.64 x 10 to 7.67 x 10 atoms/cm for O, respectively. H coverage was reproducible within 6.3. AFM showed that all etched surfaces exhibited more roughness compared to the original Si (100) surface and there was little difference between alcohols. FTIR in ATR mode detected Si hydrides mostly as a dihydride. Both IBA and FTIR detected significant levels of oxygen indicating that while the surface is better passivated than with aqueous HF and easily desorbed at low temperature, it is not completely H terminated but has a more complex composition.

P8.4 
VERY HIGHLY CHARGED IONS LIKE Au: A NEW TOOL FOR SURFACE ANALYSIS, Thomas Schenkel, Lawrence Livermore National Laboratory, Livermore, CA; A. V. Hamza, A. V. Barnes, D. H. Schneider, Lawrence Livermore National Laboratory, Physics & Space Tech Directorate, Livermore, CA.

The interaction of slow (vv), highly charged ions with surfaces is characterized by a dominance of electronic over collisional effects. A single Au ion deposits a total potential energy of 160 keV into a nanometer sized near surface volume when it neutralizes at its impact on a surface. The energy density of such a neutralization process is much higher than corresponding near surface nuclear and electronic energy losses of conventional singly charged ions. Consequently, secondary electron- and ion production rates are increased by two orders of magnitude in highly charged ion based secondary electron microscopy and SIMS. Substantial useful yield increases in highly charged ion based TOF-SIMS could result in drastically improved sensitivity limits for the detection of surface impurities beyond the current limits of 10-10 at/cm.

P8.5 
ELECTRICAL CHARACTERIZATION OF ULTRA-THIN OXIDES GROWN ON SILICON SURFACES CLEANED IN ULTRA-HIGH VACUUM, Christian Leth Petersen, Francois Grey, Technical Univ of Denmark, Dept of Microelectronics, Lyngby, DENMARK.

We are investigating the properties of ultra-thin ( <2 nm) silicon oxides, using a four-point probe technique. Prior to oxidation, the silicon surfaces are cleaned by heating to 1250 C in an Ultra-High Vacuum (UHV) chamber with a base pressure of less than 110 Torr. After cleaning, the surfaces form the well-known Si(100)2x1 or Si(111)7x7 reconstructions. 
The clean surfaces are then exposed to small amounts of molecular oxygen. During the formation of an ultra-thin oxide, the surface resistivity is monitored with a four-point probe. The changes in resistivity reveal information about the surface states (through the band bending) and the surface mobilities. The changes in surface mobilities are mainly caused by roughening. 
Our measurements on Si(100) are dominated by an effect which is consistent with falling surface mobilities, suggesting a significant roughening of the (100) surface during oxidation. On the other hand the Si(111) measurements are interpretable in terms of band bending alone, giving evidence of a multi-stage reaction. Indeed, during the adsorption of the first monolayer of oxygen, the surface conductivity actually increases significantly. 
The dependence of the surface mobilities on dopant type and dopant concentration are being investigated using the four-point probe technique, and results of these studies will be presented.

P8.6 
SCANNING TUNNELING MICROSCOPY STUDY OF THE PHOTOCHLORINATION OF H-Si(111), Christopher P. Wade, Stanford Univ, Dept of Chemistry, Stanford, CA; Matthew R. Linford, Max-Planck-Inst, Berlin, GERMANY; Huihong Luo, Stanford Univ, Dept of Chemistry, Stanford, CA; Jeff Terry, Northwestern Univ, Dept of MS&E, Evanston, IL; Renyu Cao, Stanford Univ, Stanford Synchrotron Radiation Lab, Stanford, CA; Renee Mo, Stanford Univ, Dept of Chemistry, Stanford, CA; Piero Pianetta, Stanford Univ, Stanford Synchrotron Radiation Lab, Stanford, CA; Christopher E. D. Chidsey, Stanford Univ, Dept of Chemistry, Stanford, CA.

Well-ordered H-Si(111) surfaces prepared in 40% ammonium fluoride solutions are cleanly and completely chlorinated in moderate pressure chlorine gas with illumination by 350 nm light. We have shown that this simple, non-UHV method results in a highly- ordered Cl-Si(111) (1x1) surface of a quality equal to that of the ideal H-Si(111) surface. Scanning tunneling microscopy (STM) reveals a (1x1) adsorbate lattice of Cl-Si(111). In addition, STM shows that the large terraces (500-2000 Å) of H-Si(111) are preserved upon photochlorination. Analysis of small (50-100 Å) pits seen on the H-Si(111) and Cl- Si(111) surfaces shows that no significant nucleation of new pits or growth of existing pits occurs during photochlorination; furthermore, there is no significant etching of step edges.

P8.7 
UNDERSTANDING THE CORRELATION OF SURFACE SIMS AND TXRF, Dinean Gupta, Jenny M. Metz, Michael Edgell, Charles Evans & Associates, Redwood City, CA.

TXRF is the industry standard technique for characterizing surface metals on silicon wafers. It is used to perform survey analyses of elements from S to U, with a detection sensitivity of approximately 10 atom/cm for transition metals. SurfaceSIlMS is an emerging analytical technique that relies on specialized analytical protocols to extend surface measurement capabilities two ways: by monitoring lighter Z elements such as Al, Na, and Li; and by providing detection limits of 10 atom/cm for selected elements. Applicatiom of the two techniques to the same samples has led to better understanding of surface preparation processes. Discrepancies between results from the two techniques has been traced to differences in analysis depth and area, distribution of elements with respect to the sample surface, element mobility, and SIMS RSF (relative sensitivity factor) values. This paper presents data clarifying these issues, as well as data from analysis of standard samples. The latter data confirms that the two techniques give congruent results.

P8.8 
IN-SITU CHEMICAL CONCENTRATION CONTROL FOR WAFER WET PROCESSING, Ismail I. Kashkoush, Eric Brause, SubMicron Systems Corp, Allentown, PA.

This paper demonstrates the use of conductivity sensors to monitor and control the concentration of HF, SC1 and SC2 cleaning solutions. Commercially available electrodeless conductivity sensors were used to monitor and control the chemical concentration during wet cleaning solutions. A linear relationship between the conductivity of the solution and the chemical concentration was obtained, within the range studied. A chemical injection scheme (ICE-1) was developed to maintain the chemical concentration within specified limits. Different concentrations of HF, SC1, and SC2 solutions were investigated. Results show that these techniques are suitable for monitoring and controlling the concentration of chemicals in the process tanks for better process control. These techniques provide low cost of ownership of the process by using dilute chemicals and longer bath life, i.e. more environmentally sound processes.

P8.9 
A NOVEL SURFACE PREPARATION AND POST-ETCH REMOVAL TECHNIQUE FOR InGaAs SIDEWALLS, Seyed Ahmad Tabatabaei, G. A. Porkolab, S. Agarwala, F. G. Johnson, S. A. Merritt, O. King, M. Dagenais, Y. Chen, D. Stone, Univ of Maryland, Dept of Electrical Engr, College Park, MD.

This paper describes in detail a surface preparation and post-etch removal technique developed for InGaAs sidewalls based on TMAH, IPA, and H chemistry. It illustrates the results demonstrating the effect of sidewall post-etch, surface preparation, and surface passivation on the performance of high speed InGaAs detectors. Dark current density for circular diodes with a diameter size varying between 10 and 100 m was measured at a reverse bias voltage of 5 V. The effectiveness of various surface preparation techniques was studied by measuring the immediate improvement in dark current density, as well as its long-term stability. Dark current densities in the order of 100 fA/m were obtained. The benefits of this new technique compared to other techniques we have investigated include improved device characteristics, long-term stability, as well as a much less critical process to achieve optimum surface properties.

P8.10 
Si SUBSTRATE SURFACE UV-OZONE CLEANING, Olga Bakshinska, Pavlo Galiy, Taras M. Nenchuk, Lviv State Univ, Dept of Physics, Lviv, UKRAINE.

Gaseous phase chemical processes induced by UV-photons in oxygen atmosphere are most perspective for solving the problem of Si substrate surface cleaning from carbon-containing organic contaminants in microelectronic technologies. The cleaning processes of n-Si surface during irradiation in oxygen atmosphere have been studied by Auger electron (AES) and mass-spectroscopies in-situ. The influence of such factors as chemical state of Si surface (laboratory and UHV cleavages), samples temperature, geometry of UV irradiation incidence (normal or parallel to the surface) on kinetics and cleaning degree of Si surface from carbon during UV irradiation in O atmosphere was investigated. The processes of CO absorption on UHV cleavages of Si(111) surfaces with further UV cleaning in oxygen atmosphere were studied also. The thickness of layers in layered structures n-Si/SiO created dependently on exposition time, temperature and composition of laboratory atmosphere was evaluated by quantitative AES. 
It is established that UV irradiation of Si surface in O atmosphere generates the ozone molecules (O) and active oxidant-atomic oxygen (O) and also stipulates the excitation and destruction of adsorbed on Si surface molecules of carbon contaminants, facilitating their oxidation and creation of volatile carbon compounds. The UV irradiation at elevated temperatures of Si surface in O atmosphere provides sufficient fast and complete excluding of carbon from the surface of (111) Si UHV cleavages after CO adsorption and with irradiation time and temperature raise creates on it the passivation oxide layer SiO. The UV cleaning at O atmosphere of Si surfaces exposed in laboratory atmosphere gives the possibility to reduce the carbon amount on the surfaces per 3-5 times and may be effectively applied for Si substrate cleaning in technology installations of molecular-beam epitaxy.

P8.11 
ANALYSIS OF ORGANIC CONTAMINANTS IN GASES USING NON-VOLATILE RESIDUE (NVR) MONITORS AND TIME-OF-FLIGHT SECONDARY ION MASS SPECTROMETRY (TOF-SIMS), Patricia M. Lindley, Charles Evans & Associates, Redwood City, CA; W. D. Bowers, Femtometrics, Irvine, CA; G. S. Strossman, Charles Evans & Associates, Redwood City, CA.

Increasing capabilities in semiconductor applications are often tied to more stringent requirements for surface cleanliness in the processing environment. One area of concern as a source of contamination is the chemicals supplied for various processing steps. In particular, a need has been identified to measure low levels of nonvolatile residue (NVR) contaminants in process gases used in the microelectronics industry. Current techniques for evaluating contamination in these gases are limited in that they require relatively large volumes of gas to be used for the testing process, and often only provide information about specific types of contamination. New techniques should have good sensitivity to low levels of contamination, provide specific chemical information that will allow a compound to be traced to its source, and operate under conditions that permit the analysis of a wide range of materials. This work describes a technique for gas contaminant analysis that combines a sensitive Nonvolatile Residue (NVR) monitor to quantify levels of contamination with Time-of-flight Secondary Ion Mass spectrometry (TOF-SIMS) to identify the detected contaminants. The NVR monitors are based on sensitive piezoelectric microbalance sensors that can detect submonolayer levels of airborne molecular contamination. TOF-SIMS, with its high sensitivity and ability to provide fingerprint spectra that can be compared to reference materials, can then be used to provide specific chemical identification of many types of contaminants.

P8.12 
LIFETIME CHARACTERIZATION OF POLY-SILICON BACK-SEALED WAFERS WITH BI-SURFACE PHOTOCONDUCTIVITY DECAY METHOD, Yoh-Ichiro Ogita, Yugo Uematsu, Kanagawa Inst of Technology, Dept of E&EE, Kanagawa, JAPAN; Hiroshi Daio, Showa Denko KK, Resaerch & Development Ctr, Saitama, JAPAN.

Bi-Surface Photoconductivity Decay (BSPCD) method has been useful to obtain the true bulk lifetime and surface recombination velocities in silicon wafers with variously finished surfaces. N-type CZ silicon wafers with and without poly-Si back seal (PBS) were subjected to a thermal oxidation in dry O ambient for 30 min followed by the lifetime measurement with BSPCD method using 500 MHz microwave reflection. Effective lifetimes of the wafers were 112 s for the PBS wafer and 486 s for the no-PBS one, respectively. The difference in the effective lifetime was mainly attributed to the back surface recombination velocities (S) which were measured to be 4027 cm/s for PBS and 16 cm/s for no-PBS. The very fast Sw for PBS is related to the poly-Si/Si interface character. This method can clarify the recombination properties of both the front (S) and back surfaces to obtain the bulk lifetime (). For example, for the PBS wafer (1059 s) was much higher than the no-PBS one (580 s), which reveals the PBS gettering effect against for the oxidation induced contamination.

P8.13 
THE EFFECTS OF H-PLASMA CLEANING ON THE REMOVAL OF METALLIC IMPURITIES CONTAMINATED ON Si(100), Hyeongtag Jeon, Taehang Ahn, Hanyang Univ, Dept of Metallurgical Engr, Seoul, SOUTH KOREA; Woong Park, Inha Univ, Dept of Metallurgical Engr, Inchon, SOUTH KOREA; Chomgmu Lee, Hanyang Univ, Dept of Metallurgical, Inchon, SOUTH KOREA.

Removal efficiency of metallic impurities, especially Fe and Ni, contaminated on Si substrate were investigated by dry cleaning methods such as the remote RF H-plasma and ECR H-plasma. The metallic impurities can affect the device reliability and yields significantly, and are contaminated easily in the level of 10 atoms/cm during the process steps such as RIE (reactive ion etching), sputtering, and ion implantation. These metallic impurities should be removed below the level of 10 atoms/cm through the cleaning procedures between steps. In this study, the bare Si substrates were precleaned by piranha (H=4:1, 120C) and HF (HF:HO=1:10, RT) cleans to eliminate the organic contaminants and native oxide. These bare substrates were intentionally contaminated by dipping into the 2 ppm standards solution of each metallic impurity. The remote RF H- and ECR H-plasma treatments were conducted as a function of the plasma powers, exposure times and substrate temperatures. After these plasma treatments, the characterization for each substrate were carried out using TXRF (total reflection x-ray fluorescence) and AFM (atomic force microscopy). And the changes of minority carrier lifetime were also measured by SPV (surface photovoltage) method to verify the temperature effect. The hydrophobicity and hydrophilicity of Si surface were verified by measuring the contact angles. From these results, the removal mechanism or model of metallic impurities will be proposed and discussed.

P8.14 
GROWTH CHEMISTRY OF ULTRATHIN SILICON NITRIDE AND OXYNITRIDE PASSIVATION LAYERS ON Si(100), Arvind Kamath, Univ of Texas-Austin, Dept of Chemistry & Biochemistry, Austin, TX; B. Y. Kim, D. L. Kwong, Univ of Texas-Austin, Dept of Electrical & Computer Engr, Austin, TX; P. M. Blass, Y. M. Sun, J. M. White, Univ of Texas-Austin, Dept of Chemistry & Biochemistry, Austin, TX.

The scaling Of MOS gate dielectric thickness below 50 Ådemands the use of chemically modified gate oxides and passivation layers for Si(100). It is of basic scientific and technological value to understand the initial stages of growth of technologically promising dielectric passivating thin films. In this study we compare the thermal growth chemistry and bonding structure in three ultrathin (5-25 Å) passivation layers on Si(100), namely silicon nitride, NO/Si(100) grown oxynitride and NO annealed SiO. Well characterized HF-dipped Si(100) surfaces were (oxy)nitrided using NO/NH in an Integrated CVD-Surface Analysis System. The evolution of initial stages of film growth was nondestructively evaluated from 560C (above the H-desorption temperature of 520C) to 1000C for short time durations (10-120 s) at low pressures (-4 Torr). X-Ray Photoelectron Spectroscopy was used to analyze the films. The growth kinetics of silicon nitride using NH/Si(100) show a tendency to rapidly increase and saturate within the first 60 s of growth under these conditions. The N1s Binding Energy is constant at 397.6 eV indicating a NSi bonding environment. The Si2p Binding Energy difference ranges from 1.9 eV at a thickness of 5 A to a maximum of 2.5 eV for thicker films. For NO/Si(100) growth, with increasing growth temperature and time, a bonding structure with Si-O rather than Si-N formation is favored. Simultaneously, the average volume fraction of bulk N (N/N+O) in the dielectric decreases. NO appears to remove previously incorporated N. NO annealing of 10 ÅSiO and CuF) has been investigated. This study reveals that the growth behavior of Cu particle depends on the contamination solution and the substrate condition. Contamination level is found to be insignificant in terms of Cu particle growth. When 1 ppm Cu in UPW (Ultra Pure Water) is spiked as a function of time, the amount of Cu impurity on a-Si in the early stage is 2 orders of magnitude higher than that of c-Si irrespective of contamination solution. The native oxide thickness grown on c-Si during contamination shows a dependence on the contamination solution, whereas that on a-Si is independent of contamination solution. We will present the above data in more detail and discuss the Cu particle growth behavior with contamination solution and substrate condition.

SESSION P9: ANALYTICAL STUDIES OF SURFACES 
Thursday Morning, April 3, 1997
Golden Gate A3

8:00 AM P9.1 
SILICON SURFACE METAL CONTAMINATION MEASUREMENTS USING GRAZING EMISSION XRF SPECTROMETRY, Stefan de Gendt, IMEC, UCP-VMT, Leuven, BELGIUM; Paul W. Mertens, Marc M. Heyns, IMEC, Leuven, BELGIUM; Guido Wiener, Philips Research Laboratories, Dept of Prof Instr Research, Eindhoven, NETHERLANDS; S. J. Kidd, Martin Knotter, Philips Research Laboratories, Eindhoven, NETHERLANDS; Pieter K. de Bokx, Philips Research Laboratories, Dept of Prof Instr Research, Eindhoven, NETHERLANDS.

Trace amounts of metal contamination on silicon wafer surfaces have a deleterious impact on device yield. To monitor metal contamination on silicon surfaces, Total Refection X-Ray Fluorescence (TXRF) techniques have gained worldwide acceptance. Instrumental design (energy dispersive (ED) detector system) of the commercially available tools, typically limits the applicability to metal contaminants with Z > 20. This can be resolved by using wavelength dispersive (WD) detection systems. Unfortunately, intensity loss due to monochromatization and collimation of the primary grazing incident x-ray beam in TXRF forces the use of large solid angle detectors (i. e., ED). However, inversion of the setup resolves this problem, i.e., an uncollimated, polychromatic incident x-ray beam roughly perpendicular to the substrate and x-ray detection at grazing angle. This has ]ed to the development of Grazing Emission X-Ray Fluorescence Spectrometry (GEXRF). The principle and design of a prototype instrument will be briefly discussed. This paper will describe the potential of GEXRF as an analysis tool for silicon surface contamination with Z <20. We have found that straight GEXRF analysis yields limits of detection for Mg, Al, and Ca in the order of e at/cm. It is anticipated that this figure can be improved by optimizing the design of our prototype tool. Also, the use of preconcentration methods such as Vapor Phase Decomposition-Droplet Surface Etching (VPD-DSE) are likely to improve these limits of detection. Results will be presented on VPD-DSE-GEXRF for metals with Z < 20. Additionally, we will present initial studies on the potential of GEXRF to qualitatively (and quantitatively) monitor the presence of carbon and oxygen on silicon wafers.

8:15 AM P9.2 
STATE-OF-THE-ART EVALUATION OF ULTRA-CLEAN ULSI PROCESSES, Alice Fischer-Colbrie, Hewlett Packard Co, Matls Characterization Group, Palo Alto, CA; S. S. Laderman, Hewlett Packard Co, Palo Alto, CA; S. Brennan, S. Ghosh, N. Takaura, Piero Pianetta, Stanford Univ, Stanford Synchrotron Radiation Lab, Stanford, CA; A. Shimazaki, Toshiba Corp, Kanagawa, JAPAN; D. Wherry, S. Barkan, Kevex Inc, San Carlos, CA.

Ultra-clean Si wafer surfaces are critical to the fabrication of ULSI-quality gate oxides. This work describes recent progress in implementation and applications of synchrotron radiation total reflection x-ray fluorescence (TXRF) to measure trace metals on wafer surfaces. To date, we have achieved state-of-the-art transition metal sensitivity of atoms/cm (fg) for impurities which have a monolayer-like distribution on the surface and <1fg for droplet-like impurities. Recent instrumentation breakthroughs include reduction of detector parasitic backgrounds (particularly Cu) to below our present detection limit, full 150 and 200mm wafer handling, wafer mapping capability, and a filtered cleanroom mini-environment. With these upgrades, measurements were made by our group as well as scientists from Sematech member companies of full wafers from various steps in the integrated circuit fabrication process. In particular, we compared metal levels for wafers with different cleans and cleaning equipment as well as the increase in metal levels from pre- to post- gate- oxidation. These data show that the higher sensitivity made possible with synchrotron radiation makes new applications possible. With the completion of on-going developments, this method could be integrated into ULSI process development.

8:30 AM P9.3 
DETECTION OF LOW-LEVEL COPPER CONTAMINATION ON SILICON SURFACES BY DROP NUCLEATION, Thomas D. Lee, Frans Spaepen, Harvard Univ, Engr & Applied Sciences Div, Cambridge, MA; Jene A. Golovchenko, Harvard Univ, Dept of Physics, Cambridge, MA.

Nucleation and growth of liquid drops from the vapor can be used to locate efficiently surface inhomogeneities such as topological defects, oxide patches, metallic impurities, organic contamination or particles. In this study, nucleation of water droplets was used to investigate the surfaces of copper-contaminated silicon substrates. Hydrogen-terminated silicon (111) and (100) substrates were dipped into copper-contaminated ultrapure water and exposed to supersaturated water vapor. The amount of copper deposited was varied by changing the strength of the solution or the exposure time. Nucleation occurred at vapor pressures very close to the saturation vapor pressure of water. Higher densities of nucleated drops appeared on areas with greater concentrations of copper. Using this technique, it was possible to detect copper concentrations as low as 10 cm as checked by a combination of Rutherford backscattering spectrometry and total reflection X-ray fluorescence. Below this concentration, treated and untreated substrates showed similar drop densities.

8:45 AM P9.4 
INFRARED SPECTROSCOPY OF COVALENTLY BONDED SPECIES ON SILICON SURFACES, Huihong Luo, Christopher E. D. Chidsey, Stanford Univ, Dept of Chemistry, Stanford, CA; Gregory Thomas Merklin, Stanford Univ, Dept of Chemsitry, Stanford, CA; Yves Chabal, Bell Labs, Lucent Technologies, Dept of Physics, Murray Hill, NJ.

Hydrogen-terminated surfaces are well known to be stable under ambient conditions. We show that they can be reacted with various reagents under non-UHV conditions to form other covalent bonded species, including Si-Cl and Si-Co(CO)4. These species are characterized by polarized ATR and transmission FTIR. On Si(111)-Cl surfaces, Si-Cl is found perpendicular to the surface. On Si(111)-Co(CO)4 surfaces, we found one carbonyl is perpendicular to the surface, and the other three are approximately parallel to the surface. We also investigate the deuterium-terminated silicon surfaces formed in KF/D2O/DCl by FTIR.

9:00 AM P9.5 
VALENCE BAND DISCONTINUITY AT AND NEAR THE SiO/Si(111) INTERFACE, Hiroshi Nohira, Musasahi Inst of Technology, Dept of EEE, Tokyo, JAPAN; Takeo Hattori, Musasahi Inst of Technology, Tokyo, JAPAN.

We have investigated the effect of interface structure on valence band discontinuity at the interface, in addition to the effect of structural transition near the interface on valence band structure of silicon oxide by measuring the changes in x-ray excited valence band spectra with progress of oxidation in 1 Torr dry oxygen at 600 800 C through 0.5 nm thick preoxide formed on hydrogen-terminated Si(111)-1x1 surface in the same oxidation atmosphere. By taking difference between two valence band spectra measured for two oxide film thicknesses, which are close to each other so as to eliminate the valence band spectrum of Si substrate, the valence band spectrum of oxide surface can be obtained. From the dependence of this difference on oxide film thickness, the valence band discontinuity of about 0.2 eV was found to appear in the oxide at 0.9 nm distant from the interface, which probably agrees with the thickness of structural transition layer. The difference taken between valence band spectra measured for two photoelectron take-off angles, that is, 15 and 90 degrees, so as to eliminate the valence band spectrum of Si substrate, can be explained by considering the valence band discontinuity in the oxide and non-uniformity of oxide film thickness expressed by Gaussian function with full width half maximum of 0.5 nm. Furthermore, the valence band discontinuity at the interface changes in accordance with the periodic change in interface structure with the progress of thermal oxidation [l].

9:15 AM P9.6 
GROWING BEHAVIOR OF NATIVE OXIDE ON Si SURFACE WITH VARIOUS RESISTIVITY IN UPW AND Cu CONTAMINATED UPW, Katsusyuki Sekine, Tohoku Univ, Dept of Electronics, Sendai, JAPAN; Geun-Min Choi, Hyundai Electronics Industries Co Ltd, Dept of Advanced Process, Sendai, JAPAN; Tadahiro Ohmi, Tohoku Univ, Dept of Electronics, Sendai, JAPAN.

As device dimension are decreasing more and more, the control of native oxide growth on silicon surface is one of the most important issue in ULSI fabrication process. We have used X-Ray photoelectron spectroscopy (XPS) to study the native oxide growing behavior on silicon surface with various resistivities in ultra pure water (UPW) and UPW contaminated with CuF2. Our data revealed that the native oxide growing behavior in UPW spiked with CuF2 is different from that in UPW. Native oxides grown in UPW spiked with CuF2 are thicker than those grown in UPW regardless of samples resistivity and Cu2+ ion concentration. Native oxide thickness increases with the increase of Cu2+ ion concentration in UPW. These suggest that Cu2+ ions assist growth of native oxide. In UPW native oxide thickness increases with decrease of samples resistively. In UPW native oxide thickness mainly depends on resistivity. This phenomena can be explained by the filed-assisted oxidation model. On the other hand in UPW with CuF2, native oxide thickness does not depend on resistivity for low resistivity silicon surface. We will discuss these results in more detail at the conference.

9:30 AM P9.7 
UTILIZING BATH/WAFER CONTAMINATION CORRELATIONS TO VALIDATE A PRE-GATE CLEANING STRATEGY, Terry L. Gilton, Micron Technology, Boise, ID; Kate Copsey, Willamette Univ, Salem, OR; Clarence Higdon, Micron Technology, Boise, ID.

The correlation of contaminants in a process bath with contaminants on a silicon wafer prepared in the bath is important information when developing a cleaning strategy. In this paper, we present such a correlation focused on contaminants in dilute HF (100:1) and in SC-1 (1:1:5 and 1:1:80 at 50C and 65C). We have limited the contamination levels to between 0 and 150 ppb. We have also limited the elements studied to those that are most likely to be a problem (Fe, Al, Mg, Ca, Cu, Zn and Na). The bath concentrations are measured using ICPMS and the wafer surface concentrations are measured using both VPD/TXRF and VPD/ICPMS. We demonstrate that Fe and Ca at the levels studied do not deposit on the wafers in dilute HF, while Cu most certainly does. The wafer contamination shows a linear dependence on the bath contamination. We also demonstrate that in the SC1 bath, both concentration and temperature are important variables in the contamination of wafers for a given bath contamination level. Al and Zn contaminate wafers most strongly, with Al being the largest contributor at the higher concentration of SC-1 and Zn being the largest contributor in the lower concentration. Finally, we demonstrate that a dilute HF clean can remove everything deposited in a highly contaminated SC-1 bath.

9:45 AM P9.8 
EFFECTS OF THE UNDERLAYER SURFACE STATE ON THE INTERCONNECTING ALUMINUM FILM PROPERTIES, Sam-Dong Kim, Chan-Soo Shin, Noh-Jung Kwak, Keoung-Bock Lee, Oh-Jung Kwon, Chung-Tae Kim, Hyundai Electronics Industries Co Ltd, Memory R&D Div, Kyoungki-do, SOUTH KOREA.

Aluminum has been a primary interconnecting material in ultralarge scaled integration (ULSI) silicon devices because of a variety of advantages in electrical property, film fabrication and etch. However, as device feature size becomes smaller and smaller, aluminum metallization process is facing a new challenge. This challenge includes aluminum planarization over sub-half micron vias thermal/electromigration stability of interconnection structures and residue-free etching of the aluminum metallizations. Much effort [1, 2] has been made to obtain aluminum interconnecting lines free of residue and defects by improving etch scheme. In this study, we describe effects of the underlayer oxide surface state on the aluminum surface quality. Imperfections and micro roughness of the aluminum surface shows a great deal of impacts on the metal interline bridge yield. 
For this study, we sputtered 5000 Al-1.0Si0.5Cu (at 500C) / 500 Ti on a variety of oxide underlayers. To examine the surface roughness, root mean square (RMS) value of surface altitude was measured by atomic force microscopy (AFM). Sessile drop contact angle measurement was performed to examine surface state of the oxide layers. Under clean environment, surface state of the thermal oxide was gradually altered from hydrophilic (contact angle 5 ) to hydrophobic ( 75 ) with time - delay. Carbon-complex contamination was observed by X-ray photoelectron spectroscopy (XPS) and Auger electron spectroscopy (AES) from hydrophobic thermal oxide layers which stayed in clean environment longer than a day [3]. As underlayer oxide surface state proceeds from hydrophilic to hydrophobic, we observed clear improvement in aluminum surface smoothness. Compared to hydrophobic oxide surface, hydrophilic surface produced poor (002) preferred orientation and rough surface topology of titanium layers. Subsequent aluminum layers on Ti/hydrophilic-oxide showed poor (111) preferred orientation and deep grooves between grains. By hydrofluoric acid (RF) cleaning of hydrophilic oxides, aluminum surface on these oxides showed comparable quality with that on hydrophobic oxides. Plasma enhanced chemical vapor deposited (PECVD) oxides, such as ozone undoped silicate glass (O-USG) and silicon excess silicon dioxide (SiO) have much greater surface roughness (AFM RMS 30 ) than thermal oxides (AFM RMS 2 ). Surface state of these oxides did not show clear dependence on time-delay, but strong dependence on radio frequency (RF) dry etch treatment. By using RF etch pre-treatment, we obtained hydrophobic surface state of PECVD oxides, which had hydrophilic as-deposited surface state. Surface quality of Al/Ti films was improved by RF pre-etching the PECVD underlayer oxides. We performed the conventional 0.30 m CMOS DRAM interconnection process by stacking Al/Ti/PECVD-oxides and patterning the metallizations. From this structures, metal bridge fail rate was examined with varying the surface state of underlayer oxides. Metallizations on hydrophilic oxides produced higher bridge fail rate than those on hydrophobic oxides. From these metallizations, we could observe many residual stringers, ''spot'' shaped residues and ''ring'' shaped defects, which can play key role in interline bridge fail. Metallizations on hydrophobic oxides, however, showed greatly reduced bridge fail rate, and much smaller etch defect density.

SESSION P10: WET CHEMICAL CLEANING/ ETCHING 
Thursday Morning, April 3, 1997
Golden Gate A3

10:30 AM *P10.1 
WET CHEMICAL PROCESSING IN SELECTED FRONT-END AND BACK-END APPLICATIONS, Ara Philipossian, Intel Corp, Santa Clara, CA.

This paper reviews some of the challenges encountered in wet chemical processing with respect to two front-end and two back-end applications. The first study focuses on the Ammonium-Peroxide Mixture (APM) for predate oxide clean applications and explores the effect of key parameters such as bath temperature, individual and combined trace iron and copper contents, megasonic energy, presence of wafers, fluid convection and the shape factor of the processing tank on the decomposition kinetics of hydrogen peroxide. The second study addresses the challenges encountered when using dilute hydrofluoric acids for etching sacrificial oxides in the presence of Shallow Trench Isolated areas. A new technique is presented, and integrated into mainstream CMOS processing, whereby upon implantation of nitrogen into LPCVD TEOS oxide and subsequent anneal, the field regions exhibit lower etch rates in the presence of hydrofluoric acid. The third study focuses on the effect of chloride contamination in a proprietary organic solvent used for photoresist stripping. In a controlled experiment, the organic stripper is spiked with various amounts of chloride (from different sources) and is used to strip away photoresist in the presence of submicron aluminum lines. The extent of aluminum corrosion and the types of defects are quantified using SEM. From these results, the maximum allowable chloride content is determined for the organic solvent. The results indicate that the extent of corrosion is a function of the chloride source as well as the chloride concentration. The fourth study explores the effectiveness of the APM system in etching titanium nitride. In this study, the stability of the APM (i.e., the HO, NHOH concentrations for various amounts of dissolved titanium) over time is quantified in an experimental as well as a high volume commercial wet bench. The study also proposes models for titanium nitride etch rate as well as HO decomposition.

11:00 AM P10.2 
A MODEL FOR THE ETCHING OF Ti AND TiN IN SC1 SOLUTIONS, Steven Verhaverbeke, Jennifer Parker, CFM Technologies, Dept of Process Development, West Chester, PA.

The Standard Clean 1, developed by W. Kern and D. Puotinen in 1965 and disclosed in 1970, consists of a mixture of Ammonium-Hydroxide/Hydrogen-Peroxide/ Water and is therefore also called the Ammonium-hydroxide Peroxide Mixture (APM). Originally this chemical mixture was developed for cleaning silicon wafers and has proven to be the most efficient particle removing agent found to date. Although its use as a particle cleaning solution is widespread, this mixture is also well-known for its use as a Ti and TiN strip agent. In this paper we will discuss a quantitative model for the SC1 solution. It will be shown that the etching of Ti and TiN is fundamentally different from the etching of SiO2 and the mixture of Ammonium-hydroxide and Hydrogen-Peroxide can be optimized into different ratio's for the Ti and TiN etching as opposed to the cleaning of Si wafers for particle removal. N*. Rev. B, 1996, 54(15).

11:15 AM P10.3 
THE USE OF METAL ADDITIONS TO PHOSPHORIC ACID TO ETCH POLYSILICON IN POLY-BUFFERED LOCOS PROCESSES, Charles W. Pearce, Bell Labs, Lucent Technologies, Allentown, PA; Byron C. Chung, Allentown, PA.

The use of poly-buffered LOCOS processing is a common feature of many sub-micron integrated circuit fabrication processes. However, the silicon layer interposed between the nitride oxidation mask and the pad oxide is often difficult to remove. Different strategies involve the dry and/or wet etching of the film. In this presentation, we demonstrate the utility of adding metals such as Fe or Cu to a conventional phosphoric bath used to etch silicon nitride. Additions of 60ppm of Cu+2 resulted in etch rates of 20A/min on undoped polysilicon at a process temperature of 165C. Similiar results were obtained for Fe+3.

11:30 AM P10.4 
IMPROVED RINSE QUENCH FOR A MORE UNIFORM ETCH OF THERMAL OXIDE IN BUFFERED OXIDE ETCH (BOE), Thad B. Parry, SCP Global Technologies, R&D Dept, Boise, ID.

An improved method for quenching a Buffered Oxide Etch (BOE) process in a DI water overflow rinse tank is shown. Because of its higher viscosity relative to water, and greater surface tension properties, BOE, which is a solution of HO, NHF, and HF, will leave a thick carryover layer of chemical on an oxide surface after removal from the process bath. The carryover layer continues etching oxide at a reduced rate, and if irregular in thickness will unevenly etch the oxide. The experimental setup was an SCP Global Technologies 9400 Surface Preparation System (SPS) with automated robotic transfer. Thermal oxide wafers were placed between bare silicon dummy wafers with a lot size of 50 wafers in each reduced profile cassette. An automated robot capable of control of extraction and insertion rates and delay times between chemical and rinse baths, was used to transfer the wafer lots. Within Wafer (WIW) and Wafer to Wafer (WTW) uniformity of thermal oxide etches were the process responses. The ability to precisely control the transfer, insertion and delay times proves to be necessary to enable a uniform quench. Several approaches to uniformly quench the etch were explored, with only one method showing optimum results. The intuitive solution of rapid extraction and insertion, with minimal time between baths actually increased etch irregularity. The optimal method for transfer involved a slow removal rate from the BOE bath, minimal delay until insertion into rinse, and a moderate insertion rate into the rinse. A theory of why the slow transfer rates yield better uniformity is that they allow the surface tension between the bulk of the liquid and the small volumes on the wafer surfaces, to interact and uniformly strip the chemical from the wafer surface.

11:45 AM P10.5 
WET PROCESS FOR HIGHLY UNIFORM ETCHING OF OXIDE FILMS, Michael G. Izenson, Patrick J. Magari, Creare Inc, Hanover, NH.

Modern semiconductor devices typically require several hundred fabrication steps. Wet chemical processes could dramatically reduce the cost of devices if they could be used in more of these fabrication steps. Wet chemical processes using flow-through technology promise extremely low contamination, high throughput, and low cost. However, existing wet chemical processes are not suitable for many fabrication steps because they cannot meet the uniformity requirements. We have demonstrated a flow-through, set etching process chamber that dramatically improves the uniformity of wet etching. We have performed tests to demonstrate the feasibility of the process using flow studies in a wet etching chamber. Separate tests show that the process produces zero contamination. The process uses active mixing to promote highly uniform conditions throughout the water processing chamber. Active mixing impellers mix injected fluid with resident fluid to provide a uniform concentration of etchants at all times and at all locations on the surfaces of the wafers. The impellers are coated with Teflon to resist the effects of the process chemicals, and are driven by an electromagnetic coupling with no rotating seals. The impellers are supported on noncontacting, hydrodynamic bearings. These bearings enable the shafts to turn inside the chamber with no solid-to-solid contact, so that no particles are generated to contaminate the wafers. The process promises to greatly improve the uniformity achieved in wet chemical etching processes. Commercial applications include etching and cleaning operations for all types of semiconductor manufacture. The process is well suited for large devices such as flat panel displays. Complex oxide films such as PZT and BST can be etched with high precision at low cost of applications such as IR sensors, electroluminescent displays, and micro-electromechanical systems.

SESSION P11: DRY WAFER CLEANING 
Thursday Afternoon, April 3, 1997
Golden Gate A3

1:30 PM *P11.1 
PARTICLE REMOVAL BY CRYOGENIC AEROSOLS FOR SEMICONDUCTOR MANUFACTURING, J. J. Wu, IBM Corp, Federal Sector Div, Manassas, VA.

Cryogenic aerosols dislodge and remove particles from wafer surfaces without causing physical damage or Interfering with electrical characteristics. Due to its nature being nonreactive with any material being used or considered for semiconductor fabrication, this process is applicable at any point where defect reduction is necessary. The elimination of water use and wafer drying in the cleaning procedures avoids the ''water mark'' problems that often relate to yield loss associated with high density device fabrication. By comparing to the conventional processes such as SC-1 megagonics, solvent, and brush clean for particle removal, we have begun to build some understanding on the removal mechanisms of the cryogenic cleaning process.

2:00 PM P11.2 
PULSED LASER-ASSISTED PARTICULATE CLEANING OF SOLID SURFACES, D. Kumar, Rajiv K. Singh, Univ of Florida, Dept of MS&E, Gainesville, FL.

With the continuous decrease in the characteristic linewidth in devices based on semiconductors, the need for developing new techniques to remove submicron particles from solid surfaces is becoming very important. Laser assisted cleaning of solid surfaces has lately been emerging as a very efficient and environment-friendly technique to remove very small dimension parades without damaging the sample itself. In this paper, we have examined the particulate cleaning efficiency of laser under non-normal irradiation of solid surfaces with the laser beam. The effect of liquid films on the particulate removal efficiency of laser have also been discussed. The silicon wafer was intentionally contaminated with alumina and titania particles with different sizes (0.05-0.5 m) and subjected to pulsed laser irradiation at different angles to find out threshold fluence and optimum number of laser pulses to achieve efficient surface cleaning. The mechanism and limitation of laser assisted cleaning of solid surfaces have been discussed.

2:15 PM P11.3 
MORPHOLOGY OF HF VAPOR CLEANED SI(100) SURFACES, Richard J. Carter, Robert J. Nemanich, North Carolina State Univ, Dept of Physics, Raleigh, NC; David R. Lee, Jon Owyang, LSI Logic, Santa Clara, CA; Eric J. Bergman, Semitool, Kalispel, MT.

Si(100) surfaces were vapor cleaned using HF/IPA chemistries at ambient pressure and temperature with nitrogen as a carrier gas. Three distinct cases for oxide removal were studied: vapor etching of native oxides, RCA chemical oxides, and thermal oxides. Atomic Force Microscopy (AFM) was used to characterize the surface morphology after the HF vapor etching process. AFM indicated exaggerated peaks in random places on the surface. These peaks were identified as residue from the vapor etching process. The average lateral distance of a peak was approximately 50 nm. Peak height for native and chemical oxide etched surfaces was relatively the same, approximately 8 nm. Peak height for thermal oxide removal was significantly smaller, approximately 1-2 nm. Peak density for native oxide etched surfaces was significantly greater than chemical or thermal oxide etched surfaces. We suggest that impurities in the oxide contribute to residue formation on the surface. These residues may be minimized when vapor etching contaminant free SiO2 surfaces.

2:30 PM P11.4 
GAS PHASE UV/HALOGEN(OXYGEN) PRE-TREATMENTS FOR IMPROVED DRY OXIDE ETCHING PERFORMANCE, Ty Fayfield, Brent Schwab, FSI International, Chaska, MN.

Gas phase HF based oxide etching performance is strongly influenced by wafer storage conditions. Consequently, a storage independent oxide etching process is highly desirable. In this work, UV/Cl and UV/F/O processes were used to condition SiO2 films prior to gas phase HF/alcohol etching processes. Storage induced contamination was eliminated with the pretreatments and the oxide surfaces were returned to a uniform, terminated state. The resulting etch uniformity and repeatability were greatly improved compared to untreated SiO films. We observed that the surface contamination is strongly dependent on the wafer storage box material and storage time. The pretreatment processes were run in sequences integrated contiguously with the etch step and as separate processes with a significant delay before the etch step. Both pretreatment processes were equally effective at restoring the oxide surfaces, independent of the wafer storage history, when immediately followed by the HF/IPA oxide etching step. The F/O process was more effective at inhibiting recontamination when the wafers were stored between the pretreatment and the etching steps. The two processes have different selectivities to underlying substrates when used with patterned oxide films. These effects will be discussed in the paper. In addition, pre etch incubation times and etch rates will be correlated to the different oxide pretreatment process chemistries.

2:45 PM P11.5 
NI REMOVAL FROM SI WAFERS BY LOW PRESSURE UV-CHLORINE CLEANING, Clay Henry Courtney, H. Henry Lamb, North Carolina State Univ, Dept of Chemical Engr, Raleigh, NC.

UV-chlorine (UV/Cl) cleaning is a low-temperature, vacuum-compatible process for removing transition metal contaminants from Si wafer surfaces. In this work, Ni removal from Si wafers by a low-pressure UV/Cl process was investigated using Auger electron spectroscopy (AES), x-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). UV/Cl experiments were performed in a UHV-compatible chamber equipped with an electronic-grade quartz liner, a radiantly heated sample stage, and a turbomolecular process pump. UV photons from a low-pressure Hg lamp irradiated the sample through a Suprasil® window. Typical processing conditions were 20 sccm Cl, 300 mTorr pressure, and a substrate temperature of 150-200°C. Submonolayer Ni coverages were applied to Si(100) wafers by physical vapor deposition, and the contaminated samples were transferred in vacuo to the UV/Cl chamber. UV/Cl exposure for 2 min at 200°C was found to reduce surface Ni concentrations to less than the AES detection limit and to form a relatively thick chlorosilyl layer. AES depth profiling revealed that Ni is not contained within or buried beneath the chlorosilyl layer. Ex situ XPS experiments demonstrated that the chlorosilyl layer is slowly converted in air to an oxide layer containing no detectable Cl. AFM after UV/Cl cleaning indicated that Si etching was limited to 20 Å and that the surface was very smooth (RMS roughness = 1.6 Å). Ni deposited on a thin Si oxide layer on Si(100) is not removed by UV/Cl exposure under similar conditions. This result and the extremely low volatility of Ni chlorides suggest that Ni removal from Si occurs by a "lift-off" mechanism.

3:00 PM P11.6 
OZONE CLEANING OF CARBON-RELATED CONTAMINANTS ON Si WAFERS AND OTHER SUBSTRATE MATERIALS, Hidehiko Nonaka, Electrotechnical Laboratory, Dept of Matls Science, Ibaraki, JAPAN; Akira Kurokawa, Shingo Ichimura, Electrotechnical Laboratory, Frontier Technology Div, Tsukuba, JAPAN; D. W. Moon, Electrotechnical Laboratory, Ibaraki, JAPAN.

We have investigated a novel surface cleaning technique of the natural oxide on Si wafer, in which the carbon-related contaminants are removed effectively at room temperature with pure ozone beam. The method was first found to be effective for cleaning the surface of oxides such as SrTiO and SiO to nearly an atomically flat surface at 400C, which is much lower than conventional oxygen annealing temperature. Because it is a low temperature process when applied to silicon, the method is expected to minimize the change in the surface composition when the oxide layer is flashed at higher temperatures for further process. A pure ozone beam generator is attached to an analysis chamber equipped with an XPS system. The ozone generator supplies more than 80 pure ozone by means of vacuum distillation of mixture of ozone and oxygen from an ozonizer. The flux of the ozone beam is readily controlled as the equilibrium vapor pressure of the ozone is a linear function of the temperature. After the irradiation of ozone onto the sample, its surface was analyzed by the XPS. We found that the contaminants on some Si samples were removed completely with a low dose ozone (10 Pa 10 Pa) at room temperature. For other samples, either UV light irradiation or a higher dose ozone (10 Pa) was effective to remove remaining contaminants completely. The removal of an organic monolayer deposited on Si with the ozone beam was also investigated.

SESSION P12: ENVIRONMENTALLY FRIENDLY PROCESSING 
Thursday Afternoon, April 3, 1997
Golden Gate A3

3:45 PM *P12.1 
CLEANING TECHNOLOGY USING ELECTROLYTIC IONIZED WATER AND ANALYSIS TECHNOLOGY OF FINE STRUCTURES FOR NEXT GENERATION DEVICE MANUFACTURING, Hidemitsu Aoki, Shinya Yamasaki, Masaharu Nakamori, Nahomi Aoto, NEC Corporation, ULSI Device Development Labs, Kanagawa, JAPAN; Koji Yamanaka, Takashi Imaoka, Takashi Futatsuki, ORGANO Corp, Central Research Labs, Saitama, JAPAN.

The diameter of Si wafers is becoming larger and the dimensions of the devices are becoming smaller in next-generation device manufacturing. During this progress, there are two concerns: first one is about the increased consumption of chemicals and ultrapure water (UPW) used in wet processes and next is about contamination inside of fine structures. With the increasing diameter of Si wafers, the amounts of chemicals and rinsing UPW consumed in wet processes have drastically increased. In order to reduce the consumption of chemicals and UPW, we have developed wet processes using electrolytic ionized water (EIW), which is generated by the electrolysis of a diluted electrolyte solution or UPW. The EIW can be controlled with a wide pH range and oxidation-reduction potential. The anode EIW with diluted electrolyte, which has high oxidation potential, can remove metallic contamination such as Cu and Fe on Si surfaces. EIW contains less than of the chemicals in the conventional cleaning solutions and can drastically reduce the chemical consumption in wet processes. In addition, electrolyzed UPW can be used as a substitute for conventional UPW to achieve high rinsing characteristics. Electrolyzed UPW can rinse out residual SO ions after SPM cleaning six times faster than conventional UPW. Thus the amount of rinsing water can be reduced to less than 1/6. It was estimated that and the total energy cost can be reduced to 1/10 that of a conventional rinse. Such EIW, of both diluted electrolyte solution and UPW, has high potential to realize ecological and economical wet processes in 300-mm wafer processing. In order to guarantee sufficient cleanness in fine structures, the contamination analysis technology inside fine structure is needed. We have developed an analysis method for the remaining metallic contamination and the residual ions in deep-submicron-diameter holes with high aspect ratios. The method is based on conventional atomic absorption spectrometry (AAS), and uses device patterns with high density contact holes. With this method, metallic (Fe) contamination of the order of 10 atoms/cm can be easily analyzed inside 0.1 m-diameter holes with aspect ratios of 10. The residual ions in the fine hole can be detected by thermal desorption spectroscopy (TDS). The EIW cleaning technology and the new analysis method will play important roles in future cleaning technology.

4:15 PM P12.2 
THE FORMATION OF WATER MARKS ON BOTH HYDROPHILIC AND HYDROPHOBIC WAFERS, Jin-Goo Park, Seung-Hwan Kim, Hanyang Univ, Dept of M&ME, Ansan, SOUTH KOREA.

Drying after wet wafer cleaning is a critical step to maintain the integrity of cleaning processes. Residues such as water marks should be prevented during the drying step. It has been argued that impurities such as silica and drying atmospheres may leave water residues on wafer surfaces during wet cleaning processes. In this paper, the effect of the wettability of silicon wafers and drying atmosphere on the formation of water marks was investigated along with the role of impurity concentration in DI water. DI water droplets were intentionally placed on the surface of samples with various wettabilities and then left to dry in both O and N atmospheres. It was found that both hydrophobic and hydrophilic surfaces created the water mark in O and N atmospheres. The size and dry time of residues were dependent on the wettability of surfaces. Auger analysis of residues showed that the oxidation of surface in water might be one of the causes of water mark formation. Considering the pore size of final filters in DI water generation is 0.05 m, a large number of particles less than 0.05 m may be in DI water. In order to investigate the effect of these small particles on water mark formation, PSL particles less than 0.05 m were added to DI water and made droplets to dry as a function of particle concentrations. The size of water marks was dependent on the concentration of particles in DI water after reaching a critical concentration.

4:30 PM P12.3 
THE IMPACT OF TEMPERATURE AND CONCENTRATION ON SC2 COST AND PERFORMANCE IN A PRODUCTION ENVIRONMENT, Deborah J. Riley, Jeffrey S. Glick, Val Parks, George Matamis, Advanced Micro Devices, Austin, TX.

Recent literature suggestions have been made that extremely dilute solutions of HCl are suitable replacements for the traditional SC2 clean. These studies suggest that 0.01 - 0.001 M HCl offers considerable cost savings and reduces on-wafer particle levels while maintaining control of metallic contamination. This work indicates, however, that extreme levels of dilution are not necessary to secure many of the benefits suggested for dilute HCl. Facilities uncomfortable with an ultradilute formulation can attain significant benefit by pursuing moderate concentration and temperature alterations. In this study, an intermediate dilution and temperature reduction are evaluated to assess potential production advantage. Comparison of a 1:1:20 formulation at 60 C is made to a more traditional 1:1:6 mixture at 85 C. The impact of the chemistry and temperature alteration on peroxide decomposition rate is shown to be dramatic. While initial pour-up ratios seem to suggest that the dilute recipe might require 1/3 as much peroxide as the traditional chemistry, chemical savings are significantly more dramatic due to the ability of the solution to maintain concentration over time. An additional benefit associated with the alternative formulation is a marked reduction in particle levels on silicon surfaces; particle levels on thermal oxide wafers do not appear to be influenced by specifics of the HPM recipe. TXRF and VPD-ICPMS measurements are used in this study to illustrate that the recipe change leads to no loss of metallic removal efficiency.

4:45 PM P12.4 
WATER USE EFFICIENCY IN IMMERSION WAFER RINSING, Thomas S. Roche, Motorola Inc, Cleans Process Engr, Chandler, AZ; Thomas W. Peterson, Univ of Arizona, Dept of C&EE, Tucson, AZ; Eric Hansen, SCP Global Technologies, Dept of R & D, Boise, ID.

This work describes the effort we have made to understand the rinse process in our wet process tools and to improve the efficiency of water use in these tools. We define rinse efficiency as the amount of water used compared with the amount of chemical remaining on the wafers after the rinse. Experiments were performed in a modern immersion rinse bath in a manufacturing facility. The work consist of modifying rinse parameters such as flow rate and time in the primary rinse bath and measuring the amount of chemical left on the boat and wafers as a result of these modifications. The chemical remaining on the wafers after the rinse is measured by immersing the wafers in a second rinse tank and measuring the integrated conductivity of the rinse water in this bath as the wafers are rinsed to the ultimate resistivity of the water. Results of these experiments generally agree with the description of the process of overflow rinsing as similar to that of a CSTR but also showed that pulsing of rinse water, i.e. turning the water flow on and off while the wafers are in the rinse bath, improves the effectiveness of the rinse. This result is contrary to what would be expected for a simple CSTR and our work to understand this result will be described.

5:00 PM P12.5 
OPTIMIZATION OF POST SULFURIC ACID/HYDROGEN PEROXIDE DUMP RINSING PROCESSES, W. Chen, Stanford Univ, Dept of Electrical Engr, Stanford, CA; Russ Parker, Hewlett Packard Co, ULSI Research Lab, Palo Alto, CA; C. Robert Helms, Stanford Univ, Dept of Electrical Engr, Stanford, CA.

There are significant benefits to developing optimized rinsing processes, including better performance, reduced water consumption, shorter cycle times, higher tool utilization, and higher throughputs - all leading to lower cost of ownership. If multiple exposures of the wafer to the air/water interface do not lead to significant detrimental effects, dump rinsing is a good candidate. In this paper we will report on modeling work to evaluate the possible rate limiting steps in dump rinsing, including pull-out velocity from the chemical bath, draining during transport into the rinse tank, immersion into the rinse tank, dumping, draining after a dump cycle, flow rate during filling between dumps, and between-dunp overflows. The previously developed model for rinsing performance, extended to evaluate these effects, will be discussed in this paper. A number of variables were found to be important. A low flow hold between dumps to provide sufficient time for the entrained liquid layer on the wafer surface and cassette to intermix with the new rinse water was predicted to provide rinsing as efficient as fast flow. This was verified experimentally using an automated 150 mm wet tool running 50 wafer double cassettes. The sensitivity of the overall process to drain time between the end of one dump and the beginning of the next fill was established. In creasing the draining time from ³zero² up to only a few seconds provided significantly better rinsing efficiencies. Based on the modeling and experimental investigation an optimized dump rinsing process was developed using heavily programmed flow rates and dumping cycles. This process requires 5 minutes and 75 liters of water and replaces a process that initially ran for 10 minutes and consumed 370 liters of water - a factor of five saving in water consumption and two in cycle time.