Symposium EP04 : Reliability and Materials Issues of Semiconductor Optical and Electron Devices and Materials

Doping, as a central strategy to control over free carrier type and concentration in semiconductor materials, suffers from the low efficiency at nanoscale. Especially in systems with high permittivity and large Bohr radii such as lead chalcogenide nanostructures, the doping efficiency is extremely low (~1%). One of the possible cause is the significant dielectric constant (ε) mismatch between the nanostructure and its surrounding media. We study the dielectric confinement effect on the doping efficiency of Pb, In and Se in lead chalcogenide nanostructures, utilizing the platform of PbSe nanowire field effect transistors (FETs). By increasing the \epsilon of the surrounding medium, the free carrier concentration and the calculated doping efficiency for n-type (Pb/In) and p-type (Se) dopants increases with a given number of dopants. Ultimately, the doping efficiency can be enhanced by >10 fold with barely any dielectric confinement. Mathematically, a modified Delerue’s equation is applied to describe the doping efficiency in PbSe NWs with different dielectric environment, which agrees with our experimental data both from NW arrays and single NW devices. Through single NW FET’s temperature dependent characteristics, we further extract ionization energy of Pb in PbSe NW, consistent with the theoretical calculation.

Pure boron layers deposited on Si by chemical vapor deposition (CVD) from diborane are used in photodiodes for detecting low-penetration-depth beams such as EUV/VUV light and low-energy electrons down to 100 eV. These successful applications rely on a 700°C high temperature (HT) deposition to obtain smooth, uniform layers as thin as 2 nm. When deposited directly on n-Si, these layers can form p⁺n diodes that combine nm-shallow junction depth with low dark current and high stability/robustness with respect to high-dose exposures and chemically harsh environments. In addition, the 700°C deposition is fully compatible with front-end CMOS technology. In future applications such as backside-illuminated (BSI) imagers and (single-photon) avalanche diodes, the integration of PureB would be considerably facilitated by going down to the 400°C - 500°C low temperature (LT) deposition range, thus making the deposition back-end CMOS compatible as well.
In this paper, the properties of LT PureB deposition are studied with the purpose of obtaining optimal performance for as thin as possible layers. In past research, the LT diode characteristics were found to be very similar to the well-established HT diodes, displaying ideally low dark currents, and high responsivity radiation stability. This is because the PureB junction properties are determined by the B-to-Si interface and not doping of the bulk Si. However, the very smooth coverage achieved at 700°C is not readily reproduced at LT because the adsorption rate of B on Si is much lower, as is the mobility along the Si surface. The B atoms preferably attach to other B atoms rather than the Si so vertical growth on already deposited B atoms is promoted. This gives a high probability that not all Si atoms will be connected to a B atom before overgrowth with a complete, but usually very rough layer of pure B. The roughness, several nm instead of angstrom as in the HT case, significantly reduces the chemical robustness of the PureB, preventing the application in harsh environments.
Several PureB deposition conditions were studied and as-deposited layers were evaluated using analysis techniques such as HRTEM, AFM, optical profiling, XPS, and ellipsometry, as well as electrical characterization of diode I-V behavior and sheet resistance along the B-to-Si interface. The integrity of the layer was tested using a TMAH Si-etchant that revealed any weak spots in the layers through which the Si could be attacked.
More chemically robust 6-nm-thick PureB layers with a 3-nm roughness with ideal electrical characteristics were achieved at a growth temperature of 450°C. Two main parameters proved to be important for this result. For the first the B deposition rate should be fast enough prevent oxygen contamination of the Si surface but slow enough to allow a good first coverage of the surface. Second, the Si wafer cleaning steps should not include procedures that roughen the surface or bring the Si dopant atoms to the surface.

Semiconducting oxides, especially Indium oxide (In₂O₃), are widely used as conductometric gas sensor material. In₂O₃ exhibits a surface electron accumulation layer (SEAL) in ambient conditions, possibly induced by surface oxygen vacancies [1,2] (free indium bonds at the surface). Experiments have shown, that these surface defects can be saturated by an oxygen plasma treatment [3] forming a gas insensitive surface [4].
We study the interaction of different gases (O₂, O₃, H₂O, NO_x) with textured, unintentionally doped In₂O₃(111) films grown by plasma-assisted molecular beam epitaxy. The work is focused on the influence of adsorbed gases on the surface defect concentration, analysed by photoelectron spectroscopy as well as their influence on the surface conductivity determined by in-vacuo Van-der-Pauw electrical sheet resistance measurements. The chemical composition and electronic surface properties before and after gas interaction are analysed. A well-defined adsorbate-free surface was prepared by vacuum annealing, producing free surface indium bonds. Offering the different gases results in adsorption of gas species at the free surface sites, simultaneously influencing the SEAL. The generation of defects as well as variation in surface band bending, electron concentration and surface dipole formation of In₂O₃ during gas adsorption and desorption are characterised.
O₃, O₂ or NO_x oxidation of the In₂O₃ surface result in an increase of the oxygen containing adsorbates. The adsorption of these electronegative species induces an electron transfer from the semiconductor near-surface region into localized adsorbate bonds resulting in a partial depletion of the SEAL. The variation of electric conductance of the In₂O₃ films during gas adsorption/desorption correlates directly with the observed SEAL concentration.
Another aim of our work is to identify the influence of humidity on the sensor response. Therefore, the In₂O₃ surface was saturated by water vapour before ozone interaction. Water does not change the surface electron density, but attenuates the depletion of the SEAL by a subsequent ozone oxidation. We interpret this behaviour by water adsorbates occupying surface indium bonds that are consequently not available for ozone interaction.

[1] K. H. L. Zhang et al.: Microscopic origin of electron accumulation in In₂O₃, Phys. Rev. Lett. 110 (5), 056803 (2013)
[2] A. Walsh: Surface oxygen vacancy origin of electron accumulation in indium oxide, Appl. Phys. Lett. 98, 261910 (2011)
[3] T. Berthold et al.: Consequences of plasma oxidation and vacuum annealing on the chemical properties and electron accumulation of In₂O₃ surfaces, J. Appl. Phys. 120, 245301 (2016)
[4] J. Rombach et al.: The role of surface electron accumulation and bulk doping for gas-sensing explored with single-crystalline In₂O₃ thin films, Sens. Actuators B, 236, 909 (2016)

Monolithic integration of highly mismatched semiconductor material has received much attention because it allows the integration of devices with different circuit design on a platform that require less power consumption and create new application. In particular, devices in the mid-infrared range show high potential application in thermal imaging and sensing of gas molecules[1]. However, silicon (Si) is not suitable for detection of electromagnetic wave with wavelength longer than 1.1 µm due to its indirect energy bandgap of 1.12 eV. Indium arsenide (InAs) semiconductor material is a potential candidate as it has a direct energy bandgap of 0.35 eV. The cutoff wavelength of absorption of InAs photodetector is up to 3.5 µm at 300K. Integration of mid-infrared photodetector and Si CMOS circuit can be achieved by first performing heteroepitaxy growth of InAs on Si followed by wafer bonding[2] of Si CMOS on top of the InAs layers. The heteroepitaxy growth of InAs p-i-n photodetector on Si has been demonstrated earlier[3] through a thick buffer scheme which consist of linearly graded InAlAs layer in between the InAs p-i-n layer and GaAs layer. The total thickness of the buffer layer is about 2.1 µm. In this work, we present a study of two thinner buffer layer schemes: (i) InAs/GaAs/Ge/Si, and (ii) InAs/GaAs/GaP/Si, which both uses cation exchange method to perform heteroepitaxy growth of InAs on Si substrate. Thinner buffer scheme could reduce the risk of film cracking due to large thermal expansion coefficient mismatch between Si and III-V and possibly smoother surface morphology. Scheme (ii) requires migration enhanced epitaxy (MEE) of GaAs on Ge to switch from non-polar to polar semiconductor, whereas in scheme (ii), the transition is done during the growth of GaP on Si. In scheme (i), the cation exchange was done at the InAs/GaAs interface, whereas in scheme (ii), the cation exchange was done twice; first at the GaP/GaAs interface followed by another exchange at InAs/GaAs interface. Identical InAs p-i-n photodetector structures were grown on both schemes. Standard photolithography technique and wet etch process were used to fabricate the mid-infrared photodetector. X-ray diffraction (XRD) and transmission electron microscopy (TEM) were used to examine the crystalline quality of the layers.

References:
[1] M. Razeghi, Eur Phys J-Appl Phys 23 (3), 149 (2003).
[2] X.S. Nguyen, S. Yadav, K.H. Lee, D. Kohen, A. Kumar, I.M. Riko, K.E. Lee, S.J. Chua, X. Gong, and E.A. Fitzgerald, IEEE Trans. Semicond. Manuf. 30(4), 456-461 (2017).
[3] W.K. Loke, K.H. Tan, D. Li, S. Wicaksono, S. F. Yoon, IEEE Photon. Technol. Lett. 28(15), 1653-1656 (2016).

Extreme bandgap semiconductors (xBGS) such as AlN and GaN have attracted much interest due to their potential applications in power electronics, and deep UV photonics. Recent advances in molecular beam epitaxy (MBE) technology has enabled the growth of ultra-thin AlN/GaN quantum heterostructures for deep-UV emission [1,2], which is suitable for diagnostic and therapeutic application, where thermal conductivity plays an important role in heat dissipation of operating devices.

Here, we use the 3-omega technique [3] to study thermal conductivity of AlN single crystals and ultrathin AlN/GaN superlattices over a wide temperature range (100 to 400 K) for the first time. For the 3-omega technique, four-probe metal lines are patterned on the sample surface as both heater and thermometer. A current with frequency ω causes a second harmonic temperature rise in the sample under the heater. The metal heater resistance varies linearly with temperature, thus a voltage is measured at the 3ω frequency using a lock-in amplifier, and this voltage is correlated to the thermal conductivity of the substrate.

First, we measured the thermal conductivity of AlN bulk, finding it ranges from ~680 W/m/K at 100 K to ~200 W/m/K at 400 K. Comparison with simulations based on the Boltzmann Transport equation (BTE) shows this behavior is consistent with phonon Umklapp scattering, and a contribution from atomic impurity defects, leading to roughly 1/T dependence of thermal conductivity over this temperature range. (The contribution of electrons to thermal transport is negligible in these xBGS materials.)

Next, AlN/GaN superlattices (SL) of thickness ~300 nm are grown on 1 µm AlN template on sapphire substrates by MBE, with (repeating) SL layer thickness from 0.25 nm to 2.25 nm. After subtracting the contribution of the interfaces and substrate, we obtain the SL thermal conductivity, which ranges from ~47 W/m/K at 100 K to ~33 W/m/K at 400 K. Due to strong interface scattering, the SL has much lower thermal conductivity than AlN bulk, which is an important finding for thermally-limited devices based on SLs [4].

In summary, we report the thermal conductivity of AlN and AlN/GaN SLs over a wide temperature range, uncovering the role of interfaces, defects, and their temperature dependence from 100 to 400 K. AlN/GaN SLs in deep-UV photonic devices are commonly used as light emitting regions and buffers layers, thus knowledge of their thermal conductivity is valuable in device design and heat dissipation considerations. This work is supported in part by the NSF DMREF program.

[1] S.M. Islam et al., Appl. Phys. Lett. 110 041108 (2017)
[2] D. Bayerl et al., Appl. Phys. Lett. 109, 241102 (2016)
[3] S-M. Lee et al., Appl. Phys. Lett. 70, 2957 (1997)
[4] Y.K. Koh et al., Adv. Func. Mat., 19, 610-615 (2009)

Semiconductor nanowires have the potential to emerge as the building blocks of next generation field-effect transistors, logic gates, solar cells and light emitting diodes. Use of Gallium Nitride (GaN) and other wide bandgap materials combines the advantages of III-nitrides along with the enhanced mobility offered by 2-dimensional confinement present in nanowires. Hence, the focus of this work is on developing a low field mobility model for a GaN nanowire using Ensemble Monte Carlo (EMC) techniques. A 2D Schrödinger-Poisson solver and a one-dimensional Monte Carlo solver is developed for an Aluminum Gallium Nitride/Gallium Nitride Heterostructure nanowire. A GaN/AlN/AlGaN heterostructure device is designed which creates 2-dimensional potential well for electrons. The nanowire is treated as a quasi-1D system in this work. Three scattering mechanisms: acoustic phonon scattering, polar optical phonon scattering and piezoelectric scattering are considered to account for the electron phonon interactions in the system. Overlap integrals and 1D scattering rate expressions are derived for all the mechanisms listed. A generic one-dimensional Monte Carlo solver is also developed. Steady state results from the 1D Monte Carlo solver are extracted to determine the low field mobility of the GaN nanowires. The mobility obtained by the model agrees very well with available experimental data.

AlGaN/GaN-based high electron mobility transistors (HEMTs) are model candidates for next generation radio-frequency and optoelectronic devices. Unfortunately, further understanding about device reliability and the physics of degradation mechanisms in GaN technology is still required to push GaN devices to their theoretical operating limits. This lapse in collective knowledge has led to the creation of a large research community devoted to GaN reliability physics. Directly connecting device electrical degradation with physical defects is challenging due to the complex electro-thermo-mechanical mechanisms active in these devices, but pitting, cracks, and extended dislocation structures have been observed in degraded devices.

There have been many experimental and theoretical studies on pre-catastrophic degradation of AlGaN/GaN HEMTs. Several proposed theories are based on degradation of the device active layers, including TD-based and inverse/converse piezoelectric effect-based failure mechanisms; newer theories involve time-dependent degradation based on defect percolation, electrochemical degradation, and metal-metal/semiconductor reactions. Unlike the discussion of pre-catastrophic degradation mechanisms, there is relatively little looking into the forensic material science of catastrophic device failure. Catastrophic device failure is physically realized as crater formation and electrically realized as large increases in leakage current or shorting of multiple electrodes and the cessation of device operation.

Here we present the characterization of a catastrophically degraded AlGaN/GaN HEMT in and around the breakdown area of crater formation. Specifically, we employ scanning electron microscopy (SEM) and transmission electron microscopy (TEM) based techniques to determine the microstructural and chemical changes the device underwent during catastrophic failure. We find a Ni-Ga alloy defect within the gate stack, show that the Ni/Au gate stack experienced severe morphological and diffusional changes throughout the device, and lastly we see curved and inclined dislocations emanating throughout the GaN layer near the failure region, indicating dislocation movement during device operation.

This presentation is intended to give a non-traditional look at reliability of compound semiconductor RF products. It is a review of the five main stages of reliability analysis. Although essential, the first three stages are separated as those traditional tests which are particularly applicable for process development and material selection phases. The remaining two reliability stages are the focus of real life products. These later stages are the tools used for improving reliability of established processes and families of products where significant changes and switches to new materials are not feasible. While all five steps are necessary in reliability studies, the methods of establishing and improving reliability are different.

A state-of-the-art simulator for the calculation of the low-field mobility in inversion layers is presented in this work that accounts for the collisional broadening of the electronic states via the solution of the Dyson equation for the retarded Green’s function (GF). Self-consistent Born approximation is used for the calculation of the self-energy contributions due to Coulomb, surface-roughness, acoustic and non-polar optical phonon scattering. Bethe-Salpeter integral equation is solved for the calculation of the conductivity, i.e. mobility. Simulated mobility results for three generations of MOSFET devices are in agreement with available experimental data. At nanoscale dimensions, we find that, the surface-roughness scattering dominates the collisional broadening of the states and the renormalization of the spectrum in the relatively high-field regime while depletion and interface-charge scattering dominates the mobility in the lower field regime for each generation of the MOSFET [1,2].
The 1D Schrödinger-Poisson solver uses the density of states calculated via the solution of the Dyson equation to compute the sheet charge density in various subbands, and therefore the total QM charge density in the device. This forms the self-consistent outer loop of the solver. The inner loop consists of the Green’s functions solver that solves for the retarded sub-band Green’s function self-consistently, in order to compute the corresponding self-energy. Once the collisional broadening of the states and the renormalizations of the spectrum are calculated from the corresponding self-energy, the subband density of states function (DOS) is calculated by integrating the spectral density function over momentum states and giving the updated value of the energy dependent subband “real” DOS. This, in turn, allows for the calculation of the sheet electron density in the outer loop.
Thus, for every iteration of the outer Schrödinger-Poisson loop, the subband energies, sub-band wavefunctions and the overlap integrals are updated as an input for the inner GF loop, which then iterates in itself for self-consistency. Once the value of the sheet charge density and the potential is finally calculated for the given gate voltage, the conductivity/mobility is evaluated using the Green-Kubo approach by the self-consistent solution of the subband polarizability function. In this work, Message Passing Interface (MPI) is used to parallelize the code for time efficiency.

[1] D. Vasileska and D. K. Ferry, “Scaled silicon MOSFET’s: Part I - Universal mobility behavior”, IEEE Trans. Electron Devices 44, 577-83 (1997).
[2] Kannan, Gokula, and Dragica Vasileska. "The impact of surface-roughness scattering on the low-field electron mobility in nano-scale Si MOSFETs." Journal of Applied Physics 122.11 (2017): 114303.

GaN devices for microwave and power switching are enabling for new and innovative system applications. The specific material properties of AlGaN/GaN or similar heterojunctions facilitate very compact and extremely fast devices. On system level these properties translate into advantages such as low weight and low volume for a given power handling. Most of the GaN devices implemented so far are relying on a lateral architecture. The device current flows in an infinitesimal small sheet layer located at the interface between two adjacent semiconducting materials with different degrees of spontaneous and piezoelectric polarization. Thus a 2-dimensional electron gas (2DEG) forms whose properties depend on the pairing of the adjacent semiconductor materials, their respective mechanical strain and on charged trap states in the vicinity. Traps located close to the 2DEG influence electron population and are thus affecting maximum device current and on-state resistance. In general, trap states are very dynamic in nature. Thus trapping and detrapping depends on specific device biasing conditions. Strictly spoken this means that at a given bias condition the trap population is practically frozen and cannot respond to fast device switching transients. Therefore, immediately after device switching the transition to the new bias point may be delayed as traps need to be charged or discharged according to their inherent time constants. For example, if negative charges are trapped in the vicinity of the channel the device cannot fully turn on immediately after trying to switch the device from an off-state to an on-state bias point. The new static bias point will be reached after a certain delay only. This effect is known as “dynamic on-state resistance” for power switching devices or gate or drain lagging in GaN microwave devices. It turns out that the properties of the dynamic on-state resistance strongly depend on history of device biasing, on the time elapsed since device switching, on local electric field in the active device and on temperature.
The invited presentation discusses the most important dynamic properties observed in lateral GaN devices and sheds light on the respective physical mechanisms. Furthermore, GaN devices form institutional and industrial vendors are compared against each other with respect to their dynamic switching properties. It can be shown that some of them but not all can be practically free of dynamic on-state resistance effects and show nearly ideal switching properties.

GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) are very promising for high-efficiency electrical power management systems. Thanks to its insulated gate, the MIS-HEMT offers low gate leakage and large gate swing, essential for power switching applications. Unfortunately, the gate dielectric introduces reliability and instability concerns. These issues are hampering technology commercialization.
A critical problem in GaN MIS-HEMTs is bias-temperature instability (BTI), in which important device parameters, in particular the threshold voltage, V_T, shift around under prolonged gate bias stress. This is detrimental to circuit performance. BTI in MIS-HEMTs is challenging to understand because the gate-stack has multiple layers and interfaces with many possible trapping sites raising the possibility of multiple mechanisms acting simultaneously.
To contribute fundamental understanding relevant to this problem, we have studied BTI in simpler GaN MOSFETs. This has allowed us to isolate the role of the gate oxide and the oxide/GaN interface in BTI. We have focused on the evolution of V_T, maximum transconductance (g_m,max), and drain current subthreshold swing (S). Often, BTI studies separately focus on positive stress (PBTI) or negative stress (NBTI) with often contradictory results. Our research has addressed the PBTI-NBTI continuum and has strived to build a unified model for device instability.
Our results show a universal, continuous, symmetrical, and reversible V_T shift and g_m,max change as gate voltage swings through a moderate range around 0 V. The time evolution of V_T is well described by a power law model. The observed voltage, time, and temperature dependences suggest that for moderate gate bias stress, NBTI and PBTI in our devices are due to a single reversible mechanism. Its signature is consistent with electron trapping and detrapping in preexisting oxide traps that form a defect band very close to the GaN/oxide interface. This defect band extends in energy beyond the conduction band edge of GaN and below the Fermi level at the channel surface at 0 V.
Harsher stress, positive or negative, is seen to lead to irreparable damage that permanently degrades the device figures of merit and accumulates with stress time. In both cases, positive or negative stress, the permanent damage appears to be caused by interface state density creation at the oxide/semiconductor interface, perhaps due to H broken bonds.
An additional regime of degradation is observed under mid-level negative gate stress. Here we record a recoverable positive V_T shift coupled with a recoverable increase in subthreshold swing. We attribute this to electron trapping in the GaN channel under the edges of the gate. This is an excellent example of how semiconductor trapping can confuse gate oxide-related degradation studies and how challenging is to develop a holistic understanding behind BTI in GaN MIS-HEMTs.

Extreme temperature and radiation-harsh environments, such as those involving nuclear power, advanced military applications (e.g., electronically guided missiles) or space exploration have created a high demand for more robust electronics. The ultra-wide bandgap (UWBG) semiconductor aluminum nitride (AlN) is a highly promising platform to fill this need. Commanding the largest bandgap E_g (6.2 eV) out of any semiconductor, AlN has a critical field E_c of 12 mV/cm, electron and hole mobilities of 1090 and 14 cm²/V-s, and a maximum operating temperature of 690 °C. The ultra-wide bandgap, coupled with the 11.52 eV/atom chemical bond strength and small lattice constants give AlN a natural advantage against impact ionization and lattice displacement, the two most fundamental radiation effects.

To this end, lateral Pd/n-AlN Schottky diodes were fabricated by metal organic chemical vapor deposition (MOCVD) on (0001) sapphire substrates and their current–voltage (I–V) characteristics were studied across varying temperatures and gamma-ray irradiation doses. Multiple Schottky diodes with varying geometries were fabricated. Large ideality factors, ranging from 25 at 300 K to 20 at 475 K, were obtained at forward bias. Diode breakdown voltage exhibited a negative temperature dependence at reverse breakdown conditions, leading the investigators to conclude that the breakdown mechanism is related to surface states instead of impact ionization.

The devices were bombarded with protons at 3 MeV from various: 5×10⁹ /cm², 5×10¹¹ /cm² and 5×10¹³ /cm². Neither forward- nor reverse-bias currents change appreciably until after exposure the highest dose. At the highest forward bias of 10 V, the currents reach 16.26 μA prior to radiation exposure and decrease to 13.96 μA after exposure to 5×10¹³ /cm². The devices were subjected to the high-temperature I-V tests under the following temperatures: 20 C, 40 C, 60 C, … 120 C. Forward currents increase consistently with temperature, reaching over 10 μA, and reverse-bias currents consistently decrease. Radiation exposure at the aforementioned doses does not appreciably alter the high-temperature I-V characteristics generated. Ideality factors were obtained as a function of temperature and radiation exposure. The diode ideality factors consistently decrease with temperature and radiation dose, ranging from ~7 to 3. High-resolution x-ray diffraction (HR-XRD) tests were performed after each radiation dose, four in total (including one before any exposure). In increasing order with respect to dose, each rocking curve has a full width half maximum (FWHM) of 0.04409, 0.04691, 0.06605 and 0.0563 for the (0002) plane of AlN. For the (20-24) plane, the FWHM values are 0.05895, 0.069, 0.912, and 0.268.

1.Introduction
Automotive quality GaN power switch rated 650V was realized. GaN on Si D-mode HEMT is in production with 6 inch SiCMOS manufacturing fab[ref.1,2]. Cascode configuration with low voltage SiMOSFET realized E-mode. Qualification test with AEC-Q101 automotive standard[ref.3] was successfully finished. Acceleration model for high voltage switching was established from accelerated life test. Cosmic ray induced single event burn out(SEB) test was also conducted[ref.4]. Failure rate for SEB was 1.5 FIT with zero failure at 600V that is two orders smaller than the FIT for SiMOSFET.

2.Device structure
AlGaN/GaN epitaxial layers were grown on Si wafer by metal organic chemical vapor deposition(MOCVD). Insulating gate with Al gate electrode was employed to achieve low gate leakage current. Ohmic contact was Al alloy with barrier metal layer. Metallization layer was Al with CVD Silicon dioxide and Silicon nitride layer. 30V Si MOSFET was used for cascode. Package type of industries standard TO247, TO220 and PQFN8x8 are in production.

3.High voltage reliability
Current collapse was a challenge for high voltage GaN HEMT. On resistance increase of our GaN HEMT is within 20% at 700V stress. High voltage switching test and high voltage reverse bias test at >1000V were conducted to derive the acceleration model. Acceleration model for the gate insulator TDDB was derived from the step stress test. Extrapolated life time for high voltage stress was >20 years for 0.1% failure.

4.Package reliability
Highly stressed temperature cycle test revealed the failure mode was delamination between the lead frame and the AlN insulator bottom of the die. Acceleration model was (delta-T)^n with n=-9. Stress simulation agreed with the experimental results. Extrapolated life time was >1E6 cycle for delta-T=100.

5.Single event burnout
Cosmic ray induced single event burnout(SEB) is fatal for high reliability applications. Nuclear reaction between cosmic rays and semiconductor atoms generate ionized particles. Ionized particle generates electron and hole pairs. In SiMOSFET, parasitic bipolar transistor turns on by the electron and hole current.
Accelerated neutron irradiation test was conducted at RCNP of Osaka university. Failure rate was <1.5 FIT at 600V and <3 FIT at 800V. Failure rate for commercially available 600V super junction SiMOSFET was 290 FIT at 600V. GaN HEMT is robust to SEB because of no parasitic bipolar transistor.

6.Conclusion
Cascode GaN HEMT is ready for automotive quality, small form factor and high efficiency applications.

References
[1] P. Parikh, et. al. “Commercialization of 600V GaN HEMTs,” 2014 SSDM, Tsukuba, Sep., 2014.
[2] T. Kikkawa, et. al. 600 V JEDEC-Qualified Highly Reliable GaN HEMTs on Si Substrates,” IEEE IEDM, San Francisco, Dec. 2014.
[3] AEC-Q101, Automotive Electronics Council.
[4] C. D. Davidson, et. al., 26th Ann. Int. Telecommunications Energy Conference, 2004, p.503.

Vertical gallium nitride (GaN) power semiconductor devices grown on native GaN substrates are emerging as the next frontier in power electronics, with a unipolar figure of merit (UFOM) surpassing that of SiC. This is due to the high critical electric field (E_C) of GaN, which is believed to exceed 4 MV/cm. Vertical GaN PiN diodes exhibit high breakdown voltage, low on-resistance, negligible reverse-recovery loss, and avalanche ruggedness. While these properties hold great promise to improve the efficiency and power density of power conversion circuits, little reliability characterization has been reported to date for such devices. As such, this talk reports on the reliability evaluation of 1200 V vertical GaN PiN diodes. Moreover, since hard-switching circuits represent one of the most demanding environments for power semiconductor devices, this work has focused on electrical stress of vertical GaN PiN diodes in a modified double-pulse test circuit (DPTC).

The DPTC, which consists of a power transistor in series with a diode-inductor loop, is commonly used to characterize device switching performance. Typically, a long “charging” pulse is first applied, which is followed by a short characterization pulse (hence the term “double pulse”). However, the ideal DPTC cannot be used in a continuous switching mode, as required for reliability evaluation, since the current through the circuit increases monotonically with the number of switching cycles. The presence of loss in a real DPTC, however, permits the circuit to be operated in a continuous mode with the appropriate choice of frequency and duty cycle. The talk will present an analysis of the requirements necessary to utilize the DTPC in a continuous switching mode for hard-switching reliability evaluation.

Prior to switching reliability evaluation, temperature-dependent current-voltage (I-V) measurements of the vertical GaN PiN diodes were conducted, to establish the baseline performance of the devices. Consistent with previous reports, the breakdown voltage of the diodes exhibited a positive temperature coefficient (i.e., the breakdown voltage was higher at higher temperatures), characteristic of avalanche-induced breakdown. This is critical for circuits requiring avalanche ruggedness and contrasts with lateral GaN power HEMTs, typically grown on Si substrates, that do not exhibit avalanche breakdown. Following the initial I-V characterization, the diodes were subjected to continuous switching stress in the DPTC, which was interrupted periodically to measure forward and reverse I-V curves. The vertical GaN diodes showed minimal degradation in I-V characteristics under a range of stress levels (e.g. supply voltages) tested, indicating good robustness under hard-switching conditions. These results are encouraging for the application of vertical GaN devices in demanding power switching applications.

Over the last few years, the research in the field of GaN-based power transistors has shown impressive advancements. Normally-off transistors with breakdown voltage higher than 1 kV have already been demonstrated, thus clearing the way for a massive penetration in the power conversion field. Despite the great potential of this technology, GaN based transistors may still suffer from limited reliability, and several issues still have to be solved and addressed. In this presentation, we will give an overview on our most recent results in the field of GaN transistor reliability, by focusing on the following relevant aspects: (i) the degradation of normally-off transistors with p-type gate, submitted to positive gate stress. We discuss the existence of two relevant degradation processes, one activated by the prolonged flow of a positive gate current (time-dependent breakdown of the gate junction), and the other triggered by the exposure to short ESD pulses (voltage-dependent failure of the gate stack). We will comment on the impact on Mg doping concentration on the robustness of the devices. (ii) the degradation of transistors under hard switching conditions. Thanks to the development of a custom setup, we investigated the degradation of the electrical characteristics of power GaN transistors submitted to hard switching. Electroluminescence analysis was used to demonstrate the important role of hot electrons in limiting the device performance. (iii) the degradation of the electrical characteristics of GaN-based vertical transistors submitted to gate- and drain-step stress, and the related trapping processes. We demonstrate that GaN-based vertical devices are promising since guarantee high current densities, while having a reduced dynamic Ron and high reliability.
The results presented within this talk provide an up-to-date description of the state of the art on the reliability of power transistors based on gallium nitride.

MOCVD growth of GaN-on-Si is the current standard to achieve a cost effective technology for GaN power devices. There are however some challenges related to growing on these substrates, in particular when scaling up the wafer size to 200 mm. The growth is heteroepitaxial with a large lattice and coefficient of thermal expansion (CTE) mismatch between the handling substrate, Si(111), and the (Al)(Ga)N buffer. Due to this mismatch a good control of stress during growth is required, necessitating dedicated stress compensation strategies for the buffer and this will limit the ultimate thickness which can be achieved for the (Al)(Ga)N buffer. Recently, investigations have been on-going to explore next generation substrates by looking into alternative technologies or solutions for the substrates, e.g. by modifying the silicon base material, using SOI substrates or using a completely different carrier substrate which has a better matching of the thermal expansion coefficient. For this work we have compared different novel substrate concepts from the point of reliability and buffer quality. A reliability evaluation has been performed on both the epitaxially grown buffers, as well as on devices fabricated on the buffers. For the buffers, the breakdown, lifetime and buffer induced current collapse have been evaluated. Imec’s latest p-GaN device technology has been used to fabricate power devices and evaluate the impact of the choice of substrate technology on the device reliability. For the engineered Si substrates we have investigated substrates with either a modification in the doping level and type, leading to different substrate resistivities, or miscut angles. One of the findings is the occurrence of a plateau in the vertical leakage characteristics. This plateau is thought to occur from a depletion in the silicon substrate at low p-type doping levels. Device reliability evaluation in this regime have revealed that the occurrence of the plateau is also correlated to an increase in device dispersion and V_t,shift. This is believed to occur due the a reverse polarization of the buffer just after stress. This plateau and device degradation can be completely avoided if highly doped p+ substrates are used. SOI substrates on the other hand represent an interesting alternative as they can enable co-integration of high-side and low-side power switches on a single chip, moreover a stress partitioning is happening on these wafers which allows to grow alternative buffer topologies with benefit in total thickness. Reliability testing on buffers and devices revealed the ability to reach high breakdown voltages (>900V) a very low buffer induced 2DEG collapse (<5%) and similar device reliability compared to regular GaN-on-Si.

Improving the reliability and durability of photovoltaic (PV) modules is necessary to reduce the levelized cost of electricity of PV installations. However, due to the extended deployment times (> 25 years) and multicomponent construction of these devices there are many potential degradation and failure modes. Two components which are most notably linked to module end-of-life failure include the solar cell contact metallization and polymeric encapsulation. In this framework here is presented a degradation analysis of PV ribbon wire solder joints and polymeric encapsulation in field-exposed PV modules. The modules have been deployed for 4 to 28 years in many different regions, including in desert, temperate, continental, and tropical climates. Surface and cross-sectional morphological (SEM, optical microscopy) and chemical (FTIR, Raman) characterization of the module layers has revealed several common patterns. Poor soldering practices have been identified in many of the modules, including the newer modules. These include incomplete soldering due to poor wetting and ribbon wire alignment. In addition to initially poor soldering, several types of solder joint degradation are observed, including phase separation, grain coarsening, corrosion, and cracking.

The metallization layer of a solar cell is covered by an ethylene vinyl acetate (EVA) encapsulation layer on the sun-exposed side of the modules. The most apparent degradation of this layer is yellowing, which reduces the amount of low wavelength light arriving at the solar cell, thereby decreasing extractable current. Degradation of the metallization and encapsulation do not occur in isolation, and in fact they have a direct impact on one another. The photochemical degradation of the EVA leads to formation of corrosive acetic acid which remains mostly trapped within the cells. There are also thermomechanical stresses generated between the soft, rubbery encapsulation layer, and comparatively hard metal layers, promoting and accelerating the cracking observed by by cross-sectional analysis. The metallization also prompts changes in the EVA layer, most notably by formation of carboxylate salts in the polymer, which are only found in regions where there is direct contact between EVA and PV metallization.

The degradation of the metallization and encapsulation layers has various implications for the lifetime of PV modules. Poor electrical contact with the ribbon wiring increases series resistance of the solar cells, reducing overall power. Degradation of the encapsulation means it is less capable of fulfilling its intended purpose, e.g. optical coupler, oxygen/moisture barrier. Prior work has examined each of these systems in isolation and on a very lmited number of specimens. This work correlates degradation of these two components on a comparatively large sample set, with modules from a very broad range of ages, climates, and PV technologies.

The photovoltaic market is currently dominated by multicystalline silicon (mc-Si) based solar cells with around 70% of total production. Upgrade metallurgical-grade (UMG) Si material, using metallurgical processes for purification of standard-quality silicon metal, suffer from a high dopant level which limits its application. However, UMG Si is demonstrating astonishing progress and hold the promises of lower cost than traditional Siemens proceess, being categorized as an emerging technology. In order to improve the quality of the UMG Si material, it is essential to have a deeper knowledge of the type of defects and their detrimental effects on the photovoltaic conversion. There are several techniques that allow to characterize the electrical activity in solar cells. On the one hand, full-wafer characterization techniques like electroluminescence and photoluminescence imaging (ELi/PLi) provide a fast inspection of the defects at the expense of high spatial resolution. On the other hand, high spatial characterization of solar cells can be achieved using the light-beam induced current (LBIC), but measurements can take many hours. Here we present the study of the electrical activity in UMG mc-Si solar cells using homemade ELi/PLi and LBIC systems.. Several solar cells with well established efficiencies (from 15 to 18 %) have been characterized. The ELi/PLi allow for a fast inspection of the solar cells. The images show dark lines that mainly correspond to grain boundaries and intragrain defects. The histogram level of the images correlates fairly well with the efficiency. In order to obtain a deeper knowledge of the kind of defects and their detrimental effect, high resolution LBIC maps are recorded on selected cell regions, revealing detailed information about intragrain defects, presenting low electrical activity along the core of the defects and high captures rates around them.

Cu(In,Ga)(S,Se)₂ photovoltaic devices have shown very competitive record efficiency of 22.6% and are globally manufactured at gigawatt levels. One of the most puzzling properties of high-efficiency CIGS devices is the appearance of metastabilities, which have accompanied the development of CIGS devices since its early days. These metastabilities are in most cases reversible parameter drifts of primarily open-circuit voltage and fill factor with extremely long time constants. Metastable behavior in CIGS solar cells has been explained through many mechanisms such as, (a) presence of amphoteric (V_Se-V_Cu) divacancy which can change from one configuration to another (acceptor or donor), depending on the availability of activation energies needed to promote such transformations. (b) Fast diffusion of Cu as interstitial Cu⁺ ions (c) metastable shallow and deep donor configurations for In_Cu DX-center defect or (d) Deep acceptor traps (V_Se-V_Cu)³⁻ in the defective p+ layer. The mechanisms of metastability are not clear in high efficiency CIGS devices with Cd-free buffer layers and alkali treatments.
The current paper aims at investigating metastability in CIGS solar cells with CdS and Zn(O,S) buffers as a function of alkali treatments. Our approach to this task is as follows. 3 types of CIGS cells are processed with substrate cell structure of soda lime glass SLG/Molybdenum(Mo)/CIGS/buffer/i-ZnO/ZnO:Al. Type-1 consisting of Na from the glass diffused into CIGS (no SLG barrier), and a CdS buffer. Type-2 consists of a barrier between the SLG and Mo layers, and CdS buffer. Type-3 consists of no SLG barrier and Zn(O,S) buffer. Metastability tests are conducted at elevated temperatures (50-85 C), light conditions (dark, AM1.5, blue, red), with in-situ JV measurements. Electro-optical properties of J-V-T, C-V, and QE are performed to quantify device performance, diode characteristics, carrier density, space charge width, and photocurrent losses before and after accelerated stress testing (AST). J-V, C-V, and QE measurements on the 3-types of devices have been performed, prior to AST. Initial C-V (10-100 KHz) measurements suggest carrier concentration=1.8-4.5*10¹⁵ cm^-3, and equilibrium space charge width = 360-500 nm, while QE measurements (300-1200 nm) reveal 1.) for devices fabricated with a Zn(O,S) buffer (Type-3), compared to devices with a CdS buffer (Type-1 and Type-2), a higher short wavelength response (300-500 nm); and 2.) for reduced alkali devices (Type-2), a lower infrared wavelength response (950-1100 nm), and possible bandgap shift, compared to higher alkali devices (Type-1 and Type-3). It is observed that Zn(O,S) buffer shows higher improvement in V_oc over a 15 hour stabilization test at 50 , 1000 W/m² as compared to CdS buffer. Further TRPL and DLTS measurements will be conducted on these samples to determine underlying mechanisms of metastability.

Grain boundaries play an important role on the efficiency of CdTe solar cells since they can act as recombination centers for carriers. Experiments found in the literature show that different types of grain boundaries form during the growth of polycrystalline CdTe. However, little information about the dynamics of grain boundary growth and evolution has been reported. Investigating the dynamics of grain boundary growth and evolution at the atomic scale is difficult to achieve through experiments. On the other hand, computer simulations such as Molecular Dynamics (MD) allow to study the fundamental mechanisms of growth and evolution of grain boundaries. In this work, we apply MD simulations to study the fundamental mechanisms for the migration of Σ7 and Σ11 grain boundaries in CdTe. Differential energies are systematically applied to grains to study grain boundary motion at various temperatures. Our results show the presence of full and partial dislocations at the grain boundary. This suggests that dislocations play an important role in the migration of grain boundaries. These results will add to the understanding of grain boundary migration and the fabrication of higher quality CdTe-based materials to increase the solar cell efficiency.

Cadmium Telluride is the most successful thin-film photovoltaic technology (TFPV) in today’s market. Understanding of kinetic mechanisms affecting performance / stability of CdTe TFPV on atomistic level is one of key requirements for further reduction of Levelized Cost of Electricity (LCOE) for this technology. Such understanding requires a comprehensive analysis that is only possible by using specialized software. In this work, we present a new generation of a kinetic solver for modeling reaction-diffusion processes in CdTe TFPV. Developed 2-D reaction-diffusion simulator executes on comprehensive defects chemistry models with parameters obtained from the first principles.

In order to simulate metastable processes that occur in the device under standard operating conditions, one first needs to obtain realistic initial conditions for the concentration profiles of charged and neutral defect species in the device stack. In turn, this requires simulation of the process steps used in the actual device fabrication. In this work, we demonstrate use of developed 2D solver to simulate formation of p-type CdTe absorbers by Cu diffusion/activation anneal in chlorinated CdTe thin-films deposited on n++ transparent conductive oxide (TCO) substrate.

We investigate the thermal stability of InGaN solar cells under thermal stress at elevated temperatures from 400°C to 500°C. High Resolution X-Ray Diffraction (HRXRD) analysis reveals that material quality of InGaN/GaN did not degrade after thermal stress. The external quantum efficiency (EQE) characteristics of solar cells were well-maintained at all temperatures, which demonstrates thermally robust nature of InGaN materials. Analysis of current density–voltage (J–V) curves indicates that the degradation of conversion efficiency of the solar cell is mainly caused by the decrease in open-circuit voltage (V_oc), while short-circuit current (J_sc) and fill factor (FF) remain almost constant. The decrease of V_oc after thermal stress is attributed to the compromised metal contacts. Transmission line method (TLM) results further confirmed that p-type contacts became Schottky-like after thermal stress. The Arrhenius model was employed to estimate the failure lifetime of InGaN solar cells under different temperatures. These results suggest that while InGaN solar cells have high thermal stability, the degradation in metal contact could be the major limiting factor for these devices under high temperature operation.

Catastrophic optical damage (COD) is a crucial factor that limits the operation and lifetime of ultra-high power lasers. The understanding of the COD is essential to improve the endurance of this kind of devices. The COD is observed as a process in which the active part of the laser diode is destroyed. As a result, characteristic defects are formed, the so called dark line defects (DLDs). These defects are usually generated at the front facet and propagate inside the cavity. Technologically improved mirror facets make them more resistant, and the COD is more likely to occur inside the cavity, far from the mirror facet. The DLDs are clusters of dislocations and molten and recrystallized regions. The nature of these defects suggests that both temperature and stress play a paramount role in the occurrence of the COD process. The COD arises after many hours of normal operation of the laser; therefore, it concerns lasers without grown-in threading dislocations that may cross the active zone of the laser. The dislocations are generated during the laser operation. The COD is a sudden process, in which the DLDs propagate at a very fast speed, fed by the laser self-absorption. The formation of dislocations is a mechanical process demanding that the stresses reach the onset of plasticity so that a massive generation of dislocations is induced. The origin of the forces generating the dislocations is the existence of very local hot spots in the active parts of the laser, corresponding to laser self-absorbing tiny regions. We discuss here the role of the critical temperature, the thermal conductivity, and the mechanical strength of the laser structure in relation to the COD of high power GaAs based laser diodes.

Quantum dot (QD) lasers epitaxially grown on Si are a promising light source on Si because effective lateral carrier confinement makes the lasers much less sensitive to the large dislocation densities that inevitably arise in III-V epitaxy on Si. For the past decade, considerable progress has been made to enhance the performance as well as reliability of the QD lasers.¹ Here, we present recent improvements in the reliability of the QD lasers with an extrapolated mean-time-to-failure of more than a million hours, which was enabled by a low threading dislocation density (TDD) GaAs buffer layer.

The performance of QD narrow-ridge waveguide lasers was first characterized. We have achieved continuous-wave (CW) threshold current as low as 6.2 mA and output powers up to 185 mW at 20 °C from the QD lasers grown on an optimized GaAs/Si template. Two techniques: thermal cycle annealing and InGaAs/GaAs dislocation filter layers were employed to reduce the dislocation density from ~3×10⁸ cm^-2 in past lasers to 7×10⁶ cm^-2 in these lasers, which is a factor of ~40 reduction.²

QD lasers were prepared for lifetime tests by mounting and wirebonding them onto AlN carriers. The lasers mounted on the carriers were tested at Intel Corp. at 35 °C under constant current mode. The driving currents ranged from 30 – 50 mA in order to age the lasers at roughly 2× the initial threshold currents of each laser. LIV sweeps were performed periodically during the aging test to monitor the changes in the threshold current and slope efficiency. From a nonlinear fitting method commonly used in the literature,¹ the extrapolated device mean-time-to-failure (time to double the initial threshold current) is more than one million hours (~114 years). The degradation in the slope efficiency is also studied and the average extrapolated mean-time-to-double the bias current for 10 mW output power is also more than one million hours. We also present the trend of the QD laser reliabilities depending on the threading dislocation densities in the GaAs/Si templates. The QD lasers grown on the TDD= 7×10⁶ cm^-2 GaAs/Si template achieved roughly three and five orders of magnitude higher extrapolated lifetimes than those grown on the TDD= 7×10⁷ cm^-2 and the TDD= 3×10⁸ cm^-2 templates, respectively.

Plan-view transmission electron microscopy showed a relatively high density of misfit dislocations in the QD laser active regions. Compared to the unaged device, the aged device revealed radiation-enhanced dislocation climbs, which are considered as the main gradual degradation mechanism. To achieve even higher reliability, a misfit-free QD laser on Si is going to be investigated and tested at higher aging currents and elevated temperatures.

1. A. Y. Liu, et al. IEEE J. of Sel. Top. In Quan. Elec. 21, 1900708, 2015
2. D. Jung, et al. Appl. Phys. Lett. 111, 122107, 2017

High-power single-mode (SM) and multi-mode (MM) InGaAs-AlGaAs strained quantum well (QW) lasers with emission wavelengths of 910 - 980 nm are extensively used in various fiber lasers and amplifiers for both telecom and defense applications. In particular, underseas and satellite communication systems require stringent reliability from these lasers. Since these lasers predominantly fail by catastrophic and sudden degradation due to COD, it is crucial especially for space satellite applications to investigate reliability, failure modes, and degradation mechanisms of these lasers. Catastrophic optical mirror damage (COMD) was known to be the only failure mode until our group reported a new failure mode in MM and SM InGaAs-AlGaAs strained QW lasers in 2009 and 2016, respectively. Our group reported that bulk failure due to catastrophic optical bulk damage (COBD) has become the dominant failure mode of both SM and MM lasers. Since there have been limited reports on COBD contrary to COMD, the intent of this paper is to introduce our studies on COBD that have spanned the last decade.

We investigated reliability, failure modes, and degradation processes in SM and MM InGaAs-AlGaAs strained QW lasers by performing short-term step-stress tests and long-term accelerated life-tests as well as failure mode analyses using various nondestructive and destructive micro-analytical techniques including electron beam induced current (EBIC), time-resolved electroluminescence (EL), deep level transient spectroscopy (DLTS), focused ion beam (FIB), and high-resolution TEM. EBIC and EL techniques were employed to study dark line defects generated in degraded lasers stressed under different test conditions. Time-resolved EL techniques were employed to study initiation and progressions of dark spots and dark lines in real time as lasers were aged. DLTS techniques were employed to study electron traps in both pristine and degraded lasers. Lastly, FIB and high-resolution TEM were employed to prepare cross sectional and plan view TEM specimens to study DLD areas (dislocations) in post-aged lasers. We will also present our current understanding on degradation mechanisms responsible for COBD in both SM and MM lasers.

In this presentation, the failure criteria of LED will be reviewed. And then the examples of electrical and optical failures of LED products will be discussed. Finally, various Failure Analysis techniques such as FIB, SEM, TEM, OBIRCH, TIVA, PEM, Thermal IR imaging, I-V, Electroluminescence, Photoluminescence, Cathodoluminescence, Raman, FTIR, DSC, TGA, DMA, TMA etc will be reviewed on each type of failures and defects. Brief overview of failure mechanisms of LED products will also be discussed.

In Electronics the term Failure analysis (FA) indicates the process of analyzing a failed electron devices to determine the reason for degraded performance or catastrophic failure and to provide corrective actions able to fix the problem. This procedure starts from the observation of the failure mode to discovery the failure mechanism, the physical cause responsible for the damage.
Failure Analysis has at least three tasks.: 1) Technical/scientific: to find the failure mechanism, in order to point out the acceleration factors and rules for predicting the MTTF; 2) Technological: to address corrective actions in manufacturing processes; 3) Economical: to define responsibilities, between manufacturer and customer, in case of failure.[1,2]
During a complex FA the final step of a chain reaction could be observed as the cumulative effect produced by several events that one after another finally lead the device to fail. A large number of correlated factors must be understood to recognize and remove the origin of the domino effect which is the root cause of the observed final failure.
Failure Analysis has logics and rules [3] here explained in terms of good and bad practices with the aim to demonstrate what Failure Analysis should be and should do, to show why and how it often does not.
Special emphasis will be placed on case studies of optoelectronic devices.

[1] G.Mura, M.Vanzi “Logics of Failure Analysis: 20 Years of rules of the Rue Morgue” Proc. Of Physical and Failure Analysis of Integrated Circuits (IPFA), pp. 379-382 , 2016
[2] G.Mura, M.Vanzi “Faulty Failure Analysis” Proc. Of Physical and Failure Analysis of Integrated Circuits (IPFA), pp. 599-602, 2013
[3] G.Mura, M.Vanzi "Failure Analysis of Failure Analyses: The Rules of the Rue Morgue Ten Years Later", IEEE TDMR, vol. 7, pp. 446-452, 2007

We present experimental results obtained by applying imaging techniques to the operation of edge emitting diode lasers. Standard Si-based CCD cameras, short-wave infrared (IR) and thermal cameras (for the medium IR range) were used for stationary and transient measurements. Time resolutions in the sub-microsecond range were achieved by operating diode lasers with short pulses and using the cameras as time-integrating monitors. Both GaAs and GaN-based diode lasers are involved in the study. The presented type of imaging analysis allows the detection of spatial temperature profiles, defect distributions, and non-equilibrium carrier distributions. Knowledge of these parameters is helpful for the development of new device architectures and the elimination of deficiencies in existing device designs. The time-resolved measurement of moving defect fronts reveals the kinetics of sudden degradation processes. Thus, in-situ imaging techniques represent versatile tools that complement standard failure analysis of diode lasers.

Graphene layers grown epitaxially on SiC substrates are attractive for a variety of sensing and optoelectronic applications because the graphene acts as a transparent, conductive, and chemically responsive layer that is mated to a wide-bandgap semiconductor with large breakdown voltage. Recent advances in control of epitaxial growth and doping of SiC epilayers have increased the range of electronic device architectures that are accessible with this system. In particular, a recently-introduced Schottky-emitter bipolar phototransistor (SEPT) based on an epitaxial graphene (EG) emitter grown on a p-SiC base epilayer has been found to exhibit a maximum common emitter current gain of 113 and a UV responsivity of 7.1 A/W at 365 nm. The behavior of this device, formed on an n⁺-SiC substrate that serves as the collector, was attributed to a very large minority carrier injection efficiency at the EG/p-SiC Schottky contact. This large minority carrier injection efficiency is in turn related to the large built-in potential found at a EG/p-SiC Schottky junction. The high performance of this device makes it critically important to analyze the sub bandgap visible response of the device, which provides information on impurity states and polytype inclusions in the crystal. Here, we employ scanning photocurrent microscopy (SPCM) with sub-bandgap light as well as a variety of other techniques to clearly demonstrate a localized response based on the graphene transparent electrode and an approximately 1000-fold difference in responsivity between 365 nm and 444 nm excitation. A stacking fault propagating from the substrate/epilayer interface, assigned as a single layer of the 8H-SiC polytype within the 4H-SiC matrix, is found to locally increase the photocurrent substantially. The discovery of this polytype heterojunction opens the potential for further development of heteropolytype devices based on the SEPT architecture. Additionally, a new SEPT device havs been formed using a SiF₄ precursor. The sub-bandgap response of this device will be discussed.

Ionic ligands dramatically influences various ground and excited state properties of CdSe quantum dots (QDs). Ligands therefore, can be used to tailor CdSe QDs properties for application ranging from biolabeling, solar energy harvesting to display technology. Atomic level investigation was performed via Density Functional Theory (DFT) calculations, these calculations provide insight to the effects of hydride (H^-) and Phenyldithiocarbamates (PTC) on CdSe QDs. When simulating the effect of H^- treatment on CdSe QDs, the photoluminescence (PL) increase because H^- reacts with surface ions to form H₂Se and Cd²⁺–H^- bonds. These interaction are beneficial when creating a display however, the interaction between PTC and CdSe QDs could lead to poor solar cells. When PTC ligands are exchanged with native ligands PTC decomposes. DFT calculations provide evidence that these products of the decomposition can also exchange with native ligands “polluting” the surface. This pollutants could decrease the efficient of the solar cell by causing defect states preventing the separation of the electron and hole pair. Atomic level DFT calculations has shown the necessity to understand the interaction between ionic ligands and CdSe QDs for their ground and excited state properties.

This study compares the surface energies of and effect of doping on native oxides of Si(100), Si(111) and GaAs(100), and effects from doping, via Three Liquid Contact Angle Analysis (3LCAA) and the Van Oss Theory.

In 3LCAA, contact angles are measured from three liquids (18 MΩ deionized water, glycerine, and alpha-bromonaphthalene) in a class 100 hood. A new automated Drop and Reflection Operative Program (DROP) uses polynomial curve fitting to determine the contact angle of both drops and its reflection. DROP removes subjectivity in image analysis, yielding more reproducible contact angles. When compared with the Sessile Drop method, DROP yields 10-50% lower standard deviations for sets of 20-30 drops.

Native oxide/Si(100) wafers with a low bulk p+-doping of 5 x 1013 B/cm3 (7-13 Ωcm) is hydrophilic and yields a total surface energy density γ^T of 53 ± 2 mJ/m². This is 9% larger than the γ^T for native SiO2/Si(111) n-doped, which yields 48 ± 2 mJ/m² across four Si(111) wafers. Ion Beam Analysis (IBA) using O2 nuclear resonance combined with MeV ion channeling detects that the native oxides on Si(111) contain 1.4 times more oxygen than Si(100). A decrease in the amount of native SiO2 on Si(100) would increase its surface energy. Measurements of the Lifshitz-Van der Waals surface energy component γ^LW for native SiO2/Si(100) yield 36 ± 0.4 mJ/m² equal to γ^LW for native SiO2/Si(111), 36 ± 0.6 mJ/m². Measurements of the electron acceptor surface energy component γ⁺ for native SiO2/Si(100) yield 34 ± 2 mJ/m² which is greater than γ⁺ for native SiO2/Si(111), 28 ± 3 mJ/m², by 21%.

Native oxides on Si(100) with a high bulk p+-doping level of 5 x 1019 B/cm³ (.01-.02 Ohm cm) yield γ^T of 39 ± 1 mJ/m². Consistent with a lower γ^T, it is more hydrophobic. Higher doping leads to a 20% larger γ^T, with a relative error less than 3%. IBA using O2 nuclear resonance combined with MeV ion channeling is used again to establish that it is due to a difference in native oxide thickness, in this case caused by doping rather than crystal structure .

In comparison, the surface energy density of native oxides of GaAs(100) is found to always fall around 38 ± 2 mJ/m² as measured on four GaAs wafers with different dopants and doping levels. The consistently hydrophobic native oxides found on various GaAs surfaces correlates with consistent native oxide composition and thickness.

3LCAA and IBA can detect, with an accuracy of a few percent, changes in the surface energy of native oxides due to surface composition variations arising from doping or crystal structure.

The use of interfacial misfit dislocation filtering (IMF) using GaSb/GaAs interface has been garnering interest for III-V optoelectronics and high-speed transistors applications in recent years, due to its unique characteristics that allow rapid relaxation in the growth of highly mismatched heterostructures. This feature can be beneficial for applications in high-speed electronics, where materials with lattice constants of 6.0Å or beyond (i.e., InAs, GaSb, and InSb) have significantly higher carrier mobility. These materials are also useful in mid-infrared photodetector/emitters, hence allowing their growth on a more volume-friendly GaAs substrate opens up the possibilities for improved throughput in the existing mid-IR industries and new applications such as replacing the Ge cell low bandgap sub-cell on a III-V multi-junction solar cell structure.

Despite its known properties, the relaxation mechanism of IMF and how the growth parameters can be tuned to ensure a uniform formation of the misfit dislocation still require further study. In this work, a series of GaSb/GaAs samples were grown with a varying thickness between 12nm – 500nm. The samples were characterized using atomic force microscopy, x-ray diffraction, and spectroscopic ellipsometry. Cross-sectional transmission electron microscopy (TEM) was also used on selected samples to evaluate the IMF formation. Rapid relaxation of over 90% was observed in all samples, even on the GaSb sample grown only up to 12 nm thick. This rate of relaxation is far superior compared to existing graded buffer technique which requires a thickness of ~1 micron to bridge the lattice mismatch between GaAs and InAs. Ellipsometry analyses show that the complex dielectric function of the relaxed part of the GaSb film is very close to that of bulk GaSb, while the interface region exhibits various peak shifts, charge redistributions, and doping behaviours that strongly depend on the growth parameters.

The study proposed a method on a high breakdown voltage for AlGaN/GaN high electron mobility transistor (HEMT). It has a structure of double charge region passivation layer by adding two negative charge regions in the passivation layer between the gate and drain. The negative charge can be realized with fluorine plasma treatments. Compared with the structures of conventional passivation layer and field-plate transistor, the electrons in the channel of the transistor with double charge region passivation layer are depleted by the negative charge in the passivation layer, which would result in increasing ON resistance. Futhermore, there would not be larger peak electric field in the channel layer, and also the electric field is more well-distributed. The Id of this structure has a certain improvement over the one of the field plate structure, and it is less than that of the traditional HEMT. The double charge region passivation layer can regulate the distribution of electric field in the channel layer, which could effectively improve the breakdown voltage of the device to 1200 V.

In recent years, silicon carbide has attracted more and more attention since it has advantages such as lightweight, high strength and hardness, low thermal expansion coefficient, excellent wear resistance, high chemical stability, outstanding thermal conduction ability. Therefore, silicon carbide has been utilized in many industries, especially applications in harsh environments including aerospace, astronomical, and semiconductor instruments. In this study, we develop a surface metallization process for single-crystalline silicon carbide substrate by electroless deposition of nickel. We also investigate the effect of annealing process for the as-deposited Ni-coated silicon carbide substrate. The annealed Ni-coated silicon carbide substrate undergoes electrochemical analysis to evaluate its corrosion resistance. Images from electron microscopes (SEM) confirm the formation of uniform Ni film on silicon carbide surface. X-ray diffraction (XRD) pattern indicates the existence of Ni_xSi_y phases after annealing. In addition, the cross-hatch test is carried out to test the adhesion between Ni film and SiC substrate. As a result, the cross-hatched area presents adhesive level of 5B which represents an excellent adhesion between Ni film and SiC substrate.

We report on a study of the effects of thermal annealing and electron beam irradiation on the optical properties of In_0.14Ga_0.86N films. An increase in luminescence intensity greater that 3-fold was observed after annealing at 800°C for 5 minutes. A similar luminescence intensity increase was obtained under electron beam irradiation. After subsequent anneal at 600°C for 1 hour, the improved cathodoluminescence (CL) intensity of the 800°C annealed sample was unchanged, but the CL intensity of e-beam exposed sample reversed back to as-grown level. The improvement in luminescence intensity is attributed to breaking the N-H bond of un-reacted ammonia resulting from the low temperature MOCVD growth. It is suggested that un-reacted ammonia act as non-radiative recombination centers, which are dissociated and removed when annealed at a temperature greater than 800°C or locally dissociated by electrons during e-beam irradiation. This study shows approaches that can significantly improve the optical properties of InGaN, and can be potentially beneficial to InGaN-based optoelectronic devices.

Transparent conducting oxides (TCOs) play an important role in many applications such as displays, touchscreens, solar cells and LEDs. Nowadays, for high-end optical requirements, the most commonly used TCO is indium tin oxide (ITO). With the increasing demand in such optoelectronic applications and uncertainties in indium prices, research is being conducted in order to find alternative oxides that present similar electrical and optical properties as ITO. One of these proposed alternatives is Nb doped TiO₂. While sputtered layers of Nb doped TiO₂ so far exhibit sufficient transparency and conductivity for TCO applications, wet chemical routes often produce inferior conductivity. In this study, Nb doped anatase TiO₂ nanoparticles with different Nb concentrations were synthesized by a sol-gel route and characterized by XRD, TEM and Raman spectroscopy. Pellets were pressed from the powders and used as target for pulsed laser deposition (PLD) on borofloat substrates. The resistivity of the pellets and of the coatings was measured. Coatings were evaluated regarding their optical transmission and haze. Future works will include wet chemical coatings made of nanoparticle inks on different substrates like glass and polymer foils.

Bonding heterogeneous semiconductors into monolithic devices increase performance in solar cells, sensors, and opto-electronic devices. Bonding occurs between two surfaces if electrons transfer, forming molecular cross-bonds, called Nano-Bonding™[1]. The possibility of electronic transfer is probed through the surface energy of each material via interactions with electron donors and acceptors. Total surface energy (γ^T) has been modeled by Van Oss and combines three different interactions: interaction with molecular species or Lifschitz-Van der Waals interactions (γ^LW), interaction with electron donors (γ⁺), and with electron acceptors (γ^-).

Using Three Liquid Contact Angle Analysis (3LCAA), the three surface energy components are measured with three liquids: 18 MΩ DI Water (polar), Glycerin (polar), and Alpha-Bromonaphthalene (apolar). γ^T is then computed from γ^LW, γ⁺, and γ^-, using three liquid contact angles to yield three equations with three unknowns.

On both hydrophobic and hydrophilic surfaces, γ^T scales linearly with γ^LW. However, the γ^T of hydrophobic surfaces is almost entirely due to molecular interactions (γ^LW), with little contribution from γ⁺ and γ^-.This is consistent for smooth hydrophobic surfaces since few defects and impurities interact with electron donors and acceptors. On the other hand, on very hydrophilic surfaces, the contribution of γ^- is very significant and can be as large as γ^LW, while on hydrophobic samples, γ^LW is always much larger than γ^-.The pairing of a relatively high γ^- with a relatively high γ⁺ is how electron exchange and bonding is enhanced while keeping the surface neutral. Surface modifications that adjust the energy components of each material allow for the design interactions that favor bonding [1].

3LCAA, performed on native oxides of GaAs(100) p-type Te doped, yields consistent surface energies of 37.7 ± 1.7 mJ/m² corresponding to strongly hydrophobic surfaces. After surface preparation for Nano-Bonding™, GaAs can make strongly hydrophilic reproducible surface energies of 65.5 ± 1.4 mJ/m². Ion beam analysis (IBA) combines <111> axial channeling with MeV nuclear resonance to show hydrophobic GaAs(100) native oxides have a mixture of about 2/3 Gallium Oxide and 1/3 Arsenic Oxide. After surface preparation, IBA detects the resulting hydrophilic GaAs(100) surface as terminated by an As top layer with a Ga layer underneath.Oxygen on the surface decreases by a factor of two and appears to correspond to an -OH termination. This new surface composition changes GaAs(100) from strongly hydrophobic to strongly hydrophilic. Combined with modification of Si(100) surface energies, such GaAs surfaces can be successfully Nano-Bonding™ to Si(100) in air at temperatures below 200^oC [2].

[1] Herbots et al. US Patent 9,018,077 (2015); 9,589,801 (2017).
[2] Herbots et al, US Patent Pending (2017)

In recent years, n-type In₂O₃ nanowires (NWs) have attracted tremendous attention for their excellent optical and electrical properties. Field-effect transistors (FETs) based on n-type In₂O₃ NWs have been widely applied to memory devices, solar cell, especially photodetector for UV region. However, the relatively low electron mobility of the In₂O₃ NWs grown by chemical vapor deposition (CVD) limits their further application. Here, by doping Ga, NWs with diameter down to 30nm diameter grown by chemical vapor deposition (CVD) in ambient pressure are successfully prepared. The Ga doping is found to enhance the crystal quality of In₂O₃ NWs and helps to yield thin and uniform NWs with low oxygen vacancy concentration. Comparing to the device based on pure In₂O₃ NWs grown in the same condition, the threshold voltages of field effect transistor based on 10 at% Ga doped In₂O₃ NWs shift in positive gate voltage and the corresponding carrier concentration at zero gate voltage decrease from ~1.29*10¹⁹ cm^-3 to 1.15*10¹⁹ cm^-3. Moreover, affected by the control of radial growth and reduction of oxygen vacancies that can act as ionized impurity scattering centers, FET based on single 10 at% Ga doped In₂O₃ NWs with diameter of about 30 nm with electron mobility up to ∼750 cm²V^-1s^-1 can be achieved. Meanwhile, the mobility of corresponding parallel NWs array FET is up to ∼210 cm²V^-1s^-1. All these results indicate promising potency of Ga doped In₂O₃ NWs in low-cost and large scale fabrication for high performance electronics.

The effect of the interface between the semiconductor and the gate dielectrics have been studied in amorphous Indium-gallium Zinc-Oxide (a-IGZO) based dual gate thin film transistors (TFTs) for obtaining stable sensing characteristics of dual gate ion sensitive field effect transistors (DG-ISFETs). As tantalum pentoxide (Ta₂O₅) possesses a high dielectric constant (~25) with a low band gap (~3 eV), and yttrium oxide (Y₂O₃) has a higher bandgap (~5.5eV) but a lower dielectric constant (~13), combinations of both were investigated to utilize the possible advantage of both the materials. In this work, thermally grown silicon dioxide (SiO₂) was used as the bottom gate dielectric on the silicon substrate (Si), and a-IGZO was used as the semiconductor material. Four combinations of the top gate (TG) dielectrics (i) Y₂O₃ only, (ii) Y₂O₃/Ta₂O₅, (iii) Ta₂O₅/Y₂O₃, (iv) Ta₂O₅ only were used to investigate the effect on the performance parameters and the effects on the interface between a-IGZO and the top gate dielectric. The effect of annealing was studied for minimizing the defects at the interface between the semiconductor and the dielectric. In the first case (Y₂O₃ only) a sensitivity of ~300mV/pH was obtained. The TFT characteristics were observed to improve by using the stacked Y₂O₃/Ta₂O₅ as the TG dielectric, where the sensitivity was ~450mV/pH, the threshold voltage was 3.8V, the sub-threshold swing was 1V/dec and hysteresis was zero. In the third case where the reverse stack (T₂O₅/Y₂O₃) was used, the obtained threshold voltage was 24V implying that Ta₂O₅/Y₂O₃ combination resulted in defects at the interface which reduced the device performance; thus the sensitivity test could not be performed. In the fourth case, where Ta₂O₅ acts as TG dielectric, the sensitivity of that device was observed to be 450 mV/pH but the drift and the hysteresis of the device were higher. The defect states, at the interfaces, were studied to understand the performance behavior of devices, using X-ray photon spectroscopy (XPS). All these DGISFTs require small volume (~2��L) of the analyte solution and thus can be used as chemical as well as biosensors.
Keywords: dual gate ISFETs, a-IGZO TFT, top gate dielectric, bottom gate dielectric

A novel ultraviolet photochemical method was used to prepare amorphous TiO₂ resistive-switching films at low temperature. The ratio of on-state to off-state currents was measured, and a good value of 10³ was obtained. The resistive switching behavior of the flexible device remained stable after 600 cycles of electrical switching, and 1000 cycles of bending. Using the same method, we also prepared ZrO₂ flexible films with a high ratio of 10⁴ of on-state and off-state resistance. Especially, due to the fact that the precursor solution of ZrO₂ are photosensitive to UV light of 325-365nm, we obtained ZrO₂ arrays on the PET/ITO substrate using a method combined with UV exposure, solvent rinsing and UV photolysis processes. The ZrO₂ arrays showed excellent resistive properties, stable resistive switching behavior after being bent for 10³ times, and showed stable flexibility up to a minimum bending diameter of 1.25cm.

The development of high-k dielectric precursors for advanced semiconductor applications requires molecular engineering and chemical tailoring to obtain specific physical properties and performance capabilities. Some high-k precursors such as organometallic precursors for atomic layer deposition (ALD) that have metal atoms bound to cyclopentadienyls, are stored at a sufficiently high temperature due to their low volatility and consumed through continuous deposition for a commercial semiconductor process. In this case, thermal degradation slowly occurs due to storage at a high temperature for a long time, which causes deterioration of physical properties and reliability of the thin film. However, a technique for assessing the reliability of precursor has been undeveloped and thus causing the development of new precursors to be delayed. In this study, we have developed a reliability evaluation method for cyclopentadienyl tris(dimethylamino) zirconium [CpZr(NMe₂)₃] through accelerated thermal degradation test under severe environmental conditions in a short period of time. To evaluate the lifetime of precursor, we have investigated the thermal stability and degradation mechanism of precursor by using analysis of NMR and Py-GC/MS and viscosity measurements.

Tungsten oxide (WO₃) is a transition metal oxide with a number of interesting properties and is being extensively investigated for various applications such as electrochromic devices and gas sensors. Thin films of WO₃ have been prepared by many techniques, including evaporation, sputtering, chemical vapor deposition and spray pyrolysis.
In this work, we present an optoelectronic characterization of this material deposited by flame spray pyrolysis for the synthesis and direct deposition of pure and Si-doped WO₃ nanoparticle films onto glass substrates featuring a set of interdigitated Pt electrodes
Characterization has been performed by measuring the current-voltage (IV) characteristics in dark conditions and by monitoring the time evolution of photocurrent under monochromatic radiation. These optoelectronic properties are particularly important when WO₃ is used as an active material in photoresistor and/or light emission devices.
The IV measurements show a resistive behavior of the material. Furthermore, the presence of hysteresis in the IV curves in dark conditions measured in forward and backward directions, between -0.5 and 0.5 Volts, indicates a capacitive behavior of the device due to trapping and de-trapping of carriers from defects inside the energy gap.
The presence of defects is confirmed by the time evolution of the photocurrent, measured under monochromatic radiation at 420nm. These data show an exponential increase with a time constant equal to 1600s independently on the applied voltage. This behavior can be ascribed to the presence of defects lying at 1.1eV below the conduction band. The responsivity at the steady state regime is equal to 2.5 mA/W at 0.5V.
When the radiation is turned off, the photocurrent shows an exponential decrease, once again independently on the applied voltage, with a time constant equal to 1000s. The defect level corresponding to this relaxation process corresponds to 0.92eV.
Currently we are performing experiments based on the current evolution at different temperatures and under sinusoidal signal in order to better understand the defect position and influence on the device performance. At the same time, an electrical model, based on the experimental results, is under development.

Temperature-dependent photoluminescence (PL) studies of Ge_1-ySn_y (y=4.3%-9.0%) alloys grown on Ge-buffered Si substrates by using a chemical vapor deposition have been performed as a function of Sn content. The PL results of Ge_1-ySn_y alloys with high Sn content (≥ 7.0%) exhibit typical characteristics of direct bandgap semiconductors, such as an increase of PL intensity with decreasing temperature and a single PL emission peak from the direct bandgap (Γ-valley) to the valence band at all temperatures from 10 to 300 K. While for Ge_1-ySn_y alloys with low Sn content (≤ 6.2%), both the direct bandgap (E_D) and the indirect bandgap (E_ID) PL emission peaks are appeared at most temperatures and as temperature increases, the integrated PL intensities of E_D initially increase and then decrease, and they finally increase again. However, the integrated PL intensities of E_ID peaks show different temperature-dependence, exhibiting unchanged at most temperatures, then they decrease with increasing temperature, and disappears at room temperature. The unstrained E_D and E_ID energies estimated from the PL spectra at 75 and 125 K are plotted as a function of Sn concentration, and the cross-over point of unstrained Ge_1-ySn_y is obtained to be about 6.4%-6.8% Sn by linear fits in the range of Sn content from 0% to 9.0%. Here, some of n-type doped Ge_1-ySn_y samples were used because we did not have as-grown undoped samples for all Ge_1-ySn_y samples. Based on the results at 75 and 125 K with doping correction, the cross-over Sn concentration of unstrained Ge_1-ySn_y from indirect bandgap to direct bandgap might be also about 6.4%-6.8% Sn content at room temperature, which is also in good agreement with previous predictions estimated at 125 and 175 K.

The miniaturization and flexibility are two trends of electronic/optoelectronic devices. However, traditional layer-to-layer device structures induce poor interface, complexity or high cost, hindering these trends. Novel device architectures fabricated by compatible manufacturing techniques are highly demanded for the next-generation electronics/optoelectronics to. Herein, we report a novel monolithic optoelectronic device fabricated by a laser direct writing method. The in-situ growth graphene is employed as lateral electrodes for flexible ZnS/SnO₂ ultraviolet photodetectors. This in situ growth method provides good interfaces between the graphene electrodes and the semiconducting ZnS/SnO₂ resulting in high optoelectronic performance. Moreover, the lateral electrode structure reduces the thickness of the devices, thus minimizing the strain and enhancing the flexibility of the photodetectors. The demonstrated monolithic fabrication is a simple and inexpensive method, showing a great potential for the development into roll-to-roll manufacturing of flexible electronics/optoelectronics.

Semiconductor device performance receives all the attention however, reliability of these high performance devices is equally important. Device design to improve performance can sometimes lead to unintended reliability issues. The design and structural complexities of finFET device have always posed manufacturing challenges which need to be overcome to preserve device performance and reliability. As design rule gets smaller and smaller, structures are being grown in increasingly tighter spaces. eSiGe is grown to provide stress/strain in channel region to improve device performance. The structure can grow to fill all its space in the PMOS and further overgrow into the NMOS region, creating eSiGe overgrowth defect. Depending on the size of the overgrowth and its location within the device structure, this defect can pose reliability risks. Effective and complete inline detection of eSiGe overgrowth on a wafer is difficult and this could heighten concerns over device quality and reliability. In this work, we look at inline detection of eSiGe overgrowth.

Metallic, III-V semiconductor, graphene and carbon-based photocathodes have been extensively investigated both from material perspective as well as structures that enabling higher quantum efficiency. One of the major challenges that result in poor quantum efficiency is the small optical absorption via directly illuminating photons. While metallic emitter reflects major portion of the illuminating light and optical absorption is small in monolayer graphene, III-V semiconductor has higher optical absorption. However, this interaction is limited to beam size and alignment of laser beam to appropriately focus on emitter. In addition to material, researchers proposed structured emitter such as sub-wavelength grating emitter as a means to increase optical absorption. This design requires nm scale precision for grating in metallic or semiconductor photocathodes which is a serious challenge in fabrication. Here, for the first time, we introduce an integrated photonic waveguide assisted photocathodes in which evanescent optical mode from the waveguide will be gradually coupled in to emitter layer. This method provides greater chance of interaction for photon absorption in emitter layer. Our demonstration consisting of graphene as an electron emitter layer on top of silicon nitride optical waveguide. We fabricated V-groove for coupling 445 nm CW laser from 200 µm core optical fiber in to silicon nitride waveguide. The fabricated silicon nitride waveguide has a height of 5 µm and its width tapered down from 200 µm at the opening of V-groove to 50 µm where a continuous layer of graphene is transferred using wet transfer technique on waveguide and extended on two Ti/Au contacts on two sides of the optical waveguide. We present the first demonstration of waveguide coupled laser induced electron emission and show comparative result with free space laser induced electron emission. Photocurrent observed at E-field as small as 0.3V/µm and the IV curves under different laser power indicates strong power dependency of the emission current. The current versus laser power curve indicates two photon process that matches with our expectation given graphene work function is higher than photon energy (2.78eV) in our laser source. Through experimental results, it is shown that up to 50X higher photocurrents can be obtained from graphene photocathode utilizing integrated photonic approach due to efficient absorption of photons. This approach can be used with other materials as well and with the recent advances in developing integrated laser this proposed device will be a solution for obtaining higher quantum efficiency photocathodes.

Color centers in single crystal diamond are promising candidate sources of single photons for optical and electro-optical quantum computing platforms, as well as sensitive probes of local magnetic field. One such defect, the silicon-vacancy center denoted as SiV^-, is composed of a substitutional silicon atom paired with two carbon vacancies, and is of particular interest due to its relative insensitivity to environmental perturbations. Conventional methods for creating these color centers are non-deterministic in location and have low yield. Here, we describe an ion beam implantation technique in which Si and C ions are implanted sequentially into diamond substrates with micron-scale precision using Sandia’s Tandem accelerator. Carbon is employed to increase the number of available lattice vacancies and thereby enhance the yield of color center formation. Preliminary photoluminescence results indicate that sequential implantation enhanced the SiV^- yield by ~25 - 140%. We discuss future work to increase yield by improved post-implantation annealing processes, as well as improved spatial positioning to tens of nanometers via focused ion beam implantation. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-NA-0003525.

Amorphous materials can be uniformly deposited over a large area at lower cost compared to crystalline semiconductors (Silicon or Germanium). This property along with its high resistivity and wide band-gap has found many applications in devices like rectifiers, xerography, xero-radiography, ultrahigh sensitivity optical cameras, digital radiography, and mammography (2D and 3D tomosynthesis). Amorphous selenium is the only amorphous material that undergoes impact ionization where only holes avalanche at high electric fields. This leads to a small Excess Noise Factor which is a very important performance comparison matrix for avalanche photodetectors.

Thus, there is a need to model high field avalanche in amorphous selenium. At high fields, the transport in amorphous selenium changes from low values of activated trap-limited drift mobility to higher values of band transport mobility, via extended states. When the transport shifts from activated mobility with high degrees of localization to extended state band transport, then the wavefunction of the amorphous material resembles that of its crystalline counterpart.

The only form of amorphous selenium used in ultra-fast radiation detectors is thin-films made by the process of Vapor-deposition. The local topology of a Vapor Deposited amorphous selenium has a predominantly ring-like symmetry, which has a distinct resemblance to the monomer ring like structure of crystalline monoclinic selenium. Thus, we model the transport of crystalline monoclinic selenium, to study the electrical properties of amorphous selenium.

We have studied the transport phenomena in crystalline monoclinic selenium by using a bulk Monte Carlo technique to solve the semi-classical Boltzmann Transport Equation. Here, we primarily consider acoustic and non-polar optical phonon scattering mechanisms. The band structure and the Density of States function for monoclinic selenium was obtained by using an atomistic simulation tool called the Atomistic Toolkit in the Virtual Nano Lab, Quantum Wise, Copenhagen, Denmark.

In this work, we have simulated the velocity and energy against time characteristics for a wide range of electric fields (1-1000 kV/cm), which is further used to find the hole drift mobility. The low field mobility is obtained from the slope of the velocity vs. electric field plot. The low field hole mobility was calculated to be 5.51 cm²/Vs at room temperature. The experimental value for low field hole mobility is 7.29 cm²/Vs. The energy vs. electric field simulation at high fields is used to match the experimental onset of avalanche (754 kV/cm) for an ionization threshold energy of 2.1eV. Finally, we present the Arrhenius Plot for Mobility against temperature and compare it with published experimental data. The experimental and simulation results show a close match, thus validating our study.

As designing semiconductor devices, band alignment is one of the most important parameters: various semiconductor devices such as thin-film transistors, solar cell and quantum well structure have to be designed by considering suitable band alignment. We focus on amorphous oxide semiconductor (AOSs) which have a lot of advantages such as relatively high carrier mobility compare with that of amorphous Si, low process temperature, and etc. AOSs can be the ability to tune their properties such as band gap, the energy positions of the conduction band minimum (CBM) and the valence band maximum (VBM) by changing the composition. In this study, we fabricate amorphous Cd–In–Ga–O (a-CIGO) films which were tuned the CBMs and the VBMs, independently, by tuning cations’ ratio.
n-Type a-CIGO films were fabricated by RF magnetron sputtering on silica glass substrates. CdO, In₂O₃, and Ga₂O₃ mixed powders were employed as sputtering targets. Carrier type, carrier concentration, and electron mobility were evaluated by Hall measurements using the van der Pauw method. Ionization potentials (I_p) were measured using ultraviolet photoelectron spectroscopy (UPS): UPS measurement chamber is connected with the RF magnetron sputtering chamber in UHV.
I_p which is energy difference from vacuum level (E_vac) to the valence band maximum (VBM) of a-CIGO films were increased by increasing Cd concentration. On the other hand, only CBM was shifted by tuning In:Ga ration but keeping Cd concentration. As a result, the a-CIGO system can independently be controlled energy position of VBMs and CBMs by tuning Cd:In:Ga ratios. Carrier concentration of a-CIGO system were from 10²⁰ to 10¹⁶ cm^-3 by increasing Ga concentration because Ga ion suppresses oxygen vacancy, which might origin of carriers in this system.

Silicon carbide single crystal is excellent materials for various application field such as high power, high temperature, high frequency operation of devices. Recently, in the semiconductor process, the ring shape SiC single crystal which fabricated via physical vapor transport (PVT) method is widely used to protect the electrostatic chuck, to guide the Si-wafer and to distribute the plasma uniformly. Therefore, the SiC single crystal ring is required to has low etch rate, and the electrical resistance as well. Recently, it is reported that the etch resistance had strong relation with the growth direction of SiC single crystal and showed 4H-SiC is more structural stability than 6H-SiC because of the maximum attractive interactions between the stacking layers.
In this study, we have investigated the correlation between growth direction and etch resistance in comparing etch depth by Ga+ ion beam. We confirmed the main growth direction of the SiC single crystal which growth by PVT method through electron back scattered diffraction (EBSD) and the etch rate comparison is conducted with ion beam irradiation in the focused ion beam (FIB) system.
As a result, 4H was higher than that of 15R and 6H in the indexing rate of SiC. Initially, most grains are oriented toward <0001> and all grains grow toward <0001> direction as they grow.
SiC single crystal was irradiated with different ion doses. Through this study, we compare the etch rate of the basal <0001> and the other sides to investigate the direction of the plane direction with a small etch rate and its relation to the growth direction.

The performance of transistors utilizing 2D materials as the channel is typically limited by the contact resistance. Here, we investigate the efficiency of electron injection into monolayer MoS₂ from a variety of potential contact metals. To keep the MoS₂ channel properties consistent, a single CVD-grown sample of MoS₂ on SiO₂ was broken into four pieces. On each piece, multiple identically-sized transfer length method (TLM) devices for two different contact metals were fabricated and tested in a back-gated configuration. A total of eight metals were investigated including Ag, Au, Cr, Cu, In, Mo, Ni, and Ti. All contact metals were capped with a top layer of Au and samples were kept in a nitrogen environment until testing to limit oxidation of the contact and channel material. Devices were electrically tested in vacuum before and after a 45-hour anneal at 400 °K. Device metrics including contact resistance and maximum current were extracted to compare contact metal performance. Agreeing with metal-semiconductor work function theory, metals with a low work function (Ti, In, and Ag) demonstrated the best prospects as a contact metal to monolayer MoS₂.

The search for adequate binary metal oxide dielectric nanolaminates (NLs) to prevent degradation of power semiconductor devices is ongoing and involves the atomic layer deposition (ALD)-growth of a variety of binary metal oxide combinations. In the present work, we explore the ALD growth of amorphous (x)HfO₂/(y)Al₂O₃ NLs on Si (with native SiO₂ layer) substrates and then on both GaN and Ga₂O₃ single crystals. A variety of samples ranging from their homogeneous mixtures to HfO₂ or Al₂O₃-rich NLs are assessed before and after a thermal annealing by spectroscopic ellipsometry (SE), XAS techniques such as X-ray photoelectron spectroscopy (XPS) and X-ray absorption fine structure (EXAFS) measurements in order to elucidate the structural evolution of the NL at the GaN (or Ga₂O₃)-NL interface. By quantifying the HfO₂ incorporation throughout the Al₂O₃ layer and using the programmable nature of ALD to alternate layers of the HfO₂ and Al₂O₃ in an (AB)_x-(CD)_y fashion, the influence of HfO₂ mobility within Al₂O₃ layer on the NL dielectric constant can be verified unequivocally. EXAFS is a powerful tool for determining the local coordination environment of the Hf at the GaN (or Ga₂O₃(001))-HfO₂ interface and, at low super-cycle numbers (sub-nm scale), the ultimate stability of the NLs can be probed and optimized such that the bulk material properties are retained. Finally, via a modified Kraut’s method,¹ Ultraviolet photoelectron spectroscopy (UPS) is used to obtain the valence band maximum (VBM) of the GaN and Ga₂O₃(001) substrates and combined with the high-resolution XPS data for the Hf and Ga shallow core-level photoelectrons ejected from the thin HfO₂/Al₂O₃ overlayer in order to assess the conduction band offset (CBO) at the film-substrate heterojunction. Probing the insulator properties imparted by the high-k overlayer on the wide bandgap semiconductor surfaces of GaN and Ga₂O₃(001) is crucial in order to understand and prevent the degradation problem in Ga₂O₃/GaN-based power semiconductor devices.

¹ E.A. Kraut, R.W. Grant, J.R. Waldrop, S.P. Kowalczyk, Phys. Rev. Lett. 44, 1620 (1980).

Transition metal (TM)-doped II-VI semiconductors are promising materials for mid-infrared (mid-IR) LEDs and laser sources. When a II-VI semiconductor such as ZnSe is doped with TM ions such as Cr²⁺, the resulting broadband emission in the 2-3 µm spectral range (due to emission from the dopant) creates the potential for tunable lasing in the mid-IR. A significant challenge in obtaining the electroluminescent (EL) structure needed for a laser diode based on this system is the high resistivity of the mid-IR active layer. This is because the dopant species that provide for mid-IR emission also make the host material (ZnSe) insulating. Cr²⁺:ZnSe films with strong photoluminescence exhibit resistivity as high as 1.5×10¹⁰ Ω*cm. On the other hand, samples co-doped with aluminum, which drastically reduces the resistivity to 100-150 Ω*cm, show virtually no luminescence. Finding a compromise between acceptable conductivity (for electrical pumping) and robust luminescence (for optical functionality) is essential for achieving reliable EL and lasing under electrical excitation. In this work we study the conductivity of Cr²⁺:ZnSe thin films of various thicknesses (100-600 nm) grown by pulsed laser deposition (PLD) on degenerately-doped (100) GaAs substrates at a temperature of 450°C under vacuum (base pressure ~10^-7 torr) using the focused beam of a KrF excimer laser with a fluence of 1.5 J/cm². A 300-nm layer of ZnS_0.1Se_0.9 (n-type), was also deposited by PLD on top of the Cr²⁺:ZnSe thin films as a prototype waveguiding material of lower refractive index. Future structures will feature thicker ZnS_0.1Se_0.9 layers above and below the active layer for effective optical confinement. All structures are capped with metallic contacts and annealed at 300°C in 5% H₂/N₂ in an effort to passivate defect states in the various metal/semiconductor and semiconductor/semiconductor interfaces. Thin films and structures were analyzed via x-ray diffraction to determine whether films were single crystal, textured with epitaxial orientation, or polycrystalline. In the case of Cr²⁺:ZnSe thin films below the critical thickness of ~150 nm, the entire structure is epitaxial and lattice matched to the GaAs substrate, resulting in the best conductivity characteristics. The density of extended defects is higher in thicker films, leading to poorer conductivity. Electrochemical impedance spectroscopy measurements yielded resistivity within the range 4.5×10⁵ – 1.6×10⁶ Ω*cm for all samples. These values can be almost entirely attributed to the resistivity of the mid-IR active layer. This level of resistivity offers the possibility of the high current densities needed in the active layer for electrical excitation. We describe our efforts in co-doping of this same active Cr²⁺:ZnSe layer with copper (Cu), coupled with p-type, Cu-doped ZnS_0.1Se_0.9 top layers to further tune the resistivity of Cr²⁺:ZnSe into a range amenable for efficient electrically excited laser sources.

In recent years, intensive studies have been carried out on field effect transistors (FETs) using vertical GaN or AlGaN/GaN nanowires^1–3. Compared to the conventional two-dimensional (2D) GaN transistors with gate control on top of the 2D electron gas, such devices have better gate control around each nanowire and higher power outputs. However, such devices still suffer from the overheating problem of GaN devices, which can largely deteriorate the device performance. To better understand this critical issue, electrothermal studies are performed on vertical GaN transistors using a recently developed hybrid simulation technique⁴. For the transistor region, coupled electron and phonon Monte Carlo simulations are employed to track the movement and scattering of individual carriers and thus obtain accurate temperature predictions. Away from the transistor, the conventional Fourier’s law is used to obtain the temperature distribution across the sub-mm chip. Our results show that the device overheating can be largely affected by the large ballistic thermal resistance at the nanowire–substrate junction.

1. Jo, Y.-W. et al. First demonstration of GaN-based vertical nanowire FET with top-down approach. in 2015 73rd Annual Device Research Conference (DRC) 35–36 (IEEE, 2015). doi:10.1109/DRC.2015.7175539
2. Im, K.-S. et al. Fabrication of AlGaN/GaN Ω-shaped nanowire fin-shaped FETs by a top-down approach. Appl. Phys. Express 8, 66501 (2015).
3. Im, K.-S. et al. High-Performance GaN-Based Nanochannel FinFETs With/Without AlGaN/GaN Heterostructure. IEEE Trans. Electron Devices 60, 3012–3018 (2013).
4. Hao, Q et al. A hybrid simulation technique for electrothermal studies of two-dimensional GaN-on-SiC high electron mobility transistors. J. Appl. Phys. 121, 204501 (2017).

The impact of collector-emitter voltage V_CE, bias conditions on total ionizing dose TID, in bipolar junction transistors BJTs, was investigated. The BJTs are set at forward active mode of base-emitter voltage V_BE, swept from 0 to 1.0 V at different biased conditions of V_CE, ranging from 1V to 2 V at an interval of 0.25V during ⁶⁰Co γ irradiation tests. The damage mechanism of TID in BJTs at different V_CE bias conditions were analyzed by forward Gummel characteristics, forward current gain β_f, normalized excess base current ΔI_B/I_Bpre, normalized current gain β_fpost/β_fpre and ideality factor n. The results show that the increments of base current ΔI_B, and collector current ΔI_C, are slightly different in various TID V_CE bias conditions which also effects slight changes in their current gain Δβ_f, degradation. However, the degradation effect was noticed more in low bias V_BE than high V_BE with no significant difference. This is attributed to different degradation produced and accumulated in oxide spacer of BJT. The ΔI_B/I_Bpre and β_fpost/β_fpre show similar trend of different V_CE bias conditions resulting into varying distribution of interface traps N_it, at Si-SiO₂ interface of the BJT under TID influence. The ideality factor n, for excess base current ΔI_B, is ~2 for V_BE from 0.35V to 0.6V at different V_CE bias conditions. Thus, ideality factor n, slightly increases as the V_CE bias rises and decreases with rising TID after N_it reaches saturation of 130krad (Si) in BJT. The 130krad (Si) low total dose’s ideality factor is closer to 2 than other increasing TID values.

In recent years, studies have focused on discovering promising new high- k dielectric materials for a variety of optoelectronic and microelectronic device applications. Lutetium oxide (Lu₂O₃) is one of the reported promising dielectric materials for IC applications due to its thermodynamic stability with Si, high dielectric constant and low leakage characteristics. It is known that the device characteristics are significantly affected by structural quality of dielectric layer and its interface between semiconductors. Therefore, in this work the effects of deposition parameters on structural, optical and electrical properties of Lu₂O₃ thin films were discussed in detail. The Lu₂O₃ thin films deposited on Si wafers at 230 W, 270 W and 300 W sputtering powers by reactive RF sputtering and deposited films were annealed from 500 ⁰C, 750 ⁰C and 900 ⁰C in Nitrogen environment for 1 hour. The structural characterizations were performed by using X-ray diffraction (XRD) and Atomic Force Microscopy Measurements (AFM), while optical characteristics were investigated by Uv- Vis spectroscopy. The capacitance- voltage characteristics were also measured to study electrical properties of the fabricated films. The results demonstrate that both sputtering and annealing temperature crucially effects the device characteristics and strong relation between structural, optical and electrical characteristics have been observed. Among the all fabricated devices, with low interface state density and low surface roughness, Lu₂O₃ MOS capacitors sputtered at 300 W and annealed at 750 ⁰C exhibits demanding performance future microelectronic applications.

Nowadays, researchers have been spent demanding efforts to discover new high- k dielectric materials for a variety of microelectronic device applications. The new high- k materials for microelectronics should be carefully chosen. Among various high-k dielectrics, Erbium Oxide is a one of the most promising dielectric layer for the future gate dielectric applications, owing to its charming features including the high dielectric constant, large band gap, large band offset value, and good thermodynamic stability with Si. Though various technological applications of Er₂O₃ dielectrics in electronics, there still exist reliability problem for the usage of this device under radiation environment. Numerous state of the art devices lose their reliability under operation on radiation environments. This research reports the performance of Erbium Oxide MOS capacitors under gamma radiation exposures. Both the structural, electrical and chemical structure of the Er₂O₃ devices under gamma irradiation has been reported in details. Results demonstrate that the crystalinity of the film increase with increasing the irradiation exposure and surface roughness became smoother with irradiation exposures. In addition, the flatband voltages shift toward more negative values due to accumulation of trapped holes. On the other hand, oxygen deficient oxidation states enhance with radiation exposures which demonstrate radiation basically breaks oxygen containing chemical bonds where mobile holes can be trapped. Briefly, present results demonstrate that structural, electrical and chemical parameters of Erbium Oxide-Based thin film capacitors significantly change under gamma irradiation. Hence, parameters influence should be considered for Er₂O₃ based device to be used in high radiation field, especially for space and nuclear applications.

Acknowledgement: This work is supported by Ministry of Development of Turkey under Contract Numbers: 2016K121110.

Electrically conductive hair-like structures, referred to as whiskers, can bridge the gap between densely spaced electronic devices and components. This can lead to current leakage and short circuits, causing significant losses and, in some cases, catastrophic failure in various systems, including such in the automotive, aerospace and other industry. None of the whisker growth models proposed to date is capable of answering consistently and universally why whiskers grow, in the first place. Although there are several generally accepted factors (intermetallic compound formation, tensile / compressive stress, Sn oxide layer presence, coefficient of thermal expansion (CTE) mismatch that influence the whisker growth), the most important factor in whiskering is still a matter of dispute. A recent theory [1], which considers the imperfections (small patches of net positive or negative electric charges) on metal surface, details the quantitative estimates of the metal whisker nucleation along with their growth rates and length distributions. According to this theory, the anomalous electric field (E) formed due to the imperfections will govern the whisker development in those areas. In addition an external electric field, which can be either constant (DC) or varying with time (AC) at high frequencies (including optical), can also contribute to nucleation and promote their growth by means of lowering the free energy of the system.

Here, we present a new way of controlling the growth of whiskers by using localized high-intensity DC electric fields by using an AFM setup and we refer to it as whisker engineering. A current sensing AFM scanner with a conducting cantilever was utilized. The electric field was generated by applying a voltage bias between the sample and the conductive cantilever, which is maintained at a known distance, without causing any dielectric breakdown. SEM examination of samples at the points where the AFM tip was positioned for an extended period was performed before and after electric field application. Minuscule whiskers were observed; whose growth direction matched the direction of the field. The observed whisker formation can be used to design a new non-destructive readily implementable accelerated failure testing procedure as well as in other applications.

Multi-gated metal oxide semiconductor field effect transistors (MOSFETs) have recently become important in high-performances CMOS integrated circuits. Multi-gated devices, commonly called FinFETs, have reduced short channel effects, allowing for greater scalability.[1] However, there is little in the literature about the atomic defects at the semiconductor-dielectric interface in FinFETs. In this study, we explore traps at the FinFET Si/dielectric interface with electrically detected magnetic resonance (EDMR). The devices involved in this experiment are on (100) silicon-on-insulator wafers with 90nm Si layers and 125nm buried oxides. The FETs have 1nm SiO₂ and 2nm HfSiON/TiN/polySi-capped gate stacks with an effective oxide thickness of about 1.1nm. The body of the devices are lightly doped p-type at 2x10¹⁵/cm³. Each FinFET is configured as a gated diode with n+/p-/p+ with a fin length of 500nm, fin height of 80nm, and fin width of 50nm. For a single set of contacts, 500 fins are connected in parallel. Extensive electrical measurements on these devices have been reported by Young et al.[2][3]

In order to increase the defect density and maximize the size of the resonance response, we have irradiated the FinFETs to 1 MRad through exposure to a ⁶⁰Co gamma source. During irradiation, a bias of +0.25V was applied to the gate contact. Pre irradiated EDMR spectra are weak and poorly resolved whereas quite strong signal to noise spectra appear after the irradiation.

Our EDMR measurements utilized a home-built spectrometer. The X-band (≈9.5 GHz) spectrometer includes a 4-inch Lakeshore electromagnet with a Micro-Now microwave bridge and a TE₁₀₂ cavity. Spin dependent device current was measured with a Stanford Research Systems Low-Noise Current Preamplifier. The detection utilized a home-built virtual lock-in amplifier. Measurements were conducted at room temperature.

The observed EDMR spectra involve multiple overlapping lines with g values ranging from 2.0011 to 2.0084. Such g values are generally consistent with P_b centers (silicon dangling bonds), however the linewidths of these spectra are significantly broader than those typically observed for P_b center defects.

[1] Wann, C. H., Noda, K., Tanaka, T., Yoshida, M., & Hu, C. (1996). IEEE Transactions on Electron Devices, 43(10), 1742-1753.
[2] Young, C. D., Neugroschel, A., Matthews, K., Smith, C., Heh, D., Park, H., … Bersuker, G. (2010). IEEE Electron Device Letters, 31(7), 653–655.
[3] Young, C. D., Neugroschel, A., Matthews, K., Smith, C., Park, H., Hussain, M. M., … Bersuker, G. (2010). Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010, 68–69.

Understanding and control of point defects are very important to realize high-performance/highly-reliable semiconductor devices. In particular, control of point defects is essential for fabrication processes of GaN vertical power devices, such as epitaxial growth of drift (voltage blocking) layer (low compensation), selective doping by ion implantation (recovery of point defects during implantation) and reactive ion etching to form device structures (suppression of point defect formation). There are many pioneering reports on point defects in GaN. However, most of them were based on heteroepitaxial GaN which has high-density of threading dislocations (TDs) of 10⁹ cm^-2. It is difficult to separate the effect of dislocations and point defects. In addition, it is known that dislocations interact with point defects. Last four years, the author’s group has carried out systematic investigation of point defects in GaN using homoepitaxial layers with low TD density of 10⁶ cm^-2. We investigated compensation acceptor in MOVPE-grown n-type GaN layers by using Hall-effect measurements. We found that in addition to residual carbon acceptor, there is another acceptor in the GaN layers. The acceptor concentration increases with increasing Si doping, impling self-compensation effects or Si-donor-related complex. We also showed formation of deep level trap pairs by electron-beam irradiation (400 keV). The traps are annealed out with the almost equal rate. Judging from the electron energy, the traps may originate from nitrogen atom displacement, i.e., nitrogen vacancy (V_N) and nitrogen interstitial (N_i). Annealing process reflects annihilation of vacancy and interstitial.

Strain is a key engineering degree of freedom used to modulate the carrier mobility and tune the bandgap of semiconducting materials. Strain-energy relaxation mechanisms in epitaxial thin-films and heterogeneous devices, including alloy decomposition and dislocation generation and motion, may degrade electronic properties including carrier lifetime and mobility. Herein, we describe the strain-energy release mechanisms of bent silicon (diamond-cubic structure) and GaAs (zinc-blende structure) nanowires, which were elastically strained at ambient temperature, by bending, for different values and then annealed at 920 °C and 450 °C for 4 min and 60 min, respectively. When the nanowires are annealed at 920 °C, dislocations are nucleated at the surfaces of the nanowires and those dislocations align themselves to form grain boundaries, via glide and climb, which reduces the strain energy caused by bending. Using Raman spectroscopy, which is sensitive to local strain, transmission electron microscopy and scanning electron-microscopy we find that the silicon nanowires release their strain-energy by polygonization, which is a known physical-metallurgy phenomenon. Polygonization is the formation of polygon-shaped grains separated by grain-boundaries consisting of edge dislocations. This is the first time that polygonization has been observed experimentally in nanowires. In contrast, GaAs nanowires release their strain-energy by forming nanocracks on the outer portion of a GaAs nanowire, which is under tensile strain, and no polygonization is observed. Our study of the strain-energy release mechanisms of semiconductor nanowires is relevant to possible aging mechanisms and failure modes of flexible electronics.

Amorphous oxide semiconductors (AOS) like InGaZn oxide (IGZO) have taken over from a-Si:H as the dominant thin film transistor material for displays because of their higher mobility [1]. However, they suffer from light induced negative bias stress instability (NBIS)[2]. It is not agreed what is the origin of this problem. It has been attributed to oxygen vacancies [3], oxygen interstitials [4] and single hydrogen defects [5]. However, each of these models has a problem, and it would be useful to understand the role of water and hydrogen in AOSs. Here we show that the defect of two neutral hydrogen atoms at an oxygen vacancy can give the first consistent explanation of the NBIS effect. We use density functional calculations of crystalline and amorphous ZnO, using ZnO as a model for oxide semiconductors in general. This defect, V_O(2H), forms symmetric Zn-H-Zn bridge bonds which gives rise to filled states in the lower band gap, as seen by photoemission [6]. Photo-excitation of electrons from these states to the conduction band gives a persistent photoconductivity with an excitation response as seen experimentally [2]. The states have a negative U property, explaining the recombination barrier. The IR signature of the bridge bonds were recently seen experimentally [7]. A 10²⁰ hydrogens/ cm³ is seen experimentally by thermal desorption and SIMS [8], much higher than in c-ZnO. This high concentration is consistent with the low formation energy of the defect in the amorphous phase, and requires most of the hydrogen to be compensated as in the V_O(2H) state, and not as the donor configuration of the interstitial H.
1 K Nomura,..H Hosono, Nature 488 432 (2004)
2 K. Ghaffarzadeh, et al, Appl. Phys. Lett. 97, 113504 (2010)
3 B Ryu, et al, App Phys Lett 97 022108 (2010)
4 J Robertson, Y Guo, App Phys Lett 104 162102 (2014)
5 H H Nahm, et al, Sci Reports 4 4124 (2014)
6 K Nomura, et al, App Phys Lett 92 202117 (2008)
7 J Bang,.. H Hosono, APL 110 232105 (2017)
8 K Nomura,.. H Hosono, ECS J Solid State Sci Technol 2 5 (2013)

Current largest market share of a continually growing semiconductor manufacturing sector in the US demands rapid and cost-effective quality control and characterizations of Si-based semiconducting materials. To this end, recently we have developed Laser Induced Breakdown Spectroscopy (LIBS) as a facile and effective tool for process-line quantitative analysis of silicon oxide (SiO₂) thin-films on industrial-grade Si wafers grown as metal-oxide-semiconductors (MOS).¹ Herein, we present a matrix-assisted calibration technique used in LIBS for quantitative detection of dead load interstitial oxygen contents (Oi) in industrial-grade Si crystal ingots. Si crystal samples were grown via Czochralski technique and supplied by SunEdison Semiconductor Ltd. with known Oi contents measured via gas fusion analysis (GFA) and Fourier transform infrared (FTIR) spectroscopy. The LIBS analyses presented here use and compare a direct approach based on known oxygen atomic emission line at 777.19 nm and an indirect approach based on a matrix-assisted calibration technique using a lesser known emission line at 781 nm for the first time.² Unlike the first direct approach, the latter exhibited much higher sensitivity, reliability and less error. In this approach, a matrix-assisted calibration uses systematic variations in the unique 781 nm line in conjunction with observed changes in plasma excitation temperatures as a quantitative measure of changes in plasma conditions and laser-matter interactions due to varying Oi contents in the analyte matrix. Using this technique, we establish the detection limit of LIBS in measuring Oi in Si crystal ingots down to ~ 7 ppm level, while overcoming the limitations of common industrial techniques such as FTIR that cannot provide accurate quantitative measurements for highly doped Si crystals or GFA that is too cumbersome to be an online technique. Our results establish LIBS at the forefront of alternative industrial analytical tools heretofore not considered for rapid, on-line monitoring of dead loads in commercial grade Si wafers during their growth processes.

References:
(1) S. A. Davari, S. Hu, R. Pamu, and D. Mukherjee; "Calibration-free quantitative analysis of thin-film oxide layers in semiconductors using laser induced breakdown spectroscopy (LIBS)," Journal of Analytical Atomic Spectrometry, 2017, 32, 1378-1387.
(2) Seyyed Ali Davari, Patrick A. Taylor, Robert W. Standley, and Dibyendu Mukherjee; "Detection of interstitial oxygen contents in Czochralski grown silicon crystals using matrix-assisted calibration in laser-induced breakdown spectroscopy (LIBS)," Analytical Chemistry, 2017, Submitted.

The nonradiative lifetime and spontaneous emission quantum efficiency in molecular beam epitaxy grown bulk InAs_0.911Sb_0.089 [1] are determined using excitation and temperature dependent photoluminescence measurements. The measurements are performed at temperatures ranging from 15 to 295 K and pump powers ranging from 0.4 mW to 200 mW. The quantum efficiency and lifetimes are inferred from the power law relations that link pump power and integrated photoluminescence predicted by the rate equations [2]. The Shockley-Read-Hall lifetime for bulk InAs_0.911Sb_0.089 is determined to be 5 ns at room temperature and 70 ns at low temperature. The Auger coefficient is approximately constant over the 50 K to 250 K temperature range, with an average value of 1×10^-25 cm⁶ s⁻¹. The Auger coefficient increases at low temperatures likely due to an increase in carrier occupation as the effective density of states rapidly decreases at low temperature. The quantum efficiency has a peak value of 0.60 at low temperature and decreases as temperature increases, due mainly to a decrease in the radiative recombination rate. At low injection Shockley-Read-Hall recombination dominates and at high injection Auger recombination dominates, as is typical with small bandgap materials. There is a limited excitation and temperature range where radiative recombination dominates.

[1] P. T. Webster, N. A. Riordan, S. Liu, E. H. Steenbergen, R. A. Synowicki, Y.-H. Zhang, S. R. Johnson, J. Appl. Phys. 118, 245706 (2015).
[2] S. R. Johnson, D. Ding, J.-B. Wang, S.-Q. Yu, Y.-H. Zhang, J. Vac. Sci. Technol. B, 25, 1077 (2007).

Performance and stability of optical and electron devices are sensitive to material issues such as the presence of various defects in the solid. Lattice defects induce strain fields in the lattice, which affects the mechanical stability and therefore the materials reliability of the solid. The strain field also affects the electronic reliability and device performance by distorting the electronic wave functions. Moreover, aggregation and the concentration profile of neutral as well as charged defects in solids are partly determined by the long-range strain-field interaction between defects and by the interaction of defects with the free surfaces and interfaces in solids. A precise knowledge of the strain field due to defects is required for defect engineering of semiconductors that involves control and manipulation of defects for design of novel devices. This explains the renewed topical interest in modeling of vacancy and associated lattice defects in semiconductors such as nano and bulk diamonds, used in quantum computers and other devices. Defect systems of special interest are pairs of lattice defects such as V-V (vacancy-vacancy), Si-V (silicon-vacancy) and N-V (nitrogen-vacancy) in diamond.
Modeling of defect pairs in a lattice is essentially a multiscale problem because of the long range nature of their strain field. The model must account for the disctrete atomistic structure of the lattice near the defect, along with the extended structure of the surfaces/interfaces. Standard density functional theory can be very reliable for solid state simulations because, in principle, it does not depend upon phenomenological parameters. However, it is computationally limited to small crystallites containing a few hundred atoms, which may introduce spurious size effects in strain calculations.
In our calculations, we use our multiscale lattice statics Green’s function method for modeling of defects. This method is computationally very efficient and can simulate several million atoms on an ordinary desktop computer. One advantage of the Green’s function method is that it can be formulated in ‘modules’ of increasing complexity. We first consider a single mono-vacancy, and then a single di-vacancy in diamond. In the final stage, we introduce an interstitial defect such as silicon or nitrogen and an extended defect such as a free surface. The vacancies are assumed to be neutral. We calculate the elastic strain field due to isolated defects and the strain field interaction between the defect and a free surface. In the presentation, we will describe the multiscale Green’s function method along with its limitations, and its application to modeling of lattice defects with actual numerical results for diamond.

The expansion of Shockley stacking faults (SSFs) during forward operation of 4H-SiC bipolar devices remains a technical issue in the practical application of the devices. Basal plane dislocations (BPDs) are responsible for the nuclei of expanding SSFs and the SSF expansion is activated by minority carrier injection exceeding a certain level. To avoid such phenomenon, conversion of BPDs in the substrate to threading edge dislocations (TEDs) at the beginning of epitaxial growth has been attempted to eliminate the nuclei of stacking faults from the drift epilayer. However, the expansion of bar-shaped SSFs was revealed to initiate from a BPD segment bellow the BPD-TED conversion points which located near the epilayer and substrate interface in the 4H-SiC PiN diodes [1]. Recently, reduction of carrier lifetimes in a buffer layer inserted between the drift epilayer and substrate and prevention of the SSF formation in the PiN diodes have been demonstrated by employing high N doping to enhance direct and Auger recombination in the buffer layer [2]. Meanwhile, a thinner buffer layer having a stable carrier lifetime is more preferable and a technique to obtain shorter carrier lifetimes compatible with the practical epitaxial growth and device fabrication processes will be promising.
Epitaxial growth of 4H-SiC with intentional N and V doping was performed using N₂ and VCl₄ as the doping sources. The N and V concentrations were determined by SIMS. Minority carrier lifetimes in the epilayers were evaluated by time-resolved photoluminescence measurements.
Wide-raging control of V doping concentrations within 10¹³-10¹⁵ cm^-3 was achieved by changing the VCl₄ flow rates and C/Si ratios of the source gasses. The epilayer doped with N only (N=5×10¹⁸ cm^-3) shows minority carrier lifetimes of 66-120 ns within the temperature range RT-250°C, where the carrier lifetimes are mainly controlled by direct and Auger recombination due to the high density of majority carriers. The N+V-doped epilayer (N=5×10¹⁸ cm^-3, V=7×10¹⁴ cm^-3) shows much shorter carrier lifetimes of ~20 ns or less at RT-250°C. The minority carrier lifetimes in the N+V-doped epilayers became shorter with increasing V concentrations, indicating that V effectively controls minority carrier lifetimes in the 4H-SiC epilayers. In the electrical tests for the PiN diodes employing a ~2 µm-thick N+V doped buffer layer (N=~3×10¹⁸ cm^-3, V=~2×10¹⁵ cm^-3) and ~10 µm-thick n^- drift layer (N=~1×10¹⁶ cm^-3), showed no increase in forward voltage drop, nor any formation of stacking faults, even after high current density conduction at 600 A/cm² for 1h.
This work was supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics/Consistent R&D of next-generation SiC power electronics” (funding agency: NEDO).
[1] A. Tanaka et al., J. Appl. Phys. 119, 095711 (2016).
[2] T. Tawara et al., J. Appl. Phys. 120, 115101 (2016).

Epitaxial regrowth essentially involves a multi-sequential material growth process along with intervening wafer processing steps. This process has played a significant role in realizing several semiconductor devices including distributed feedback (DFB) lasers, photonic crystal surface-emitting lasers (PCSELs), transistors and sensors[1-4]. One of the critical factors in this process is the quality of the regrowth interface. The prevention of impurities and abnormalities at this interface is paramount to device performance. In order to obtain good material quality, several parameters such as pre-growth treatments, passivation techniques, surface oxide removal and growth parameters such as growth temperature need to be optimized. This work focuses on developing an epitaxial regrowth process specifically for devices based on quantum-size-controlled photoelectrochemical (QSC-PEC) etching of semiconductor nanostructures[5]. The optimization of the regrowth step is especially significant in QSC-PEC due to the proximity of the active region (quantum wells or quantum dots) to the regrowth interface.
In this work, we have investigated the effect of the regrowth interface on structural and optical properties of pre-grown active components such as InGaAs quantum wells (QWs) or InAs quantum dots (QDs). The structures used in this study are grown using elemental molecular beam epitaxy (MBE) in a VG Semicon V80 reactor on GaAs substrates. The original structures (before regrowth) include InGaAs QWs or InAs QDs grown with different GaAs cap thicknesses, thus varying their proximity to the regrowth interface between 0 and few hundreds of nm. The samples are then exposed to atmosphere before regrowth is attempted. The regrowth process includes pre-treatment for cleaning, surface oxide desorption and an extended GaAs cap at the interface. Different recipes for surface cleaning and both in-situ and ex-situ oxide desorption methods are attempted. A comprehensive photoluminescence (PL) study is carried out from 10K to room temperature to study the effect of the cap thickness and the various cleaning techniques on the optical properties of the QWs and QDs. On the other hand, the effect of these parameters on the structural parameters is studied using X-ray Diffraction (XRD), atomic force microscopy (AFM) and transmission electron microscopy (TEM). Although the results obtained here are not directly from PEC-etched nanostructures, these findings can be used to tailor the properties of etched nanostructures. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

[1] Groom, Kristian M. et. al (2009)
[2] Ha, Yuk L, et al. (2011)
[3] Hjort, Klas, et al. (1992)
[4] Noda, Susumu et al. (2017)
[5] Fischer, Arthur J. et al. (2016)

We present here growth temperature dependence of crystallinity of low-temperature-grown (LTG) In_xGa_1-xAs on InP substrates and its electrical and optical properties. LTG-GaAs-based III-V compound semiconductors have been studied actively because they are candidate materials to realize photoconductive antennas (PCAs) activated by femtosecond fiber lasers with wavelengths of 1.5 μm for terahertz (THz) wave emission and detection. These lasers are less expensive and more compact than conventional optical sources, and therefore, THz time-domain spectroscopy systems with these PCAs will be put into widespread use. The materials for the PCAs are required to have three properties of high carrier mobility, an ultrashort carrier lifetime, and high resistivity. However, there are some difficulties to obtain them in LTG-GaAs-based compounds. For LTG GaAs, the high density of defects such as excess As, Ga vacancy and the formation of As precipitates which is induced by low-temperature growth and thermal annealing generate the high resistivity and short carrier lifetime. Therefore, revealing the key defects is essential for efficient THz-wave emission and detection in LTG-GaAs-based compounds. For this reason, we focus on defects, and electrical and optical properties of one of the candidate materials, LTG In_xGa_1-xAs, in this study.
LTG-In_xGa_1-xAs samples (x = 0.42–0.54), with thicknesses of 1.0-2.0 μm, were grown on (100)InP substrates by molecular beam epitaxy at temperatures of 130 and 240 °C. Be was doped into In_xGa_1-xAs layers with a concentration in the range of 3.00×10^17–18 cm^-3. After the growth, the samples were annealed at 550 °C for 1 h in an H₂ atmosphere. We performed X-ray diffraction (XRD) measurements, transmission electron microscope (TEM) observations, and optical absorption and Hall effect measurements at a temperature in the range of 120–300 K for these samples.
The (400) reflection XRD showed that the sample grown at 220 °C exhibited clear XRD peak while the samples grown at 200 °C did broad spectra with low intensities, suggesting that crystalline quality deteriorates drastically at a growth temperature between 200 and 220 °C. High-resolution XRD reciprocal space mapping measured around (115)InP and cross-sectional TEM images for In_xGa_1-xAs demonstrated that single crystalline In_xGa_1-xAs layers can be grown by solid-phase epitaxy at the substrate temperatures of 130-180 °C. The measured carrier densities for the LTG-In_xGa_1-xAs samples using Hall effect measurements were fitted by simulation based on the charge neutrality of carriers and impurities. These simulation fitting showed that the localized level lay 100 meV below the conduction band minimum (CBM) for the sample grown at 220 °C. As for the sample grown at 200 °C, it was shown that it lay 10-18 meV below the CBM. Depth of these localized levels were evaluated by optical absorption, and the results implied that there were fluctuations of CBM for these LTG In_xGa_1-xAs layers.

III-V optoelectronic materials with tunable cutoff wavelengths are desired for the development of infrared photodetectors and emitters for several applications, including, navigation, night vision, launch detection, communications, imaging, and spectroscopy. Alloying III-V materials with the heavier element bismuth enable a greater rate of bandgap reduction without introducing high levels of strain compared to other group-V elements [1]. The present work analyses microstructure and composition of epilayers of InAsSbBi on GaSb (100) and GaAsSbBi on GaSb (100) using high resolution and aberration corrected transmission electron microscopy techniques to evaluate the quality of the quaternary epilayers.

Several pseudomorphic, 210 nm thick, narrow bandgap InAsSbBi and GaAsSbBi layers are grown by molecular beam epitaxy on GaSb substrates at temperatures from 280 to 430 °C and are examined using transmission electron microscopy (TEM), X-ray diffraction (XRD), and Rutherford backscattering spectrometry (RBS). The samples are grown with near-stoichiometric V/III flux ratios of ~ 1.01 to aid in the incorporation of bismuth that typically surface segregates due to its large size [2]. Cross sectional TEM samples are prepared for observation along the <110> projection using standard mechanical polishing and dimple grinding, followed by argon-ion-milling (maximum beam energy 2.3 keV) with liquid-nitrogen cooling to reduce ion-beam damage [3]. Defect analysis based on high resolution TEM indicates excellent crystallinity with no visible defects over large lateral distances. However, surface droplets are formed during high temperature growth at 430°C. Selected area diffraction patterns and fast Fourier transforms indicate the sole presence of zinc blende crystal structure with no atomic ordering. Aberration corrected high angle annular dark field (HAADF) scanning TEM images exhibited coherent defect free interfaces and geometric phase analysis of interfaces provides interfacial strain. Normalized HAADF intensities are used to study the compositional variation of bismuth. Random RBS measurements provide the average Bi content and XRD measurements determine the lattice parameters.

[1] P. T. Webster, A. J. Shalindar, S. T. Schaefer, S. R. Johnson, Appl. Phys. Lett. 111, 082104 (2017).
[2] J. Lu, P. T. Webster, S. Liu, Y.-H. Zhang, S. R. Johnson, D. J. Smith, J. Cryst. Growth 425, 250 (2015).
[3] C. Wang, S. Tobin, T. Parodos, J. Zhao, Y. Chang, S. Sivananthan, D. J. Smith, J. Vac. Sci. Technol. A 24, 995 (2006).

Efficient high-performance infrared detection and emission is desired for numerous applications, including missile guidance, gas detection, thermal imaging, and infrared spectroscopy. The incorporation of bismuth in InAs alloys results in a larger bandgap reduction per unit strain than antimony [1] and provides an efficient means of tuning mid-IR (3 – 5 µm) to long-IR (8 – 12 µm) wavelengths without introducing high levels of strain that can introduce point defects and reduce optical quality. The growth of InAsSbBi and GaAsSbBi quaternary alloys on GaSb substrates permits the designer to independently adjust bandgap and strain by varying the antimony and bismuth mole fractions. GaAsSbBi exhibits a type-II band lineup with InAsSbBi, and heterostructures composed of these bismide quaternary alloys open up the possibility of highly tunable multiple quantum well/superlattice active layers with a type-II band alignment.

The molecular beam epitaxy growth of InAsSbBi and GaAsSbBi on GaSb substrates is investigated, and optimal growth temperatures and group-V fluxes are identified for droplet-free, high-quality crystalline material. A key challenge for the bismide quaternary material systems is identifying growth conditions that yield appreciable bismuth incorporation, defect-free growth, and high optical quality. Since the large Bi atoms tend to surface segregate and not evaporate, they accumulate on the surface and form surface droplets. Therefore bismuth alloys are grown at near-stoichiometric V/III flux ratios of ~ 1.01 and reduced growth temperatures to facilitate incorporation. Both low temperature (280 to 340 °C) and high temperature (430 to 420 °C) growth regimes are explored. The material grown at low temperature exhibits high structural quality and unity bismuth incorporation at 280 °C, but exhibits poor optical quality. On the other hand, the materials grown at high temperature yield greatly improved optical quality and quantum efficiency, but with reduced structural quality due to the formation of Bi droplets. These and other challenges will be presented.

[1] P. T. Webster, A. J. Shalindar, S. T. Schaefer, and S. R. Johnson, Appl. Phys. Lett. 111, 082104 (2017).

Gallium oxide (Ga₂O₃), supported by ultra wide bandgap of ca. 5 eV, has attracted attention as a material for highly endurant power devices. Ga₂O₃ takes at least five phases, among which the research has been concentrated on orthorhombic b-Ga₂O₃ because it is the thermally stable phase and highly-crystalline bulk substrates are available being fabricated by conventional solution methods. Evolution of devices by homoepitaxy is ideal as evidenced by history of such as GaAs, InP, and SiC devices. However, orthorhombic structure is rare in semiconductor systems and therefore fabrication of heterostructures is limited. We, on the other hand, have developed corundum-structured a-Ga₂O₃ on sapphire substrates because a-Ga₂O₃ can make heterostructures with other corundum-structured materials. It should be noted that there is corundum-structured p-type (Ir,Ga)₂O₃ nearly lattice-matched to a-Ga₂O₃ [1], allowing pn junction; this is advantageous for fabricating power devices of Ga₂O₃. However, due to heterospitaxy of a-Ga₂O₃ on sapphire, defects cannot be eliminated because of the lattice mismatch between a-Ga₂O₃ and sapphire. The key is how to reduce the defects formed in a-Ga₂O₃. In this presentation, we report our efforts to control the defects by growth conditions, buffer layers, and epitaxial lateral overgrowth (ELO).

We have reported that a-Ga₂O₃ is grown on sapphire substrates by the mist CVD method below 500^oC. The growth and/or annealing at higher temperature resulted in formation of b-phase which is the thermally stable one. Under this growth condition, an a-Ga₂O₃ layer has been suffered from the defects of the order of 10¹⁰ cm^-2 [2]. As a method to reduce the defects, we proposed the insertion of quasi-alloy buffer layers, resulting the defect density to the order of 10⁸ cm^-2 [3]. The a-Ga₂O₃ layer fabricated on the buffer layer was thermally stable for the thermal annealing at 650^oC. This means that the reduction of defects is effective to stabilize the a-phase. With the use of GaCl₃, instead of gallium acetylacetonate with which a-Ga₂O₃ had been grown only below 500^oC, a-Ga₂O₃ was formed at the temperature at as high as 800^oC. The high temperature growth is desirable for reducing defects because of the enhanced migration of precursors on the underlying surface. ELO is a promising technology for reducing dislocation defects markedly. With the SiO₂ masks, we confirmed the lateral growth on the masks. We are continuing to characterize the behavior of defects in detail and the results will be shown at the meeting.

This work was supported in part by the Advanced Research Program on Energy and Environmental Technologies of NEDO.

[1] K. Kaneko et al., 232nd Electrochem. Soc. Meeting, National Harbor, USA, 2017 #1155.
[2] K. Kaneko et al., Jpn. J. Appl. Phys. 020201 (2012).
[3] R. Jinno et al., Appl. Phys. Express 9, 071101 (2016).

Plasma etching, a commonly used method for the patterning of III-V materials for electronic and optoelectronic devices, is known to induce defects. These defects and the associated strain modify the material band structure, which may in turn impact device performance and stability. Plasma induced defects have been extensively studied on blanket substrates, much less on pattern sidewalls.
We have developed a battery of tools and methods for the three-dimensional characterization of patterns. Atomic force microscopy (AFM) on a tilted sample enables the measurement of line edge roughness (LER) at all heights along sidewalls with a resolution in the nanometer range, while auger electron spectroscopy (AES) provides information about surface chemistry. Based upon the work of Cassidy on polarized photoluminescence, we have also developed a polarized cathodoluminescence technique to measure strain anisotropy in the surface plane with a much improved resolution (around 100 nm). These measurements are enabled by the specific configuration of our Attolight instrument, which does not include a fiber optics connection. To our knowledge, no previous work on polarized cathodoluminescence for strain measurement has been reported. By combining the obtained in plane strain anisotropy with the global strain derived from the energy shift of the emission, we are able to extract the strains in the directions across patterns and perpendicular to the wafer. Cathodoluminescence is also used to measure emission intensity.
These techniques, and others, are applied to InP lines, in order to correlate the luminescence intensity with the observed strain and LER, as well as structural and chemical modifications. To evaluate the influence of plasma conditions, two chemistries and two temperatures are selected: Cl₂ / CH₄ and CH₄ / H₂ at 100°C and 200°C. To evaluate the influence of the edge roughness, two masking strategies are used, leading to LER of 6 to 12 nm. To evaluate the total impacted depth, 1, 3 and 6 μm wide lines are patterned. Damage depth is assessed by wet etching the patterns in H₂O₂ / HCl and/or annealing them at 350°C to recrystallize in volume.
Within an InP line, we observe a compressive strain in the direction across the line and a tensile strain in the direction perpendicular to the wafer, both extending about 2 μm from the edges. These measurements are compared to those obtained by μRaman spectroscopy and X-Ray diffraction, and correlated to structural defects observed by TEM and chemical modifications obtained by AES.
In conclusion, we have developed a series of tools, including AFM and AES on a tilted sample, to characterize patterned sidewalls. We have also developed a new high resolution strain measurement technique based upon cathodoluminescence. These techniques, and others, were used to understand the modifications induced by patterning in InP structures, with the aim of improving plasma parameters and ultimately device performance and stability.

In this study, on one hand, we present our theoretical analysis of III-N photonic waveguides at visible spectral wavelength. Due to the n-type conductivity and high dislocation density inside GaN, free carrier absorption contributes significant amount of loss when waveguide scale is on order of microns. Moreover, at high power density operation, two photon absorption loss dominates in GaN waveguide. However, for AlN waveguide, the optical loss is still contributed from sidewall scattering. The theoretical analysis may guide the design of III-N waveguide for wide range of applications.
On the other hand, we developed a fabrication process for GaN and AlN waveguide on sapphire substrate and did a comprehensive study on the process to minimize the optical loss. Samples in this work are all grown by metal-organic chemical vapor deposition (MOCVD) Different types of masks for this process (Photoresist, Cr/SiO2, Cr/SiNx, Cr, Ni) are investigated and our results show that Cr/SiO2 and Cr hardmasks are good for GaN/AlN waveguide fabrication when using electron beam lithography (EBL). Inductively coupled plasma (ICP) etching parameters are optimized to minimize sidewall roughness. Scanning electron microscope (SEM) is used to justify the surface morphology for different etching recipes. 500/70W ICP/Platen power at 5mT pressure with 30/8/5 sccm Cl2/BCl3/Ar2 etching chemistry is found to be good for GaN etching, while for AlN, 400/180W ICP/Platen power at 2mT pressure with 30/8/5 sccm Cl2/BCl3/Ar2 etching chemistry is found to be good for etching. The low pressure and high platen power for AlN etching recipe is to enhance the ion directionality in order to break chemical bonds efficiently.
To minimize sidewall roughness, Tetramethylammonium hydroxide (TMAH) wet etching post treatment is implemented. SEM images show that the chemical wet etching process behaves totally different for low temperture (buffer layer) and high temperture grown III-N layers. SEM imags also indicate that wet etching has different impact on straight and curved sidwalls.
To remove mask, buffered HF and diluted HCl are used for SiO2 and Cl hardmasks, respectively, while for photoresis, the mask is removed by O2 plamsa and acetone. The HF is found to cause surface erosion on AlN which is also observed in sputtered AlN. Edge polishing is performed to increase coupling efficiency after the whole process.
Using the process developed in this research, low loss GaN waveguides are fabricated at the height of 1.5 um and width varies from 1.2 to 2 um. Testing is performed using a Ti:S laser at 800 nm and 720 nm. Our characterization shows that 70% of the waveguide exhibits optical loss <10dB/cm, 20% of waveguides show low loss <2dB/cm. The lowest loss obtained in this work is less than 1dB/cm, which is the lowest loss to the best of our knowledge on GaN waveguide. We will also discuss the pathway to improve the fabrication process. We hope our works bring valuable information to the society.

Aluminum gallium nitride (AlGaN) is a promising material system in the application for deep ultraviolet LEDs, power electronics, and piezoelectric devices. Due to the large polarization electric field along c axis, novel heteropolar devices making use of polarity inversion are expected to be realized. For example, quasi phase-matching wavelength converters and film bulk acoustic resonators have been reported. In the case of polarity inversion by crystal growth, N polar surface tends to be rough owing to the severe growth condition. Recently, polarity inversion by direct wafer bonding is receiving increased attention as an alternative. This approach enables realization of heteropolar films with high crystallinity. Additionally, heterogeneous material integration is possible even if a large lattice mismatch exists. In this paper, we report the direct bonding of 2-inch sputtered AlN wafers with the use of nitrogen plasma activation.
The fabrication starts with the preparation of a pair of 2-inch AlN wafers by sputtering an AlN target onto vicinal c-plane sapphire substrates. The sputtering conditions were an RF power of 700 W, a chamber temperature of 600 °C, and an AlN thickness of 200 nm. The AlN sample for this bonding experiment showed a root mean square surface roughness of 0.6 nm and curvature of 12 km^-1. Subsequently, the +c-oriented sputtered AlN wafers were directly bonded by using N₂ plasma activation. Plasma irradiation conditions were an RF power of 500W, a chamber pressure of 120 Pa, and an irradiation time of 50 s. Then the wafers were brought into contact for the temporary bonding. With a load application of 300 kgf, the temperature of annealing stage was ramped up from RT to 400 °C through 3 h. Subsequently, the stage temperature was held at 400 °C for 6 h in order to form the strong bond at the AlN/AlN interface. Despite the curvature of AlN, almost whole area of the 2-inch wafer was successfully bonded. Longer annealing time was found to be effective because the wafer did not bond at the near-edge section in the case of an annealing time of an hour. This result suggests the effectiveness of direct bonding approach for heteropolar device application in III-N material system. In the future, the combination of plasma activated bonding and high-crystallinity AlN will be the next target for device applications. We have already reported significant improvement in crystallinity of sputtered AlN by high temperature annealing at 1700 °C. This approach markedly decreased FWHM of X-ray rocking curve in (10-12) from 6031 arcsec to 287 arcsec. If the curvature of 89 km^-1 caused by annealing is managed well, novel device applications can be realized.

Nano-Bonding™ [1] consists of direct molecular cross-bonding between two surfaces at the nanoscale over a wafer area. This can occur if surfaces are planarized to make full contact at the macro-, micro-, and nano-scale. Wafer warping, typically a 25-60 microns of vertical displacement across the wafer focal plane has to be eliminated. At the micro-scale, surfaces need to be planar over micron lengths. At the nano-scale, atomic terraces need to extend over tens of nm so atomic steps are spread far apart.

With planarization, direct cross-bonding occur with direct exchange of electrons between the two surfaces without an adhesive or bonding phase. Nano-Bonding™ between heterogeneous semiconductor surfaces can create more efficient solar cells and integrate, optical and electronic devices into monolithic devices.

Nano-Bonding™ of GaAs(100) to Si(100) is conducted at near atmospheric pressure in air without the use of plasma activation or ultra high vacuum conditions.

Three Liquid Contact Angle Analysis (3LCAA) measures the surface energies of the GaAs(100) and the Si(100) surfaces to bond. Initial native oxides GaAs(100) are hydrophobic with an surface energy of 37.7 ± 1.7 mJ/m². GaAs(100) is prepared into a hydrophilic surface with an energy of 65.4 ± 1.4 mJ/m². Si(100) is processed to undergo an opposite transition Si(100) native oxides initially exhibit a hydrophilic surface with an energy of 52.7 ± 1.4 mJ/m². Si(100) is then made hydrophobic with a surface energy of 48.2 ± 1.0 mJ/m².

Ion Beam Analysis (IBA) evaluates the effect of surface preparation of GaAs(100) and Si(100). Oxygen Nuclear Resonance combined with MeV Ion Channeling allows for detection of oxygen and displaced GaAs and Si atoms in oxides before and after surface preparation. GaAs(100) hydrophobic native oxides contain about 30% Arsenic oxide and 60% Gallium oxide. After surface preparation, IBA detects an Arsenic-terminated surface with a layer of Gallium beneath.

In a set of identical experiments using seven pairs of 4” wafers, following native oxide removal and surface preparation, hydrophilic GaAs(100)/hydrophobic Si(100) pairs are Nano-Bonded™ at near atmosphere at temperatures of T < 200°C with a 57% success rate, measured via Confocal Scanning Acoustic Microscopy (C-SAM) imaging. An improved coverage of bonded area is anticipated once modification to equipment is performed. Bonded regions near atmosphere correspond to regions of compression during the Nano-Bonding™ process but can extend beyond. Finally, Transmission Electron Microscopy (TEM) imaging is used to examine the quality of GaAs/Si Nano-Bonded™ interface.

[1] Herbots et al. US Patent 9,018,077 (2015); 9,589,801 (2017).
[2] Herbots et al. US Patents Pending (2017)