Symposium EP01 : Materials for Beyond the Roadmap Devices in Logic, Memory and Power

Among high mobility channel materials, germanium is a unique candidate which offers both high hole and electron mobilities required for future CMOS. Forming a high-quality MOS interface is mandatory to bring out the full potential of Ge, while maintaining sufficient gate stack reliability is also compulsory on real devices. Recent reliability studies on Ge gate stack pointed out that the BTI of GeO₂-based gate stack is a serious concern, while the use of Si-passivation layer on Ge shows potential to satisfy the reliability requirements [1]. An epitaxial grown Si passivation layer enables the use of a similar high-k/SiO₂ gate stack, which has been intensively studied on Si devices. The presence of an SiO₂ interface layer also makes band engineering possible by forming an interface dipole at the high-k/SiO₂ interface [2]. On Ge pFETs, high hole mobility and superior NBTI reliability has been successfully demonstrated using a Si passivation layer [3]. In contrast, it is more challenging to achieve low Dit [4] and superior gate stack reliability on Ge nFET [5], even with a Si passivation layer. This presentation describes a way to achieve low Dit (5x10¹⁰ cm^-2eV^-1 around mid-gap) and superior gate stack reliability (effective oxide trap density of low x10⁸ cm^-2 at Eox=3.5 MV/cm) by using a Si-cap layer. While thinning down the Si-cap layer to an optimum thickness reduces Dit and improves electron mobility, while it increases the effective oxide trap density and degrades reliability because of the quantization in Si-cap layer and/or increase in the amount of Ge in the SiO₂ interface layer [6]. To improve the gate stack reliability, La- or Mg-induced interface dipole is formed at the HfO₂/SiO₂ interface by inserting a thin ALD cap layer [7]. The interface dipole energetically decouples the electron traps in the high-k and the channel electrons, resulting in smaller V_TH or V_FB shift. Insertion of ALD LaSiO or MgOx is found to also suppress intermixing between HfO₂ and SiO₂, resulting in a 2-3x Dit reduction. Significant further Dit reduction is demonstrated by performing high-pressure anneal (HPA) in H₂, lowering the Dit level down to 5x10¹⁰ cm^-2eV^-1 (1/20x) around mid-gap. Additionally, this presentation will also discuss EOT scalability and V_TH tunability on Si-passivated Ge nMOS gate stack.

[1] J. Franco et al., IEDM 2013, p. 397.
[2] Y. Yamamoto et al., JJAP 46, p. 7251 (2007).
[3] J. Mitard et al., VLSI 2014, p. 34.
[4] C. H. Lee et al., IEDM 2010, p. 416.
[5] H. Arimura et al., IEDM 2015, p. 588.
[6] P. Ren et al., VLSI 2016, p. 32.
[7] H. Arimura et al., IEDM 2016, p. 834.

The use of high mobility SiGe channels in CMOS technology has been impeded by the presence of a high interface defect density between the SiGe and oxide layers. Ge-O_x suboxide bonds at the interface are the main source of these defects. By selectively forming Si-O_x bonds or suppressing formation of Ge-O_x bonds, the interface defect density can be minimized. The higher heat of formation of SiO_x compared with GeO_x can be used to selectively remove GeO_x using an oxygen scavenging metal as the MOSCAP gate metal [1,2]. Previously, Al gate metal has been demonstrated as reducing D_it for Al₂O₃. In the present work, Al gate metal is used to attain an even lower D_it using HfO₂ as the oxide and an optimized forming gas anneal. In this work, thermally deposited aluminum was used as an oxygen scavenging gate metal to achieve an ultra-low defect density of 3x10¹¹ eV^-1cm^-2 on ALD deposited Al₂O₃ and HfO₂ oxides on Si_0.3Ge_0.7(100). Aluminum gate metal MOSCAPs were also shown to have an order of magnitude lower leakage current than nickel gate MOSCAPS sweeping from -2 to 2 V_g. Ni gated MOSCAP showed a higher maximum capacitance (2.1 μF/cm²) in comparison with Al gated MOSCAPs (1.5 μF/cm²) due to the growth of Al₂O₃ during oxygen scavenging. STEM-EDS and EELS results confirm the oxygen scavenging mechanism by showing a silicon rich, sub 5Å thick SiGe-oxide interface.

References
[1] Kim, H., McIntyre, P. C., Chui, C. O., Saraswat, K. C. & Stemmer, S. Engineering chemically abrupt high-k metal oxide/silicon interfaces using an oxygen-gettering metal overlayer. J. Appl. Phys. 96, 3467–3472 (2004).
[2] Liu, C. W., Östling, M. & Hannon, J. B. New materials for post-Si computing. MRS Bull. 39, 658–662 (2014).

The high mobility semiconductor Ge is limited by the high resistance of its n-type contacts due to the Fermi level pinning (FLP) of Schottky barriers (SBs) close to the valence band maximum (VBM). It turns out that this pinning occurs only for SBs of elemental metals whereas the compound metals like germanides and silicides have a different experimental behavior [1]. This ‘extrinsic behavior’ in which the Schottky pinning factor, S, depends on both metal and semiconductor facet is potentially very useful and can be exploited to reduce the large n-Ge SBH. We studied this SBH effect using density functional supercell calculations. The S factor is found to vary from 0.5 to 0.3 for silicides on Si(100) to Si (111), and to 0.3 to 0.2 for germanides on Ge(100) to Ge(111), with also a strong dependence of the effective charge neutrality level’ on the facet. This behaviour is found to be consistent with early experimental results for Si(100) and Si(111) of Tung [2]. Interestingly, it contradicts some later experimental data for Ge [3], however the ability to make abrupt epitaxial Ge/germanide interfaces is much more difficult for the germanide system than for silicides [3], and it is proposed that the calculated germanide results are used as guidance for the Ge system.
[1] T Nishimura, T Yajima, A Toriumi, APX 9 085201 (2016)
[2] R Tung, JVST B 11 1546 (1993)
[3] P S Y Lim, Y C Yeo, APL 101 172103 (2012); Y Deng, S Zaima, Thin Solid films 557 84 (2014)

Future electronic systems may employ monolithic or heterogeneous integration of various material systems such as III-V, Ge, and Si to sustain the historical trend of performance enhancement of metal-oxide-semiconductor field-effect transistors (MOSFETs) for high performance and low power logic applications and to enable hybrid circuits consisting of nano-electronic and photonic devices on the Si platform.
In this paper, we present our recent research advances in heterogeneous integration of III-V and Ge-based devices on the Si substrate. In the first part, we discuss the application of the interfacial misfit (IMF) technique which is capable of relieving strain resulting from the large lattice mismatch between two materials and minimizing the formation of threading dislocations. A very thin buffer with sub-120 nm was used prior to the growth of the high-quality channel materials with this technique. Two integration schemes will be covered including the co-integration of vertically-stacked nanowire GaSb p-channel FETs (pFETs) and InAs n-channel FETs (nFETs) as well as the co-integration of Ge pFETs and InAs nFETs on Si substrates using common contact formation, digital etch, and gate stack formation modules. In the second part, we discuss our research effort to enable large-scale monolithic integration of opto-electronic devices for low cost and multi-functional opto-electronic integrated chips (OEICs). The monolithically integrated InGaAs FETs and GaAs/AlGaAs lasers on a Si substrate will be presented. The high-quality layers for the realization of InGaAs transistors and lasers were grown using molecular beam epitaxy (MBE) on a Si substrate using Ge and GaAs buffer layers. The InGaAs FETs show good electrical characteristics with high drive current, high I_ON/I_OFF ratio, and small subthreshold swing. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers were also realized at room temperature with a spectral linewidth of less than 0.5 nm.

Tunnel Field Effect Transistors have the potential to reduce the power consumption in logic operating at very low off-state current levels and at moderate switching speed. Key metrics include a high on-state current with a high I_on/I_off-ratio that needs to be combined with a low hysteresis. A low subthreshold slope combined with a high transconductance are needed to meet these requirements.
III-V nanowire Tunnel Field-Effect Transistors have demonstrated hysteresis-free operation of 48 mV dec with a I_on of 10 µA/µm for V_gs=0.3 V. Statistical analysis of a large number of transistors with subthermal operation show that the subthreshold slope mainly is limiting I_on for low V_ds (0.1) while g_m is limiting for higher V_ds (0.3V). Enhancing the transistor performance is thus not only related to the subthreshold slope, but also the on-state performance is critical. III-V heterostructures offers an excellent opportunity based on the wide range of the combinations possible.
The understanding of how different defects contribute to the measured I-V characteristics is essential to identify routes to improve the performance. Bulk traps, interface states, and oxide defects all contribute in different ways, as well as the possible contribution from gap states formed around the band edges. The different contributions may be quantified by careful I-V spectroscopy, demonstrating that such defects can be controlled on a sufficient level for advantageous Tunnel Field-Effect operation.
This work is supported by the Swedish Foundation for Strategic Research and the Swedish Research Council.

The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. We combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS₂) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 μA/μm, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS₂ negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied. In this talk, we will review the experimental progress at Purdue University on MoS₂ n-type 2D NC-FETs, WSe₂ p-type 2D NC-FETs, and nano-membrane β-Ga₂O₃ NC-FETs for wide bandgap CMOS applications.

Advanced logic CMOS devices require aggressive shrinking for performance and cost. Among many parameters to be scaled, it is particularly difficult to achieve the lowest threshold voltage (Vt) for p-FET (Field Effect Transistors) devices because of higher process sensitivity due to Fermi-level pinning and oxygen out-diffusion at high-k metal gate stacks. These challenges demand work function engineering for the future technologies. For reducing P-FET Vt, increasing the effective work function (EWF) can be one solution. There have been reports that oxygen has the property to boost the work function of the metals such as titanium silicon nitride, molybdenum and tantalum carbide [1-3].
In this paper, we demonstrate a method to reduce the p-FET Vt without the penalties associated with typical gate stack processing. We selected a Transition Metal Composite (here after, Metal-A) having a p-band edge work function as the metal gate for p-FET. Metal-A is deposited using Atomic Layer Deposition (ALD) on high-k dielectric layers, and also it is carefully treated using a modified oxidation method. Measurements from fully integrated advanced transistors showed around 80 mv of Vt modulation without degradation of the inversion thickness (T_inv), which means no increase of equivalent oxide thickness (EOT) through the modified oxidation.
For further understanding of the oxidation effect on EWF (Effective Work Function) change, ab-initio investigation was performed using stacks of Metal-A on a High-K layer (here, Hafnium oxide, HfO₂ was chosen as a general material). We computed the EWF from the interface dipole and the vacuum work function of the metal, which can eliminate the need to compute the band offsets. Thus, it avoids the errors introduced in the band structure and the valence band offset calculations.
By comparing EWF values computed for a defect-free-reference against EWF values for the same reference containing oxygen defects at or near the HfO₂/Metal-A interface, we found that the presence of oxygen vacancies (Vo) and oxygen interstitials (Oi) plays a big role in modulating the interface dipole. Furthermore, when oxygen interstitials are incorporated in the bulk Metal-A, the resulting EWF is substantially higher. Based on the simulation, we explain the physical mechanism of EWF modulation (accordingly, Vt modulation) obtained in the above experiments: (1) the oxygen atoms diffused from Metal-A replace Vo in high-k layer and also modify the dipole configuration and (2) the residual oxygen interstitials in the Metal-A also increase the bulk EWF value. These results clearly demonstrate the possibility of EWF engineering towards the p-FET band edge in advanced FETs through the proposed modified oxidation method.
[1] H. Luan, et.al., App. Phys. Lett, vol. 88, p. 142113, 2006.
[2] Z. Li, et. al., J. Electrochem. Soc., vol. 155 pp. H481-H484, 2008.
[3] W. Mizubayashi, et. al., VLSI Technology, 2008 Symposium on pp. 42-43, 2008.

We report the depletion of silicon dopants at the surface of epitaxially grown in-situ doped InAs layers. The lower concentration of Si doping at the surface is technologically significant as it leads to increase in contact resistance.
The depletion of Si was observed in metal-organic chemical vapor deposition (MOCVD) grown Si doped InAs layers as well as in InAs layers grown by atomic layer epitaxy (ALE). In situ doping was employed to make InAs layers with [Si] concentration from 2E18 to 8E19 cm^-3.
Secondary ion mass spectrometry (SIMS) was used to study the Si profile in the Si doped InAs layers. It was found that the silicon depletion was larger for higher doping levels of Si in the bulk of the InAs layer. The Si depletion extends to about 5 nm from the InAs surface. We have employed Ultra-Low Energy (ULE-) SIMS (250 – 400 eV Cs+ ion impact energy) to demonstrate that the Si depletion width extends well beyond the InAs native oxide thickness and SIMS surface transient depth.
The top 8 nm of the InAs layers were controllably etched by self-limited digital etching to remove the Si depleted region. The SIMS Si profile of etched InAs does not exhibit Si depletion, thus suggesting that depletion of Si atoms near the surface takes place during the layer growth.
Co-doping the InAs layer with silicon and zinc (a p-type dopant) did not change the Si depletion profile near the surface. This suggests that the depletion of the silicon atoms near the surface is not a result of an electrical field induced by surface pinning [1].

References:
1. E. F. Schubert, Doping in III-V Semiconductors, Cambridge university press, 1993.

An attractive approach to realizing enhancement-mode (E-mode) GaN-based lateral heterojunction power transistors is to recess the barrier layer under the gate electrode, and thus remove the inherent positive polarization charges to obtain positive threshold voltage V_TH [1]. To suppress the gate leakage, the barrier layer should be replaced by insulating gate dielectric, forming a fully recessed MIS-FET or partially recessed MIS-HEMT. High electron mobility in the gate-controlled channel is maintained in MIS-HEMT with a thin barrier layer. However, the manufacturing of MIS-HEMT faces challenge in V_TH uniformity control due to difficulties in precisely controlling the recess etching depth. In addition, the buried-channel MIS-HEMT typically exhibits worse V_TH thermal stability than the surface-channel MIS-FET [4] as a result of the floating dielectric/AlGaN interface. Thus, the E-mode fully recessed MIS-FET possesses practical benefits in terms of manufacturing capability and device stability.
Obtaining high-quality interface with low D_it is one of the most critical challenges in MIS-gate. According to a first-principles calculation study, the GaN surface states distribution can be modified by nitridation with the shallow trap (i.e. close to E_C) density greatly reduced [2]. Interface protection is another technique to prevent the GaN surface from degradation at high temperatures (~ 800 ^oC) [3] at which high-quality gate dielectric is deposited. The high temperature is necessary to obtain a densified dielectric film with reduced defect density. With these techniques, SiN_x gate dielectric (with the benefits of large conduction band offset of ~2.3 eV with GaN and relatively high dielectric constant of 7) deposited at 780 ^oC by LPCVD (low pressure chemical vapor deposition) is successfully integrated with recessed-gate structure to obtain E-mode MIS-HEMT/FET with enhanced V_TH stability and gate dielectric reliability.
Both MIS-FETs and MIS-HEMTs exhibit small hysteresis △V_TH < 0.1 V and low subthreshold swing SS ~ 97 mV/dec, benefiting from the greatly improved interface quality. As fully-recessed gate can reduce the sensitivity of V_TH on the recess depth, higher V_TH uniformity is obtained in MIS-FET. The MIS-FET also has more positive V_TH (~2.4 V) than MIS-HEMT (~0.4 V). R_ON of MIS-FET (~13 Ω●mm) is slightly larger than that of the MIS-HEMT (~10 Ω●mm) due to lower MIS-channel electron mobility. The MIS-FET has a much better V_TH stability than the MIS-HEMT, benefiting from the limited movement of E_F at dielectric/GaN interface. In addition to thermal stability, the V_TH of MIS-FET also shows better stability in long time NBTI stress.
In summary, surface nitridation and interface protection play critical roles in enabling a high-quality dielectric/III-N interface with low D_it. The fully recessed MIS-FET possesses many advantages in larger recess-depth tolerance, more possitive V_TH, and higher V_TH stability.

Silicon germanium (SiGe) channels are being developed for CMOS technology due to their high intrinsic carrier mobility. The superior properties of SiGe can be utilized only if SiGe-high k interfaces with a low interface defect density (D_it) can be fabricated. Germanium oxide (GeO_x) is known to be the source of interface defects and by selective reduction, selective removal of GeO_x, or selective formation of interfacial silicon oxide (SiO_x), low-defect interfaces can be formed. Previously, ozone has been employed to form a GeO₂ rich interlayer on high Ge content SiGe to passivate the interface (1). In this work, a new method, selective oxidation with ozone nano laminate, was employed; in this method, ozone pulses are dispersed evenly within the HfO₂ during ALD HfO₂ deposition. Optimized ozone pulsing between 5nm thick HfO₂ oxide layers reduced the defect density by 60% compared to standard HfO₂ ALD on the same samples. With the ozone nanolaminate and optimized forming gas anneal, an interface defect density of D_it=5x10¹¹ eV^-1cm² with accumulation capacitance of 1.75uF/cm² was demonstrated for the HfO₂/Si_0.7Ge_0.3 interface. The distribution of the defect density across the band gap was calculated according to full interface state model and integrated Dit of <1x10¹¹ eV^-1cm² was obtained. High resolution STEM images shows thin interface and Si enriched composition compared to the bulk was observed in STEM-EELS and EDS analysis. The data demonstrates that dry selective oxidation can be used to form the SiOx layer required to passivate Si_0.7Ge_0.3(001).

References
Ando et al, IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 3, MARCH 2017

In recent years, much effort has been made to find alternative materials and geometries to achieve ultra-small stable electronic devices. Among all, high electron mobility transistors (HEMTs) are very promising in terms of both high carrier mobility and high breakdown voltage. However, the commonly used AlGaN/GaN interface still shows limitations, such as high defect concentrations and gate leakage, that need to be overcome. For this reason, the exploration of novel ternary and quaternary nitrides, as well as the engineering of their lattice parameters, band gaps and their relationship, have been encouraged.
Transition metal nitrides (TMN) have recently received increasing attention due to their unique electronic and structural properties [1]. The optoelectronic properties of Sc_xGa_1-xN are very interesting for HEMTs: ScN and GaN are stable in two different structures, therefore, as x increases from 0 (GaN) to 0.5 (Sc_0.5Ga_0.5N) the wurtzite structure distorts, the c/a ratio decreases, eventually producing a structural phase transition to a non-polar 5-fold coordinated hexagonal crystal structure. In the composition range around this phase transition, Sc_xGa_1-xN shows unique properties, such as huge piezoelectric constant, high electron mobility, and good lattice match with GaN.
Another interesting TMN material for electronic application is FeGaN [2]. If GaN is doped with small concentration of iron, the thin film shows semi-insulating properties with high quality structure and high resistivity. When FeGaN is employed in HEMTs, its semi-insulating behaviour will better isolate the device by lowering the leakage from both the gate and the substrate interfaces.
In addition, the quaternary material FeScGaN is expected to show intermediate properties between the two ternary TMN materials. Thus, if it is employed in ScGaN/GaN HEMTs, the gate leakage will decrease without introducing lattice-mismatch defects at the FeScGaN/ScGaN interface.
To successfully employ these novel materials in HEMT devices, it is then necessary to achieve deep knowledge of both their electronic and structural properties. For this reason, ScGaN, FeGaN and FeScGaN thin films are grown on sapphire using Electron Beam Epitaxy technique and then fully characterized. HR-TEM, STEM, XRD are used to explore the change in the microstructure of all the thin films for different TM content. SIMS is employed to calculate both the TM element content and the level of impurities in each film. Finally, the electron mobility, band gap and Raman shift are reported to investigate the electronic and optical properties of these materials and their dependence on the TM concentration.
These TMNs show high-quality crystal structures and larger band gap for higher TM content; from these preliminary results ScGaN, FeGaN and FeScGaN seem to be promising materials for enhanced electronic devices.

[1] M.A. Moram S. Zhang, J Mater Chem A, 2014,2, 6042-6050
[2] A. Bonanni, Semicond Sci Technol, 2007, 22, R41-R56

Introduction
The effect of the annealing temperature on the perpendicular magnetic anisotropy (PMA) of composite structures was studied. We merged a MgO/CoFeB bilayer [1] and an ultra-thin [Co/Pd]6 multilayer separated by a non-magnetic Ta spacer [2] of variable thickness tTa. Composite magnetic structures with PMA are technologically relevant in developing high-density memory devices.
Experimental Procedure
The stacks were deposited using magnetron sputtering at room temperature in the absence of an external magnetic field. Thermally oxidized (100) Si wafers were used as substrates. After deposition, samples were heat-treated for 2 hrs. at 250, 300, or 350 C in a high-vacuum magnetic annealing oven with a field of 5 kOe perpendicular to the film plane. Magnetic properties were studied by using an alternating gradient magnetometer (AGM) where magnetization vs. applied
magnetic field (M-H) hysteresis loops were obtained with either out-of-plane or in-plane magnetic fields.
Results
Hysteresis loops show sharp switching characteristics indicating ferromagnetic coupling between the MgO/CoFeB bilayer and the Co/Pd multilayers. Structures lacking a Ta layer show not PMA regardless of whether or not they were magnetically annealed. PMA is obtained after inserting a Ta layer and is observed even in the as-prepared state [3].
Conclusions
Our results show that Ta layer is essential for obtaining perpendicular axis in the composite MgO/CoFeB/Ta/[Co/Pd]6 structure. Composite structures retain PMA upon magnetic annealing up to 350 C. The ferromagnetic exchange was strong enough to switch MgO/CoFeB and [Co/Pd]6 together, with the magnetic moment either lying along the film plane when tTa = 0, or pulled out of the film plane when tTa ≠ 0. No antiparallel magnetic coupling was observed within the Ta thickness interval explored (0 ≤ tTa ≤ 0.7 nm). Perpendicular composite structures with sharp magnetization reversal and annealing stability are relevant in perpendicular CoFeB-based magnetic tunnel junctions for the development of gigabit-scale nonvolatile memory.

Ultra-shallow junctions have become more desirable in the semiconductor industry as devices have continued to shrink in size and non-planar devices such as FinFETs and 3D nanostructures have become more common. Semiconductor devices are traditionally doped using a combination of ion implantation or spin-on dopant and thermal diffusion techniques; however, these have limitations such as crystalline damage, use of hazardous chemicals, or glassy skin formation. Monolayer doping (MLD) is an attractive alternative for forming sub-50 nm junctions. A dopant-containing compound forms a conformal self-assembled monolayer on the surface, then is capped with an insulating oxide and activation via rapid thermal anneal to form an ultra-shallow junction. The monolayers are formed with a phosphorous-containing compound for n-type doping, and a boron-containing compound for p-type doping. Techniques such as SIMS and sheet resistance measurements are used to characterize junctions and doping profiles. P+N and N+P diodes are fabricated and characterized. An in-house process for fabricating MOSFETs utilizing MLD for source/drain doping is developed. Electrical data on sub-50 nm emitter diodes and MOSFETs will be presented.

Ferroelectric Zr doped in HfO₂ as gate stack has been intensively and extensively investigated to integrate with FETs due to following current CMOS architectures and feasibility ALD (atomic layer deposition) supercycle approach [1][2]. The bi-stable state feature of hysteresis loops by ferroelectric materials satisfies the demands of voltage amplification concept for negative capacitance (NC) [3][4] and storage signal purpose for memory [5].
The discussion about NC reliability with sub-2.3k_bT/q SS and wake-up effect is demonstrated. The ferroelectric (FE) coercive voltage for dipole switching is effectively reduced to a practicable NC onset voltage (<1V) after wake-up. This is one of ferroelectric characteristics for complete dipole switching beyond coercive voltage [6]. In order to observe this phenomenon of NC-FETs, the 5nm FE-HZO FETs are performed double sweep with the range from small to large. In order to reach the FE/NC region, the applied voltage needs high enough for complete dipole switching, and coercive E-field approaches to 2MV/cm. A gradual transition of ferroelectricity with crystallization temperature increasing results in subthreshold swing (SS) < 60mV/dec and hysteresis loop formation. The device by gate-last is more stable than that of gate-first due to well Source/Drain activation. It is promising to use ultra-thin FE-HZO as the guidelines for NC and memory applications. To develop a practicable FE-coercive/NC-onset voltage is an important issue for evaluating this technology.
The authors are grateful for the funding support from the National Science Council (MOST 105-2628-E-003-002-MY3, 106-2221-E-003-029-MY3 & 106-2622-8-002-001), process supported by National Nano Device Laboratories (NDL) & Nano Facility Center (NFC), Taiwan.
Reference:
[1] M. H. Lee et al, IEEE J. of the Electron Device Society, vol. 3, no. 4, pp. 377-381, 2015.
[2] M. H. Lee et al, IEEE Electron Device Letter, vol. 36, no. 4, pp. 294-296, 2015.
[3] S. Salahuddin and S. Datta, NanoLetters, vol. 8, no. 2, pp. 405-410, 2008.
[4] S. Salahuddin and S. Datta, in IEDM Tech. Dig., 2008, pp. 693-696.
[5] J. Müller et al, in Symp. on VLSI Technology and Circuits, 2012, pp. 25-26.
[6] P. Sharma et al, in Symp. on VLSI Technology and Circuits, 2017, pp. T154-T155.

In the continuous scaling down of the device for logic circuits, germanium has been considered as a candidate for high performance logic device because of its high mobility. [1,2] However, one of the most difficult challenge in realizing high performance device on germanium is the reduction of source/drain (S/D) resistance because of its low dopant solubility. [3] The use of the shallow metal S/D is a likely way to solve this limitation. The research of germanide/germanium Schottky junction has been popular in recent years. [4] In this paper, we propose a simple, novel and reliable technique to modulate the barrier height of NiGe/n-Ge contact formed by microwave annealing (MWA) with capping another pure metal on top of NiGe. [5,6] The physical and electrical properties of capping metals on NiGe/n-Ge Schottky junctions will be discussed by depositing various work function metals (Al (4.26 eV), Ti (4.33 eV), Ni (5.15 eV) and Pt (5.65 eV)) [7,8] as capping metals.
After DHF cleaning on (100)-oriented n-type Ge substrate, the 10-nm-thick Ni was deposited by physical vapor deposition (PVD). Next, MWA (5.8 GHz, 600W, in N₂ ambient, for 150 s) was performed for NiGe alloy formation. The X-ray diffraction (XRD) pattern shows that NiGe was the only phase formed by MWA. The transmission electron microscopy (TEM) figure shows that the 10-nm-thick Ni was consumed completely and transformed into a smooth and 20-nm-thick NiGe was formed by MWA. And the energy dispersive spectroscopy (EDS) analysis is consistent with XRD pattern on NiGe composition. Afterwards, various 100-nm-thick metals with different work function were deposited by PVD including Al, Ti, Ni and Pt.
Upon completion of the process mentioned above, we obtained NiGe Schottky junctions with various work function metals as capping metal. The first thing we want to mention is the ION/IOFF ratio. With different work function metals as capping metal including Al, Ti, Ni and Pt, the ION/IOFF ratio at +/- 1V are 2.89×10⁴, 6.50×10⁴, 9.12×10⁴ and 1.31×10⁵ respectively. Furthermore, we obtain the difference of Schottky barrier height (SBH) from 0.570 eV to 0.591 eV between Al and Pt as capping metal. These two results indicate that with different work function metals as capping layer, we can modulate the SBH of NiGe/n-Ge junction so that we can improve the ION/IOFF ratio. The last thing we want to mention is the ideality factor. The ideality factors of Al, Ti, Ni and Pt as capping metal are 1.28, 1.21, 1.13 and 1.12 respectively indicating that the higher work function of capping metal is the more approaching-to-one ideality factor is. In conclusion, by choosing higher work function metal as capping metal on NiGe, we can improve the performances of the NiGe/n-Ge Schottky diode with higher on current, ION/IOFF ratio, lower leakage current and closer to one ideality factor by SBH modulation. This is simple, novel and suitable technique for fabricating high performance Schottky Ge pMOSFET.

Among the members of tin-chalcogenides family, the narrow-band semiconductor SnTe has recently emerged as a 3D crystalline topological insulator (TCI) exhibiting band inversion at the L point where certain crystalline symmetries allow the protection of robust topological states at the surface. We investigated the electronic band structures of pristine P-doped SnTe doped using density functional theory (DFT) calculations followed by synthesis. The substitution of a Sn vacancy by P maintained the intrinsic band inversion at the L point but the direct band gap reduced to 30 meV upon the incorporation of spin orbit coupling (SOC), which is relatively smaller than the experimentally observed band gap of pristine SnTe. The experimental methods for P-doped SnTe synthesis was based on the vapor-liquid-solid technique. The morphology of the synthesized crystals was exotic in the form of micro-needles, as a consequence, it led to the amplification of signal arising from the topological surface states due to the reduction of surface area to volume ratio. Moreover, the modified effective mass, lattice imperfection and related charge carrier conductivity acted as our motivation to implement them in Ferro-electric Field Effect Transistor (FeFET). The application of a cyclic potential resulted in an exceptionally large memory window of 3.1 V accompanied by a drastic current change within a certain potential range.

We present some recent results on the transient electron transport that occurs within bulk alloys of zinc-magnesium-oxide. These results are obtained using an ensemble semi-classical three-valley Monte Carlo simulation approach. Starting with steady-state electron transport simulations, we find that, for electric field strengths in excess of 180 kV/cm, that the steady-state electron drift velocity associated with these alloys exceeds that associated with bulk wurtzite gallium nitride. We also present evidence that suggests that the negative differential mobility exhibited by the velocity-field characteristic associated with alloys of zinc-magnesium-oxide is not related to transitions to the upper valleys. The transient electron transport that occurs within this alloy is then studied by examining how electrons, initially in thermal equilibrium, respond to the sudden application of a constant electric field. From these transient electron transport results, we conclude that for devices with dimensions smaller than 0.1 microns, gallium nitride based devices will offer the advantage, owing to their superior transient electron transport, while for devices with dimensions greater than 0.1 microns, electron devices based on alloys of zinc-magnesium-oxide will offer the advantage, owing to their superior high-field steady-state electron transport. The device implications of these results will be explored. Our results show that the Monte Carlo simulations of the materials response to the instant change of the electric field could be used for establishing the figures of merit for materials applications for short channel ultra high-speed semiconductor devices.

We study how electrons, initially in thermal equilibrium, drift under the action of an applied electric field within bulk wurtzite zinc oxide. We find that the optimal cut-off frequency ranges from around 50.3 GHz when the device thickness is set to 1000 nm to about 11.5 THz when the device thickness is set to 10 nm. These results suggest that zinc oxide holds great promise for future high-speed electron device applications.

Unlike graphene, the existence of bandgaps in transition metal dichalcogenides such as MoSe₂ offers an attractive possibility of using single layer MoSe₂ field-effect transistors (FETs) in low-power switching devices and photodetectors. Yet, the fabrication demands and the physics of MoSe₂, among other reasons, suggest that multilayer MoSe₂ may be more attractive than single layer MoSe₂ for FET applications in a thin-film transistor configuration. In this presentation, we explore the optoelectronic properties of bottom-gate multilayer MoSe₂ phototransistors fabricated on SiO₂/Si substrates with mechanically exfoliated flakes. Our MoSe₂ phototransistors exhibit decent field-effect mobilities (> 50 cm² V^-1 s^-1) and high on/off-current ratio (> 10⁶). For 650 nm incident laser, the device shows high photoresponsivity (> 500 A W^-1) , high detectivity (> 10¹¹ jones) and a fast response time (< 2 ms) at room temperature. These optoelectronic properties are better than those of MoSe₂ phototransistors reported in literature. These results demonstrate a compelling case of multilayer MoSe₂ phototransistors for applications in photodetectors.

Unlike graphene, the existence of direct bandgaps in transition metal dichalcogenides such as MoS₂ offers an attractive possibility of using single layer MoS₂ in optoelectronic devices. Because of the absence of dangling bonds in MoS₂, surface treatment such as ultraviolet-ozone (UV-O₃) treatment is necessary before the deposition of high-k dielectrics on MoS₂ to fabricate optoelectronic devices such as phototransistors. However, little interest has been given to the effect of UV-O₃ treatment on the optoelectronic properties of single layer MoS₂. In this presentation, we systematically investigate the effect of UV-O₃ treatment on the photoluminescence of mechanically exfoliated single layer MoS₂ flakes. We observe photoluminescence quenching in single layer MoS₂, accompanied by reduction and broading of MoS₂ Raman modes with increasing UV-O₃ treatment time. X-ray photoelectron spectroscopy confirms the formation of oxygen bonding. We demonstrate that the formation of oxygen bonding upon exposure to UV-O₃ treatment leads to a direct-to-indirect bandgap transition in single-layer MoS₂. These results also demonstrate the significant impact of UV-O₃ treatment on the optoelectronic properties of single layer MoS₂ suggesting the importance of using optimized process conditions.

Unlike graphene, the existence of direct bandgaps in transition metal dichalcogenides such as MoS₂ offers an attractive possibility of using single layer MoS₂ in transistors, sensors, optoelectronic devices, and flexible systems. Because of the absence of dangling bonds in MoS₂, surface treatment such as ultraviolet-ozone (UV-O₃) treatment is necessary before the deposition of high-k dielectrics on MoS₂ to fabricate various devices. However, little interest has been given to the effect of surface oxidation of single layer MoS₂ by UV-O₃ treatment. In this presentation, we systematically investigate the effect of UV-O₃ treatment on the monolayer MoS₂ thin films obtained by chemical vapor deposition (CVD). We observe photoluminescence quenching in monolayer MoS₂ thin films with increasing UV-O₃ treatment time. We also observe the reduction and broading of MoS₂ Raman modes with increasing UV-O₃ treatment time. X-ray photoelectron spectroscopy indicates the nature of oxygen bonding changes with increasing UV-O₃ treatment time. These results demonstrate the significant impact of surface oxidation by UV-O₃ treatment on monolayer MoS₂ thin films suggesting the importance of using optimized surface treatment conditions for device applications.

The introduction of III-V materials onto a Si-platform has been of tremendous interest for a very long time. III-V compound semiconductors high electron mobility and direct bandgap properties have been deemed to be the solution to the scaling problems in Si CMOS (complementary metal oxide semiconductor) transistor, through the use of high mobility channel and light emitting devices for optical interconnects. The application of such technology, however, is hindered by numerous issues. The considerable lattice mismatch between Si and high mobility III-V materials (i.e., (In)GaAs, InAs, GaSb, and InSb) and the lack of processes that are amiable to Si manufacturing environment for surface passivation, gate stack dielectric, and metal contacts schemes are some of them. Furthermore, as the substrate cost difference between III-V wafers and Si wafers is significant, a way to reuse and recycle the III-V substrates or create new III-V-on-Si substrates is needed.

In this work, a variety of solutions to bridge the lattice constant gap and to realize III-V CMOS and III-V laser on Si-based substrates will be highlighted. A combination of high-temperature annealing, migration enhanced epitaxy and buffer engineering techniques was developed on a Si-based substrate to minimise anti-phase boundary and threading dislocation defects. Two different buffer engineering were explored, an approximately 800nm-thick graded InAlAs buffer for lattice constant = InP lattice constant and a thinner interfacial misfit (IMF) buffer for lattice constants ≥ 6.0Å. The graded buffer approach was deployed to demonstrate InGaAs nFET and InGaAs n-FET monolithically integrated with AlGaAs/GaAs multiple quantum well laser on GeOI (germanium on insulator) substrate. Furthermore, the IMF sub-120 nm buffer approach allows integration of highly mismatch materials on GeOI substrate without having to go through a thick graded buffer process. This buffer technique alleviates some of the fabrication process challenges caused by the significant step height difference which exists where the graded buffer was used and allows a common gate stack formation processes to be developed. The use of IMF buffer enables demonstration of novel III-V (InAs) n-FET and (GaSb) p-FET or InAs n-FET and Ge p-FET monolithically integrated on the same Si-based substrate with excellent I_ON performance. Some III-V (InAs and InSb) and Ge(Sn) photodetectors grown on Si-based substrate operating at the mid-IR range will also be presented. Lastly, GaAs/Si heterogeneous wafer bonding with a specific bond energy of 478 mJ/m2 was realized at an annealing temperature as low as 140°C following a plasma activation step. This can potentially be combined with epitaxial lift-off processes to create new III-V on insulator wafers. The work done in this report was supported by the Singapore National Research Foundation through a Competitive Research Program (Grant No: NRF-CRP6-2010-4).

The voltage controlled charge-density-wave (CDW) phase transition in quasi-2D 1T-TaS₂ offers a possibility of using the switching behavior of these macroscopic quantum states for electronic applications. We have recently demonstrated a frequency tunable oscillator based on an integrated graphene–h-BN–TaS₂ device that is capable of operating at room temperature [1]. The carrier concentrations in the nearly commensurate (NC) and incommensurate (IC) CDW phases in 1T-TaS₂, which are utilized for switching the device, are very high, on the order of 10²¹ cm^-3 and 10²² cm^-3, respectively. The high carrier concertation creates conditions for resilience to the total ionizing dose (TID) effect, which is radiation damage to semiconductor device in space and high-energy accelerator environment. In conventional MOSFET, electron–hole pairs generated in the oxide during TID irradiation can accumulate in the oxide layers and interfaces, leading to the shifts in the threshold voltage and increase in the leakage current. Unlike conventional field-effect-transistors (FETs), the 1T-TaS₂ device is a two-terminal CDW device, in which the switching is controlled by the source-drain voltage rather than the gate voltage. No gate oxide is needed for its operation [1]. In this work, we evaluate the TID response of 1T-TaS₂ CDW devices by examining the current-voltage (I-V) characteristics under X-ray irradiation at doses up to 1 Mrad(SiO₂). We find that the threshold voltage, V_TH, for the abrupt resistance change shifts by only ~2%, the resistance of the CDW states changes by less than ~2 % (low resistive state) and ~6.5 % (high resistive state), and the self-sustained voltage oscillations in this 1T-TaS₂ oscillator function well after the full irradiation sequence [2]. The obtain results indicate that 1T-TaS₂ CDW devices are promising for applications in space and other high-radiation environments.

The work at UC Riverside was supported, in part, by NSF EFRI 2-DARE project: Novel Switching Phenomena in Atomic MX₂ Heterostructures for Multifunctional Applications and by UC-National Lab Collaborative Research and Training Program.

[1] G. Liu, B. Debnath, T. R. Pope, R. K. Lake, T. T. Salguero and A. A. Balandin, Nature Nanotechnology, 11, 845 (2016).
[2] G. Liu, E. X. Zhang, C. D. Liang, M. A. Bloodgood, T. T. Salguero, D. M. Fleetwood, A. A. Balandin, IEEE Electron Device Letters (accepted, 2017) 10.1109/LED.2017.2763597.

Silicon-on-Insulator (SOI) technology possesses many advantages over bulk silicon such as the reduction of parasitic capacitances, excellent subthreshold slope, elimination of latch up and resistance to radiation [1]. For these reasons, SOI is the preferred technology for high-speed, high-temperature, and low-power microelectronic devices. SOI MOSFET devices employ a buried insulating thin layer, usually made of SiO₂ to electrically isolate devices from the bulk semiconductor. Due to the poor thermal conductance, the buried dielectric layer thermally insulates the MOSFET from the bulk [2]. Consequently, the heat generated in SOI MOSFETs causes a larger temperature rise than in bulk devices under similar conditions, and this self-heating effect results in reduced carrier mobility and a corresponding decrease in the transconductance and speed. The self-heating effect can have significant impact on the device reliability as well.
This paper is an attempt to understand the effects of heat generation in SOI technology using a multiscale simulation and modeling scheme developed at Arizona State University in collaboration with IMEC in Belgium [3]. This scheme allows for simulation of carrier self-heating in the device and the corresponding thermal transport at the interconnect level, both at the same time. Previous work has successfully simulated self-heating in bulk devices, but this work strives to model the self-heating in SOI devices.
This scheme involves two components: 1). A numerical device level simulator that uses the Monte Carlo (MC) method to solve the Boltzmann transport equation (BTE) which is coupled with a Poisson solver to evaluate the charge distribution, while a self- consistent, energy balance equation is solved for optical and acoustic phonons to account for the self-heating effects. 2). The device simulator is coupled to a Silvaco module which solves for thermal transport in circuit interconnects using the Fourier law. Hence this multi-scale thermal simulation and modeling scheme is capable of analyzing thermal effects in nanoscale integrated electronics.


[1] R. Chau, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros, and M. Metz, “Silicon nano-transistors and breaking the 10 nm physical gate length barrier,” in Proc. Device Res. Conf., Jun. 2003, pp. 123–126.
[2] T. Numata and S. Takagi, “Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2161–2167, Dec. 2004.
[3] S. S. Qazi, A.R. Shaik, R.L. Daugherty, A. Laturia, X. Guo, E. Bury, B. Kaczer, K. Raleva and D.Vasileska, “Multi-scale modeling of self-heating effects in silicon nanoscale devices”, proceedings of the 15th International Conference on Nanotechnology (IEEE NANO), Rome, Italy, pp. 1461 - 1464, 2015.

Two-dimensional hafnium diselenide (HfSe2) and hafnium disulfide (HfS2) have impressive theoretical properties but are among the less well-studied transition metal dichalcogenides. Further research is needed to realize high-performance Hf-based devices. We investigated the air stability of mechanically exfoliated layers of HfSe2 and HfS2 via atomic force microscopy and Raman spectroscopy studies. With continued exposure to air, the surface of HfSe2 progressively transforms from HfSe2 to HfOx and Se, as confirmed by changes in Raman spectra and by the appearance of Se-rich, spire-like features. We determined that sample thickness, total time of air exposure and and exfoliation in a glove box versus in air all affect the degree of transformation. HfS2 was much more stable in air and served as a comparison for the study of HfSe2. This work lays out initial steps toward controlling the behavior of HfSe2 surfaces, which can inform future efforts to fabricate Hf-based transistors.

The integration of complementary metal-oxide-semiconductor field effect transistors (CMOSFET) with photonics requires photodetectors to operate at hundreds of giga hertz (GHz). This can be achieved by scaling down the size of photodetectors ^[1]. But a smaller device volume will reduce the light absorption, resulting in a poorer photosensitivity. High gain photodetectors such as avalanche photodetectors are often employed for such applications. Unfortunately, such photodetectors suffer from excessive avalanche noises in particular when the devices operate at high gain. In this work, we develop a novel core-shell nanowire phototransistor that has a gain of 10⁶ and a potential 3dB bandwidth of ~300 GHz. The device is made on a highly doped p-type silicon nanowire that is patterned out of the device layer of a silicon-on-insulator (SOI) wafer. A section of the nanowire is doped to be n-type by self-assembled molecular monolayers ^[2-3], forming a core-shell pn junction around the nanowire like a structure of “a ring on a finger”. For an appropriate nanowire width, the pn junction will pinch off the nanowire channel without voltage bias. Under light illumination, the channel will open, inducing a high saturation photocurrent. Experimental results show that the nanowire phototransistors show a photoresponsivity of 10⁶ A/W with a potential 3dB bandwidth of 300GHz.

References
[1] O. Hayden, R. Agarwal, and C. M. Lieber, “Nanoscale avalanche photodiodes for highly sensitive and spatially resolved photon detection,” Nat. Mater. 5(5), 352–356 (2006).
[2] Ho, J. C. et al. Controlled nanoscale doping of semiconductors via molecular monolayers. Nat. Mater. 7, 62–67 (2008).
[3] Guan, B. et al. Nanoscale Nitrogen Doping in Silicon by Self-Assembled Monolayers. Sci. Rep. 5, 12641 (2015).

This work explores the thermal and electrical characteristics of CMOS devices and circuits using a multiscale dual-carrier approach. Simulating for electron and hole transport simultaneously allows for complementary logic gates to be simulated at the device level, while current and voltage continuity are maintained at the circuit level. Further, the electrical model couples with a multiscale thermal solver, which solves for electron-phonon and hole-phonon interactions at the device level and phonon-phonon thermal transport in the packaging level. This methodology allows for the study of package level thermal transport without sacrificing the nuances of device self-heating, ultimately providing a more comprehensive understanding of how these interactions affect power consumption in CMOS systems.

The electrical model is comprised of an ensemble Monte Carlo simulator coupled with a Poisson solver. This framework provides accurate electrical characteristics in quasi-static regimes by iteratively solving for the potential profile and the electric fields then simulating the effect of the electric field on charge carriers. The Monte Carlo simulator solves the Boltzmann Transport by balancing each particle’s movement in real and momentum space with the collision integral through probabilistic scattering mechanisms. This framework provides current and voltage characteristics for each device; current and voltage continuity are maintained by solving at the circuit level.

Similarly, the methodology for simulating thermal characteristics includes two scales. At the device scale, the energy balance equation determines the transfer of energy from charge carriers to phonons. High-energy electrons or holes relinquish energy to optical and acoustic phonons through scattering and optical phonons decay into acoustic phonons. At the package level, a Fourier law solver simulates the subsequent conduction of heat in the form of lattice vibrations.

This framework proved effective in previous simulations for the electro-thermal characteristics in NMOS devices. This work demonstrates the effectiveness of the dual-carrier electrical solver in simulating CMOS circuits. Future work requires the coupling the dual-carrier electrical solver with the previously proven thermal solver to provide comprehensive electro-thermal simulations of CMOS systems.

The memory effects in a memristor can be realized through the switching behavior between two distinct resistance states, low resistance state (LRS) and high resistance state (HRS) driven by low pulse voltages. ZnO-based thin films such as undoped ZnO, Mg-doped ZnO, Na-doped ZnO and Mn-doped ZnO have attracted considerable interest as promising resistive switching materials. Gallium doping electrically modulates the behavior of ZnO to suit low power switching behavior. Non-lattice oxygen ions and oxygen vacancies as detected by XPS are found to play important role in imparting forming-free resistive switching behavior.All deposition for fabrication of device has been done by dual ion beam sputtering(DIBS).

To start with fabrication of device, a 60 nm thick Ga-doped ZnO thin film as switching layer is deposited over bottom electrode (BE) Au/SiO2/Si, at a substrate temperature of 100 °C, with DIBS background pressure of 1 × 10^-8mBar and Ar:O₂ (1:4) (flow rate in sccm), respectively. Finally, circular Au electrodes of 300 µm is deposited on the surface of switching layer. Similarly, Al/ZnO/Al/SiO₂/Si device is fabricated to compare the electrode and doping effect using Ar:O₂ (2:3) and substrate temperature of 400 °C. The current-voltage (I-V) characteristics of the device are measured using Keithley 2612A sourcemeter and Everbeing probe-station. Al(BE)/ZnO interface has been observed by cross-sectional high-resolution transmission electron microscopy (HR-TEM) using HR-TEM: JEOL JEM-2010 for formation of any AlO_x layer. X-ray photoelectron spectroscopy (XPS) having PHOIBOS 100 analyzer with an Al Kα radiation (1486.6 eV) as an excitation source, has been utilized to analyze the binding energy and the composition of each element in switching layer.
I-V characteristics are measured by sweeping a DC voltage in sequence of 0-10 mV-0--10 mV-0 in steps of 1 mV and 0-(+8 V)- 0-(-8 V)-0 in steps of 0.5 V for both devices respectively with a compliance current of 1 mA. I-V of Al/ZnO/Al (AZA) shows device with varying ramp rate exhibiting decreasing hysteresis with increasing ramp rate. Similarly I-V for Au/Ga-ZnO/Au (AuGZAu) conforms to zero crossing of I-V hysteresis loop and shrinking of loop area with increasing ramp rate. Device sets and resets to lower voltage as compared to AZA device. XPS of the switching layer conforms to presence of oxygen vacancies and non-lattice oxygen ions which assist in switching. An amorphous AlO_x interfacial layer (~4-5 nm) [5] formed at Al(BE)/ZnO interface as confirmed by HRTEM for the device in high resistance state (HRS) state which assists in set/reset process.

Ga doping increases conductivity of ZnO film and hence sets and resets at lower voltages. AuGZAu device depicts unipolar memristive behavior as it shows pinched hysteresis with varying frequency, whereas AZA behaves as an ideal bipolar memristor with good endurance and retention. AuGZAu device can be utilized for low power resistive switching.

Herein, we have reported on structural, chemical and electronic properties of two-dimensional (2D) tin disulfide (SnS₂) crystals grown on silicon dioxide (SiO₂) substrates by vapor-phase method. High-resolution annular dark-field (ADF) scanning transmission electron microscope (STEM) analysis indicate that the SnS₂ crystals crystallize in 1T phase, which is in consistent with the ab-initio density functional theory (DFT) calculations predicting that SnS₂ stabilizes 1T phase at ground state. Photoluminescence (PL) and ultraviolet-visible (UV-vis) spectroscopy measurements suggest that the SnS₂ crystals have an indirect band gap of 2.20 eV and 2.35 eV, respectively, which is in good agreement with the DFT-calculated band gap of 2.31 eV. The electrical transport measurements performed on back-gated field-effect transistors (FETs) exhibit n-type semiconductor characteristics of the SnS₂ crystals. High-angle annular dark-field (HAADF) STEM imaging and STEM energy dispersive X-ray (EDX) chemical analysis demonstrate that the SnS₂ crystals are chemically homogeneous with a stoichiometric S/Sn atomic ratio of 2. Electron energy loss spectroscopy (EELS) and X-ray photoelectron spectroscopy (XPS) analysis present the characteristic Sn and S peaks of SnS₂, confirming the phase purity of the SnS₂ crystals. Ultraviolet photoelectron spectroscopy (UPS) measurements of the SnS₂ crystals provide an ionization potential of 7.51 eV, which is in a perfect agreement with the DFT-calculated ionization potential of 7.51 eV. Resonance Raman spectroscopy in conjunction with ab-initio DFT calculations reveal the characteristic first-order and second-order Raman modes of 1T phase of the SnS₂ crystals. Angle-resolved polarized Raman spectroscopy (ARPRS) mappings with different polarization angles show unique edge features of the SnS₂ crystals.

The performance of ultrafine wires in the back end of the line (BEOL) is degraded by the persistent polygranular microstructure in copper which introduces more diffusion pathways for copper atoms and which leads to faster electromigration failure times. To improve interconnect reliability, Co-containing capping layers have been used to reduce surface diffusion. Applying the same logic to other interfaces, alloying solutes have been proposed to slow down grain boundary diffusion by increasing the activation energy for atomic motion, but the mechanisms are not well understood and there are many conflicting reports as to their efficacy. One challenge for improving interconnect performance through alloying is a lack of information regarding segregation interactions at grain boundaries and interfaces when minute concentrations are introduced into the copper lattice. Historically, solute was expected to pin GBs, increase resistivity, and reduce diffusivity by GB “stuffing”. More recent studies on GB interface states called ‘complexions’ suggest a more complicated relationship, which can explain these results as well as cases where segregation increases mobility or enhance diffusion. To apply complexion analysis in technologically relevant alloy systems, we are investigating dilute copper alloys created by co-electrodeposition or nanolaminate fabrication using a microfluidic device with separate inputs for solvent and solute. Alloying copper with cobalt may offer a means for stabilizing grain boundaries against electromigration void formation in advanced interconnects. Here we present a means for co-depositing dilute copper alloys, using Co and Ag as the solutes of interest. Microstructure and compositional analysis are presented.
Initial work in the co-deposition of dilute copper alloys has yielded insights into the plating requirements, microstructure and composition of the subsequent films. Additional refinements to the process and analysis are being pursued for comparison to alloys deposited in our 300 mm processing line. Less Co diffusion is observed than expected from literature values of the diffusivity, even under fairly aggressive conditions (500°C for 5 hours). Microstructural analysis with concurrent SIMS testing is used to describe these results in terms of the recrystallization of the alloy. In particular, we discuss whether or not the presence of the alloying element influences the final microstructure of the film and provide a mechanistic explanation for these observations.

In filamentary resistive switching memory cells (RRAM) the resistance of the on-state, R_on, is determined by the limiting (compliance) current, I_cc, by the relation R_on~1/I_ccⁿ, where the exponent n in many RRAM cells with a metal atom filament is close to unity¹. Our RRAM cells are MIM Cu/TaO_x/I structures with 25nm TaO_x and inert electrode I=Pt,Rh, or Ru. We show that at low I_cc (roughly <50μA), the resulting high resistance R_on (~100kΩ) is fragile and operatively undefined as any read operation is bound to disturb its R_on value. The R_on can increase or decrease depending on the read voltage polarity, read voltage starting point, read voltage ramp rate and its sweep direction. In contrast, a set operation performed at a high I_cc (>150μA) leads to a stable, low resistance R_on independent of reasonably chosen reading conditions. For I_cc<50 μA, the measured R_on will return different values depending whether the measurement within a 100mV voltage interval started at 0.0V, -0.1V or +0.1V. The highly resistive conductive filament (CF) is fragile and subject to small displacement of individual atoms or defects, charging and discharging reactions. The starting point of the applied voltage determines (non)-equilibrium conditions for Cu⁺, oxygen O^2-, and oxygen vacancy V_o charge states and electron concentrations, all of which impact the properties of CF. For highly resistive CF, most read measurements tend to decrease R_on. The underlying strengthening of the CF, ascribed to aggregation or displacement of Cu⁺, V_o, and O^2-, is, often, impermanent and auto-reversible upon suspension of the read operation. However, the rate of atomic displacement depends strongly on the voltage ramp rate. In general, we find that the R_on resistance decreases with decreasing ramp rate which was has been varied from 10V/s to 0.1V/s. The geometric shape of CF, is approximated by that of a truncated cone. The bulk part of the resistance resides at the tip of CF. As soon as the current exceeds I_cc ,used at the set operation, it generates at the tip high electric field which depending on its polarity causes new transport of Cu⁺, O^2-, and V_o. The voltage ramp rate determines the time scale of the ionic transport at high fields. Thus ramp rate dependence gives insight into the time scales of the ionic transport. The R_on disturbances by electric fields yield insight into the transient mechanisms for CF formation and rupture.
One implication is that during reset operations the differences between high R_on values are brought to the same value before the filament is ruptured, i.e. the reset is rendered independent of the set operation conditions in contrast to a low resistance CF². The ionic mechanisms and the time scales involved that lead to the change of R_on during the read and reset operations will be discussed in detail.

[1] T. Liu, Y. Kang, S. El-Helw, T. Potnis, M. Orlowski, Jap. J. Appl. Phys. 52, (2013) 084202
[2] G. Ghosh, M. Orlowski, IEEE Trans. Elect. Dev. 62(9) (2015) 2850-56

Molybdenum disulfide (MoS₂) with atomic-scale flatness has potential candidate in the applications of high speed and low-power logic devices due to its scalability and intrinsic high-mobility. However, to realize 2D materials as to be viable technology, large-area growth with high quality and uniformity must be pre-requisite. Here, we present the simple and highly uniform growth of four layered molybdenum disulphide (MoS₂) on 2 inch wafer scale substrate via the combination strategy of sputtered molybdenum trioxide (MoO₃) and post sulfurization of chemical vapour deposition (CVD). The spatial spectroscopic analysis of Raman and PL mapping shows that as-synthesized MoS₂ thin film exhibit extremely high uniformity on 2-inch sapphire substrate. With this approach, we assembled almost 1200 MoS₂ transistors integrated on Si wafer that yield high density and extremely uniformity (device yield of ~95%, average mobility of ~0.8 cm²V^-1s^-1, and log on-off ratio of ~4.3). And, the quantitative analysis using pulsed I-V measurement with millisecond time scale could achieve more intrinsic device parameters suppressing the charge trapping of 2D materials-based device.

Silicon Carbide (SiC) based insulated gate bipolar transistor is a promising candidate for use in high voltage power devices, due to faster switching and high voltage blocking capabilities. The type of dielectric layer used in SiC power devices plays an important role in how the device performs. While SiC based transistors are commercialized, the combination of Silicon dioxide (SiO₂) and SiC interface had compatibility concerns, and cannot sustain higher electric fields. An alternative is to replace the conventionally used SiO₂ with high-K dielectrics that can sustain high electric fields. This approach has been attempted earlier with Hafnium dioxide (HfO₂) as the main gate dielectric and sandwiching SiO₂ between of HfO₂ and SiC. Earlier research work has shown initial reduction and then increase in forward voltage drop (V_f)/ON state resistance (R_ON) with respect to temperature. However, there is no complete analysis of the static characteristics using HfO₂-SiO₂ as dielectric stack at higher temperatures. The purpose of this work is to understand the influence of HfO₂ on the capacitance and switching characteristics at higher temperatures. This work highlights the changes in electrical characteristics by varying lattice temperature from 300 K to 700 K. The structure of the device is modeled by using Sentaurus TCAD. Apart from usual drift-diffusion and recombination models, lombardi model has been used to take mobility degradation at the interface into consideration. Uniform trap distribution up to the conduction band and the exponential distribution closer to the conduction band edge is defined within the band gap of SiC in the dielectric interface. Breakdown voltage (BV), switching characteristics using a clamped inductive load and variation of miller capacitance with respect to temperature is analyzed along with static characteristics. The doping of p-well and thickness of dielectric has been designed to adjust threshold voltage(V_th) closer to 3.5 V. It is to be noted that V_th generally reduces with an increase in temperature. The I_c-V_g and I_c-V_ccurves at different temperatures are simulated. As expected, the reduction in V_th and transconductance (g_m) has been observed from the I-V curves with increase in temperature. It has been observed that the saturation of trapping occurs at a lower gate voltage with the increase in temperature. The carrier lifetime in the buffer region is calculated using doping and temperature dependent carrier lifetime model. The turn off characteristics and ON state energy (E_ON) / OFF state energy (E_OFF) with respect to temperature are simulated. It has been observed that the temperature has more influence on E_ON compared to E_OFF. The influence of external gate resistance (R_g) on the switching characteristics will be discussed in the full paper.

Although silicon-based electronics are used to power light-emitting diodes and electric vehicles, their utility in high power applications is limited by a low breakdown voltage. Wide-bandgap semiconductors, such as gallium nitride and related alloys have been proposed as alternatives, but the effective p-type doping at high concentrations remains elusive. For example, Mg dopant activation following ion implantation, selective diffusion, and metal-organic vapor deposition requires high temperature annealing which may disrupt active device structure. In the case of molecular-beam epitaxy, surfactants and co-dopants such as O and Si have been explored, but the concentration of substitutional Mg is often limited, leading to limited p-type doping efficiency. Here, we are developing a novel approach to enhance the p-type doping of GaN and related allows. We describe a combined computational-experimental approach consisting of focused ion-beam (FIB) nano-implantation of Mg in GaN during molecular-beam epitaxy (MBE), followed by computational and experimental ion channeling studies of the Mg incorporation mechanisms. This approach is likely to result in p-type doping at ultra-high concentrations, without the need for subsequent high temperature annealing. We will discuss the development of a modified Mg-Ga alloy source for nano-implantation and our progress towards its implementation in a modular MBE-FIB system. We also present our Monte Carlo-Molecular dynamics simulations of ion channeling in wurtzite GaN crystals, and discuss our progress towards quantifying the influence of growth and annealing sequences on Ga and/or N vacancy formation and the result substitutional vs interstitial incorporation of Mg in GaN. We have examined the influence of Mg defect type in GaN on the [0001], [10-10], and [11-20] channeling yields.

Niobium oxides have recently been demonstrated as excellent candidates to make memristors and memdiodes in neuristor circuits for application in neuromorphic computing. The Poole-Frenkel conduction in the niobium oxide layer is very sensitive to localized temperature and Joule heating. Additionally, thermal confinement and overheating in eventual microelectronics devices may result in significant degradation of performance and reliability. Therefore, it’s of great importance to understand and quantify thermal transport in these oxides. However, very few papers about thermal properties of niobium oxides have been published. Here, we report the first thermal conductivity (k) measurement of amorphous niobium oxide (a-Nb2O5-d) thin films by Time-domain Thermoreflectance (TDTR) method. We observe very low k of a-Nb2O5-d thin films (around 1 W/m-K) that are tunable (about 80% change) through varying oxygen vacancy concentrations (d). Additionally, the thickness dependence of k in a-Nb2O5-d films is studied to explore the influence of size effects in the context of locons, diffusons, and propagons. To complement this discussion, longitudinal wave velocities and vibrational energy spectra are measured by the picosecond acoustic method and Fourier-transform infrared (FTIR) spectroscopy, respectively.

Highly oriented 0.90[PbZr_0.53Ti_0.47] 0.10[La_0.2Scc_0.8]O_3-δ (PLZTS) thin films were deposited on La_0.67Sr_0.33MnO₃ (LSMO) coated MgO (100) substrates utilizing the laser ablation process in oxygen atmosphere. The optimized PLZTS depositions were conducted at a substrate temperature of 700 °C in the experimental setup (KrF excimer laser λ = 248 nm, f = 5 Hz, energy/pulse 270 mJ) and subsequently annealed at the same temperature for 30 minutes in an ultrapure oxygen atmosphere. The (100) orientation of the PLZTS films was obtained from x-ray diffraction results. The nearly stochiometric of fabricated thin films were obtained from the high-resolution X-ray photoemission spectroscopic (XPS) data. Atomic force microscopic (AFM-Veeco) result in contact mode suggests a homogeneous distribution of grains with surface roughness ~ 3.5 nm, and the grains are interconnected with distinct grain and grain boundaries. Piezo force microscopy (PFM) measurements, operated in single frequency excitation, suggests the presence of ferroelectric domains. at ambient conditions. The temperature dependent dielectric measurements carried out on LSMO/PLZTS/Pt metal-ferroelectric-metal capacitors in 100-600 K and frequency (10²-10⁶ Hz) exhibits a broad dielectric maximum. At room temperature, we observed high dielectric constant ~ 650 at 10² Hz. Ferroelectricity of the thin films was ascertained from the observation of well-saturated hysteresis loops with P_r = 22.35 µc/cm² and E_c =92.46kV/cm respectively at frequency 2kHz. The high dielectric constant, low losses and excellent ferroelectric PLZTS thin film capacitor insights into its potential application in electronic devices

Due to the increasing power demands, there is a need for more efficient, high power switching devices. GaN sees a lot of promise as a mean to meet this demand due to good on-resistance vs. breakdown voltage relationship. As a result, GaN-based electronic devices have seen a great deal of success in high power applications. The development of first generation GaN power devices has focused on lateral architectures, such as high-electron mobility transistors (HEMTs), fabricated in thin GaN layers grown on foreign substrates (e.g., sapphire, SiC, and Si). HEMTs achieve their high electron mobility with a lateral heterostructure
Despite the successful demonstration of GaN HEMTs in various power applications, these lateral devices have several drawbacks which significantly limit their performance especially for high power and high voltage applications (e.g., > 1,200V). These lateral devices suffer from several major degradation mechanisms including current-collapse, dynamic on-resistance, and an inability to support avalanche breakdown performance. Furthermore, at higher operation powers, lateral HEMTs become less attractive, since the blocking voltage is held laterally, the device length must increase in order to increase the breakdown voltage.

Recently, bulk GaN substrates have become widely available, thus enabling a new generation of GaN power devices based on vertical architectures. These vertical GaN power transistors hold the blocking voltage vertically, which allows the devices to achieve very high breakdown voltages without increasing device area. As in a lateral device, a heterostructure is used to create 2DEG. However the electrons are drawn by the drain into the bulk. Because of this, current collapse is not as much a concern in these devices since most of the conduction path is not near the trap rich surface. Current blocking layers (CBLs) are employed to confine the current to an aperture directly beneath the gate. Typically, p-GaN is used for the CBL, however, growing the p-GaN layer via metal organic chemical vapor deposition (MOCVD) results in the Mg being passivated by H, and therefore the hypothetical >3eV blocking layer is not achieved.

Therefore, there is impetus to explore other materials for CBL applications, such as SiO₂, however, previous work on SiO₂ CBL’s neglected thermal considerations. This work simulated using Silvaco TCAD two GaN Vertical HEMT devices, one with a conventional p-GaN CBL and one with a SiO₂ CBL under both isothermal and non-isothermal conditions. At V_D = 20 V and VG = 0 V, the SiO₂ devices saw more heating, possessing a hotspot of 396 K, compared to the 379 K hotspot of the p-GaN device. In spite of the increased heating, the on-resistance was still lower for the SiO₂ CBL device (0.266 mΩ cm²) than that of the conventional p-GaN CBL device (0.331 mΩ cm²).

Copper is the dominant material used in electrical conductors due to its availability and excellent electrical conductivity. However as the electronic devices are getting smaller concerns regarding the ampacity of copper conductors have arisen. Moreover poor mechanical properties and relatively high weight resistivity of copper wires and cables have motivated researchers to develop new materials and systems for power transmission. Carbon nanotubes (CNTs) offer high electrical and thermal conductivity, excellent mechanical properties and ampacity 1000 times higher than copper. Although these outstanding properties make CNTs a very promising candidate, complex and costly processing impedes their application as a sole conductor. On the other hand previous research has shown that utilizing CNTs as a filler in a metallic matrix can simplify the processing and results in remarkable properties. In this case interfacial interactions between the two phases significantly influence the morphology and properties of the composite.
In this report electrospinning was utilized to produce Cu-CNT nano-fibers. The effect of CNT surface treatment and electrospinning parameters on the morphology and electrical conductivity of copper-CNT electrospun fibers were studied. For this purpose four different types of CNTs (pristine, oxidized, exfoliated and thiol activated) in different concentrations were used. Also two types of polymeric carriers were studied. Results showed that generally CNT introduction will decrease the uniformity and smoothness of the Cu-CNT fibers. Above a certain critical concentration, fibers cannot be produced. Pristine CNTs have the lowest and exfoliated CNTs have the highest critical concentration. Exfoliated CNTs with concentration as high as 5 wt% yields very smooth fibers with high uniformity which can improve the electrical conductivity. Also, it was shown that although PVP application as the carrier polymer makes the electrospinning process easier, PVA produces fibers with higher smoothness and uniformity. It should be noted that that in nano-scale surface smoothness has a significant effect in the conductivity of fibers.

The through silicon via (TSV) is one of 3D integration methods to achieve high density interconnects with a good electrical performance and a small form factor on wafer level. In this work, we investigated the TSV filling performance dependent on the functional groups of levelers such as amines, imines, pyridines and pyrrolidones. To elucidate the behavior of functional groups in TSV filling, the mass adsorption rate was measured using quartz crystal microbalance (QCM) and electrochemical QCM (EQCM). It was found that the amines only exhibited the void-free filling in TSV, whereas other functional groups showed the void in TSV. This could be inferred that the amine favored the local adsorption on the top edge of via during electroplating, as evidenced by low mass adsorption rate of QCM and the large difference of mass adsorption rate between QCM and EQCM.

In the panel level packaging, it is necessary to control the thickness uniformity of electroplated Cu redistribution layer because non-uniform thickness of Cu electrodeposits is resulted in severe electrical resistance fluctuation. In this work, we studied the thickness uniformity of Cu electrodeposits in the presence of organic additive containing imine functional group modified with different degrees of quaternization. The degree of quaternization of imine functional group was controlled to be in the range of 0 to 100 % using the dimethyl sulfate solvent. The surface morphology and thickness uniformity of Cu electrodeposits were characterized by optical microscopy and confocal laser microscopy. In the case of adding the organic additive containing the imine functional group modified without quaternization into Cu electroplating solution, the shape of Cu electrodeposit represented dome shape with poor uniformity. Additionally, excessive dish-shaped surface was formed with the degree of quaternization of 100 %. However, with the degree quaternization of 50 %, the flat shape of Cu electrodeposits with high uniform thickness was obtained.

HfO2 makes a very useful ferroelectric oxide because it is thermodynamically stable in contact with Si, unlike the traditional ferroelectrics PZT and SBT. HfO2 can be brought into the ferroelectric Pca2 phase either by suitable thermal annealing process or by use of alloying or dopants such as group III elements Y, Sc, Al, or N at the O site, or the group IV elements Si, Ge, Zr. Si, Ge, and N could be called efficient dopants in that only a small fraction is needed [1]. However, some of them introduce gap states which will act as traps, or encourage leakage currents, or in the worst case breakdown. Trivalent dopants act by creating O vacancies which lower the mean O coordination and thus stabilise the lower symmetry phase [2]. We recall that previously N and Y were shown to behave beneficially in removing the gap states due to O vacancies from the gap band, but this is true only if they are adjacent to the vacancy [3,4]. We find that ‘efficient’ dopants are less satisfactory in that they will not necessarily be close to the vacancies, so their gap states are not removed. Ge is found to have too small a gap. Si does not introduce gap states.
1 A Toriumi et al, IEDM (2016)
2 J P Goff et al, PRB 59 797 (1999)
3 K Xiong, J Robertson, JAP 99 044105 (2006)
4 D Liu, J Robertson, APL 94 042904 (2009)

The mechanism of stability of the phases of HfO₂, ZrO₂, and HZO (Hf_xZr_1-xO₂) were systematically investigated with density functional theory molecular dynamics (DFT-MD) to determine the mechanism for HZO having a much larger process window for formation the ferroelectric phase as compared to doped HfO₂ or ZrO₂. For the bulk states, the monoclinic phase (“m”) is about 80 mV per formula unit more stable than either the orthorhombic ferroelectric (“f”) phase or tetragonal (t-phase) for all three oxides. The surface free energies of the (001), (110), and (111) surfaces of all three oxides were calculated using an identical DFT technique. For all three oxides, the (111) face has the lowest surface free energies consistent with experimental data on columnar HZO grains showing [111] is the preferred growth direction. However, the surface free energy for all direction are nearly degenerate between HfO₂, ZrO₂, and HZO; therefore, even for nanocrystal formation the surface free energy does not favor f-phase formation. The effect of stress/strain was calculated by determining the free energy of formation as a function of the volume of the unit cell. When the oxides are grown in the low density amorphous phase but a post deposition anneal is perform for crystallization. The crystalline forms are more dense than the amorphous forms and the DFT calculation show that a higher surface area per unit cells will greatly favor f-phase formation. However, the effect is nearly identical for HfO₂, ZrO₂, and HZO; this is consistent with experiments showing the molar volumes of HfO₂ and ZrO₂ being within 2%. Instead, formation of nanocrystalites is hypothesized to be the source of the enhanced processing window for HZO. Experimental data is consistent with partial phase separation in HZO. Atom probe tomography imaging of the chemical composition of TiN/5 nm HZO/Si(001) ferroelectric films show an asymmetric distribution of the Hf and Zr within the HZO layer with the Zr being concentrated near the TiN/HZO interface; this is consistent with ZrO₂ having a 100C lower crystallization temperature than HfO₂ and therefore initiate the crystallization starting on the TiN(111) surface. It is hypothesized that the nanocrystals which template on TiN(111) can produce the interfacial stress/strain needed to stabilize f-phase formation; high resolution TEM shows regions of epitaxial alignment between HZO and TiN consistent with this mechanism.
Funding by LAM Research is gratefully acknowledged.

The 2011 discovery of a ferroelectric phase in doped hafnium oxide [1] and hafnium zirconium oxide solid solution [2] re-established the competitiveness of ferroelectric memory technologies. Mainly driven by the outstanding scalability and CMOS-compatibility of this new ferroelectric material, classical concepts such as FRAM, FeFET and FTJ are reentering the race for leading edge embedded and stand-alone memory solutions [3-6]. Especially the FeFET concept with its simple one-transistor cell design, non-destructive and low power read operation appears to be the main beneficiary of this new development. Scalability to the 2X nm node [3] and highly yielding memory arrays in the Mbit range are currently being demonstrated for hafnium oxide based FeFETs [7]. Nevertheless, a fundamental material understanding is needed to identify the main parameters improving the ferroelectric performance of the hafnium oxide thin films.
In this contribution we give an overview of the main parameters and their impact on the ferroelectric behavior of hafnium oxide. The thickness dependence and the directly associated consequence for the doping concentration of the film will be reviewed. The impact of different thermal treatments will be also discussed in relation to CMOS process flows, illustrating how the thermal budget of subsequent processes in the entire process flow can distinctively change the ferroelectric film properties. Furthermore, specific treatment conditions will be shown, which are further enhancing the ferroelectric properties of hafnium oxide films.

[1] T. Böscke et al., Applied Physics Letters 99 (10), 102903-102903, 2011
[2] J. Müller et al., Applied Physics Letters 99 (11), 112901-112901, 2011
[3] J. Müller et al., Symposium on VLSI Technology (VLSIT), pp. 25-26, 2012
[4] P. Polakowski, IEEE 6th International Memory Workshop (IMW), pp. 1-4, 2014
[5] K. Florent et al., Symposium on VLSI Technology (VLSIT), pp. T158-T159, 2017
[6] S. Fujii et al., Symposium on VLSI Technology (VLSIT), 2016
[7] S. Dünkel et al., IEEE International Electron Devices Meeting (IEDM), accepted for publication, 2017

Following the first report on ferroelectricity in Si-doped HfO₂ thin film in 2011 [1], fluorite-type ferroelectrics have attracted great interest in the field of ferroelectricity [2]. Even with an extremely small film thickness of ~10 nm, they could have remanent polarization as high as 15 – 30 μC/cm², which is already comparable to that of much thicker perovskite-type ferroelectric films [2]. Moreover, they are environmental-friendly with an absence of Pb and have deposition techniques (atomic layer deposition), mature enough for mass production [2]. Thus, they are considered highly promising for both memory and energy devices [2]. Especially, the field-induced phase transition in fluorite-type ferroelectrics enables energy storage, energy harvesting and solid-state-cooling comparable to or even better than the previous candidates [3].
The crystallographic origin of the unexpected ferroelectricity is now believed to be a formation of Pca2₁ orthorhombic phase [2]. However, this phase cannot be found in phase diagrams of bulk HfO₂ and ZrO₂, and the monoclinic phase is always a stable phase under process conditions. To understand the formation of the unexpected orthorhombic phase, various thermodynamic causes such as surface energy, interface/grain boundary energy, stress, and doping were suggested [2,4]. From a comprehensive comparison of our experimental results to the theoretical models, we suggested that the kinetic mechanism of phase transition should also be considered [5,6]. In this presentation, therefore, the thermodynamic/kinetic origin of the formation of orthorhombic phase in fluorite-type ferroelectrics and their properties will be comprehensively examined.
[1] T. S. Boescke et al., Appl. Phys. Lett. 99, 102903 (2011).
[2] M. H. Park et al., Adv. Mater. 28, 7956 (2015).
[3] M. H. Park et al., Nano Energy 12, 131 (2015).
[4] R. Materlik et al., J. Appl. Phys. 117, 134109 (2016).
[5] M. H. Park et al., Nanoscale, 9, 9973 (2017).
[6] M. H. Park et al., submitted to Nanoscale.

We discuss dopant effects on the ferroelectricity of HfO₂. We prepared many kinds of doped HfO₂ with both cations (Y, Sc, Al, Si, Ge, Zr, Nb) and anion (N)^[1]. We found not only dopant-dependent but also dopant-independent contributions to ferroelectric properties. The former one obviously comes from dopant atomic nature such as ionic charge or size, while the latter one is the point we are interested in.
Total polarization P_SW as a function of the dopant concentration X, in which X and P_SW denote the dopant ratio in total atoms including anion and the absolute value of polarization at V=0, respectively. A small amount of N doping enables to achieve the ferroelectric HfO₂, while Zr slowly and Ge moderately help the ferroelectric phase formation of HfO₂. More interestingly, the sensitivity curve seems to be similar in shape irrespective of dopant species^[2]. This fact suggests that HfO₂ ferroelectricity is achieved by HfO₂ intrinsic properties. In HfO₂ and ZrO₂, the structural phase transitions from the tetragonal to monoclinic phases are understandable from the martensitic transition viewpoint. In the doped HfO₂ case, it is inferred that the ferroelectric orthorhombic phase may be along this phase transition. In that sense, the dopant may help to increase the kinetic barrier against stabilizing the monoclinic phase irrespective of dopant species.

Acknowledgnment
This work was supported by JST-CREST Grant Numbers JPMJCR14F2, Japan.

References
[1] L. Xu, A. Toriumi et al., Appl. Phys. Express 9, 091501 (2016).
[2] L. Xu, A. Toriumi et al., J. Appl. Phys. 122, 124104 (2017).

Today, in the era of the Internet of Things era, the demands on enhanced integrated functionalities and on energy efficiency are even more important as the system miniaturization. Despite the fact that new paradigms in computing consider possible future roles of neuromorphic and quantum computing, it appears that, at least for next decade, CMOS will continue to play a dominant role. One of the remaining challenges for transistors with nanometer dimensions is the voltage scaling, today saturated at value near 0.7V. Today’s CMOS is a multi-material, three dimensional technology, which exploits quantum effects in semiconductors. However, the voltage supply of most advanced CMOS technologies is saturated due to incompressible thermionic subthreshold slope of the MOSFET, having as limit 60mV/decade at room temperature. In recent years, tremendous research efforts have been dedicated to devising new types of so called subthermionic steep slope switches, where the principle of the MOSFET switch is replaced with physical mechanisms that can provide such steeper transition between OFF and ON state, such as band-to-band tunneling and impact ionization. The goal is to enable further supply voltage scaling down to 0.2-0.3V, where logic state distinguishability is still granted with an improvement of energy efficiency of about 100x. Another idea is to apply a radically new technology booster on MOSFET and extend his life, by amplifying the gate signal using a differential negative capacitance (NC) in the gate stack. This could be done in a similar way in which a differential negative resistor would amplify a small signal. The result is a transistor body factor smaller than unity, reflecting the differential surface potential amplification, possible because of ferroelectric materials that can provide such a negative capacitance in the transistor gate stack.
In this paper, we will review, discuss and provide some concrete examples of how to achieve such sub-unity m factors by the negative capacitance effect materials to boost both MOSFETs and tunnel FETs performance at sub-10nn channel dimensions. The paper will discuss theoretical and experimental matching and stabilization conditions for NC and quantitative performance improvement in NC-MOSFETs and NC-Tunnel FETs by using PZT and, most interesting, ferroelectricity in doped high-k capacitors. The role of mono-domains versus multi-domains in ferroelectrics showing negative capacitance will be clarified. Moreover, we will present investigations about the very important role of gate leakage current in order to exploit the NC effect.
Overall, the paper will demonstrate that a deep sub-unity body factor by negative capacitance effect of field effect transistors can be engineered and applied for both MOSFETs and Tunnel FETs and stands as one of the most universal performance booster at nanoscale.

Two-dimensional (2D) semiconductors such as transition metal dichalcogenides have great potential as post-silicon channel materials that could suppress short channel effects. However, 2D semiconductors still suffer from the thermal limit for the subthreshold swing, as long as conventional metal-insulator-semiconductor (MIS) structures are employed. To overcome the fundamental limit, we introduce the metal-insulator transition material VO₂ as a contact electrode in an atomically thin WSe₂-based MIS transistor. Polycrystalline VO₂ films with thicknesses of ~ 50 nm were grown on Al₂O₃ by the pulsed layer deposition method and observed to show the metal-insulator transition near 340 K. The VO₂ films were etched down to ~ 1 μm in width. Then, few-layer WSe₂ was transferred directly onto the VO₂ wire so that the VO₂ served as one of the contact electrodes. After defining another electrode by depositing Ti/Au on WSe₂, a gate dielectric of hexagonal boron nitride was transferred, followed by the definition of the gate electrode. The WSe₂ transistor is on the off-state, with the VO₂ electrode being in the insulating phase at room temperature. However, the drain current shows abrupt and discontinuous increase at a given gate voltage, suggesting that the insulator-to-metal transition in VO₂ is induced thermally by Joule heating. Since the on-off switching is governed by the phase-transition in the VO₂ electrode, the subthreshold slope is, in principle, expected not to be limited by the thermal voltage. We observe a relatively small value of 150 mV/decade for the subthreshold slope in this transistor, but this is still larger than the thermal limit of 60 mV/decade. We envision that the subthreshold slope could be further improved by employing single crystalline VO₂ as well as a high-k gate dielectric such as HfO₂. This work is an important first step in demonstrating steep-slope transistors based on 2D semiconductors.

Over the last couple of decades, there have been continuous efforts to scale down both logic and memory components of microelectronic devices to nano regimes in the pursuit of enhancing speed and storage density, respectively [1]. However, with reducing the dimension of these devices, the significant energy losses in the form of heat has been one of the key issues for the microelectronic industry [2]. In order to continue further improvement in device-level or even bring next breakthrough in computing devices, a novel physical mechanism beyond-CMOS concept is needed to be explored.
The electric-field manipulation of magnetism in mutltiferrroic based devices promises to reach in the energy landscape of atto-Joule (aJ) range for per bit operation in logic and memory devices [3]. Among other multiferroic materials, BiFeO₃ (BFO) exhibits robust magnetoelectric coupling at room temperature [4]. The canted antiferromagnetically aligned spins in BFO, give arise to the weak ferro-magnetism due to the Dzyaloshinskii–Moriya(DM) interaction, causes strong exchange interaction with ultrathin ferromagnet, e.g. CoFe, which can be exploited to electrically control the spin valve device [5]. Here we have demonstrated scaling behavior of applied voltage to electrically control the spin-valve devices at room temperature by engineering the strain state and doping level in BFO thin films. We show that with reducing the thickness of BFO layer down to 20 nm along with 10-15 % of La doping, the switching voltage can be reduced to sub volt regime (~150 mV). Besides this, we have shown large angle dependent exchange bias in these system that can be reversible controlled by electric field. The magnetic coupling of BFO with CoFe in these devices is strongly stabilized by its ferroelectric (FE) ordering. Orientation of the device structure with respect of the BFO FE domains play a crucial role in determining the degree of exchange bias and its manipulation with electric field. In addition to these findings, enhancement of magnetoelectric coupling with miniaturization of these devices down to ferroelectric domain size (~ 200 nm) provides a pathway to integrate BFO as a key material in the fabrication process for ultra-low energy, non-volatile beyond-CMOS computing.

[1] Ferain I. et al., "Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors" Nature 479 310-316 (2011).
[2] Meindl J. D et al., "Limits on silicon nanoelectronics for terascale integration." Science 293 2044-2049 (2001).
[3] Manipatruni S., et al., "Spin-orbit logic with magnetoelectric nodes: A scalable charge mediated nonvolatile spintronic logic" arXiv preprint arXiv:1512.05428 (2015).
[4] Wang J. et al., Epitaxial BiFeO₃ multiferroic thin film heterostructures. Science 299, 1719–1722 (2003)
[5 Heron J. T. et al., "Deterministic switching of ferromagnetism at room temperature using an electric field", Nature 516, 370–373 (2014).

According to the ITRS projections, the level of the current density will soon increase to ~5.35 MA/cm2 at the half-pitch width of 7 nm. There is no existing technology with the breakdown current density high enough to sustain such currents. No feasible interconnect solutions are known for the beyond-the-roadmap nanoscale devices. Scaling deep to the nanoscale range presents problems for conventional metals due to their polycrystalline structure, surface roughness and increased electrical resistivity owing to the electron–boundary scattering. In this presentation, we report the results of our investigation of quasi one-dimensional (1D) van der Waals metals as possible materials for ultimately down-scaled interconnects. Unlike copper some transitional metal trichalcogenides (TMTs) MX₃ (where M = Mo, W, and other transition metals; X = S, Se, Te) can be exfoliated or grown into quasi-1D single crystals without grain boundaries, surface roughness or dangling bonds. As a result, the onset of electromigration can be delayed to higher current densities. We have demonstrated prototype interconnects implemented with quasi-1D TaSe₃ nanowires with the current density exceeding J_B~32 MA/cm², which is an order of magnitude higher than that for the Cu interconnects [1]. The reliability of the prototype quasi-1D van der Waals metallic interconnects has been tested using the temperature-dependent low-frequency noise (LFN) spectroscopy. The LFN spectrum at elevated temperatures are directly correlated with the electromigration failure mechanisms in interconnects. The LFN data can be used for extracting the information about the vacancy migration along the nanowires and the onset of the electromigration failure. The noise activation energies extracted from the two commonly accepted physical models, the Dutta–Horn model and the empirical noise model in metals, have shown an excellent agreement with the activation energies obtained from the industry standard electromigration mean-time-to-failure (MTF) tests [2]. The obtained results suggest that the quasi-1D van der Waals metals are promising candidates for the ultimately downscaled local interconnects.

This project was supported, in part, by the by the Emerging Frontiers of Research Initiative (EFRI) 2-DARE project: Novel Switching Phenomena in Atomic MX2 Heterostructures for Multifunctional Applications (NSF EFRI-1433395) and by National Science Foundation (NSF) grant #1404967 to A.A.B. on defect engineering in materials.

[1] M. A. Stolyarov, G. Liu, M. A. Bloodgood, E. Aytan, C. Jiang, R. Samnakay, T. T. Salguero, D. L. Nika, S. L. Rumyantsev, M. S. Shur, K. N. Bozhilov, and A. A. Balandin, “Breakdown current density in h-BN-capped quasi-1D TaSe3 metallic nanowires,” Nanoscale, 8, 15774 (2016).
[2] G. Liu, S. Rumyantsev, M. A. Bloodgood, T. T. Salguero, M. Shur, and A. A. Balandin, “Low-frequency electronic noise in quasi-1D TaSe3 van der Waals nanowires,” Nano Lett., 17, 377 (2017).

Transition metal disilicides which have tunable work-functions, are of significant interest as contact silicides. Moreover, selective deposition of silicides obviates the need for lithography onto complicated 3D structures on sub 10 nm 3D devices. Metallic tungsten (W) deposition on H-terminated Si in preference to OH-terminated SiO₂ via a selective ALD process has been demonstrated using WF₆ and SiH₄ or Si₂H₆ by B. Kalanyan et al. In these processes, SiH₄(g) or Si₂H₆(g) are considered a sacrificial reductant for W film by forming SiF₄(g) and SiHF₃ as byproducts: 2WF₆(g) + 1.5Si₂H₆(g) à W(s) + SiHF₃(g) + 3.5H₂(g) + 2SiF₄(g) + HF(g). Here, we demonstrated that sub-stoichiometric silicide, MoSi_x (x=0.4 – 1.1), can also be selectively deposited on a nanometer scale on H-terminated Si (001) but not on silicon oxide and silicon nitride using MoF₆ and Si₂H₆.
X-ray photoelectron spectroscopy (XPS) was used to investigate the chemical composition of MoSi_x at each experimental step. The growth rate of MoSi_x on Si was ~0.8 Å/cycle or higher thus even 5 selective ALD cycles are sufficient for deposition of contacts. By dosing extra Si₂H₆ pulses after 5 ALD cycles, more Si could be selectively inserted into the film. To confirm an in-situ selective deposition as well as the thickness of the film, MoSi_x was deposited on a sample patterned with SiO₂ and Si₃N₄ and cross-section of the patterned sample was observed using tunneling electron microscope (TEM). From the TEM image, selectivity of MoSi_x on Si over SiO₂ and Si₃N₄ was 100%. From in-situ STM, MoSi_x on Si had a conformal and atomically flat surface with root mean square (RMS) roughness of 2.8 Å. Post-annealing in a ultra-high vacuum at 500°C for 3 mins further decreased the RMS roughness to 1.7 Å. A 900°C spike anneal on the MoSi_x film under the 5% H₂/N₂ atmosphere showed RMS roughness of 4.75 Å measured by ex-situ AFM. A resistance of the 900°C annealed MoSi_x film was obtained using 4-probe measurement. The resistance of the film was determined to be ~500 µohm-cm using a sheet approximation model. The high selectivity achieved on patterned samples shows that this process should be applicable for selective contact silicide deposition on the nano scale.

Nonvolatile spintronics based VLSIs, which are composed of memory cells of magnetic tunnel junctions (MTJ) with high endurance and high speed operation, are attracting much interest for realization of low power consumption edge devices with the arrival of the IoT era [1-3]. Perpendicular anisotropy CoFeB-MgO based MTJ (p-MTJ) with a synthetic ferrimagnetic (SyF) reference layer is a building block in the nonvolatile memory cells [4,5]. Thermal tolerance for annealing at temperature of 400C is required for the integration of the p-MTJs using standard CMOS back-end-of line process. We have demonstrated 10 nm diameter CoFeB-MgO based p-MTJs with the thermal tolerance of 400C [7]. Here, we review development in the p-MTJs [8-10]. In particular, we describe about the material design knowledge of the controlling boron composition of CoFeB free layer, variation of magnetic properties in the reference layer by high temperature annealing, and dependence of the MTJ properties on the sputtering gas species.
This work was supported by STT-MRAM R&D program under Industry-Academic collaboration of CIES consortium, JSPS-EPSRC Core to Core Program, JST-ACCEL, and JST-OPERA.

References:
[1] H. Ohno et al., Tech. Dig. -Int. Electron Devices Meet. 2010, 9.4.1.
[2] T. Endoh et al., IEEE J. Emerging and Selected Topics in Circuits and Systems, Vol. 6, 109 (2016).
[3] T. Hanyu et al., Proceedings of the IEEE, 104, 10, pp.1844-1863 (2016).
[4] S. Ikeda et al., Nature Mater. 9, 721 (2010).
[5] H. Sato et al., Jpn. J. Appl. Phys. 56, 0802A6 (2017).
[6] H. Sato et al., Jpn. J. Appl. Phys. 53, 04EM02 (2014).
[7] H. Honjo et al., 2015 Symp. on VLSI Tech. Dig. of Tech. Paper 2015, T161.
[8] H. Honjo et al., IEEE Trans. Mag. 52, 3401104 (2016).
[9] H. Honjo et al., AIP Adv. 7, 055913 (2017)/.
[10] H. Honjo et al., IEEE Trans. Mag. 53, 2501604 (2017).

The introduction of functionally improved materials such as magnetic heterostructures in magnetic tunnel junctions (MTJs) is a major driver to enable the continued down-scaling of circuit density and performance enhancement in logic and memory devices beyond the roadmap. In this talk, I will discuss current research advances in multifunctional and complex material systems, especially in engineering and patterning of complex stacks of thin films at the atomic scale.
Understanding and control of the factors affecting the interfacial phenomena at the CoFeB|MgO interface in a MTJ, from which the perpendicular magnetic anisotropy (PMA) of the CoFeB originates, are crucial to the realization of MTJ’s full potential. Efficient manipulation of PMA using an applied voltage, known as the voltage-controlled magnetic anisotropy (VCMA) effect, offers significant energy savings over electric-current-controlled alternative memory devices. Ab initio studies in the literature revealed a dependence of the VCMA effect on the oxidation state of interfacial Fe atoms in an Fe/MgO interface and on the heavy metal insertion layers at the CoFeB/MgO interface. This work addresses experimentally the dependence on the VCMA effect of oxide and metallic insertion layers in the MTJs. For oxide insertion layers, an atomic layer deposited lead zirconium titanate (PZT) layer in a MgO/PZT/MgO structure resulted in a 40% increase in the VCMA coefficient, despite the PZT layer being amorphous. For metallic insertion layers, Mg was found to be the most effective and a 1.1-1.3nm layer improved the VCMA coefficient by more than a factor of 3 and gave rise to the highest perpendicular magnetic anisotropy and saturation magnetization, as well as to the best CoFe and MgO crystallinity. These results demonstrate that a precise control over the material’s type and oxidation level in the MTJ is crucial for the development of electric-field-controlled perpendicular magnetic tunnel junctions with low write voltages.
Finally, to address the high density integration challenges of MTJs, a generalized methodology, combining thermodynamic assessment and kinetic verification of surface reactions, will be presented to define atomic layer etching processes that enable the patterning of these complex magnetic and noble metal heterostructures, including etching efficacy, directionality, and selectivity at the atomic scale.

Emerging memories have the potential to disrupt the memory hierarchy if they satisfy stringent requirements needed to integrate them into a high-density memory. As traditional memory ( DRAM and NAND) scaling is becoming increasingly difficult, various emerging memories are being considered as options for future memory scaling as well as for niche applications in compute systems. In this talk we will specifically discuss traditional memory scaling issues, fundamental limitations, scaling and integration challenges associated with emerging memories like Ox-ReRAM, Metal-ReRAM and STTRAM.

Redox-based resistive random access memories (ReRAM) are one of the key technologies for revolutionizing the memory device market in the near future. The performance of ReRAM devices position them as ideal candidates for Storage Class Memories, whose purpose is to fill the cost-performance gap between the DRAM and NAND flash technologies. Tantalum oxide (TaO_x) is one of the most promising materials for the integration as an insulator in ReRAM devices, showing high endurance and high switching speed. The resistive switching in TaO_x-based devices is commonly explained by the filamentary valence change mechanism, in which the formation / dissolution of a conductive filament plays a key role in switching between different resistance states. However, the filament structure, its exact composition and its impact on the performance of the devices are still a matter of debate. We targeted these questions by performing a detailed study of the electronic transport through conductive filaments in TaO_x-based ReRAM devices in the low-resistance state (LRS or ON state) at temperatures from 300 K down to 2 K. To further understand the origin of the transport properties of the filaments, we also measured, in the van der Pauw (vdP) geometry, substoichiometric TaO_x thin films which, for certain compositions, exhibit the same transport behavior as conductive filaments in the ReRAM devices. Thus, by studying the substoichiometric TaO_x films, it was possible to learn more about the conduction mechanisms in the filaments.
The conductance of the TaO_x ReRAM devices shows two different regimes in the measured temperature range. At higher temperatures, the conductance exhibits a T ^1/2 dependence, while at lower temperatures, an exp(–T ^1/2) dependence is observed. The temperature range where the transition between the two regimes takes place varies slightly from device to device. A positive magnetoresistance is observed in the low temperature regime, and it decays exponentially with increasing temperature. These features were also observed in the substoichiometric TaO_x films with x ∼ 0.5, both for conductance and for magnetoresistance. For these films, Hall measurements give a very high carrier concentration of the order of 10²² cm^-3 and a low Hall mobility of 0.1 cm²V^-1s^-1. The carrier concentration is of the same order of magnitude as the one measured in a reference Ta film. Furthermore, this Ta film shows the same distinctive T ^1/2 behavior corresponding to the aforementioned high temperature regime of the conductance in the TaO_x devices and vdP samples. This T ^1/2 behavior is commonly reported for disordered metals where quantum corrections to the conductivity dominate the transport. Based on these experimental findings we propose a model where the transport properties of both TaO_x ReRAM devices and TaO_x vdP samples are determined by a percolation path of disordered Ta granules.

Resistive switching (RS) plays an important role of Resistive Random Access Memory (ReRAM). The formation and rupture of conductive filaments have been widely accepted as an origin of RS mechanism especially in binary Transition Metal Oxides (TMOs). “Forming” by applying electrical stress to a pristine cell is an initial process generally required to create conductive filaments in TMO layers between top and bottom metal electrodes. The forming exhibits some analogies with dielectric breakdown of thin SiO₂ films [1]. In this study, we examine Time-Dependent Forming (TDF) characteristics in Pt/NiO/Pt RS cells.
Two kinds of Pt bottom electrode (BE) on a SiO₂/p-Si substrate were prepared, deposited either by Electron Beam (EB) evaporation or RF Sputtering (SP). A sample with the Pt/NiO/Pt cells using Pt BE deposited by EB or SP is referred to as EB-Pt samples or SP-Pt samples, respectively. A NiO film as a resistance change layer was deposited on the BE by rf reactive sputtering. Pt top electrodes were deposited on the NiO layer by EB evaporation. The time to forming (t_form) in the cells was measured while keeping a constant applied voltage. Cell resistance remains almost unchanged before forming. After forming, all of the cells in both samples were confirmed to show repeatable RS characteristics.
Cross-sectional Transmission Electron Microscopy (TEM) uncovers that Pt BE and NiO layers in EB-Pt samples contain granules, and that those in SP-Pt samples exhibits a columnar polycrystalline structure with a grain diameter of tens of nm. Moreover, the layers in EB-Pt samples exhibit diffraction peaks by both (111) and (200) planes and columns of the layers in SP-Pt samples are preferentially oriented to the [111] direction as confirmed by X-ray diffraction curves. NiO crystallinity is turned out to strongly depend on the BE crystallinity [1].
TDF measurements reveal that the slope of Weibull distribution (Weibit) of t_form is clearly different between EB-Pt samples (1.5) and SP-Pt samples (0.9). These values are independent of NiO thickness, applied voltage, initial resistance, and surface roughness of cells. Furthermore, the Weibits normalized by cell sizes according to the area scaling law overlay each other. These results indicate that formation of the filaments at forming follows a weakest-link theory, and that weakest spots are almost randomly distributed in a NiO film according to Poisson statistics, each of which can contribute conductive paths locally generated by an electrical stress.
We also confirm inverse correlation between variation of initial resistance and that of time to forming. The different values of the slope of Weibits between EB-Pt and SP-Pt samples are considered to originate from a difference of NiO crystallinity. These results suggest that distribution of grain boundaries is the key to form the conductive filaments in NiO by the forming.
[1] Y. Nishi, et al, J. Appl. Phys. 120, 115308 (2016).

In the next generation of digital technology, which includes forward-looking consumer electronics and the internet-of-things, non-volatile memory will play a decisive role where flash memory is currently the key player. However, as flash memory fails to meet the commercial demands of scalability and endurance, the industry is looking for an alternative where resistive memory devices are leading candidates. Organic resistive memories are of particular interest because of their low-cost solution-processability and synthetic tunability. However, to date, they have been lacking reproducibility, endurance, retention, switching speed, and the mechanistic understanding required for commercial translation. In this report, we demonstrate a resistive memory device with a spin-coated active layer of a transition metal complex where we have achieved unprecedented reproducibility (~350 devices), fast switching (<30 ns), excellent endurance (~10¹² cycles), and retention (>10⁶ s). We establish a definitive switching mechanism via in-situ Raman and UV-Vis-spectroscopy alongside spectroelectrochemistry and quantum chemical calculations and find that the redox state of the ligands determines the switching states of the device while the counterions control the hysteresis. Both in terms of device performance and understanding, this study presents a significant step forward in organic resistive memory technology [1,2].

[1] Goswami, Sreetosh, et al. "Robust resistive memory devices using solution-processable metal-coordinated azo aromatics." Nature Materials (2017), DOI: 10.1038/NMAT5009
[2] Valov, Ilia, and Michael Kozicki. "Non-volatile memories: Organic memristors come of age." Nature Materials (2017): nmat5014

Resistive switching (RS) phenomenon of TiO₂-based resistive random access memory (ReRAM) can be explained with the formation and rupture of a conductive filament (CF) in the TiO₂ layer. However, the origin of a CF is still unknown and switching mechanism has not been fully clarified yet. In this work, a transition to a resistance state different from low resistance state (LRS) or high resistance state (HRS) at specific forming processes in Pt/TiO₂/Pt stack structures was discovered.
TiO₂ layers were deposited on Pt(70 nm)/Ti(5 nm)/SiO₂/Si substrates by a reactive radio-frequency sputtering method. The thickness of the TiO₂ layer was varied from 10 nm to 40 nm. Pt top electrodes with a 100 µm diameter were deposited by electron beam evaporation on the TiO₂ layer. The transitions at forming processes were investigated by DC voltage or current sweeping to the cells.
Cells with TiO₂ thickness of 40 nm showed a transition to LRS (less than 100 Ω) by voltage sweeping under 10 mA compliance current, followed by typical RS operation. On the other hand, the cells exhibited a transition to resistance state with large resistance (about 1 kΩ to 1 MΩ) compared to LRS by either current sweeping or voltage sweeping under 0.1 mA or 1 mA compliance current, followed by the transition to LRS by voltage reapplication and subsequent RS performance. This characteristic resistance state with a large resistance compared to LRS is designated as “semi-HRS: SHRS”. We clearly observed that the thicker TiO₂ thickness became, the more frequently SHRS tended to appear after current sweeping.
As another feature of SHRS, the cell resistance in SHRS after current sweeping gradually increased as the applied voltage increased, which is different from conventional HRS before resistance state changes to LRS. To clarify the main driving force of the resistance increase, the maximum (stop) voltage to the cells of positive or negative voltage sweeping increased. The cell resistance was confirmed to increase after each voltage sweeping by a certain voltage in both (positive and negative) cases. This result indicates that the resistance increase in SHRS originates from current flow through the cells instead of the polarity of electric field applied to the cells. In other words, Joule heat caused by the current flow is heavily involved in the state change of a CF in a TiO₂ layer.
Here, a CF is considered to be a row of oxygen vacancies (V_o). Resistance increase were observed owing to possible reduction in a CF width because Joule heat enhanced concentration diffusion of V_o to the horizontal direction. Furthermore, inhomogeneous distribution of V_o density around a CF in a TiO₂ layer along the thickness direction may cause the difference of SHRS appearance after the forming processes to suppress overcurrent.

To date, transition metal dichalcogenides (TMDs) have been synthesized on a variety of substrates including SiO₂, quartz, sapphire, mica, and gold foils. However, synthesis on these substrates typically leads to polycrystalline films due to the random orientation of the triangular domains. Epitaxial growth has been achieved on annealed sapphire substrates, but sapphire is not a suitable substrate if one wants to explore 2D/3D vertical semiconductor heterostructures. III-nitrides, on the other hand, can be an active component of a 2D/3D vertical heterostructure and also possess a small lattice mismatch with a variety of TMDs. As a result, synthesis of TMDs on III-nitrides can lead to epitaxial growth of aligned triangles on a 3D semiconductor substrate. In this talk, we will discuss the synthesis of molybdenum disulfide (MoS₂) on n-type and p-type GaN via powder vaporization (PV). We will show epitaxial growth of aligned MoS₂ triangles on both n-type and p-type GaN and the importance of sample preparation in achieving epitaxial growth. We will also present our findings involving the characterization of the MoS₂ triangles using techniques such as scanning electronic microscopy (SEM), atomic force microscopy (AFM), Raman spectroscopy, photoluminescence (PL), conductive atomic force microscopy (CAFM), x-ray photoelectron spectroscopy (XPS), modeling, and transmission electron microscopy (TEM).

Molybdenum disulfide (MoS₂) is one of the most investigated 2D crystals. In order for MoS₂ to be effectively used in electronic devices, such as top-gate field-effect transistors (FETs), a high-k dielectric layer must be deposited directly onto the 2D material – either as an integral part of the device or as a protective layer. The most common method to deposit a high-k dielectric is using atomic layer deposition (ALD). However, thin ALD films are not possible due to the inability of precursor molecules to uniformly react with the inert basal plane of MoS₂. In order to achieve thin high-k dielectrics on MoS₂ either the surface must be functionalized, a buffer layer must be first deposited, or a different method of film deposition needs to be employed. Recently, it has been shown that ultrathin high-k dielectrics can be realized on MoS₂ using plasma-enhanced ALD (PEALD); however, the mechanism of the film growth and impact of the PEALD process, including its effects on the monolayer MoS₂ crystal structure, have not been examined thoroughly. In this work, these effects are studied for the PEALD process on mono- and bi-layer MoS₂ using Raman spectroscopy, photoluminescence (PL), and electrical characterizations.
In order to understand the impact of the PEALD process on MoS₂ as well as gain insight on the PEALD growth mechanism, Raman and PL spectra were collected on chemical vapor deposition (CVD) grown monolayer and bi-layer MoS₂. Raman and PL were carried out using a WiTec Raman setup at a wavelength of 532 nm. Spectra were collected at room temperature (under vacuum (in a N₂ environment) and in ambient) and at liquid N₂ temperatures. Characterization of the MoS₂ was performed before and after the deposition of either ALD or PEALD HfO₂ – study of film growth with and without the plasma enhancement provided further insight into the impacts of the plasma process. Raman spectra indicate that the PEALD process is damaging the top MoS₂ layer, but is leaving the underlying layers intact. In addition to the spectroscopic studies, electrical characteristics of back-gated MoS₂ FETs from CVD-grown mono- and bi-layer MoS₂ were also tested before and after either the deposition of ALD or PEALD HfO₂ to examine the impact of the process on the electrical properties of the 2D crystal. This work aids in the attainment of ultra-thin high-k dielectrics on mono- and bi- layer MoS₂ and thoroughly examines the impact that the PEALD process has on their crystal structure and electrical properties.

Molybdenum disulphide (MoS₂) is one of the more promising channel materials for field effect transistor devices and have recently been investigated due to its high current density, excellent electrostatic integrity, large on/off ratio (>10⁸), high carrier mobilities, and good electrical conductivity (~0.03 Ω^-1 cm^-1) when used as a monolayer (0.65 nm). However, depositing a large uniform area of MoS₂ remains challenging, and most of the above properties deteriorate when layer thickness increases more than 2 to 3 layers. Here we show, despite higher thickness (20 nm), uniformly deposited PLD grown MoS₂ can show significantly high mobilities as a result of the substrate choice. Boron doped p-type (<100>), phosphorous doped n-type (<100>), polysilicon, sapphire (c-axis oriented), and Si/SiN (polycrystalline) are chosen as model substrates to study the carrier mobilities of MoS₂ films influenced by substrate selection. We observe MoS₂ grown on all type of silicon substrates show significantly higher mobilities (3 to 7.5×10³ cm²/V.s) than grown on the insulating substrates where mobilities are in the range of 5 to 50 cm²/V.s at 300 K. Cross sectional transmission electron microscopy (TEM) reveals that due to the formation of out of plane twin boundary at the MoS₂-silicon interface the mobility of MoS₂ significantly increases as twin boundaries are the weak scattering centers of the charge carriers. Reduced mobility of MoS₂ on insulating substrates (sapphire and Si/SiN) is due to the formation of layer growth morphology where dislocation and stacking faults are prevalent. These defects are the coulomb scattering centers of the carrier pathways which majorly affects the mobility of the carriers¹. We believe this important result has a rich implication towards MoS₂ based electronic devices for future applications².

References
Goswami et.al., “Effect of interface on mid-infrared photothermal response of MoS₂ thin film grown by pulsed laser deposition” Nano Research, 10 (10) (2017), 3571-3584.

Liu et.al., “Direct-current triboelectricity generation by sliding-Schottky nanocontact on MoS₂ multilayers” , Nature Nanotechnology, 2017 (in press)

Tin sulfides constitute a diverse group of compounds containing tin (Sn) and sulfur (S) elements and can exist in a variety of phases and polytypes. A subset of these phases and polytypes take the form of layered two-dimensional (2D) structures that give rise to a wide host of electronic and optical properties. Hence, achieving control over the phase and polytype is necessary to utilize this wide range of properties exhibited by the compound. Herein, we demonstrated the phase-controlled growth of 2D tin sulfides, SnS₂ and SnS, on silicon dioxide (SiO₂) substrates by vapor-phase method. While the structural, chemical, optical and electronic properties of both the SnS₂ and SnS phases were studied by using state-of-art experimental and theoretical techniques, special attention was given to the SnS₂ phase. High-resolution annular dark-field (ADF) scanning transmission electron microscope (STEM) analysis indicate that the SnS₂ crystals crystallize in 1T phase, which is in consistent with the ab-initio density functional theory (DFT) calculations predicting that SnS₂ stabilizes the 1T phase at ground state. Photoluminescence (PL) and ultraviolet-visible (UV-vis) spectroscopy measurements suggest that the SnS₂ crystals have an indirect band gap of 2.20 eV and 2.35 eV, respectively, which is in good agreement with the DFT-calculated band gap of 2.31 eV. The electrical transport measurements performed on back-gated field-effect transistors (FETs) exhibit n-type semiconductor characteristics of the SnS₂ crystals. High-angle annular dark-field (HAADF) STEM imaging and STEM energy dispersive X-ray (EDX) chemical analysis demonstrate that the SnS₂ crystals are chemically homogeneous with a stoichiometric S/Sn atomic ratio of ~ 2. Electron energy loss spectroscopy (EELS) and X-ray photoelectron spectroscopy (XPS) analysis present the characteristic Sn and S peaks of SnS₂, confirming the phase purity of the SnS₂ crystals. Ultraviolet photoelectron spectroscopy (UPS) measurements of the SnS₂ crystals provide an ionization potential of 7.51 eV, which is in a perfect agreement with the DFT calculations. Raman spectroscopy in conjunction with the ab-initio DFT calculations reveal the characteristic first-order and second-order Raman modes of the 1T phase of the SnS₂ crystals. Angle-resolved polarized Raman spectroscopy (ARPRS) mappings with different polarization angles show unique edge features of the SnS₂ crystals. Furthermore, we found that the SnS₂ can occasionally crystallize in the 4H phase in our growths. The 4H-SnS₂ was identified by both the measured and calculated Raman spectra. Finally, we discussed possible strategies for the polytype-engineering in 2D SnS₂.

In this talk, I will present our recent results in the synthesis of wafer-scale high-quality two-dimensional transition metal dichalcogenide (TMDC) materials with precisely controlled physical features (including composition and layer number) using self-limiting chemical vapor deposition processes. We may also perfectly transfer the synthesized wafer-scale films onto any arbitrary substrates without compromising the quality and surface smoothness. With this synthetic and transfer capabilities, we have systematically studied the electronic, optical, thermal, and catalytic properties of 2D TMDC materials, and developed a variety of novel devices.

The two-dimensional atomic crystals (2DACs) of transitional metal dichalcogenides (e.g., MoS2, MoSe2, WS2 and WSe2) have attracted intense recent interest. With a nearly perfect crystalline structure and dangling bond free surface, these atomically thin materials have emerged as a new material platform for fundamental materials science and diverse technology opportunities at the limit single atomic thickness. To explore the full potential of these 2DACs requires the integration of highly disparate materials and the construction of heterostructures with designed spatial modulation of chemical compositions and electronic structures, much like the traditional semiconductor heterostructures and superlattices that form the fundamental material foundation for all modern electronic and optoelectronic devices. The traditional material integration approach to create the heterostructures from such atomically thin materials can often lead to considerable damage to the lattice structure and compromise their intrinsic properties. Considerable efforts have been devoted to produce various 2DAC heterostructures by using either a van der Waals assembly approach or synthetic chemistry approach. Here I will discuss our recent efforts in exploring various 2DAC heterostructures and devices.

Two-dimensional (2-D) semiconductors exhibit excellent device characteristics, as well as novel optical, electrical, and optoelectronic characteristics. In this talk, I will present our recent advancements in defect passivation, contact engineering, surface charge transfer doping, ultrashort transistors, and heterostructure devices of layered chalcogenides. We have developed a defect passivation technique that allows for observation of near-unity quantum yield in monolayer MoS₂. The work presents the first demonstration of an optoelectronically perfect monolayer. Forming Ohmic contacts for both electrons and holes is necessary in order to exploit the performance limits of enabled devices while shedding light on the intrinsic properties of a material system. In this regard, we have developed different strategies, including the use of surface charge transfer doping at the contacts to thin down the Schottky barriers, thereby, enabling efficient injection of electrons or holes. We have been able to show high performance n- and p-FETs with various 2D materials, including the demonstration of a FET with 1nm physical gate length exhibiting near ideal switching characteristics. Additionally, I will discuss the use of layered chalcogenides for various heterostructure device applications, exploiting charge transfer at the van der Waals heterointerfaces.

With a direct band gap of 1.88eV and a reasonable carrier mobility of ~100 cm²/(Vs)[1], 2D MoS₂ is a promising candidate for next generation semiconductor devices. Despite those excellent features, intrinsic defects reduce carrier mobility and quench photoluminescence. Sulfur vacancies are the dominant defect. Therefore, passivation of the Sulfur vacancy is highly useful. Here, we investigate possible passivation schemes which have been proposed by experimentalists. Unlike in HfO₂, substitutional doping to complete a closed shell [2] does not passivate because the Mo-S bond is not ionic, so there is no atomic relaxation around the vacancy due to its charge state. An alternative is to use molecules which might be chemically adsorbed at the vacancy. The dehydrogenated cysteine acid cation [3] and neutral O₂ [4] might combine with the vacancy and move the Fermi level to the middle of the gap. However, both of them give rise to localized states just above the valence band maximum (VBM). Finally we consider adsorption of organic super acid TFSI, which is strong protonating agent, and is known to greatly improve the PL efficiency [5]. We consider the effect of hydrogen. The vacancy has one doubly degenerate state of e symmetry at the VBM and a pair of doubly degenerate states of e symmetry in the upper gap, whose energy becomes split by occupancy. To avoid producing half-filled states in the gap, we need a spin-paired system with trigonal symmetry. Unlike in a-Si, the bonding in MoS₂ is multi-centered. Thus one Mo dangling bond does not bond to one H atom. We place three hydrogens with four electrons symmetrically around vacancy center, which is calculated to be an energetically favorable configuration. Each hydrogen bonds symmetrically to a Mo dangling bond, forming bonds and anti-bonds with the a₁ state and double degenerate e states which originally lie in the upper band gap [6]. The hydrogen forms a filled deep bonding state and an empty strongly anti-bonding state with a₁ symmetry. The anti-bonding state e_H* is pushed up to conduction band. The Mo d_xy, d_yz, d_xz and d_x²_-y² states form bonding states e_H with hydrogen, which are occupied by four electrons. These lie below VBM. Therefore the combination of three hydrogens and 4 electrons passivation produces a MoS₂ with a clear band gap, and the Fermi level in mid-gap. The mechanism will improve the performance of MoS₂.
1 B Radisavljevic, et al. Nature Nanotec, 6 147 (2011).
2 D Liu, et al. Appl. Phys. Lett. 103 183113 (2013).
3 D M Sim, et al. ACS nano 9 12115 (2015).
4 P K Gogoi,.. A T S Wee, PRL 119 077402 (2017);
Y Liu, P Stradins, S H Wei, Angew Chem Int Ed 55 965 (2016)
5 M Amani M,… A Javey, Science, 350 1065 (2015), Nanoletts 16 2786 (2016).
6 J Y Noh et al, Phys. Rev. B 89 205417 (2014).

Two dimensional (2D) semiconductors are promising materials for application in ultrascaled electronic devices.^[1] Tin sulfides are interesting layered semiconductors as they exist in different phases which exhibit different types of conduction. SnS₂ is a n-type semiconductor with hexagonal crystal structure while SnS is a p-type semiconductor with orthorhombic crystal structure.^[2] Chemical vapor deposition (CVD) is an alternative to grow 2D materials with monolayer control and large grain size (μm) over wafer scale.^[3] The CVD of tin sulfides using SnCl₄ and H₂S has been reported.^[4] However, the phases control of SnS₂ vs SnS was not understood and the layers were μm thick with uncontrolled grain orientations, resulting in insulating rather than semiconducting properties.^[4]
Insight on the phases control of SnS₂ and SnS is required to obtain pure phase while the nucleation and growth mechanisms need to be studied for the monolayer thickness scaling and grain orientation control. Therefore, we first investigate the process window of the tin sulfides CVD using SnCl₄ and H₂S on thermally grown SiO₂ at atmospheric pressure. For a H₂S/SnCl₄ flow ratio of 10, SnS is formed at temperatures higher than 450°C, while SnS₂ is formed at lower temperatures. Interestingly, for a H₂S/SnCl₄ flow ratio of 20, SnS is formed at temperatures higher than 350°C with SnS₂ formed at lower temperatures. This mechanism is attributed to the catalytic decomposition of H₂S upon SnS₂, whereby H₂ and sulfur are generated. We propose that SnS₂ is reduced to SnS by the generated H₂ if large enough H₂S/SnCl₄ flow ratio and sufficiently high temperature are used, which provide sufficient reductant and thermal budget for the reduction of Sn⁴⁺, i.e. chemisorbed SnCl₄ surface species and/or possible intermediate SnS₂. Then, the n-type behavior of SnS₂ and p-type behavior of SnS are verified using back-gated FETs.
Secondly, similar nucleation and growth behaviors of SnS₂ and SnS on SiO₂ are observed. A low nuclei density (10⁵/cm²) and a large domain size of several μm for SnS is obtained at 400°C because of the large surface diffusion length of adatoms. Isolated 2D crystals of several monolayers thick are formed with basal plane parallel to the substrate. These 2D crystals preferentially grow laterally due to a higher reactivity of the crystal edges while the vertical growth can hardly be observed due to the relative inertness of the basal plane. Interestingly, the thickness of 2D SnS on SiO₂ can be scaled by decreasing the deposition temperature. We propose that the thickness of 2D SnS is determined by the extent of agglomeration, which is impacted by temperature and hydrophilicity of substrate. This insight may guide the SnS₂ and SnS CVD towards monolayer growth control.
[1] M. Chhowalla et al., Nat. Rev. Mater. 2016, 1, 16052
[2] J. Ahn et al., Nano Lett. 2015, 15, 3703-3708
[3] Kang et al., Nature 2015, 520, 656-660
[4] L. Price et al., Chem. Mater. 1999, 11, 1792-1799

Two-dimensional (2D) transition metal dichalcogenide (TMDC) semiconductors are potential candidates as channel materials for future CMOS technology. A major roadblock in realizing a technologically relevant MOSFET with 2D materials is the lack of methods of creating fixed, controllable doping, which is a critical element in MOSFET design, especially for realizing low resistance source and drain contacts. This work investigates doping techniques such as spin-on-diffussant (SoD) processing and ion implantation to realize doping in 2D materials such as MoS2 and WSe2.
For both materials (flakes and large area CVD-grown), significant changes in the current-voltage characteristics is observed with commercially available phosphorus-containing SoD. By spin-coating and curing at up to 1000 C, the ON state current is improved to ~100 uA/um while the gate modulation of the channel current is almost completely suppressed. With MoS2 which typically shows n-type behavior, only the OFF-state current is affected. On the other hand, WSe2, which typically shows ambipolar behavior, the I-V properties show a dependence with anneal temperature: at 500 C, the n-branch and the OFF-state currents are significantly suppressed while the p-branch current significantly increases; for annealing at 1000 C, the ON-state current remains the same while the OFF-state current increases by a few orders of magnitude. Raman measurements show that the characteristic peaks for the TMDC are not significantly affected by the SoD processing, indicating preservation of the TMDC crystal structure. This, combined with the gate-field independent conductance indicates a change of the background charge density in TMDC, and is an encouraging result for contact-region doping in TMDC.
With ion-implantation, directly implanting the TMDC with species such as P, N and As with ion energies 5-20 keV is observed to lead to significant crystal damage, indicated by a decrease in the characteristics Raman peak intensity as a function of ion energy. Electrically, both the OFF and the ON state currents are degraded, likely due to the amorphization of the TMDC. Post-implant anneals up to 1000 C are observed to not significantly affect the characteristics. SIMS measurements indicate the presence of the ion species inside the MoS2, suggesting the anneal temperatures are insufficient for dopant activation. Indirect ion implantation approaches such as implanting the substrate prior to MoS2 growth are explored. XPS analysis shows barely detectable levels of the ion species inside the MoS2, consistent with the relatively lower effective ion dose achieved with this method. However, electrical characterization shows shifts in the threshold voltage, suggesting modifications in the background charge in the MoS2, without degradation in the ON or OFF-state currents. A statistical improvement in carrier mobility is also observed with substrate implantation, likely due to modification of the charged impurity distribution.

HfS2 and SnS2 have been proposed as components of stacked layer heterojunction Tunnel Field Effect Transistors (TFETs) in combination with WSe2, because of their suitable band offsets. It is calculated that both semiconductors have quite small effective masses of order 0.2 – 0.3 and thus high carrier mobilities of order 1000-2000 cm2/V.s, which arises from the largely p-like character of their band edges. It is also because HfS2 has largely non-polar bonding, despite Hf being a very electropositive metal. The intrinsic point defects are also calculated. The key defects are the S vacancy, which acts as a shallow double donor in HfS2 and slightly deep double donor in SnS2, plus the adatom S interstitial. Substitutional dopants at the S site a found to be unreconstructed and shallow, unlike in black phosphorus, making them ‘well behaved’ as semiconductors. It is argued that HfS2 is the preferred material over SnS2 for CVD synthesis, because HfS2 is stable over a wide range of chemical potentials and has easier Hf-based precursors, whereas SnS2 has a limited range of chemical stability due to existence of SnS. Thus HfS2 is an effective semiconductor for TFETs like InSe and unlike b-P.

The current electronics industry has been completely dominated by Si-based devices due to its exceptionally low materials cost. However, demand for non-Si electronics is becoming substantially high because current/next generation electronics requires novel functionalities that can never be achieved by Si-based materials. Unfortunately, the extremely high cost of non-Si semiconductor materials prohibits the progress in this field. I will discuss about my group’s efforts to address these issues. Our team has recently conceived a new crystalline growth concept, termed as “remote epitaxy”, which can copy/paste crystalline information from the wafer remotely through graphene, thus generating single-crystalline films on graphene. These single-crystalline films can be easily released from the slippery graphene surface by a 2D material-based layer transfer technique. Therefore, the remote epitaxy technique can produce expensive non-Si semiconductor films with unprecedented cost efficiency with the potential to reuse graphene-coated substrates while allowing additional flexible device functionality required for current ubiquitous electronics. I will discuss about our demonstration on remote homoepitaxy and transfer of GaAs, InP, GaP, LiF, and SrTiO₃. And the principle of remote epitaxy of those various materials through graphene will be discussed.

Single monolayer transition metal dichalcogenides (TMDs) exhibit exceptionally strong photoluminescence dominated by a combination of distinct neutral and charged exciton contributions. The dielectric screening is very low due to their two-dimensional character relative to bulk material, and their properties are thus strongly affected by their immediate environment. Because the exciton and trion binding energies are very large (~ 600 meV and ~30 meV, respectively), these characteristic emission features persist to room temperature. We show here that the surface charge associated with ferroelectric domains patterned into the lead zirconium titanate (PZT) film with a conductive atomic force microscope control the lateral spatial distribution of neutral and charged exciton populations in the adjacent WS₂ monolayer [1]. This is manifested in the intensity and spectral composition of the photoluminescence measured in air at room temperature from the areas of WS₂ over a ferroelectric domain with polarization dipole pointed either out of the surface plane or into the surface plane. Samples were fabricated by mechanically transferring large area monolayer WS₂ grown by a CVD process onto a 100 nm thick (PZT) film on a conducting n-type strontium titanate wafer. The photoluminescence spectra from areas of the WS₂ over up polarization domains in the PZT are dominated by neutral exciton emission, while those over down domains are dominated by trion emission, consistent with the corresponding charge produced by the domains at the WS₂ / PZT interface. The hysteretic character of ferroelectric materials means that the TMD properties can be selectively reconfigured in a nonvolatile manner by changing the state of the ferroic substrate. This approach enables spatial modulation of TMD properties with a spatial resolution determined by the polarization domains in the underlying ferroelectric layer, with the potential for fabrication of lateral quantum dot arrays or p-n junctions in any geometry of choice.

[1] C.H. Li, K.M. McCreary and B.T. Jonker, ACS Omega 1, 1075 (2016).
This work was supported by core programs at NRL and the NRL Nanoscience Institute, and by the Air Force Office of Scientific Research #AOARD 14IOA018-134141.

Two-dimensional (2D) van-der-Waals (vdW) materials such as graphene, transition metal dichalcogenides (TMDCs), and hexagonal boron-nitride (h-BN) have received an increasing level of interest due to their unique properties. The electronic and optical properties of these materials depend on the number of stacking layers and substrate type and are mainly governed by vdW interactions between layers. An efficient integration of 2D functional materials with three dimensional (3D) substrates remains a challenge and our recent study demonstrates successful growth and device characterization of a single layer (SL) of molybdenum disulfide (MoS₂) on a GaN substrate through vdW epitaxy for vertical transistor applications [1]. In that work, we observed that the SL-MoS₂ acts as an interfacial barrier layer and modulates (to a small extent) the threshold voltage and on-current during device operation, suggesting a need for multilayer (ML) MoS₂ growth on GaN [2].
Motivated by these observations, in this study, we perform a systematic first-principles study of layer-dependent structural and electronic properties of MoS₂ on a GaN substrate. Material properties such as layer binding energies, formation energies, in-plane lattice constants, and vdW spacing between the layers have been computed and compared to experimental data. Further, we also attempt to establish a correlation between the calculated and observed electronic properties such as band gap, band alignment, work function, and Schottky barrier height (SBH). Finally, a qualitative understanding of the required critical 2D thickness for an appreciable on-current in a 2D/3D system will be presented.

1. Ruzmetov, D.; Zhang, K.; Stan, G.; Kalanyan, B.; Bhimanapati, G. R.; Eichfeld, S. M.; Burke, R. A.; Shah, P. B.; O’Regan, T. P.; Crowne, F. J.; Birdwell, A. G.; Robinson, J. A.; Davydov, A. V.; Ivanov, T. G. Vertical 2D/3D Semiconductor Heterostructures Based on Epitaxial Molybdenum Disulfide and Gallium Nitride. ACS Nano 2016, 10, 3580–3588.
2. O’Regan, T. P. Ruzmetov, D.; Neupane, M. R., Burke, R. A., Herzing, A. A.; Zhang, K.; Birdwell, A. G.; Taylor, D. E.; Byrd, E. F. C.; Walck, S. D.; Davydov, A. V.; Robinson, J. A.; Ivanov, T. G. Structural and Electrical Analysis of Epitaxial 2D/3D Vertical Heterojunctions of Monolayer MoS2 on GaN. Appl. Phys. Lett. 2017, 111, 051602.

Two-dimensional (2D) layered materials have emerged as potential platforms for novel electronic and optical devices, especially the semiconducting 2D transition metal dichalcogenides (TMDs) and their heterostructures. However, significant synthesis and processing challenges will be reviewed that limit their development, including wafer-scale, bottom-up synthesis of uniform layers of crystalline 2D materials that are comparable in quality to exfoliated flakes of bulk materials. Few-layered, as-synthesized crystals of 2D TMDs display remarkable heterogeneity on both the atomistic level, including vacancies, dopants, and edge terminations, and on the mesoscopic length scale involving misoriented grains, layer orientations, and interactions with substrates and adsorbates. This heterogeneity can strongly influence the structure and electronic properties in 2D materials, offering at the same time a serious challenge to synthesis control for reliable properties and a tremendous opportunity to tailor functionality.
Here we will present recent developments in both vapor-transport and laser-based synthesis and processing approaches for the synthesis of a variety of atomically-thin 2D crystals (e.g., MoSe₂, WS₂, Mo_[1-x]W_xSe₂, GaSe) and understanding of mechanisms for the introduction of heterogeneity during growth, including the incorporation of defects and dopants, the role of topology-induced strain, and the orientation of layers during heterostructure growth by van der Waals epitaxy (e.g., GaSe/MoSe₂). To provide rapid assessment of the effects of synthesis on the properties of 2D materials used for optoelectronic applications, laser spectroscopy-based characterization methods such as low-frequency Raman spectroscopy, low-temperature photoluminescence, and ultrafast pump-probe spectroscopy techniques are being developed to reveal different aspects relating synthesis and function, such as atomistic stacking configurations between layers, band gap shifts due to doping, the nature of defects, and quasiparticle dynamics. The prospects for use of these spectroscopic techniques as remote, real-time diagnostics will be discussed. These measurements are correlated with atomic-resolution electron microscopy to understand the exact nature, concentration, and density of defects as well as the evolution of preferred edges associated with changing crystal shapes during growth and etching. Associated theory and modeling is used to infer the responsible synthetic driving forces. Transport measurements with prototype devices are correlated to understand the effects on functionality.
Research sponsored by the U.S. Dept. of Energy, Office of Science, Basic Energy Sciences, Materials Science and Engineering Div. (synthesis science) and Scientific User Facilities Div. (characterization science). Throughout the presentation, facilities available for collaboration at the Center for Nanophase Materials Sciences (CNMS) user facility will be presented.

Over the past 50 years, Moore’s law has successfully predicted and motivated the scaling of the length scale of transistors on Si wafer. This continuous scaling and development of semiconductor technology have enabled an incredible growth of the computational power of personal electronics from generation to generation. However, several physical limitations, especially power dissipation, have halted this exuberant era for semiconductor manufacturing industry. Thus, the development of low-power consumption and non-volatile memory in nanoscale is becoming a critical key to trigger another technological evolution. Here, we demonstrate a low-voltage (1V) and non-volatile manipulation of ferromagnetism at room temperature via the heterostructure of Pt/Co_0.9Fe_0.1/Cu/Co_0.9Fe_0.1/BiFeO₃. BiFeO₃ (BFO) is a multiferroic material exhibiting two order parameters, ferroelectricity, and antiferromagnetism, above room temperature. It also shows a weak ferromagnetism (M_c) induced by the canted spin configuration described by the Dzyaloshinskii–Moriya (DM) interaction. Moreover, these ferroic orderings are strongly coupled. Thus one can switch the ferroelectric polarization (P) and the weak ferromagnetism (M_c) simultaneously by an electrical field. We utilized this electrically controllable M_c in BFO to manipulate the magnetic property of the CoFe layer and created a non-volatile low- and high-resistive state. Yet, to realize the sub-one-volt switching of ferroic ordering in BFO, we need to scale the thickness of BFO down to few nanometers range. In this work we will provide a comprehensive understanding of the evolution of ferroelectricity and antiferromagnetism in BFO as the scaling of thickness via several techniques including photoemission electron microscopy (PEEM), X-ray magnetic linear dichroism (XMLD), X-ray magnetic circular dichroism (XMCD), HR-transmission electron microscopy (HRTEM), and Piezo-force microscopy (PFM).
Finally, with this background knowledge, we are able to design a proper material combination to achieve one-volt switching of two resistive states at room temperature. Our results provide a solid building block for ultra-low power consumption spintronics beyond Moore’s law.

The famous phrase "the interface is the device" [1] is exemplified in two-dimensional (2D) materials, reminding us that the challenge of controlling the interface chemistry and structure is a differentiating opportunity for engineering 2D semiconductor devices. Nearby ions, molecules, or compounds have been demonstrated to dope 2D semiconductors without introducing chemical or structural defects, yet these surface charge transfer doping schemes employ molecular species that are overly sensitive to environmental changes such as temperature and humidity. [2] Here we report that controlling the stoichiometry of amorphous molybdenum oxide (MoO_x) deposited by atomic layer deposition (ALD) on monolayer MoS₂, a representative transition metal dichalcogenide (TMD), modulates its carrier density. Concurrently, MoO_x with a dielectric constant exceeding 5 encapsulates the TMD and mitigates the influence of defects. We employ a low-oxidation-state molybdenum precursor (Mo(NMe₂)₄) enabling ALD at temperatures below 100 °C to provide a encapsulation scheme for TMDs that is gentle and compatible with nanolithographic patterning [3]. X-ray photoelectron spectroscopy (XPS) reveals that the ALD oxidant (here H₂O and ozone) and process conditions control the MoO_x stoichiometry (film oxidation). Intrinsic properties including the optical absorption edge and resistivity vary monotonically with the oxygen content in MoO_x. To evaluate doping, we probe the MoS₂ carrier density with spectroscopic (Raman) and field-effect transistor (FET) measurements before and after ALD MoO_x deposition on monolayer (and few layer) MoS₂. Depending on the stoichiometry of the MoO_x dielectric overlayer, the threshold voltage of MoS₂ FETs shifts to the negative (V_th ≤ -75 V) or to the positive (V_th ≥ 80 V) with respect to the back gate voltage suggesting p- or n-type doping of the underlying TMD over a wide range (ΔN_D= 7×10¹² cm^-2). Interestingly, the effect of MoO_x on the carrier density and mobility in MoS₂ is reversible; selective etching of the MoO_x layer in KOH reproduces the initial current-voltage characteristics, and Raman spectra suggest that this process maintains the van der Waals interface without significant chemical changes. Combining control of carrier concentration with selected area deposition via lithography provides an attractive route to the formation of p-n junctions for logic and other applications.

[1] Kroemer, H. Nobel Lecture 2000.
[2] Schmidt, H.; Giustiniano, F.; Eda, G., Chem. Soc. Rev. 2015, 44, 7715-7736.
[3] Jurca, T.; Moody, M. J.; Henning, A.; Emery, J. D.; Wang, B.; Tan, J. M.; Lohr, T. L.; Lauhon, L. J.; Marks, T. J., Angew. Chem. Int. Ed. 2017, 56, 4991.

Due to their switchable polarization, ferroelectric materials have been used to modulate the electronic transport properties of two-dimensional (2D) semiconductors. Polarization reversal in ferroelectrics is typically realized via application of an electric field. Recently, it has been demonstrated that mechanical stress and change of chemical environment could also induce the polarization switching. In this work, we have demonstrated the optically-induced polarization switching in the hybrid MoS₂/BaTiO₃/SrRuO₃ tunnel junctions, which is realized via photo-absorption in 2D MoS₂. We have found that the switching time of the heterostructure highly depended on the light intensity. Based on the DFT (Density Function Theory) simulations, we attribute the optically-induced switching to the light absorption in the MoS₂ electrode via the dominant intra-layer excitons that eventually decay into inter-layer excitons resulting in the interfacial charge favoring polarization reversal. The observed effect should be a common phenomenon for the 2D/ferroelectric heterostructures, which would provide a viable way to modulate the functional properties of ferroelectric-based electronic devices remotely through optical illumination.

Multilayer transition metal dichalcogenides (TMDs) potentially provide opportunities for large-area electronics, including flexible displays and wearable sensors. However, most TMDs suffer from a Schottky barrier (SB) and non-uniform defects, which severely limit their electrical performances. We present a new chemical doping scheme to significantly enhance electrical characteristics of multilayer MoSe₂ devices, including on-current (~2,000-fold higher) and photoresponsivity (~10-fold larger) over the baseline device. By simply coating a planar conjugated polymer (PDPP3T) on as-synthesized multilayer MoSe₂, the coated PDPP3T induces strong n-doping phenomena. Based on comprehensive analysis using X-ray photoelectron spectroscopy (XPS), 2D-grazing incidence wide-angle X-ray diffraction (2D-GIWAXD), near edge X-ray absorption fine structure (NEXAFS), and other supporting spectroscopy techniques, we show that two mechanisms (dipole-induced and charge-transfer doping effects) account for such enhancements in the multilayer MoSe₂ device. We further demonstrate the methodical generality of the strong n-doping behaviour of multilayer MoSe₂ by applying thiophene instead of PDPP3T.

As a wide gap semiconductor, Ga₂O₃ is rapidly emerging as a promising candidate for power electronics applications. While most of the studies have focused on its stable β-phase, there are a handful of reports on its metastable polar ε-phase having a spontaneous polarization. Numerous experimental groups have recently attempted to stabilize ε-Ga₂O₃ using epitaxial strain using substrates such as Al₂O₃(0001)¹, GaN(0001)¹, AlN(0001)¹, MgO(111)² and SiC(0001)³. However, due to the lack of an understanding of the stability of various Ga₂O₃ phases under epitaxial strain, these trial-and-error based attempts have been of limited success. All the films are observed to be of inherently poor quality. There are also diverging reports on the structure and properties of the deposited thin films. A recent experimental report of ε-Ga₂O₃ grown on Al₂O₃ substrate has even suggested the film to be ferroelectric, where the direction of the spontaneous polarization could be switched with an external electric field. It implies that the stabilization of ε-Ga₂O₃ will open new avenue of polarization engineering in Ga₂O₃ power electronics⁴.

We have used first-principles density-functional theory (DFT) calculations in combination with coincidence site lattice theory to develop a phase-diagram of Ga₂O₃ under epitaxial strain. We show that all the previously used substrates impose an epitaxial strain over 3% on ε-Ga₂O₃, which explains the poor structural quality of the deposited thin films. In this presentation, we will discuss promising commercially available substrates that can stabilize ε-Ga₂O₃ with epitaxial strain < 1 %. We will discuss the electronic structure of ε-Ga₂O₃ under epitaxial strain, including properties such as the band gap, polarization constants and its ferroelectric nature. We will theoretically demonstrate a way to achieve two-dimensional electron gas (2DEG) in ε-Ga₂O₃ heterostructure simply by using polarization engineering. Finally , the sheet-charge density and the electrical properties of the heterojunction of ε-Ga₂O₃ and the substrate will be discussed.




1. Y. Oshima, E.G. Víllora, Y. Matsushita, S. Yamamoto and K. Shimamura: Journal of Applied Physics 118, 085301 (2015).
2. H. Nishinaka, D. Tahara and M. Yoshimoto: Japanese Journal of Applied Physics 55, 1202BC (2016).
3. X. Xia, Y. Chen, Q. Feng, H. Liang, P. Tao, M. Xu and G. Du: Applied Physics Letters 108, 202103 (2016).
4. F. Mezzadri, G. Calestani, F. Boschi, D. Delmonte, M. Bosi and R. Fornari: Inorganic Chemistry 55, 12079 (2016).

Sandhaya Koirala, Seon Namgung, Mahmoud Atalla, Matthew C. Robbins, Rui Ma, Sang-Hyun Oh, and Steven J. Koester

Monoclinic beta gallium oxide (β-Ga₂O₃) has recently emerged as an interesting material for next generation high power device applications, UV transparent electrodes, and solar blind photodetectors due to its ultra-wide bandgap of 4.6 eV and high breakdown field of ~ 8 MV/cm. Electronic and optoelectronic devices such as field-effect transistors [1] and photodetectors [2] have recently been demonstrated on β-Ga₂O₃. Recently, β-Ga₂O₃ has also been shown to be realizable in thin films enabling high-performance transistors to be fabricated [3], and offers a path to improving the thermal conductivity limitations of bulk β-Ga₂O₃. Bulk β-Ga₂O₃ is also known to have anisotropic electrical, and optical properties [4], but these properties have not been studied extensively in 2D thin films. In this work, we study the anisotropic optical properties of thin-film exfoliated β-Ga₂O₃ using polarization dependent Raman mapping, and describe the surprising result that multiple surface orientations of β-Ga₂O₃ are obtained through this process.
Samples were prepared by mechanical exfoliation from n-type Sn-doped (5.0×10¹⁸ cm^-3) β-Ga₂O₃ wafers with (-201) surface orientation. Different thicknesses of films were characterized using optical contrast analysis, atomic force microscopy, and Raman spectroscopy. Interestingly we observed different surface orientations including (010) and (-201) from the (-201) host β-Ga₂O₃ crystal. This was confirmed optically from Raman spectroscopy by observing the polarization dependence of the allowed A_g and B_g phonon mode, i.e. in (010) only the A_g phonon modes are allowed, while on (-201) only the B_g mode is allowed, consistent with previous work on bulk crystals [5]. Polarization dependent Raman mapping of (010) oriented flakes shows strong optical anisotropies. The Raman mode A_g¹⁰ shows strong polarization dependence due to bending and stretching of Ga-O bonds. Similarly, the A_g^3, A_g⁵, and A_g⁶ modes which are due to octahedral symmetry stretching and bending vibrational O-Ga-O modes also show polarization dependent intensity changes. Finally, Raman intensity mapping was performed to confirm the orientation-dependence and evaluate information on surface uniformity. Electrical measurements on the different orientation samples were found to be consistent with the Raman results. In conclusion, these results demonstrate the utility of using polarized Raman spectroscopy as an effective method for identifying the crystal orientation of exfoliated thin film β-Ga₂O_3. This work was supported by the University of Minnesota MRSEC under NSF Award DMR-1420013.
[1] W. S. Hwang, et al., Nat. Photonics 9, 247 (2015); [2] H. Zhou, et al., IEEE Elect. Dev. Lett. 38, 103 (2017); [3] G. C. Hu, et al., Optics Express, 23 13556 (2015); N. Ueda, et al., Appl. Phys. Lett. 71, 933 (1997); [5] C. Kranert, et al., Sci. Rep., 6 35964 (2016).

We report here on effect of HC(NH₂)₂PbI₃ (FAPbI3) crystal structure on resistive switching behavior. We have fabricated Pt/FAPbI₃/Ag(or Au) device for studying resistive switching behavior. Crystal structure of FAPbI₃ crystal is changed by different annealing temperature. Black alpha phase FAPbI₃ is obtained at high temperature, while yellow delta phase can be obtained at relatively lower temperature. RESET failure of 1st sweep occurs in I-V curve for alpha phase, whereas much better resistive switching property is observed from delta phase. XRD analysis reveals that (0k0) planes are dominant for delta phase, which indicates that (0k0) planes are aligned in parallel with metal electrode. Thus, conducting filament might be formed perpendicular to (0k0) plane. DFT calculation support our assumption, where we confirm that activation energy of iodide migration in <0k0> direction of delta phase is 0.4 eV but in-plane iodide migration requires higher activation energy of about 0.9 eV. Since switching behavior can be influenced by film morphology, we have measured surface and cross-sectional scanning electron microscopy, but pin-hole-free with smooth surface is confirmed. SET voltage of the device based on delta phase FAPbI₃ occurs near 0.20 V and RESET voltage is less than -0.4 V. ON/OFF switching takes places over 1000 cycles with ON/OFF ratio being close to 10⁶. Multilevel data storage is also confirmed by changing compliance current from 10^-2 to 10^-5 A. Long retention time of more than 2000 s is exhibited from low-temperature delta phase FAPbI₃

As devices are scaled to sub 5nm, it is critical to prepare clean and atomically flat surfaces. The traditional aqueous HF clean for removal of native Si oxide suffers from an inevitable air exposure resulting in re-oxidation of the Si surface as well as carbon contamination. The Siconi™ process is a dry clean which utilizes a low temperature (<30C) NF₃/NH₃ based plasma to selectively etch the native oxide layer on Si without significantly etching the underlying Si layer. The selectivity is based on the plasma chemistry NF₃ + NH₃ --> 3F + 3H + 2N --> 3HF + N₂ where HF is formed in the gas phase and then proceeds to etch the native oxide in a similar manner to aqueous HF. However, unlike aqueous HF the Siconi™ process leaves behind a hexafluoroammonium silicate salt, (NH₄)₂SiF₆, which must be removed in a subsequent anneal. In this work we present a modification of the Siconi™ process which eliminates (NH₄)₂SiF₆ salt formation and provides a surface which is just as flat as with the traditional aqueous HF clean.
The silicon surface following removal of the native oxide with an NF₃/NH₃ plasma was studied using X-Ray Photoelectron Spectroscopy (XPS) for elemental analysis as well as Scanning Tunneling Microscopy (STM) and Atomic Force Microscopy (AFM) for surface roughness. It was found that when the silicon substrate is held at 65-70C during the etching no (NH₄)₂SiF₆ salt formation is observed. The NF₃:NH₃ ratio was found to be a critical parameter for controlling the surface roughness, with the surface roughness decreasing with decreasing NF₃:NH₃ ratios. A NF₃:NH₃ ratio of 1:5 gave a Si surface with an RMS roughness of 3.4nm while a NF₃:NH₃ ratio of 1:10 gave a Si surface with an RMS roughness of 1.9nm. Further decreasing the NF₃:NH₃ ratio is expected to provide an even smoother surface, and experiments towards this end are ongoing. The plasma time was also optimized, and it was found that exposure to the NF₃/NH₃ plasma for 10 seconds and 1 minute resulted in essentially no removal of the native oxide, while exposure for 2 minutes resulted in complete removal of the native oxide. For comparison, Si surfaces cleaned with aqueous HF in our laboratory typically have ~10% oxygen and ~10% carbon contamination, while after cleaning with a NF₃/NH₃ plasma with NF₃:NH₃ = 1:10 for 2 minutes at 70C there was 3% O, 0% C, 4% F and 4% N impurities. Additionally, all of the silicon was in an oxidation state of 0 which means that there was no (NH₄)₂SiF₆ salt formation since this salt has silicon in an oxidation state of +4. To validate the applicability of this process, a molybdenum silicide film was deposited via atomic layer deposition (ALD) on dry-cleaned Si as well as on HF cleaned Si. The RMS roughness of the ALD MoSi_x film on the dry-cleaned Si was 2.26nm while on the HF cleaned Si the RMS roughness was 2.78nm. This shows that the dry clean developed in this study is capable of producing cleaner and smoother Si surfaces than the traditional aqueous HF clean.

Titanium nitride (TiN) has been extensively studied in semiconductor devices because of its ideal thermal, mechanical, and electrical properties. It has served as a diffusion barrier to WF₆ during W metal fill [1]. Similarly, tantalum nitride (TaN) has been utilized as a diffusion barrier on SiOCH to Cu, as Cu can readily diffuse, causing device reliability issues [2]. ALD TiN and TaN films have previously been grown using a wide range of precursors including metal halides (i.e. TiCl₄, TaF₅) and metal organics (i.e. TDMAT, TBTDET), as well as nitrogen sources (thermal/plasma NH₃, N₂/H₂). Metal halide precursors are preferred over organometallic grown films when there is no concern about substrate etching or damage; organometallic-grown films usually contain higher levels of carbon and oxygen contamination, which has been correlated with an increase in film resistivity [3].

In this study, low temperature thermal ALD TiN_x from anhydrous N₂H₄ vs. NH₃ and TiCl₄ was performed on degreased and UHV annealed SiO₂/Si substrates at temperatures of 300°C and 400°C. The deposited films were studied using x-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). TaN_x films were grown at 150°C utilizing N₂H₄ and tris(diethylamido) (tertbutylimido)tantalum (TBTDET) and characterized similarly. In addition, the resistance of air-exposed ultra-thin films was measured using a 4-point probe technique. Resistivities were estimated from thicknesses obtained from cross-sectional scanning electron microscopy (SEM) images.

First, saturation dosing was performed to determine optimal half-cycle pulses of TiCl₄ and N₂H₄. After TiN_x ALD cycles, AFM imaging showed uniform deposition with sub-nanometer RMS surface roughness. The corrected and normalized XPS showed near stoichiometric Ti₃N₄ with low O and C and ~10% Cl. There was approximately 2x more O and C and 50% more Cl in NH₃ grown films at 400°C. N₂H₄ films exhibited lower resistivities (359 vs. 555 µohm-cm), attributed to this lower contamination and likely better nucleation density. For TaN_x films, XPS of 15 cycles ALD TaN_x films resulted in 9% O and 4% C and had a Ta/N ratio of 4/5. Analysis on the Ta 4d peaks confirmed nucleation after the initial exposure of TBTDET (Si-O-Ta formation) based on the Ta 4d 5/2 peak BE of ~231.5 eV. A chemical shift to 229 eV was observed upon forming Ta-N bonds. Resistance measurements indicated insulating films consistent with the formation of Ta₃N₅. In summary, N₂H₄ grown TiN_x films showed lower resistivities with fewer impurities. The anhydrous N₂H₄ chemistry was extended to an organometallic Ta precursor, in which nearly stoichiometric films were deposited with low contamination at a modest substrate temperature of 150°C.

References:
[1] Sidhwa, A., et al. (2002). MRS Proceedings, 716.
[2] Chen, F., et al. (2006). Reliability Physics Symposium Proceedings, 44th Annual IEEE International.
[3] Musschoot, J., et al. (2009). Microelectronic Engineering 86.1: 72-77.

Two-dimensional transition metal dichalcogenides (TMDs) are currently considered as promising materials to complement or even supplant current Si-based device technology [1].The electronic and optoelectronic properties of MoSe₂, have been extensively studied in recent years. MoSe₂ has been implemented in FETs, exhibiting a promising performance (i.e. μ_FE 150-200 eV) according to previous reports [2,3]. We have studied the surface of bulky MoSe₂ crystals, grown by chemical vapor transport by means of various nanometrology methods such as X-ray photoelectron spectroscopy (XPS), low energy electron diffraction (LEED), and scanning spectroscopy microscopy/spectroscopy (STM/S) [4]. The “as-exfoliated” surface shows the presence of surface imperfections caused by defects and impurities with an inherent n-type conductivity. The air stability of MoSe₂ semiconductor has been investigated from first-principles calculations based on DFT and XPS measurements of the elemental oxygen concentration and work function as a function of exposure time to air and O₂ at room temperature. We find that the surface chemistry of the sulfides and selenides is relatively stable in air [5]. Moreover, surface defects were induced by either vacuum annealing or ions sputtering and then studied in-situ by XPS, LEED, and STM/S. Both microscopy and spectroscopy data reveal a change in the intrinsic electronic properties caused by the creation of metallic defects. The interfacial chemistry between contact metals and MoSe₂ and its dependence upon the deposition chamber ambient was monitored in-situ using XPS. Significant variation in interfacial reactivity between contact metal and MoSe₂ were observed. Particularly, Pd and Au form a van der Waals interface (no alloying) with MoSe₂ under either ultra-high vacuum (UHV) or high vacuum (HV) conditions, whereas Sc and Cr aggressively react with the substrate under both UHV and HV conditions as shown previously with MoS₂ and WSe₂ [6,7].

This work is supported part by NSF Award No. 1407765 under the US/Ireland UNITE collaboration, the Center for Low Energy Systems Technology (LEAST), one of six centers supported by the STARnet phase of the Focus Center Research Program (FCRP), a Semiconductor
Research Corporation program sponsored by MARCO and DARPA, and by the Southwest Academy on Nanoelectronics (SWAN) sponsored by the Nanoelectronic Research Initiative and NIST.

References.
[1] D. Jena, Proc. IEEE 101 1585–160 (2013).
[2] N. R. Pradhan et al. ACS Nano, 8 (8), 7923–7929 (2014).
[3] B. Chamlagain et al. ACS Nano 8 5079-88 (2014).
[4] R. Addou et al. ACS Appl. Mater. Interfaces 7, 11921–11929 (2015).
[5] R. C. Longo et al. 2D Mater. 4, 025050 (2017).
[6] C. M. Smyth et al., J. Phys Chem. C. 120, 14719-14729 (2016).
[7] C. M. Smyth et al., 2D Mater. 4, 025084 (2017).

In this work, we demonstrate the high-quality MBE heterostructure growth of various layered 2D materials by van der Waals epitaxy (VDWE). The coupling of different types of van der Waals materials including transition metal dichalcogenide thin films (e.g., WSe₂, WTe₂, HfSe₂) and topological insulators (e.g., Bi₂Se₃) allows for the fabrication of novel electronic devices that take advantage of unique quantum confinement and spin-based characteristics. We demonstrate how the van der Waals interactions allow for heteroepitaxy of significantly lattice-mismatched materials without strain or misfit dislocations. Yet, at the same time, the VDW interactions are strong enough to cause rotational alignment between the epi-layer and the substrate, which plays a key role in the formation of grain boundaries.
We will discuss TMDs and TIs grown on atomic layer deposited (ALD) high-k oxides on a Si platform. WSe₂ grown by MBE on ALD-grown Al₂O₃ on Si is demonstrated in field-effect transistors with back-end-of-line (BEOL) compatible fabrication temperatures (< 525 °C). Transistors exhibiting ambipolar behavior with drain currents exceeding 1mA/mm and ON-OFF ratios greater than 10⁴ are demonstrated from the grown films. Field-effect hole mobilities greater than 40 cm²/V-s are measured, which is orders of magnitude higher than other MBE reported TMD mobilities and the highest to date for low-temperature grown TMDs. The achievement of relatively high-mobility transistor channels at BEOL compatible processing temperatures shows the potential for integrating transition metal dichalcogenides (TMDs) into CMOS process flows.
This work is supported in part by the Center for Low Energy Systems Technology (LEAST), one of six centers supported by the STARnet phase of the Focus Center Research Program (FCRP), a Semiconductor Research Corporation program sponsored by MARCO and DARPA. It is also supported by the SWAN Center, a SRC center sponsored by the Nanoelectronics Research Initiative and NIST.

In recent years there has been an unprecedented interest in two-dimensional (2D) materials with unique physical and chemical properties that cannot be found in their three-dimensional (3D) counterparts. One of the important advantages of 2D materials is that they can be easily integrated with other 2D materials and functional films, resulting in multilayered structures with new properties. We fabricated and tested electronic and memory properties of field-effect transistors (FETs) based on a single-layer graphene combined with lead zirconium titanate (PZT) substrate. Previously studied graphene-PZT devices exhibited an unusual electronic behavior such as clockwise hysteresis of electronic transport, in contradiction with counterclockwise polarization dependence of PZT. We investigated how the interplay of polarization and interfacial phenomena affects the electronic behavior and memory characteristics of graphene-PZT FETs, explain the origin of unusual clockwise hysteresis and experimentally demonstrate a reversed polarization-dependent hysteresis of electronic transport. In addition we fabricated and tested properties of MoS2-PZT FETs which exhibit a large hysteresis of electronic transport with high ON/OFF ratios. We demonstrate that MoS2-PZT memories have a number of advantages over commercial FeRAMs, such as nondestructive data readout, low operation voltage, wide memory window and the possibility to write and erase them both electrically and optically.

Transition metal dichalcogenides (TMDs) are exciting new materials that have received much attention due to their semiconducting properties in the direct bandgap. Well-studied TMDs, such as molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂), exhibit a direct bandgap in the monolayer form, but an indirect bandgap in the bulk form. Rhenium disulfide (ReS₂), on the other hand, is a new TMD that is unique in its ability to retain a direct bandgap independent of thickness. By using chemical vapor deposition (CVD), few-layer ReS₂ is synthesized and characterized by optical methods such as Raman spectroscopy and photoluminescence. We also show characterization results for atomic force microscopy (AFM), x-ray photoelectron spectroscopy (XPS), scanning electron microscope (SEM), transmission electron microscope (TEM), and electrical transport to determine thickness, crystallinity, homogeneity, and electrical characteristics for use in future flexible electronics.

A strong interest of the materials research community to quasi two-dimensional (2D) and quasi one-dimensional (1D) van der Waals materials has recently led to a renewed attention to layered materials that reveal the charge density wave (CDW) effects [1]. Most of these materials belong to the group of transition metal dichalcogenides (TMDs) or trichalcogenides (TMTs) [2]. Some of TMDs and TMTs have very high transitions temperatures, often above room temperature, to different CDW phases. The switching between CDW phases can be utilized for various device applications [3]. This explains the motivations behind the search for new polymorphs of materials that can have CDW properties. In this presentation, we report results of Raman spectroscopy of recently discovered two new polymorph of Niobium Trisulfide, NbS3-IV and NbS3-V, which crystallize in the monoclinic space group P21/c and P21/m, respectively [4]. Raman spectroscopy is a powerful tool for understanding CDW material structure and crystal lattice dynamics near the CDW transition points. The samples for this study have been prepared by the chemical vapor transport synthesis, and characterized using the X-ray diffraction and transmission electron microscopy. The Raman spectroscopy has been carried out in a wide temperature range from 90 K to 640 K using the low-wave-number filter. The peak assignment has been performed using ab initio calculations and comparison with experimental data for other polymorphs of this material. Temperature coefficients of higher frequency A_1g mode for NbS₃ – IV and NbS₃ – V were determined to be approximately -0.01076±0.00032 cm^-1/K and -0.01641±0.00241 cm^-1/K, respectively. For NbS₃ – V a significant deviation from a linear trend was observed at 180 K and 350 K suggesting possible phase transitions. The Raman spectroscopy results are in line with the preliminary electrical resistivity data.
This work was supported, in part, by the NSF EFRI 2-DARE project: Novel Switching Phenomena in Atomic MX2 Heterostructures for Multifunctional Applications and by UC-National Lab Collaborative Research and Training Program.
[1] R. Samnakay, D. Wickramaratne, T. R. Pope, R. K. Lake, T. T. Salguero, and A. A. Balandin, “Zone-folded phonons and the commensurate-incommensurate charge-density-wave transition in 1T -TaSe2 thin films,” Nano Letters, 15, 2965 (2015).
[2] G. Liu, S. Rumyantsev, M. A. Bloodgood, T. T. Salguero, M. Shur, and A. A. Balandin, “Low-frequency electronic noise in quasi-1D TaSe3 van der Waals nanowires,” Nano Letters, 17, 377 (2017).
[3] G. Liu, B. Debnath, T. R. Pope, T. T. Salguero, R. K. Lake, and A. A. Balandin, “A charge-density-wave oscillator based on an integrated tantalum disulfide–boron nitride–graphene device operating at room temperature,” Nature Nanotechnology, 11, 845 (2016).
[4] M. A. Bloodgood, P. Wei, E. Aytan, K. N. Bozhilov, A. A. Balandin, and T. T. Salguero, “Monoclinic structures of Niobium Trisulfide,” APL - Materials (accepted 2017).

MoS₂ and WSe₂ are semiconductors with atomic-scale thickness and high mobility, which are favorable as channel materials for the next generation field effect transistors. To achieve high performance and good device stability, MoS₂ and WSe₂ have to be integrated with high quality high-k dielectric as the gate dielectric or passivation layer. However, the dangling-bond free surface of MoS₂ and WSe₂ has made it challenging to deposit high-k dielectric on them. Remote O₂ (similarly UV-O₃) or N₂ plasma treatment [1-3] has been used as a surface functionalization technique to enhance the uniform dielectric deposition on MoS₂ and WSe₂, via O or N atom adsorptions on top of S and Se atoms. However, severe damages, such as oxidation or nitridation of MoS₂ and WSe₂, could be easily induced once the sample is overexposed. An in situ characterization technique (which can be easily integrated with the treatment and ALD chamber), becomes valuable to enable the real-time monitoring of the surface functionalization conditions. In this work, resonant Raman spectra of MoS₂ and WSe₂ with various O or N atom adsorption densities are studied by first-principles calculations for the first time, aiming to provide guidelines for Raman spectroscopy as a tool to monitor the O/N adsorptions for subsequent high-k dielectric integration.

Finite-difference method is used to calculate the Raman tensors in density functional theory (DFT) [4]. MoS₂ and WSe₂ supercells are adopted to study the influences of O/N adsorptions. The activations of both acoustic- and optical-phonon Raman scattering are analyzed based on the breaking of translational and reflection symmetries. Specifically, the low-coverage O/N adsorptions will act as perturbation to the periodic crystal lattice, breaking the translational symmetry and activating the acoustic-phonon Raman scattering. High-coverage adsorptions will further break the reflection symmetry in z direction, activating and intensifying the previously silent A_2u and E_1g Raman modes. High-coverage adsorptions also introduce new phonon modes associated with the local adatom oscillations with A₁ and E symmetries. With increasing adsorptions, the previously active E_2g¹ peak shifts continuously, and the A_1g mode is monotonously softened. To better identify the shift trends, Raman intensities are decomposed according to the phonon symmetries by adopting both (zxxz) and (zxyz) scattering geometries. The above observed A_1g and E_2g¹ peak shifts, together with the activations of acoustic- and optical-phonon Raman scattering, can be used as valuable scalars to quantify the adsorption coverage density, and to realize robust surface functionalization of MoS₂ and WSe₂ for subsequent high-k dielectric integrations.

[1] A. Azcatl et al., Appl. Phys. Lett. 104 (2014) 111601.
[2] H. Zhu et al., ACS Appl. Mater. Inter. 8 (2016) 19119.
[3] Q. Qian et al., Nanotechnology 28 (2017) 175202.
[4] H. P. C. Miranda et al. Nano Lett. 17 (2017) 2381.

Titanium trisulfide (TiS₃) is a layered n-type semiconductor in which chains of sulfur trigonal prisms with Ti⁴⁺ centers form a two-dimensional (2D) layer. Monolayer TiS₃ was predicted to have an electron mobility over 10000 cm²/Vs. With electronic band gap similar to silicon, it is a very promising material for electronic applications.
Several-mm-long TiS₃ whiskers can be conveniently grown by the direct reaction of titanium and sulfur. In this study, we exfoliated these whiskers using the adhesive tape approach and fabricated few-layer TiS₃ field-effect transistors (FETs). The TiS₃ FETs showed an n-type electronic transport with room-temperature field-effect mobilities of 18-24 cm²/Vs and ON/OFF ratios up to 300. We demonstrate that TiS₃ is compatible with the conventional atomic layer deposition (ALD) procedure for Al₂O₃. ALD of alumina on TiS₃ FETs resulted in mobility increase up to 43 cm²/Vs, ON/OFF ratios up to 7000, and subthreshold swing decrease from 19.1-44.3 to 3.4-4.8 V/dec. This study shows that TiS₃ is a competitive electronic material in the family of two-dimensional (2D) transition metal chalcogenides and can be considered for emerging device applications.
Conventional mechanical exfoliation of TiS₃ tends to produce narrow nanoribbons, that are not visible by optical microscopy. Additionally, the low yield of the mechanical exfoliation method is not compatible with large-scale applications. To address these issues, we investigated the liquid phase exfoliation of TiS₃ in different solvents. SEM and UV-vis data revealed that ethanol is the most effective solvent for liquid phase exfoliation of TiS₃, while TEM confirms the formation of single layers. The data on exfoliation of TiS₃ crystals along different crystallographic directions is supported by DFT calculations. We further demonstrate the utility of the liquid-phase exfoliated TiS₃ for gas sensor applications. We fabricated TiS₃-based gas sensors that can reliably recognize low weight alcohols.

The wide band gap gallium nitride is an excellent material for the production of high power, high speed transistors as well as semiconductor lasers and light emitting diodes (LEDs). While GaN bulk substrates are still too expensive for practical application in solid state lightning, much attention is drawn towards GaN on Si technology. One possibility to integrate GaN on Si is the heteroepitaxial growth using erbium oxide as a buffer. Er₂O₃ reduces the lattice mismatch between Si and GaN. However due to thermal expansion coefficient mismatch the cracks are observed after the growth of GaN thick layers. If the substrate is patterned into separate areas, the stress can be relieved by elastic relaxation of the film at the pattern edges. Therefore cracks can be prevented to occur in the formed films. This study is aimed to develop growth technology of GaN on Si substrates using Er₂O₃ as buffer layer in the application field of photonics.
Two types of substrates were studied in this work for GaN growth. The first one was designed to fabricate a wave guide in the visible region. Therefore 300 nm-thick Er₂O₃ (111) layers were prepared on Si(111) substrate by molecular beam epitaxy (MBE). Afterward, the substrates were covered with photoresist, exposed to UV light and finally wet etched to produce the slab like patterns. The chemical etching kinetics was analysed in detail by determining the etching rates and activation energy. The optimization of the wet etch process was necessary in order to get well defined 100x100um structures. For the second set of samples a plane structure with several periods of Er₂O₃/Si layers were grown on Si(111) by MBE. The latter structure can act as a Bragg reflector with the reflection maximum at a wavelength of 480 nm. Prior GaN growth, the structures were analysed by spectrometer and optical microscopy. The finite difference time domain (FDTD) modelling was performed to explain the light propagation in the designed structures both in the patterned sample and the plane one. The close-coupled showerhead metalorganic chemical vapour deposition reactor (MOCVD) was used to grow GaN on a plane substrate with Bragg reflector structure. The morphological and structural properties of GaN were investigated by X-ray diffraction (XRD) and atomic force microscopy (AFM).

Voltage or current-controlled memory-resistive switching in metal-insulator-metal (MIM) structures has been extensively explored in circuit-research, over the past 50 years, and is expected to continuously grow to expedite the establishment of the “memristor” technology in replacement to the conventional RRAM [1-3]. While the research on memristive devices is heavily pursued for advanced computing, alternative uses are emerging in environmental sensing, where the actual computing reservoir is tailored to co-act as an environmental signal transducer [4]. Sensing ionizing radiations is a hot topic in radiation protection and dosimetry [5], and an example target application of memristive materials are high-Z metal-oxides owing to their attractive photo-electrical properties and popularity among thermoluminescent dosimeters. In this study, the microstructure of native HfO₂ memristor is engineered with gadolinia (Gd₂O₃) doping so as to examine the co-functionality of the novel high-Z computing reservoir, as a low power gamma-ray detector, under preliminary ambient conditions. In this work, a 2 mm × 2 mm crossbar micro-thick Ag(TE)/Hf_1-xGd_xO₂(~50 µm)/Cu(BE) (where 0 ≤ x ≤ 50 at.%) MIM stack is developed via a sol-gel drop-coating technique. The effect of Gd(III) doping composition on the memristive switching behavior (i.e. unipolar or bipolar), resistance ratio, retention time and endurance of the device is systematically examined by electrical characterization, and is supported by SEM /EDX analyses to establish a preliminary understanding of the governing switching mechanism. The I-V measurement results on the native HfO₂ memristor demonstrated a bipolar switching behavior with a high endurance (above 60 cycles) and large R_OFF/R_ON window (up to 10⁶). A key finding in this portion of the work is that the Gd₂O₃ doping in the HfO₂ reservoir alters the memristive switching behavior of the native oxide. Moreover, measurable changes in key electrical characteristics of the doped memristor stack in response to Cs-137 662 keV gamma-rays used as a model (source activity ~0.67 MBq), are demonstrated and discussed.
The proposed project is in line with United Arab Emirates Space Agency’s Space Science, Technology and Innovation (ST&I) Roadmap aimed at developing enabling technologies for Space exploration, which is intended to accomplish the objectives of the UAE Space strategy.

Ferroelectric Field Effect Transistors (FE-FET) with a ferroelectric material as a gate dielectric are the potential candidates for the next generation non-volatile memory technology because of their low operating voltage, non-destructive read out. On the other hand, two dimensional (2D) layered semiconductor materials have received considerable research interest as channel materials for next generation electronics because of their unique properties. Among these materials, more emphasis is given to molybdenum disulfide (MoS₂), a member of transition metal dichalcogenide family [1], in many fields such as FETs, memories, photodetectors etc., because of its excellent properties such as intrinsic bandgap (1.2 eV), high electron mobility (410 cm²/V.s), good thermal stability and due to the possibility of creating atomically thin semiconductor membranes for a variety of applications. Therefore, MoS₂ based FE-FETs can be the potential candidates for future ferroelectric memories. However, very few reports are available on FE-FETs based on MoS₂ and hence device aspects such as materials physics and interface properties need to be understood to realize viable technology [2].
In this work, we report on the fabrication and characterization of Lead Zirconium Titanate (PZT) back gated MoS₂ FETs for ferroelectric memories. The initial step of this work is the optimization of PZT films for their structural, compositional, electrical and ferroelectric properties using pulsed laser deposition. PZT (PbZr_0.52Ti_0.48O₃) films of good ferroelectric properties (C= 4 µF/cm², P_r= 40 µC/cm², E_c= 170 kV/cm) have been deposited on Pt coated Si substrates using KrF (λ= 248 nm) laser where Pt severed as back gate electrode. MoS₂ flakes were directly exfoliated on PZT film using standard scotch tape method. Multilayer MoS₂ flakes (~7-10 nm) have been identified using optical microscope and confirmed with Raman spectroscopy, photoluminescence (PL) and atomic microscope. PZT back gated MoS₂ FETs have been fabricated using standard two step e-beam lithography process followed by 50 nm Ni deposition using e-beam evaporation and lift off.
MoS₂ FET with PZT back gating shows typical n-type MoS₂ FET characteristics and the memory window of the devices significantly increases with the increase in gate voltage sweep ranges. A memory window of ΔV_M~3.2 V has been realized when the gate voltage sweeps from -5 to 5 V at a fixed drain voltage (V_d= 1 V). The devices exhibited reproducible hysteresis, nonvolatile memory behavior with high I_on/I_off ~10⁵.

References:
[1]. A. Kuc et al, Phys.Rev. B, 83, 24, 245213 (2011).
[2]. X-W. Zhang et al, IEEE Electron Device Letters, 36, 8, 784-786 (2015)

Silicon-germanium (SiGe) alloys are promising for advanced FinFET channels due to their electronic properties and ease of integration into existing Si CMOS processes. However, Ge-O bonds at the channel/insulator interface introduce defect energy states. Previous investigations into suppressing Ge-O bond formation have involved liquid sulfur treatments or ammonia plasma pre-deposition, or post-deposition N₂ plasma nitridation. Sulfur treatment presents reliability concerns, while post-deposition nitridation lacks control over oxide nucleation. In this work, an in-situ downstream RF plasma containing a mixture of N and H species on Si_0.7Ge_0.3(001) surfaces prior to deposition of high-k oxides Al₂O₃ and HfO₂ by atomic layer deposition (ALD) has been investigated using metal-oxide-semiconductor capacitor (MOSCAP) structures. C-V and I-V characterization was performed, demonstrating improved interface state density (Dit) and leakage current for plasma-cleaned devices. X-ray photoelectron spectroscopy (XPS) was used to investigate the chemical environment at the SiGe/high-k interface.
Al₂O₃ and HfO₂ MOSCAPs were fabricated to compare the in-situ N₂/H₂ plasma clean with an HF(aq) only preclean. 40 Al₂O₃ cycles were grown with TMA and H₂O precursors at 250 C, and 50 HfO₂ cycles were grown with TDMAH and H₂O precursors at 250 C. Prior to deposition, SiGe substrates were treated with 2.5 cycles of 2% HF(aq) followed by deionized water, with plasma cleaned devices receiving an exposure to 20s downstream RF plasma at 20 W with 500 mTorr N₂, 25 mTorr H₂, and 475 mTorr Ar. A significant improvement to D_it was observed for the plasma cleaned devices; HF + plasma Al₂O₃ MOSCAPs had an EOT of 3.14 nm and peak D_it of 7.2 x 10¹¹ cm^-2eV^-1, compared with 3.39 nm EOT and 3.6 x 10¹² cm^-2eV^-1 for the HF only device, illustrating Dit improvement without a decrease in EOT. On HfO₂ devices, HF + plasma and HF only MOSCAPs had EOT values of 1.61 and 1.77 nm and peak D_it values of 2.9 x 10¹² and 4.8 x 10¹² cm^-2eV^-1. Leakage currents at -2 V bias were 100x lower for HF + plasma Al₂O₃ and HfO₂ MOSCAPs, consistent with a more uniform oxide layer after plasma clean.
Using capacitance- and conductance-voltage measurements, a full interface state model across the band-gap was used to find the integrated Dit, demonstrating a 5x improvement in integrated Dit on Al₂O₃ HF + plasma MOSCAPs compared with HF only, and a 30% improvement compared with sulfur-passivated devices. With HfO₂ MOSCAPs, integrated D_it value was decreased 2x for HF + plasma devices compared with only HF.
To investigate the chemical structure at the interface, a thin Al₂O₃ layer was deposited using 5 ALD cycles on both HF only and HF + N₂/H₂ plasma cleaned surfaces, and XPS spectra were recorded. Plasma-treated SiGe exhibited lower intensity Si and Ge peaks, consistent with improved Al₂O₃ nucleation. Si and Ge nitride peaks appear after plasma treatment, consistent with a nitride layer suppressing Ge-O bond formation.

While various electronic components based on carbon nanotubes (CNTs) have been produced, a micron-scale planar induction coil has not been demonstrated yet. Our group previously created defect-free single-wall CNT coils, but short-circuiting between turns prevents the coils from acting as inductors. To overcome this limitation, here we explore the use of few-wall CNTs, in which the outer walls may act as sheathing for the inner walls. We show the successful formation of the first few-wall CNT coils with accessible ends, low defect densities, and a µm-scale. We characterized their structural, optical, vibrational, and electrical properties using optical microscopy, SEM, AFM, top-view TEM, cross-sectional FIB-TEM, Raman spectroscopy and electrical transport measurements. The coils comprised CNTs of two, three and four walls with up to 163 turns and diameters of a few µm.
Based on the structural results and molecular dynamics simulations, we suggest they are formed according to the falling elastic rod mechanism. These ordered coils of uniform chiralities extend the known repertoire of self-organized structures of one-dimensional nanomaterials. They are also promising candidates for inductive devices, and for manifesting other interesting properties, such as electromagnetism, superconductivity, and inter-wall coupling.

The extraordinary properties of carbon nanotubes have driven a search for new nanotubes with unique properties. Here we present detailed analyses on the electronic properties of two novel nanotube families, phosphorene and porphyrin nanotubes, from large-scale DFT calculations (up to 1476 atoms and 18,432 orbitals). In the phosphorene nanotubes, we uncover a direct-to-indirect bandgap transition with decreasing nanotube diameter, a property which has direct implications for applications that require either (i) fast charge recombination and high light absorption (i.e., a direct bandgap ) or (ii) slow recombination and large diffusion length (i.e., an indirect bandgap). In the porphyrin nanotubes, we find extremely large oscillations in the bandgap as a function of size, in contradiction to quantum confinement effects (i.e., the bandgap increases with size in several of these nanotubes). As a result of these unusual oscillations, we find that both type I and type II p-n heterojunctions are possible in this single nanotube family. We emphasize that each of these families possess properties not present in conventional carbon nanotubes, each offering a wide range of tunability for applications in both light-emitting diodes (LEDs) and solar cells.

In this work, we demonstrate thermodynamically driven geometrically constrained wetting of liquid metal templates on diverse substrates, and utilize that to directly grow templated thin films of indium and tin based crystalline compound materials on a variety of epitaxial and non-epitaxial substrates through templated liquid phase (TLP) method. Based on the interfacial energies, a critical aspect ratio of templates exists, below which complete wetting of the template area occurs, and above which partial dewetting of varying extent takes place. This behavior has been verified with a thermodynamic model. This also allows us to reproducibly obtain templated thin films of pre-determined geometry of III-V (such as InP, InAs, InGaP) and IV-V (SnP, Sn₃P₄) compounds on an array of amorphous and crystalline ceramic substrates. Tuning the growth conditions ensures a single nucleation site in each template, resulting in single-crystal templates which have also been characterized with high resolution transmission electron microscopy. Micro-photoluminescence measurements of InP attest to the high optoelectronic quality of the grown material comparable to that of a single crystal commercial wafer. Tin phosphide of two different stoichiometries were obtained based on the growth temperature: SnP and Sn₃P₄, with distinct Raman, X-ray photoelectron, and absorbance spectra. Further, we obtained a lateral heterostructure of InP and Sn₃P₄, with a naturally formed atomically sharp interface between two distinctly different materials with widely different crystal structures. These demonstrations potentially mark the beginning of a new genre of material growth technique with increased opportunity for device and system design with novel functionalities.

Memristor suggested to be fourth fundamental element in 1971 has recently gained wide attention after HP scientists fabricated a real memristor. Resistive random access memory (RRAM) based on transition metal oxides has been widely investigated as a next-generation non-volatile memory to be an important application for memristor. RRAM is a two terminal device which reversibly switches between low resistance state (LRS) and high resistance state (HRS) upon applying electrical stimulus in a particular range at RESET/SET voltages respectively. In this work, we demonstrate a forming-free resistive memory with memristive characteristics using ZnO thin film. Oxygen vacancies/interstitials defects in ZnO thin film are engineered by a novel technology of Dual Ion Beam Sputtering (DIBS) to suit switching needs. In general, a forming process is necessary to activate the resistive memory devices before performing any resistive switching (RS). Abundant oxygen vacancies in film ensures forming- free behavior of device. Besides, sufficient non-lattice oxygen ions in ZnO thin film assist set/reset of device. Interfacial AlO_x formation/dissolution at Al/ZnO interface ensures bipolar resistive switching with smooth transition between resistance states (HRS and LRS). To start with fabrication of device, 60 nm thick ZnO thin film is deposited over Al/SiO₂/Si substrate at a substrate temperature of 100 °C, with DIBS background pressure of 1 × 10^-8 mBar and Ar:O₂ (2:3) (flow rate in sccm), respectively. Finally, circular Al electrodes of 500 µm is deposited on the surface of ZnO thin film. Further, I-V characteristics are measured by sweeping a DC voltage in sequence of 0-(+8 V)- 0-(-8 V)-0 in steps of 0.5 V for a compliance current of 1 mA. Set and reset voltages of device are evaluated to be at -6/6 V. Device shows excellent endurance measured at 0.1 V for 250 cycles Retention performance assessed at 0.1 V read voltage exhibits outstanding non-volatile behavior for 10⁶s extrapolated to 10 years. Presence of oxygen vacancies (VO), interstitial oxygen ions (IO) and lattice oxygen ions are confirmed by X-ray photoelectron spectroscopy (XPS) Photoluminescence (PL) of ZnO thin film. HR-TEM image of Al/ZnO interface shows an amorphous AlO_x interfacial layer (~4-5 nm) formed at interface for the device in high resistance state (HRS) state. Formation of this interfacial layer at RESET voltage transits the device from LRS to HRS and dissolution at SET voltage leads to change device state to LRS. Our memory device as fabricated by DIBS exhibits excellent performance parameters, retention and endurance to implement it for a practical RRAM. Our work could play a very significant role in realizing similar memristive devices with high performance parameters in future.

Besides utilization of resistive switching structures in non-volatile memories, increasing interest is given to their application as a logic element. Resistive switches are suitable for Boolean logic, neuromorphic computing and for the implementation of Zadeh fuzzy logic [1].
Min and Max functions are two fundamental logic operations of the Zadeh fuzzy logic. A complementary resistive switch, (CRS) [2] connected as a three terminal device was proposed as a basic element for the Min/Max implementation [1]. In the application as Min or Max gate CRS has two inputs and detects the higher or lower input voltage at the output. The complementary switches can be integrated into logic circuit for sorting input signal to minimal and maximal values (Min/Max functions). The sorting circuit is able to separate signals with the amplitude difference higher than the threshold voltage. Such sorting circuit presents basic element of the logics for pattern recognition.
In our contribution we present study of the performance of resistive switching structures based on HfOx and TaOx in circuits for implementation of Min and Max functions. HfO_x film in the resistive switching structures Pt/HfO_x/TiN was prepared by atomic layer deposition. TaO_x switching in the Pt/TaO_x/Ta structure layer was formed by annealing of the Ta bottom electrode in oxygen. The TiN and Pt electrodes were prepared by reactive sputtering and vacuum evaporation, respectively.
The complementary switches for Min-Max function implementation were analyzed using quasi-static voltage sweeps at the input of the CRS. When one of the input and output contacts is grounded, both Min and Max voltage time evolution can be recorded simultaneously. Properties of the HfO_x- and TaO_x-based CRS devices are discussed in connection with their implementation for Min/Max functions.


Acknowledgements
This research was funded by APVV (project APVV-14-0560) and VEGA (project 2/0136/18).

References
[1] M. Klimo, O. Such, “Memristors can implement fuzzy logic,” http://arxiv.org/abs/1110.2074.
[2] E. Linn, R. Rosezin, C. Kügeler and R. Waser, Nat. Mater 9 (2010) 403-406.

Reliable charge storage in dielectric materials enabled recent three dimensionally integrated flash memory devices. Currently known dielectric stack based on silicon nitride charge storage layer may challenge further dimensional and voltage scalings. The definite electrostatic requirement of dielectric material parameters for a further scaling is the enhancement of dielectric constant values. However, hundreds of suggestions based on higher dielectric constant materials for memory application have been failed in commercialization. In this talk, it will be shown that the dielectric thin film for charge storge should have amorphous phase to exhibit nonvolatile charge storge characteristics. Furthermore, a further design in its spatial band engineering is shown to be necessary and effective for the enhancement of memory window, which provides a promising scaling technology for reliable high density flash memories.

Due to its material properties such as the large bandgap of ~ 4.8 eV and breakdown electric field of ~ 8 MV/cm, wide bandgap semiconductor β-Ga₂O₃ has garnered tremendous interest for efficient power conversion applications in smart grids, renewable energy, data center, automotive electronics, and so on. β-Ga₂O₃ exhibits a much larger Baliga’s figure of merit (FOM) than SiC and GaN, indicating β-Ga₂O₃ power electronics have the potential to outperform SiC and GaN devices. In addition, the cost-effective single-crystal β-Ga₂O₃ substrates are also commercially available, which will enable high performance vertical electronics devices. β-Ga₂O₃ based field-effect transistors (FETs) and Schottky barrier diodes (SBDs) have been demonstrated on single-crystal substrates with various orientations including (-201), (010), (001), and (100). Studies have shown that the material properties of β-Ga₂O₃ are different along different crystal orientations (i.e., anisotropic) because of the highly asymmetric monoclinic crystal structure of β-Ga₂O₃. However, systematic study on the effect of crystalline anisotropy on the electrical properties of β-Ga₂O₃ electronic devices is still lacking. In this work, we fabricated vertical (-201) and (010) β-Ga₂O₃ SBDs on single-crystal substrates grown by the edge-defined film-fed growth (EFG) method. Their electrical properties such as temperature-dependent I-V and C-V characteristics were comprehensively measured and compared. The (-201) and (010) SBDs exhibited on-resistances of 0.56 and 0.77 mΩcm², turn-on voltages of 1.0 and 1.3 V, Schottky barrier heights (SBH) of 1.05 and 1.20 eV, electron mobilities of 125 and 65 cm²/(Vs), respectively, with a high on-current of ~ 1.3 kA/cm² and an on/off ratio of ~10⁹. At the forward bias, the (010) SBD had a larger turn-on voltage and SBH than the (-201) device due to different surface Fermi level pinning and band bending, as confirmed by X-ray photoelectron spectroscopy measurements. The difference in the electron mobilities results from the anisotropic electronic transport properties of β-Ga₂O₃. According to the temperature-dependent I-V, both devices had inhomogeneous SBHs, where (-201) SBD showed a more uniform SBH distribution. The homogeneous SBH was also extracted: 1.33 eV for the (-201) SBD and 1.53 eV for the (010) SBD. At the reverse bias, the leakage current of the devices could be simulated by either the two-step trap-assisted tunneling model or the one-dimensional variable range hopping conduction (1D-VRH) model. Further investigations are needed to determine the dominant mechanism. The (010) SBD showed a smaller leakage current and larger breakdown voltage due to its higher SBH. These results indicate the crystalline anisotropy of β-Ga₂O₃ can significantly affect the electrical properties of vertical SBDs and should be taken into consideration when designing β-Ga₂O₃ electronics.