Symposium EP2 : Silicon Carbide---Substrates, Epitaxy, Devices, Circuits and Graphene

Recent advances in wide bandgap (WBG) power devices fabricated in Silicon Carbide (SiC) and Gallium Nitride (GaN) provide new opportunities for substantial circuit improvements in power density and efficiency. Their material characteristics in regards to electric breakdown fields and high channel mobility result in substantially lower on resistance, higher frequency and temperature capabilities with higher breakdown voltages, compared to comparable silicon based power devices.

These advances are fueling the realization of more advanced power converters with potentially lower overall cost, size and weight than previously possible utilizing silicon devices. To date, low voltage devices using WBG semiconductors have largely been restricted to the use of GaN for LED and RF applications. Limitations in existing SiC processing, including the availability of a useful SiC p-type MOSFET, have limited the successful commercial application of SiC for low- and medium-voltage analog and digital integrated circuits. Consequently, most applications using SiC power devices still rely on conventional, silicon low-voltage circuits for control and monitoring purposes. The use of silicon gate drive and protection circuits can ultimately limit the system level performance in harsh environment applications, negating the benefits achieved from the WBG devices.

In this presentation, an overview of the state-of-the-art in silicon carbide low voltage integrated circuits will be provided, including a discussion of the technical and fiscal challenges associated with their wide-spread adoption. Potential application areas will be summarized in view of the advantages and disadvantages realized by highly integrated systems utilizing low-voltage, MOS-based, silicon carbide integrated circuits. Published research will be reviewed including recent circuits designed, developed, and tested through cooperative activities between the Oak Ridge National Laboratory and industrial collaborators. Finally, commercial SiC offerings including both production devices and custom designs will be reviewed. These efforts collectively demonstrate the potential of SiC as a technology option for low- to moderate-voltage control and monitoring applications.

Silicon Carbide (SiC) bipolar integrated circuits (ICs) are promising candidates for operation in harsh environments with high ambient temperature. Owing to its wide bandgap (3.2 eV for 4H-SiC), compared to silicon and silicon on insulator (SOI), SiC has remarkable advantages including a high intrinsic temperature of about 1000°C. However, there are many challenges in designing analog circuits in an immature in-house SiC bipolar technology such as the one used in this work. The relatively low transistor forward current gain, the temperature drift of the integrated resistors, and lack of complete ac models of the transistors are few examples.
This work presents the design and characterization of a 40dB negative feedback voltage amplifier. The amplifier was designed using the gm-I_C method. Compared to conventional circuit design methods, gm-I_C leads to more stable and optimized amplifiers provided that the circuit parameters including speed, noise, and power consumption are orthogonal in this design method.
The circuits consisting of low-power BJTs and epi resistors were fabricated in-house on 100 mm wafers with an ion-implantation free technology. The fabricated circuits have been characterized over a wide temperature range from 25°C up to 500°C. The measured gain of the amplifier is reduced from 39 dB at room temperature to 34 dB at 500°C. The amplifier has a 3-dB bandwidth of 195 kHz at room temperature which decreases to 100 kHz at 500°C. The measured power-supply-rejection-ratio (PSRR) is reduced from -78 dB at room temperature to -62 dB at 500°C. Likewise, the measured total harmonic distortion (THD) of the amplifiers is reduced from -57 dB at room temperature to -49 dB at 500°C. Moreover, the unity-gain bandwidth (f_u) of the amplifier drops from 4.34 MHz at room temperature to 3.1 MHz at 500°C. The input and output swing of the amplifier has been also measured. As the temperature increases from 25°C up to 500°C, the output voltage swing decreases from 8 V to 5 V. The achieved positive and negative slew rates at room temperature are 2.1 V/µs and 4.39 V/µs which decrease to 0.52 V/µs and 1.639 V/µs at 500°C. In future designs, this voltage amplifier with the achieved performance can be used in a system preceded by a charge amplifier and a level shifter to collect the charges of a capacitive sensor. In summary the paper demonstrates the feasibility of high-performance amplifiers using the gm-Ic method in bipolar 4H-SiC technology for high-temperature applications.

Humidity control and the stability of MOS interfaces are critical specifications for device performance and may be particularly relevant for the high temperature uses of SiC MOSFETs. Previously we reported^1,2, the water exposure to a variety of oxide/semiconductor structures, including Si (100), 4H-SiC Carbon face (000), Silicon face (0001) and a face (110) substrates at 400^oC. The accompanying electrical measurements showed that the deuterium (D) at the interface induced by water vapor exposure changes the interface defect density thus shifting the flat band voltage. The change of the flat band voltage is linearly proportional to the interface D content. In order to understand the full scope of the interaction between deuterium and the interface, nuclear reaction analysis (NRA) was used to quantify the deuterium uptake from water vapor exposure to Si-face SiC, C-face SiC and Si at temperatures from 100^oC to 1000^oC. Results show a non-monotonic behavior where D content increases up to temperatures of ~ 700^oC and then decrease. The trend is similar to the behavior of hydrogen accumulation at the Si/SiO₂ interface, although with significantly different characteristic temperatures for content peaking and loss. Loosely, the process is characterized in terms of two competing chemistries—passivation of dangling bonds in the up-take stage and the formation of H₂ molecules and their release in the loss stage. In conjunction with this study, H₂¹⁸O anneals were conducted to further understand the chemical nature of D/H at the interface, by which we were able to distinguish whether D/H interacted with the interface as “-D” or “-OD”. It was found that ¹⁸O concentration is extremely low compared to D suggesting that the D bonds to the interface as –D instead of –OD.

(1) Liu, G., Xu, C., Yakshinskiy, B., Wielunski, L., Gustafsson, T., Bloch, J., Dhar, S.; Feldman, L. C. Appl. Phys. Lett. 2014, 105, 191602.
(2) Liu, G., Xu, C., Yakshinskiy, B., Wielunski, L., Gustafsson, T., Bloch, J., Dhar, S.; Feldman, L. C. Appl. Phys. Lett. 2015, 106, 123502.

Fabrication of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high channel mobility is important in order to obtain the full advantage of Silicon Carbide’s (SiC) excellent material properties for energy efficient high power, high temperature electronics. Nitridation of the oxide/4H-SiC interface is the most established method for the producing commercial quality devices with acceptable mobility of about ~25 cm² V-1 s^-1 and adequate oxide stability and reliability. Improvement of the channel mobility ‘beyond nitridation’ while maintaining adequate oxide stability and reliability, is extremely desirable for next-generation devices. In 2014, D. Okamato et al (IEEE Electron Device Letters, Vol. 35, Dec. 2014) reported that introduction of Boron (B) atoms into the SiO₂/4H-SiC interface results in a significant improvement of channel mobility. Device stability under high temperature gate bias (HTGB) stress was not reported in that work. In this study, we have fabricated 4H-SiC lateral MOSFETs using B doped SiO₂ as the gate dielectric and focused on the device stability. Boron was introduced in thermally grown oxide layers on SiC via annealing in the presence of a B₂O₃ planar diffusion source. MOSFETs fabricated using this process have a peak channel field-effect mobility of about 115 cm²V^-1s^-1and a threshold voltage of 6 V, which is extremely attractive. In addition, capacitance-voltage measurements performed on MOS capacitors indicate significantly lower interface trap densities compared to as-grown thermal oxides. In spite of these promising properties, the oxide exhibits significant instability under HTGB stress, compared to standard nitride gate oxides. To understand if this instability is intrinsic to the B annealed oxide or processing related, further investigations are currently being conducted. The new studies employ Polysilicon gates in place of sputtered metal to diminish the effect of sputtering induced gate instability, as well borosilicate glass (BSG) deposition via PECVD with controlled B concentration. In this talk, we will report the results of these new experiments in addition to discussing the channel mobility and interface trap characteristics of BSG gated SiC MOSFETs in detail.

SiC has attracted a lot of attentions for high-voltage, high-power applications and most of the research focus lies on vertical devices because their advantages of carrying large currents in a small chip size. In recent years, SiC MOSFETs and IGBTs with > 10 kV blocking voltage have been demonstrated for ultra-high-voltage applications such as electricity transmission and distribution. To achieve such voltage ratings for vertical semiconductor devices, the edge termination plays a crucial role. In this work, a comparison of different techniques for SiC high-voltage devices is performed using numerical simulations. Specifically the method of counter doping (CD) introduced in the junction termination extension (JTE) region to create a multi-zone termination effect is investigated. Simulation shows that compared to other edge termination techniques, CD-JTE greatly reduces the sensitivity of breakdown voltage to JTE doses and surface charges. The multi-zone CD-JTE with outer rings shows that for a 30 μm thick epi-layer, 90% of the theoretical breakdown voltage is achievable with a wide tolerance of 11x10¹² cm^-2 to the JTE dose. The CD-JTE structure was also experimentally implemented and studied. Two groups of 4H-SiC PiN diodes were fabricated with two n-type drift layer thicknesses of 11 μm and 30 μm respectively, and with different termination structures, in order to demonstrate the wide JTE dose tolerance of CD-JTE. Three different doses, 1.7×10¹³ cm^-2, 2.2×10¹³ cm^-2, and 2.8×10¹³ cm^-2, were used for the critical JTE implantation. The measured breakdown voltages of the diodes with all termination structures and JTE doses were compared with simulation predictions. Electroluminescence at the breakdown voltage was recorded and used to locate the peak electrical field. The test results matched well with simulation. As a result of the effectiveness and robustness of the CD-JTE, the best achieved BVs from the diodes on the 11 μm and 30 μm epi-layers were 1850 V and 4800 V, respectively.

Many have noted that SiC MOSFETs experience charge-trapping-related threshold voltage (V_T) degradation, in the form of drift and hysteresis after unipolar and bipolar stresses [1]. Since power conditioning is a major application for SiC MOS, robust operation under AC switching at high temperature is essential. Some work (e.g., [2], [3]) has been done so far to study the effects of high temperature gate switching (HTGS), generally finding weaker effects than with similar DC stress conditions. However, reports of “non relaxation” [4] and ultra-fast measurements [5] have shown that V_T rapidly recovers following the removal of stress. The studies of HTGS so far have relied on post-stress characterization, resulting in data that is significantly underestimating the impact. This work will report on new results using ultra-fast measurement techniques to monitor V_T in situ during HTGS of commercially available SiC DMOSFETs.

DMOSFETs (Cree C2M0280120D), rated for 175 °C at V_GS of –10 V/+25 V, were stressed at 200 °C with an AC waveform applied to the gate and a small drain-source bias. The gate was switched at the maximum bias ratings at 10 kHz (50% duty) with 0-100% rise and fall times of 4 μs. These bias and temperature conditions were maintained continuously throughout the test. V_T was monitored in situ by sampling I_D during the transitions and interpolating to find V_GS at I_D=10 mA. V_T measured on the down (V_T⁺) and up (V_T^-) sweeps, along with the net hysteresis for a given cycle (ΔV_T), were collected as a function of stress time.

The stress response can be broadly grouped into two regions based on the trends of the observed data: Region 1 for the first ~1,000 s and Region 2 for stress times after ~1,000 s. The earlier Region 1 is characterized by V_T⁺ remaining nearly constant and V_T^- slowly decreasing by about 30 mV/dec, resulting in a widening of ΔV_T. During the longer stress times of Region 2, both V_T⁺ and V_T^- were seen to rapidly shift positively at rates of ~180 mV/dec and 90 mV/dec, respectively, causing ΔV_T to increase even further. Over the course of 54 hours of HTGS, V_T shifted by +0.5 V and ΔV_T increased from 0.2 V to 0.7 V. These results show that AC stress is causing not only a change in the amount of trapped charge at the interface and in the oxide, but also an increase in the number of actively switching traps. DC I_D-V_GS measurements carried out before and after the stress were able to see the same V_T drift but not the increase in ΔV_T. This degradation persisted after returning to room temperature and during subsequent biasing at high temperature.

[1] A. J. Lelis et al., IEEE T. Elec. Dev. 62(2), 316-323 (2015).
[2] R. Green et al., Mater. Sci. Forum 740–742, 549–552 (2013).
[3] D. A. Gajewski et al., Mater. Sci. Forum 778–780, 967–970 (2014).
[4] M. Sometani et al., Mater. Sci. Forum 821–823, 685–688 (2015).
[5] D. B. Habersat et al., presented at the ICSCRM, Giardini Naxos, Italy, 2015 (to be published in Mater. Sci. Forum).

4H-SiC MOSFETs show promise for use in high temperature and high voltage applications. Unfortunately, defects at the SiC/SiO₂ interface reduce the performance of these devices. Previously, our group utilized electrically detected magnetic resonance (EDMR) detected via spin dependent recombination (SDR) to identify defects at or near the SiC/SiO₂ interface utilizing the BAE biasing scheme: the SiC silicon vacancy [1], the E-prime center, and the 10.4 Gauss doublet [2]. These defects must have levels fairly near the middle of the SiC band gap, as they are effective recombination centers. We have expanded previous studies to include EDMR detection via spin dependent charge pumping (SDCP) [3] at both low field (~350 MHz) and X band (~9.5 GHz) in order to allow EDMR exploration of nearly the entire 4H-SiC band gap. Perhaps the most important finding of the (nearly) full band gap measurements is the absence of the carbon dangling bond spectrum in the SDCP. Our nearly full band gap measurements detect several previously observed spectra and several new features. However, with high signal to noise ratios, we do not observe the dangling bond spectrum; since nearly the entire band gap is now within our observational capabilities, we conclude that these defects are not present in numbers remotely comparable to those of several other centers and are thus not significant to device performance. In nMOSFETs, we observe a charge pumping EDMR spectrum dominated by a single line spectrum with an isotropic g = 2.0030. In pMOSFETs, we additionally observe a dominating, nearly isotropic single line spectrum with g = 2.00244 and 2.00248 when the c-axis is nearly parallel and perpendicular to the magnetic field, respectively. The results indicate that silicon vacancy centers very much dominate in the nMOSFET case and that additional defects also play some a role in pMOSFETS. Cantin, et al. report g-tensor components for a carbon dangling bond of g = 2.0023 and g = 2.0032 when the c-axis is parallel and perpendicular to the magnetic field, respectively. With quite high signal to noise ratios, we do not detect this spectrum in either n- or p- MOSFETs. An additional feature of some interest in the SDCP measurements is that in comparisons of NO annealed and non-NO annealed devices, we find that NO annealed devices have a significantly wider line width at both low and high magnetic fields. This broadening is likely due to a significantly higher concentration of nitrogen atoms in the SiC near the interface. In preliminary energy resolved SDCP measurements, we are also able to crudely distinguish differences in the distribution of defects involved in the interface densities of states, providing a proof of concept demonstration that SDCP can relate defect structure to interface densities of states.
[1] C. J. Cochrane, et al., Appl. Phys. Lett., 100, 02, 2012
[2] M. A. Anders, et al., IEEE IIRW conference proceedings, 2014
[3] B. C. Bittel, et al., Appl. Phys. Lett., 99, 7, 2011

Silicon carbide (SiC) is an attractive material for lots of different fields. These span from high power electronics, due to its properties as a high-temperature stable wide-band gap semiconductor, over to material engineering, with its high Mohs hardness of 9.6 and enormous chemical stability. During the last decades organic photovoltaics gets into focus of research, because of the benefits that such devices are offering: easy processability, flexibility and tunability of the absorbed wavelength range, by tailoring the materials properties. Hybrid photovoltaics go even further and combine the benefits of both organic and inorganic semiconductors. So, we suggest one novel application for SiC: as potential electron acceptor in organic hybrid solar cells. As this material offers a relatively high electron mobility and low toxicity, compared to currently dominating lead or cadmium-based compounds. In this study, we present a novel bottom-up approach for preparation of suitable nanocrystalline and nanoporous SiC for integration in organic semiconductor films. This material is obtained by a sol-gel-based and carbothermal reduction-assisted approach. The process is suitable for the fabrication of material of the cubic polytype in the nano- to microscale and even enables in-situ n- and p-doping. To gain nanocrystals (NCs) in a distinct size range, which allows to reach quantum confinement and accordingly tuning of the bandgap by changing the size of the NCs, a template assisted fabrication route is used. This method allows an easier and more cost efficient fabrication of SiC NCs compared to commonly used top-down methods like wet-chemical etching with hydrofluoric acid or laser ablation of commercial SiC wafers. We show first results on the properties of the obtained NCs, depending on the chosen process parameters. Investigations on the shape and crystal structure of the fabricated NCs and porous structures, performed by utilizing electron microscopy and X-ray diffraction will be shown. Photoelectron spectroscopy determination of the surface termination and chemistry (XPS) and relevant band energies (UPS) will be presented. Finally, an estimation of defect densities and photophysical properties will be given, which are important criteria for their applicability in hybrid solar cells.

Silicon carbide (SiC) has remarkable physical and electronic properties and has therefore been investigated intensively. There are more than 250 polytypes of SiC, among which β phase 3C SiC and α phase 4H and 6H SiC are the most frequently used. Different polytypes of SiC have different properties. 4H SiC has outstanding electrical properties such as a high bandgap, breakdown voltage and carrier mobility, and is mainly used in power device applications that require high voltage, power, and frequency.
The physical vapor transport (PVT) method is frequently used to grow single crystal 4H SiC. SiC produced using this method is characterized by a large diameter and high growth rate. In the process of growing single crystal SiC using the PVT method, the most sensitive and important factor is temperature. The occurrence of a temperature gradient inside the growth cell acts as a driving force for SiC crystal growth. Temperature gradients are also a significant parameter for determining both the growth rate and the quality of the resultant crystal. In addition to the overall temperature gradient in the growth cell, axial and radial temperature gradients can appear within the SiC crystal ingot.
To determine the impact of the temperature gradient on the SiC crystal ingot during growth of the single crystal SiC using the PVT method, we studied differences in the properties according to the growth stages of the SiC crystal ingot. This was accomplished by examining different locations within the ingot.
We analyzed changes in thermal stresses caused by these temperature gradients according to their location within the SiC crystal ingot. Using finite element method (FEM) simulation and nano beam electron diffraction (NBD) analysis, we confirmed that thermal stresses including tensile and compressive stresses differed in accordance with their location inside of the SiC ingot. In particular, large compressive stresses were observed near the edge of the wafer that was sliced close to the SiC ingot growth interface. SiC wafers were analyzed by the Synchrotron White Beam X-ray Topography method. Through this method, defects such as micropipe and dislocation behavior within SiC crystal ingot was evaluated according to temperature gradients that are one of the causes of defects in growing single crystal SiC. We also analyzed the correlation among thermal stresses, crystallinity and dislocation density of the SiC crystal. We confirmed that lower crystallinity and higher dislocation density not only reduce the SiC bandgap, but also increase the resistivity and diminish the electrical properties of SiC.

BPD half loops arrays (HLAs) formed in conjunction with interfacial dislocations (IDs) in homoepitaxial layers of 4H-SiC are responsible for introducing an increase in the forward voltage drop via the electron-hole Recombination Enhanced Dislocation Glide (REDG) and therefore are harmful to the device operation [1]. Previous studies [2] showed that screw-oriented BPD segments in the substrate intersecting the epilayer interface replicate through and form IDs and HLAs during the epitaxy growth. Other sources of IDs and HLAs include epilayer surface, scratches, micropipes and 3C inclusions. In this study, however, we have observed that short edge-oriented BPD segments in the substrate are drawn towards the interface during the epitaxy growth where IDs and HLAs are then observed to form [3]. A model has been developed to explain this observation, in which the edge-oriented segment of BPD in the substrate was drawn towards the interface under thermal stress, producing screw-oriented segments intersecting the growth surface; these screw segments of BPDs subsequently glide under the mismatch stress when the critical thickness is reached, and HLAs and IDs are then formed. Preliminary analysis suggests that thermal stresses in addition to image forces and mismatch stresses could play a role in the glide of the edge segments towards the interface. A detailed mathematical analysis will be carried out to determine the influence of each factor and the implications for optimum conditions for epilayer growth will be discussed.

[1] K. Maeda, M. Sato, A. Kubo and S. Takeuchi, J. Appl. Phys. 54, 161 (1983).
[2] Huanhuan Wang, Fangzhen Wu, Michael Dudley, Balaji Raghothamachar, Gil Chung, Jie Zhang, Bernd Thomas, Edward K. Sanchez, Stephan G. Mueller, Darren Hansen, and Mark J. Loboda, “Measurement of Critical Thickness for the Formation of Interfacial Dislocations and Half Loop Arrays in 4H-SiC Epilayer via X-ray Topography” Materials Science Forum, Vols. 778-780 (2014) pp328-331.
[3] Huanhuan Wang, Fangzhen Wu, Yu Yang, Jianqiu Guo, Balaji Raghothamachar, T.A. Venkatesh, Michael Dudley, Jie Zhang, Gil Chung, Bernd Thomas, Edward K. Sanchez, Stephan G. Mueller, Darren Hansen, and Mark J. Loboda, “Studies of the Origins of Half Loop Arrays and Interfacial Dislocations Observed in Homoepitaxial layers of 4H-SiC” Materials Science Forum, Vols. 821-823 (2015) pp319-322.

Schottky diodes based on SiC have shown potential in applications of power switching. In previous work on metal/Si and carbon/Si diodes, the presence of a thin insulating layer has been reported to significantly influence the electrical properties [1] resulting in devices of very high quality. Similar effects of a thin insulator layer on properties of Schottky diodes have been identified in experiments [2] and in modelling [3]. In this paper, finite element simulations have been used for the first time to optimise the structure of Schottky diodes in both n-type SiC and n-type Si in relation to the thickness and dielectric constant of an interfacial insulating layer, the metal workfunction, semiconductor type and doping. Modelling has been performed using Sentaurus Technology Computer-Aided Design (TCAD). The Schottky contacts were comprised of a metal film of variable work function formed on SiC or Si substrates with doping in the range from 10¹⁶ to 10¹⁸cm^-3. The effect of thickness (0-2 nm) of an insulating layer at the interface has been examined in terms of the current/voltage characteristics and other parameters of the diodes. The results have shown that increasing the thickness of the layer to 0.5 nm has reduced the reverse leakage current by a factor of ~10³ with only a slight reduction (~0.8 times) or even an increase (~1.3 times) in the forward current, depending on material properties and applied bias. The effect of variation in the dielectric constant of the interfacial layer on the Schottky barrier height and ideality factor of the diodes has also been examined in the simulations. Results are reported for the design of diodes to give an optimum rectification ratio. Both SiC and Si have significantly lower reverse current by the inclusion of an interfacial layer, however, the advantage in the forward bias was more difficult to design in SiC. We identify design parameters to achieve both lower reverse current and higher forward current in typical operation of a SiC power diode.
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Minority carrier lifetime is an important parameter of interest in high voltage bipolar devices such as PiN diodes and Insulated Gate Bipolar Transistors. We have carried out extensive characterization of free standing lightly doped 4H-SIC epitaxial layers using SEM, AFM and photoconductive decay technique by microwave reflectance measurements. Microwave energy produced by a Gunn diode at 36 GHz is incident on the wafer and the wafer is also illuminated with a pulsed laser at 266nm and 355nm. Thick (>180μm), lightly doped (