AlGaN/GaN high electron mobility transistors (HEMTs) are ideal for high-frequency and high power devices. One main and urgent issue that degrades this device is a large leakage current. To address this issue, metal insulator semiconductor HEMTs with high-k dielectrics is favorite method. Among a great number of insulator materials, atomic layer deposited (ALD) Al₂O₃, HfO₂ and plasma enhanced atomic layer deposited (PEALD) AlN are attractive. However, there are still some challenges for AlGaN/GaN due to its unique properties. For example, the insertion of the insulation layer would shift the threshold voltage to negative values, which is not desirable for enhancement mode AlGaN/GaN HEMT. The interface state density (D_it) occupying levels below the conduction band edge at the oxide/AlGaN interface, which degrades the device stability, is another concern. Whether ALD of Al₂O₃, HfO₂ and PEALD AlN could passivate the AlGaN surface is still not clear.
In this work, the ALD-Al₂O₃/AlGaN, ALD-HfO₂/AlGaN and PEALD-AlN/AlGaN interfaces were systematically investigated using in situ XPS, and ex situ electrical characterization. Band alignments are also proposed from high resolution XPS measurements. Initial results have shown that the Al₂O₃ and HfO₂ dielectric layers reduce the leakage current as expected with respect to metal/AlGaN/GaN Schottky. However, a high density of interface states and positive charges are detected, which originate from the AlGaN interface. The passivation effect of Al₂O₃, HfO₂ and AlN on AlGaN will be presented.
This work is supported by the AFOSR Asian Office of Aerospace Research and Development (AOARD) under Grant No. FA2386-14-1-4069.

In recent years, significant research efforts have focused on developing enhancement mode (E-mode) GaN-based devices fueled by many potential applications. Simpler power amplifier circuits using a single polarity voltage supply and increased safety using a normally-off device can be achieved using E-mode devices leading to lower cost and an improvement of system reliability. Using the combination of E-mode and depletion mode (D-mode) devices in direct coupled logic open up also new applications for nitride semiconductors. To realize normally-off operation of GaN transistors, several approaches have been reported in the past including recessed gate structures [1], p-type gate injection [2], fluorine plasma treatment [3], surface channel GaN [4], thermally oxidized gate insulator [5] and oxide charge engineering [6]. In this project, we report two approaches to modify the threshold voltage (V_th)/flat band voltage (V_fb) of GaN based devices. We present the application of fixed and oxide charges after TiO₂-alloying and annealing processes of Al₂O₃ on GaN and AlGaN/GaN based devices. As reported in [7], the use of Al_xTi_yO_z mixtures on p-Si device can shift the flat band voltage to more positive values after annealing due to the increasing number of negative fixed charges. In a second approach, we extend the previous research in [3] on fluorine plasma treatment by implanting fluorine ions directly into Al₂O₃ gate dielectrics to modify their fixed charge values. The effectiveness of these approaches for fixed charge modification of ALD-grown Al₂O₃ will be presented.
References:
[1] W. B. Lanford, et al., Electron. Lett. 41, no. 7, 449 (2005).
[2] Y. Uemoto, et al., IEEE Trans. Elect. Dev. 54, no. 12, 3393 (2007).
[3] Zhang et al., Appl. Phys. Lett. 103, 033524 (2013).
[4] W. Huang, et al., IEEE Elect. Dev. Lett. 27, no. 10, 796 (2006).
[5] K. Inoue et al., Elect. Dev. Meet., IEDM Technical Digest. International, pp. 25.2.1 (2001).
[6] B. Lu, et al., in Proc. Int. Workshop Nitride Semicond. Abstr.,536 (2008)..
[7] Jogi et al., J. Appl. Phys. 102, 114114 (2007).

In this presentation, the current status of the PowerGaN consortium, a ~$10M UK project in the area of GaN power electronics will be reviewed. The project consortium comprises over 30 researchers in the Universities of Bristol, Cambridge, Glasgow, Liverpool, Manchester, Nottingham and Sheffield with expertise in the areas of GaN on silicon materials growth, power electronics device design, silicon compatible semiconductor process optimisation, power electronics device reliability evaluation, power device packaging and power device evaluation in realistic power switching testbeds.
The overall aim of the project is to demonstrate a diversity of GaN-based power electronic devices which are fully compatible with silicon manufacturing approaches.
The presentation will review recent developments in the optimisation of areas such as the growth of the buffer layer between the silicon substrate and the GaN device channel with emphasis on the routes to minimise buffer leakage current, imcrease breakdown voltage, and minimise device current collapse. The status of the high-k/GaN gate stack optimisation will emphasis on device threshold voltage control, gate leakage current and hysteresis minimisation will be discussed. In addition, routes to mitigiate current collapse by appropriate engineering of the surface of the drift region between the gate and drain of the transistor will be considered.

Wide band gap semiconductors are of special interest for device applications that require high temperature operations, high frequency and high power density. Recent advance in polar oxide thin film growth ( e.g MgO, CaO, and Al₂O₃) on SiC and GaN growth has open possibilities for metal-oxide wide band gap semiconductor heterostructures with large tunable electronic properties. In this work we present experimental and theoretical study on MgO(111)/SiC(0001), and MgO(111)/GaN(111) heterostructure interfaces with focus on atomic and electronic properties. Atomic resolution transmission electron microscopy imaging reveals that molecular beam epitaxy grown MgO(111) films form atomically sharp interfaces with both SiC and GaN. In addition we demonstrate that the atomic interface structure of these interfaces can be engineered by suitable preparation of the substrate surfaces. First principle total energy calculations show that the driving force that determines atomic stacking at these interfaces is the screening of the interfacial dipole moment. The interface electronic properties are very sensitive on the atomic structure due to abrupt change of the electrostatic potential across the polar heterostructures. For example, the Mg terminated MgO(111)/SiC(0001) interface is insulating with valence- band offset of 3.5 eV, in contrast to n-doped O terminated interface that has a 1.5 eV valence-band offset. The systematic studies by density functional theory with GW corrections show that band offsets at these heterostructures can vary from ~ 1eV to ~3.7 eV as a function of the interface atomic structure. This property makes polar oxide/semiconductor heterojunctions very attractive for device applications.

Silicon dioxide is a stable dielectric with large band offsets that may be suitable for wide bandgap semiconductors. This research is focused on the band offsets and band bending for PEALD grown SiO₂ on in situ cleaned GaN. We have investigated the ALD deposition of low-temperature SiO₂ using tris(dimethylamino)silane (TDMAS) and oxygen plasma on GaN substrates. Samples were cleaned ex-situ with acetone, methanol, and NH₄OH to increase the number of OH groups on the surface and increase nucleation during ALD deposition. PEALD was then used to deposit thin films using varied parameters to ensure self-saturating deposition. Thin film thicknesses, compositions, and band offsets were then determined with in-situ x-ray photoelectron spectroscopy (XPS). Results show the growth rate for TDMAS and oxygen plasma process increases as temperature decreases—at least within the ALD regime. The growth rate is higher at 550 °C, which is likely the result of thermal decomposition of TDMAS. In addition, the high-temperature films demonstrate small concentrations of contamination from the molybdenum sample holder. Results demonstrated temperature does not greatly affect the stoichiometry of the films. In addition, a more detailed analysis of the films shows increasing the deposition temperature resulted in the increase of a secondary O1s peak; however, this peak was not present for thick films, where the substrate was undetectable. This secondary peak suggests the high temperature may oxidize the substrates. This effect may also explain the variation in the valence band offsets (VBO) of the materials deposited at different temperatures which varies by nearly 0.5 eV, where the measurement technique does not account for the potential drop across the interfacial Ga-O layer. The next stage of this work will employ electrical measurements to ascertain the quality of this interface on SiO₂/Si and ascertain the effects of potential plasma damage.
This research is supported by the Office of Naval Research through the DEFINE MURI program, N00014-10-1-0937.

Strong spin-orbit coupling leading to band inversion in bulk is necessary for creation of topological insulator states (TI) or quantum spin Hall systems. Electric field can also be used to invert the band structure. Nitrides in wurtzite phase possess an internal electric field due to spontaneous and piezoelectric polarization which is sufficient to invert the band-ordering of a narrow-gap InN. A TI state exists in a thin-film of InN sandwiched between GaN layers [1]. InN is specifically chosen as quantum well material because it is a low band-gap material and has considerable lattice mismatch with GaN giving a pronounced piezoelectric effect in addition to spontaneous polarization. For a certain quantum well thickness, inversion of bands happen at a threshold value of the polarization field. Polarization fields in nitrides can be controlled by selecting a facet orientation of the quantum well layer determined by the dominant polarization mechanism.
The dispersion of GaN/InN/GaN quantum well heterostructure is computed with a 6-band k.p Hamiltonian. The 6-band Hamiltonian is used in conjunction with the electrostatic and strain effects that are present in the GaN/InN/GaN heterostructure. The strain Hamiltonian is computed using the Bir-Pikus deformation potential theory. In a normal ordered wurtzite material, the Γ₁ symmetry point is energetically placed over Γ₆ . The band structure of the GaN/InN/GaN heterostructure due to the strong internal electric field has this sequence reversed demonstrating the inverted band profile. Band-gap closing edge states (degenerate Dirac cones) are therefore found when a nano-ribbon is constructed from the inverted quantum well. The nano-ribbon is confined along the y and z-axes and periodic along x-axis. The edge states of this ribbon are also determined to be spin-polarized.
Under the influence of an external electric field (1.5 MV/cm), the two degenerate Dirac cones split in energy and separate along the energy axis. Similarly when an external magnetic field is applied along the z-axis, the two Dirac cones shift along the x-axis. The B-field therefore acts like a horizontal gate and allows the possibility of a spin-tunnel device between the two shifted states with opposite spin polarization.
Further, at a finite k-vector, the Rashba-induced spin-splitting on the surface of this heterostructure is computed. The splitting under a first-order approximation is independent of k-vector [2] and corresponds to the polarization field&’s contribution to the Rashba coefficient. Finally, the interplay of mechanisms that control spin-relaxation times is used to design a spin transistor. An enhancement in the lifetime of the spin-polarized states under certain growth conditions is observed due to mutual cancelation the Rashba and Dresselhaus splitting [3] to suppress spin-relaxation.
[1] M.Miao et al., Phys. Rev. Lett. 109, 186803
[2] V. Litvinov, Appl. Phys. Lett. 89, 222108
[3] Q. Zhang et al., Appl. Phys. Lett. 95, 031902

Two-dimensional (2-D) semiconductors exhibit excellent device characteristics, as well as novel optical, electrical, and optoelectronic characteristics. In this talk, I will present our recent advancements in contact engineering, surface charge transfer doping, and heterostructure devices of layered chalcogenides. Forming Ohmic contacts for both electrons and holes is necessary in order to exploit the performance limits of enabled devices while shedding light on the intrinsic properties of a material system. In this regard, we have developed different strategies, including the use of surface charge transfer doping at the contacts to thin down the Schottky barriers, thereby, enabling efficient injection of electrons or holes into MoS2 and WSe2 mono- and multi-layers. Additionally, I will discuss the use of layered chalcogenides for various heterostructure device applications, exploiting charge transfer at the van der Waals heterointerfaces.

The layered transition metal dichalcogenides (TMDs) such as MoS2 are being extensively studied as possible channel materials for ‘beyond-Roadmap devices&’ [1]. However, their contact resistances are often rather large, and it is not clear what controls contact resistances and how to improve them. The standard model of contact behavior would be the metal induced gap state (MIGS) model of Schottky barrier heights (SBHs) [2,3]. However, for top contacts on layered materials, it might be argued that that the van de Waals bonding causes the metal to semiconductor distance to be too large, so that the MIGS model is less relevant, and that the SBH becomes ‘unpinned&’ as in one previous analysis [4]. Here we calculate the SBH of for the top and edge contacts on various TMDs, both bulk and monolayer, covering metals with a wide range of work functions from Sc to MoO3, using a supercell (slab) model and density functional theory. We extract the SBH in each case by using the Mo 4s core level as a reference energy to identify the valence band top in cases of strong hybridization with the metal - the theory analogue of Kraut&’s method. We find that the Schottky barrier pinning factor S is of order S=0.34 and 0.28 for bulk and monolayer MoS2, respectively. This is consistent with the stronger pinning of S= 0.1 found experimentally [1], and not with the weakly pinned S=0.7 found by Gong [4]. We then find that S follows the standard dependence on optical dielectric constant found for 3 dimensional semiconductors found many years ago within the MIGS model by Monch [2]. We note that old SBH data for layered GaS, GaSe and GaTe [5] also follow the MIGS model. Thus, TMD contacts do follow a pinned MIGS model, despite van de Waals gaps. This might lead to larger SBHs in some cases. We find that substitutional doping can be used to lower depletion lengths and thereby reduce contact resistances in some cases.
1. S. Das, H. Y. Chen, A. V. Penumatcha, and J. Appenzeller, NanoLett 13, 100 (2013)
2.W Mönch, Phys Rev Lett 58 1260 (1987);
3. J Robertson, J Vac Sci Technol B 18 1785 (2000)
4. C Gong, L Colombo, R M. Wallace, K J Cho,Nano Lett., 14, 1714 (2014)
5. S Kurtin, C A Mead, J Phys Chem Solids 30 2007 (1969)

Recently, transition metal dichalcogenides (TMDs) have stimulated much interest because of their two-dimensional structures and sizable band gaps for potential applications in electronic devices². Among all TMDs, MoS₂ a promising candidate with thickness-dependent band gaps: 1.8 eV for monolayer to 1.2 eV for bulk ¹. As a major strategy for modulating the properties of semiconductors, doping on monolayer MoS₂ has been widely studied including the S vacancies³_, alkali adsorption, halogen, nitrogen group elements substitution and molecular adsorption doping^5,6,7. Some doping have been applied to experiments and device fabrications^{8, 9}. Regarding doping in multilayer MoS₂, there are only a few investigations in the literature. As doping will usually cause the effect of scattering which will decrease the mobility of electrons, it is important to investigate the effect of doping in multilayer MoS₂.
In this work, the first-principle calculations are adopted to investigate the doping effect on the electronic structure of monolayer and multilayer MoS₂ by substitutional doping at S site with halogen group (F, Cl, Br, I) and nitrogen group (N, P, As, Sb) species. It is found that halogen doping causes an n-type doping and nitrogen doping causes a p-type doping of MoS₂. In the multilayer case the energy bands of the doped layer are shifted with respect to the undoped layer, resulting in the decoupling between layers. These results are interesting for TMD electronics, optoelectronics, and catalyst applications. Furthermore, in order to know the energetic stability, formation energy is also calculated and for the charged case there is an artificial electrostatic interaction between image charges which will cause inaccurate formation energy. Gaussian model charge and the scaling scheme are used to eliminate this effect.
This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA.
References
[1] Kuc, A., N. Zibouche, and T. Heine, Phys. Rev. B, 83(24), 2011, 245213.
[2] Radisavljevic, Branimir, et al., Nature nanotech. 6(3), 2011, 147-150.
[3] Komsa, Hannu-Pekka, et al., Phys. Rev.Lett., 109(3), 2012, 035503.
[4] Dolui, Kapildeb, et al., Phys. Rev. B 88(7), 2013,075420.
[5] Zhao, Peida, et al., ACS nano (2014) DOI: 10.1021/nn5047844
[6] Mouri, Shinichiro, et al., Nano letters 13, no. 12 (2013): 5944-5948
[7] Choi, Min Sup, et al., ACS nano 8, no. 9 (2014): 9332-9340.
[8] Yang, Lingming, Kausik Majumdar, Han Liu et al., Nano letters (2014) DOI: 10.1021/nl502603d.

Dynamic electrical control of conductivity in two-dimensional (2D) materials is one of the most promising schemes for realizing energy-efficient electronic devices. Monolayer transition metal dichalcogenides (TMDs) are 2D materials that can exist in multiple crystal structures, each of different electrical conductivity. Using density functional approaches, we discover that a structural semiconducting-to-metallic phase transition in some monolayer TMDs can be driven by electrical stimuli, including change of charge density and bias voltage. We find that a bias voltage approximately 0.5~1 V can trigger the phase transition in MoTe₂, while a larger voltage is required for the transition in other monolayer TMDs. The threshold bias voltage is strongly influenced by the substrate on which the monolayer is placed. Carefully choosing the substrate could greatly reduce the threshold bias voltage for the phase transition, and therefore consume much less energy, suggesting potential applications in electronics with very high energy efficiency. The dynamic control of this semiconducting-to-metallic phase transition can be achieved utilizing standard electronic devices like the electrostatic gating employed in a field-effect transistor. We have also calculated the phase boundary of a reported metallic-to-metallic phase transition in TaSe₂ to compare with earlier STM experimental results and reasonable agreement is observed. Our findings open up the possibility of manufacturing ultrathin flexible two-dimensional phase change electronic devices with potential for higher energy efficiency than conventional electronic devices.

Group III-Sb compound semiconductor is a promising material family for future transistors owing to their superior hole and electron transport properties for future CMOS and large controllable band offsets for high-performance TFETs. The heteroepitaxial growth of GaSb on Si substrate has significant advantage for volume fabrication of III-V ICs. High lattice mismatch between III-Sb&’s and Si results in 3D nucleation that is usually mitigated by incorporation of metamorphic nucleation layer (NL) with low adatom mobility, such as AlSb. We studied NL coverage rate and growth morphology of the AlSb NL grown by Migration-Enhanced molecular-beam Epitaxy (MEE) using in-situ Auger electron spectroscopy and AFM. The coverage kinetics was analyzed with Avrami&’s approach that allowed for accurate determination of nucleation density and evolution of the 3D islands. Effect of AlSb NL growth parameters and surface morphology on mobility and hole density in strained InGaSb quantum wells was studied. The optimum growth temperature of 300 ⁰C is found for AlSb NL, resulting in room temperature Hall mobility of 660 cm²/V s at 3x10¹¹ cm² sheet hole density in the strained InGaSb QW p-channel. Using various designs of metamorphic superlattice buffers, thick GaSb layers were grown on Si(001) ,6⁰ to [110] miscut Si(001), SOI (001) and GaAs (001) substrates by molecular beam epitaxy. Buffer design controls the defect density in GaSb that affects the electrical properties of the layers. Acceptor states related to the defects are quantified using differential Hall measurements in undoped progressively etched structures and TEM/AFM imaging. Optimized buffers allow to reduce defect density below 10⁸ cm^-2 that results in ~1x10¹⁷ cm^-3 concentration of defect-related acceptors. The effect of growth-related defects (threading dislocations and microtwins) on hole concentration and mobility in strained InGaSb QWs is observed and quantified. The result on strained InGaSb p-MOSFETs grown on Al(Ga)Sb metamorphic buffers are summarized.

Thin films of Polyvinylidene Fluoride (PVDF) copolymers have been incorporated within ferroelectric field effect transistors, all organic thin film transistor devices (OTFTs), piezoelectric actuators, and recently proposed as the ferroelectric layer in a promising multiferroic tunnel junction^[1]. The properties of most of these devices would benefit from reduced thickness and better thickness control of the ferroelectric layer during device processing.
A proven means of making ultrathin films of the PVDF copolymer is the Langmuir-Blodgett (LB) technique. This technique involves dissolving the polymer in a volatile solvent which is then dispersed dropwise onto a purified water subphase, leaving an ultrathin layer of the copolymer on the water surface. The ability to control the thickness on the molecular level is the most prominent feature of this technique.
In some early studies^[2], the thickness was found to be about 5 Angstroms, or roughly the same thickness as the intermolecular spacing of the all-trans β phase for the ferroelectric polymers. Later studies have led to the fabrication of films composed of thicker transfer steps: ~ 1.8 nm per deposition^[3]. The discrepancy is likely explained by the nature of the VDF molecule: it is not an amphiphile.
In this study, we further investigate the properties of Langmuir films of ferroelectric copolymers using Brewster Angle Microscopy and discuss the observation of a film phase transition based on abrupt changes observed in the compressibility of the films. The main goal of this project is to discover the extent to which the device properties (like thickness) of PVDF films can be modified through processing conditions.
1. J. P. Velev, J. M. Lopez-Encarnacion, J. D. Burton, and E. Y. Tsymbal, “Multiferroic tunnel junctions with poly(vinylidene fluoride),” Phys. Rev. B, vol. 85, 125103 (2012).
2. A. V. Bune, V. M. Fridkin, S. Ducharme, L. M. Blinov, and S. P. Palto, “Two-dimensional ferroelectric films,” Nature (London), vol. 391, pp. 874-877, Feb. 1998.
3. M. Bai, A. V. Sorokin, D. W. Thompson, M. Poulsen, S. Ducharme, C. M. Herzinger, S. Palto, V. M. Fridkin, S. G. Yudin, V. E. Savchenko, and L. K. Gribova, “Determination of optical dispersion in ferroelectric vinylidene fluoride (70%)/trifluoroethylene (30%) copolymer langmuir-blodgett films,” J. Appl. Phys., vol. 95, no. 7, pp. 3372-3377, Apr. 2004.

By reaching the limit of the scaling down, there are many attempts to overcome the physical problems. Among them, strain engineering has been used widely to enhance mobility of carriers effectively with doping process. However, in case of highly doping, it is known that several problems such as surface segregation, interface defects happen. To reduce these side effects, it is important to analyze the facet grown within epitaxial layer. In the study, after detecting (111) oriented stacking faults within the epitaxial layers, we attempted to find the critical moment that the defects are generated. And we investigated the optimized condition to minimize the generation of the defects.
In-situ P-doped epitaxial layers were grown by using ultra-high vacuum chemical vapor deposition (UHV-CVD) on the blanket bare and patterned Si wafers. The source gases are disilane (Si₂H₆) and phosphine (PH₃, 1% in H₂). The analysis of the microstructure and defects was conducted by high resolution transmission electron microscopy (HR-TEM), and the strain within the epitaxial layers was measured by high resolution x-ray diffraction (HR-XRD). The phosphorus concentrations were measured in secondary ion mass spectroscopy (SIMS) depth profile experiments.

The area of molecular spintronics became a subject of rising interest during the last few decades because it has the potential for devices in which information is stored and manipulated at the scale of a single molecule. In this work, electronic properties of different ferrocene containing cyclic molecules are studied within the Density Functional Theory (DFT) formalism as implemented in the Quantum espresso [1] and Turbomole [2] codes. Furthermore, trends for electron transport mechanisms of these molecules within molecular junctions shall be predicted theoretically with the use of maximally localised Wannier functions and the Landauer formalism. The motivation for this work is based on the experimental research of Tim Albrecht et al. [3] who examine molecular junctions by carrying out Scanning Tunnelling Microscopy (STM) to obtain single molecule conductance spectra.
[1] http://www.quantum-espresso.org#8232;
[2] http://www.turbomole-gmbh.com#8232;
[3] W. Haiss, T. Albrecht, H. van Zalinge, J. Phys. Chem., 111(24), 6703-6712, 2007

The continuous trend of achieving more complex microelectronics with smaller nodes yet larger wafer sizes in microelectronics manufacturing lead to aggressive development requirements for chemical mechanical planarization (CMP) process. Reactive additives such as surfactants, oxidizers, and pH regulators are being used for the CMP slurry formulation to manipulate CMP selectivity by changing the chemical and physical properties of the first few atomic layers on the wafer surfaces. Most frequently the utilization of surface-active agents became a common practice to achieve selectivity as well as provide slurry particle stability for defectivity control [1-3].
There is an increased focus on germanium (Ge) and III-V semiconductors as potential channel materials for sub-22 nm devices, since both electron and hole mobilities in Ge are higher than those in silicon (Si). CMP is an enabler for integration of these materials into future device applications.
In this study, we implemented a design of experiment (DOE) methodology in order to understand the optimized CMP slurry parameters such as optimal concentration of surface active agent (sodium dodecyl sulfate-SDS), concentration of abrasive particles and pH from the viewpoint of high removal rate and selectivity while maintaining a defect free surface finish. The responses examined were particle size distribution (slurry stability), zeta potential, material removal rate (MRR) and the surface defectivity as a function of the selected design variables. The impact of fumed silica particle loadings, oxidizer (H₂O₂) concentration, SDS surfactant concentration and pH were analyzed on Ge/silica selectivity through material removal rate (MRR) surface roughness and defectivity analyses.
References:
1. Basim G.B., Engineered Particulate Systems for Chemical Mechanical Planarization, Lambert Academic Publishing, ISBN 978-3-8433- 6346-4, 2011.
2. Vakarelski I. U., Brown, S.C, Basim G.B, Rabinovich, Y. I., and Moudgil B.M., "Tailoring Silica Nanotribology for CMP Slurry Optimization: Ca²⁺ Cation Competition in C₁₂TAB Mediated Lubrication", ACS Applied Materials & Interfaces, Vol. 2, No 4, pp. 1228-1235, 2010.
3. Rosen, M. J., Surfactants and Interfacial Phenomena, ,Wiley, New York, p. 337, 1989.

Complex fabrication process and poor signal scaling laws of the silicon based memory devices have increased the interest in perusing the fabrication of non-transistor based memory structures. Previously a redox-based memory system based on the variable doping has been demonstrated by our group^1,2. This memory system consists of a solid-state junction between compensatively-doped polymer and undoped WO₃ in a net low conductivity state formed by electrochemical deposition. In the presence of a sufficiently high electric field, dopant ions relocate into the metal oxide layer, resulting in an n-doped metal oxide and p-doped polymer and a net high conductivity state. This system is capable of producing transient current-voltage characteristics that can be controlled by electric field and act as a memory. As a non-transistor memory structure, this system has the potential to be integrated into standard CMOS technology. To do so, the junctions should be formed on metals commonly used in CMOS technology. In recent work, our group has focused on use of these metals including aluminum and copper as the top. Early tests on the aluminum contacts did not show promising results, however a deposition method on copper has been demonstrated³. The new system consists of an electrochemically deposited tungsten oxide film covered by electrophoretically deposited conducting polymer (poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)) all formed at negative potentials on copper substrates. The electrical properties of these junctions demonstrate that they have the potential of creating CMOS-compatible polymer based memory devices. Current efforts are focused on demonstrating the similar electrical behavior on an array of small junctions. A crossbar structure of copper contacts has been fabricated to form a 10x10 array of these junctions. The resulting electrical properties of the memory array junctions, their current-voltage behavior has been used for modeling them as an element that can be used in CMOS device simulation tools, such as Hspice. The junction has been modeled as a voltage controlled current source and a piece-wise linear model has been developed to model the real current-voltage characteristics of the junction as the function between the voltage and current of this voltage controlled current source in the simulations. This model is currently under study for simulating and designing a complete CMOS chip with a deposited array of the polymer memory junctions on top which will work as a full memory system, capable of addressing, writing and reading operations on different bits of the memory.
References
[1] Rahman, et al. "Engineering dopable heterojunctions for modulating conductivity in the solid state" American Chemical Society.
[2] Kumar, et al. "Controlling volatility in solid-state redox-based memory devices" Chemical Communications.
[3] Yahyaie, et al. "Polymer-Based Memory Structures on Copper Substrates" Electrochemical Society.

Rare earth doping is widely used to improve the properties of high-$k$ dielectric oxides. We have performed the density functional theory calculations for Gd doping in HfO$_2$. Our calculated results indicate that the tetragonal phase is more stable than the monoclinic phase when the Gd doping concentration is greater than 15.5\%, which is in a good agreement with the experimental observations. The dopant's geometric effect is mainly responsible for the phase stability. The Gd doping enlarges the band gap of the material. The dielectric constant for the Gd-doped HfO$_2$ is in the range of 20-30 that is suitable for high-k dielectric applications. Moreover, we have investigated the structural and electronic properties of the dopant-oxygen vacancy complexes in Gd-doped HfO$_2$. Our calculations indicate that the Gd dopants interacting with oxygen vacancies can substantially shift up the V$_O$ energy states towards the conduction band edge. This together with other effects, such as capturing the localized electrons at the oxygen vacancy by Gd dopants and suppressing the randomicity of oxygen vacancy formation, improves the reliability of the devices made from Gd-doped HfO$_2$. Based on the calculated results, we have presented an explanation for the experimentally observed decrease of the V$_O$-related photoluminescence intensities upon Gd doping in HfO$_2$.

Resistive random access memory (RRAM) which is a strong contender to replace charge-based memories (e.g. Flash memory, dynamic random access memory) has promising potential as the next generation nonvolatile memory owing to its excellent properties, such as extreme scalability, low power consumption and high write/erase speed. However, in order to initially activate the fresh memory cell into the switchable states, high electroforming voltage is required which consumes power and may cause permanent damage to the switching performance and lower the device yield.
In this work, the RRAM device (Ag/amorphous Si/Au NPs/Au) was fabricated by inserting a gold nanoparticles (Au NPs) mono-layer within the amorphous Si sandwiching between the active top and inert bottom electrodes. We demonstrate the Au NPs-interlayer amorphous Si memory devices deliver great improvements in lowering the electroforming voltage as well as enhancing the ON/OFF ratio, as compared to a pure amorphous Si memory structure. In addition,we also demonstrated that the low electroforming voltage can be realized by replacing the amorphous Si with zinc oxide layer in the similar configuration with Ag as the electrodes (Ag/ZnO/Au NPs/Au), whereas this does not happen in the Au/ZnO/Au NPs/Au memory structure with Au electrodes.From these observations, a possible switching mechanism is discussed based on the formation of Ag filaments around the tips of Au NPs, where the filaments can be nucleated and propagated easily and quickly. At the same time, the electroforming voltage can be tuned by changing the size of Au NPs. This fabrication approach offers a versatile structural platform for next-generation memory applications with enhancement of the switching properties.

Analog memristive and memcapacitive switching characteristics were demonstrated in Pt-Fe₂O₃ core-shell nanoparticles (NPs) assembly on p⁺-Si substrate. Memristor having memristive characteristics, i.e. reversible resistance change with memory function, has been actively explored for a variety of device applications including a nonvolatile resistive random access memory (RRAM) with digital-type resistance change, analog switch, analog memory, and neuromorphic devices with analog-type resistance change. In particular, the analog memristor emulates the biological synaptic motion with varying synaptic weight, called potentiation and depression, so it is considered to be a good candidate device for synaptic element in neuromorphic device. Besides the memristor, the memcapacitive characteristics defined to show the capacitance change with memory function has been recently reported. In this study, we demonstrate the concurrent analog and polarity-dependent memristive and memcapacitive characteristics in the assembly of g-Fe₂O₃ NPs having Pt core (called Pt-Fe₂O₃ core-shell NPs) on p⁺-Si substrate, which can be potentially applied to neuromorphic and analog devices. These NPs have large surface and interfacial area that effectively provides trapping and hopping sites for charge transport and consequently influences on the resistance and capacitance change. Also, the applied electric field is concentrated in the metallic Pt cores inside the insulating Fe₂O₃ shell; therefore the memristive and memcapacitive characteristics associated with charge trapping is thought to be facilitated by using Pt-Fe₂O₃ core-shell NPs. The Ti/NPs/p⁺-Si structure exhibited the sequentially decreasing resistance and increasing capacitance as repeating the application of negative voltage at top Ti electrode. It is thought that the negative charging of the assembly increased free electron density in the assembly or reduced the Schottky barrier height, which increased the current and diffusion capacitance at n-NPs/p⁺-Si junction. On the other hand, the positive biasing increased the resistance and decreased the capacitance by reducing the free electron density and increasing depletion width at the junction. These concurrent analog memristive and memcapacitive characteristics emulated the biological synaptic potentiation and depression motions, which is indicative of potential application to neuromorphic devices as well as analog nonvolatile memory and circuits.

The electrical manipulation of ultra-thin magnets via strong spin-orbit coupling is currently the focus of strong research interest, because this phenomenon may offer significant advantages with respect to energy efficiency and high-speed operation in technological applications including non-volatile memory and logic devices. Very recently a new method for electrical control of magnetization has been demonstrated where spin-Hall induced spin torques from in-plane currents achieve deterministic magnetic reversal of a magnetic layer in multilayer NM/FM/MO_x samples consisting of a nonmagnetic heavy metal (NM) adjacent to an ultra-thin ferromagnet (FM) that is capped with a thin metal oxide (MO_x): for instance, Pt/Co(<1nm)/AlO_x or Ta/CoFeB(~1nm)/MgO on rigid substrates. At the same time a magnetic system with a sufficient perpendicular magnetic anisotropy (PMA) offers superior areal densities and thermal stabilities than in-plane magnetic system. However such demonstrations utilizing spin-orbit torques have been performed on rigid substrates, while only in plane magnetized system have been studied on flexible substrates as far as we know. Implementation of perpendicularly magnetized thin films and of electrically functional devices on flexible substrates may offer new degree of freedom such as strain effect on the ultrathin magnetic films with a strong spin-orbit coupling. Moreover the flexibility has advantages in applications with bendable, stretchable and/or mobile environment.
In this talk we present the magnetic characteristics of ultrathin multilayers with a sufficient PMA that were grown on a flexible plastic substrate by dc/rf magnetron sputtering. In addition we fabricate cross-Hall bar devices and demonstrate fully deterministic magnetic reversal of perpendicularly magnetized square dots via in-plane dc and/or pulsed currents. We believe that integration of two emerging technologies promises new spintronic devices that can be utilized in arbitrary surface geometries and be worked in ultra small dimensions.

Indium nitride (InN) has attracted much attention because of band offset to GaN and related materials. However, there has been difficulty in using InN as commercial devices due to the presence of electron accumulation at the surface. The electron accumulation layer is hypothesized to be due to an In-In double layer at the surface. To utilize InN in practical devices, it is critical to remove this In-In double layer and form a non-metallic surface. The atomic, elemental, and electric structure of InN(0001) surface before and after removal of the In-In double layer was investigated with using scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), and scanning tunneling spectroscopy (STS) under different cleaning and atomic layer deposition (ALD) methods.
(1) In-situ atomic hydrogen cleaning of InN(0001) surface was investigated since this process is successful on GaN(0001). STM images were consistent with rows of indium dimers due to the preferential nitrogen depletion resulting in high indium to nitrogen ratio. STS measurement showed that there was no band gap states, indicating metallic characteristics of InN surface consistent with an In-In double layer surface termination.
(2) ex-situ wet cleaning using HCl, NH₄OH, and (NH₄)₂S solution was performed. After wet cleaning, STM images showed that the surface was smooth and uniform. XPS spectroscopy showed that the wet cleaned surface had less than 10% carbon and oxygen. STS spectroscopy showed a finite band gap of 0.7 eV with highly n-type characteristics consistent with strong intrinsic accumulation of electrons on the InN surface.
(3) O₂ passivation of InN surface was performed to remove the In-In double layer. STM imaging showed that the oxidized surface was atomically flat and uniform. STM line traces illustrated that clusters were formed with step height of 3.5 angstrom which belongs to two monolayers of InO_x. The band gap at O₂ passivated InN surface was ~0.8 eV which is slightly larger than the wet cleaned surface of ~0.70 eV. Furthermore, the n-type characteristic was eliminated due to the formation of O-In-O layer which reduces accumulation of electrons on the InN surface The Fermi level lie in the center of the band gap . XPS showed oxidized InN surface has less than 5% carbon and provides high density of nucleation sites for trimethyl aluminum (TMA).
(4) ALD nucleation was studied using TMA pre-dosing and an additional 10 cycles of TMA and H₂O dose on an O₂ passivated InN substrate. After the 10 cycles of ALD, ratio of Al to O ratio was 2:3 corresponding to stoichiometric ratio of Al₂O₃. The ALD process broadened the band gap from ~0.8 eV to ~1 eV due to the formation of Al-O-Al bonding. A larger band gap than conventional InN surface is an ideal template for InN metal oxide semiconductor (MOS) capacitor fabrication. In sum, an unpinned non-metallic interface can be formed on InN using an oxidant to remove the In-In layer and a reductant to nucleation the ALD.

Non-volatile memory (NVM) devices based on ferroelectric thin films show bistable polarization at zero bias, designated as ‘0&’ and ‘1&’ logic states. Current emphasis on developing flexible and large area devices requires use of polymeric and organic materials which makes organic ferroelectric polymers such as P(VDF-TrFE) worth exploring due to their low temperature and solution processibility. The optimum performance of a ferroelectric NVM device needs a remnant polarization of over 4-5 mu;C/cm², low operating voltage and low leakage current. To meet these requirements, we investigated the variation of process variables such as cooling time and electrode on the film formation and its electrical properties. We found that fast cooled samples possess higher β-phase fraction which characterizes the ferroelectric nature of P(VDF-TrFE), leading to an increased polarization by 30%, decreased coercivity by 60% and reduced electrical leakage in capacitive memory devices. These improvements in the ferroelectric characteristics are attributed to evolution of a favorable microstructure and crystallographic alignment. For further reduction of leakage characteristics of the P(VDF-TrFE) devices, we incorporated PMMA, a dielectric material, along with P(VDF-TrFE) with different amounts in three different configurations : in the form of blend, and two bilayer structures, one with PMMA films below P(VDF-TrFE) films and another with PMMA films on top of P(VDF-TrFE) films. We find that PMMA incorporation leads to nearly two orders of magnitude reduction in the electrical leakage rendering bilayer devices more suitable for device applications than P(VDF-TrFE) only devices: 60 nm PMMA led to a smother dielectric stack with remnant polarization between 4-6 µC/cm². Organic ferroelectric field effect transistor (FeFET) fabricated by thermal evaporating pentacene on the smooth P(VDF-TrFE)/PMMA films showed enhanced electrical characteristics (large drain to source current at lower gate voltage) with promising non-volatile memory functionality with an order of magnitude improvement in I_on/I_off ratio.

Resistive random access memory has engaged great attention because of superior characteristics, such as simple metal-insulator-metal structure, high density integration, fast write/erase/read operation and low-power consumption compared to Si-based nonvolatile memory.
Most of the active materials for those memory devices have relied mainly on perovskite and related compounds, for instance, SrZrO₃ and metal oxides such as TiO₂, NiO, Cu_xO [1-2]. One of these materials, titanium oxide (TiO₂) exhibits promising oxide semiconductor for the application of nano-scale electronic behaviors such as resistive random access memory and switching of memristive devices[3]. In particular, great interest has been engaged on TiO₂ semiconductors as an active layer for memory devices due to their low cost, the abundance of Ti element, and their high transparency owing to a wide band gap.
Although the TiO₂ active layer have been demonstrated by the several methods, such as solution-process, pulsed laser deposition, magnetron sputtering[4]. The performances of these exhibited the relatively low electrical characteristic limiting the effects of process parameters. Furthermore, these methods can not to assure the deposited thickness of below 50 nm. To prepare high-performance and driven by low voltage TiO₂ based memory, it is necessary that a well understanding of how the interface structure affect the memory performance and a comprehensive investigation of the optimization conditions.
In this presentation, we report on resistive switching behaviour in a memristor device composed of a bilayer TiO_x/TiO₂ fabricated with atomic layer deposition based on key process parameters, such as the rapid thermal annealing temperature. The oxygen-deficient TiO_x active layer annealed at 600°C acted as a trap for electrons and contributed to the resistive switching. The proposed ultra-thin memristor exhibited nonvolatile memory characteristics, such as write-erase-read operation and repeatable hysteresis loops in I-V curves.
Acknowledgement
This work was supported by the Human Resources Development of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korea government Ministry of Trade, industry & Energy (No. 20144030200450).
References
[1] A. Beck, J.G. Bednorz, C. gerber, C. Rossel, and D. Widmer, Appl. Phys. Lett., 77, 139, (2000)
[2] L.-E. Yu, S. Kim, M.-K. Ryu, S.-Y. Choi, and Y.-K. Choi, IEEE Electron Device Lett., 29, 331, (2008)
[3] S.-H. Kim, Y.-K. Choi, IEEE Electron Device, 56, 3049, (2009)
[4] P.-C. Yao, J.-L. Chiang, and M.-C. Lee, Solid State Sciences, 28, 47, (2014)

Electret and organic floating-gate memories are technologies of next-generation flash storage for printed organic nonvolatile memories. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. P(VDF-TrFE) as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

The nonpolar resistive switching (RS) exhibits both unipolar as well as bipolar switching characteristics which do not depends on the polarity of applied voltages. Such switching can be considered advantageous due to faster switching speed, better uniformity (features of bipolar switching), and high integration density (feature of unipolar switching), which can potentially serve the advanced application scopes of resistive random access memories (RRAMs). We investigated the nonvolatile resistive switching (RS) behaviour in pulsed laser deposited amorphous LaHoO₃ thin films. Nonpolar RS was observed in Pt/ LaHoO₃/Pt device with all four possible modes (I. Positive unipolar, II. Negative unipolar, III. Posive bipolar, and IV. Negative bipolar) with R_ON/R_OFF ratio in the range of ~ 10⁵-10⁶. X-ray photoelectron spectroscopy studies combined with temperature dependent switching characteristics divulged the formation of mixed conductive nanofilaments consisting metallic Ho atoms and oxygen vacancies in the low resistance state (LRS). Detailed analysis of current-voltage relationship further confirmed the formation of conductive filaments on the basis of observed Ohmic conduction in ON-state. Simmons modified Schottky emission was ascribed to be the dominant conduction mechanism in OFF-state of the device. We will present the aforementioned properties of these memory cells and will discuss the intended nonvolatile memory applications of this novel high-k dielectric material in detail.

Transitional metal oxides (TMOs), such as HfO₂, NiO, TiO₂, ZrO₂, Cu_xO, TaO_x and ZnO are engendering great research interest as promising materials for resistive random access memories (RRAMs). Among different TMOs, HfO₂ has paved the way as gate dielectric in complementary metal oxide semiconductor (CMOS) transistors due to its compatibility with the semiconductor fabrication process. First principles calculations [Appl. Phys. Lett. 96, 123502 (2010)] showed that the trivalent ion doping in HfO₂/ZrO₂ matrix can reduce oxygen vacancy formation energy (E_f,V) and consequently induced more oxygen vacancies (V_O), which could be useful for localized growth of conductive filaments (CFs) depending on the dopants location. Under this context, we present experimental studies on the effect of trivalent rare-earth doping on improving the resistive switching performance of Sm/Gd-doped HfO₂ thin films. Highly crystalline thin films were fabricated on Pt/TiO₂/SiO₂/Si substrate by sequential ablation of HfO₂ and Sm₂O₃/Gd₂O₃ ceramic targets using pulsed laser deposition. The desired dopant concentrations were achieved in the film by controlling the ablation time of Sm₂O₃/Gd₂O₃ targets. X-ray diffraction analysis showed that 2% Sm/Gd-doped films have monoclinic structure, while stable tetragonal phase of HfO₂ was observed in the films having 5 and 10% doping concentrations. Electroforming free non-volatile unipolar resistive switching behaviour was observed in all the doped films, where improved memory performances in terms of switching parameters were observed with the increase in Sm/Gd-doping concentrations. In 10% Gd/Sm-doped films, ON/OFF ratios were found to be three orders of magnitude higher (~ 10⁶) and the SET/RESET voltages were observed to be almost one third (SET ~ 0.5 V and RESET ~ 1.5) as compared to the films having 2% doping. Improved switching performances with increase in doping concentration can be attributed to the easy formation of CFs due to the high concentration of oxygen vacancies, where Sm/Gd-doping further facilitate the localized growth of CFs and hence improved the switching parameters. Detailed analysis of current-voltage relationship confirmed the formation of CFs based on Ohmic conduction in ON-states. Our work provides a useful technique to design HfO₂-based RRAM devices for improved performance.

Organic field-effect transistor (OFET) memories have rapidly advanced from low-cost and flexible electronics with relatively low memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. To this end, various types of OFET memory devices have been designed, including ferroelectric, molecular gate storage, polymer electret, and nano-floating gate memory devices. The nano-floating gate memory (NFGM) devices with metal nanoparticles (NPs) embedded in the gate dielectric are advantageous over other types of OFET memory devices due to discrete and stable memory elements. Here, we report that the high-capacity NFGM based on the multi-stacking of densely packed hydrophobic metal NP layers in place of the traditional NFGM composed of a single charge trapping layer. We demonstrated that the number density of the charge trap sites, which has a decisive effect on the memory performance, can be easily modulated via the adsorption isotherm behavior, number of stacked layers of the charge trapping metal NPs and hydrophobicity of metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-Au_NPs) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD) driven by the high affinity between the metal NPs and the amine groups. Notably, the hydrophobic TOA-Au_NPs, which did not display inter-particle electrostatic repulsion, formed densely packed layers on the PAD layer in nonpolar solvents. This approach has an important advantage in that the number density of hydrophobic metal NPs (i.e., charge trap elements) can be remarkably increased, thereby forming the multi-stacked charge trapping layers (i.e., (PAD/TOA-Au_NP)_n multilayers). The formed (PAD/TOA-Au_NP)_n films which induced a memory effect by a charge trap/release mechanism were deposited at the interface between the tunneling dielectric layer and the SiO₂ gate dielectric layer. When we increased charge trapping layers according to vertical dimension from a single layer to 4 layer stacks, the number density of TOA-Au_NPs increased from 1.82 × 10¹² to 7.54 × 10¹² cm^-2, the ΔV_th of the Au_NP-based NFGM devices increased from 97 to 146 V, yielding a P/E current ratio of approximately 10⁶ after the application of a program/erase (P/E) bias of V_G = ± 100 V. Additionally, the multi-layer stacked NFGM exhibited a fast switching speed and good electrical stability during operating the devices. The importance of this work lies in the fact that the memory performances of nano-floating gate memory devices can be notably improved through precise control over the charge trap densities in the vertical dimension as well as in the lateral dimensions. Compared with other fabrication techniques, our approach can significantly enhance the memory capacities of transistor memory devices simply by modulating the number of bilayers present and the packing density of charge trap elements.

Comprehensive density-functional theory molecular dynamics (DFT-MD) simulations of GaN and SiGe interfaces with a-Al₂O₃, a-HfO₂ and a-TiO₂ oxides were performed. Single and double amorphous oxide stacks of a-Al₂O₃ and a-HfO₂ on GaN were simulated. The simulations used high-quality models of a-Al₂O₃, a-HfO₂ and a-TiO₂ oxides generated by multi-step melt-and-quench hybrid Classical-DFT MD simulations. The electronic structure of investigated stacks was calculated with higher-order HSE06 hybrid-functional, expanding band-gap to correct values and providing additional insight into electronic structure. While the GaN surface is dominated by either filled or empty dangling bonds, the SiGe surface is dominated by half-filled dangling bonds so the interaction with oxide is expected to be much stronger.
Due to its wide band-gap of 3.4 eV, gallium nitride (GaN) is a promising semiconductor for applications in optoelectronic, high-power and high-frequency devices. We have performed a large set of DFT-MD simulations of a-Al₂O₃ and a-HfO₂ on GaN using various GaN surface terminations and passivating interlayers (a-AlN, a-Al₅N₃O₃, O, O-Ga-O, O-Al/O-Ga-O, S, As, etc). In addition, double oxide stacks were simulated such as a-Al₂O₃/a-HfO₂/GaN, a-HfO₂/a-Al₂O₃/GaN, a-Al₂O₃/a-Al₅N₃O₃/GaN, and a-Al₂O₃/a-AlN/GaN. The investigated stacks were DFT-MD annealed, cooled and relaxed. The HSE06 hybrid-functional DOS curves revealed that a-HfO₂/a-Al₂O₃/GaN(0001) stack has better electronic structure with a slightly wider band gap than a-Al₂O₃/a-HfO₂/GaN(0001) stack. The effect of interlayers on electronic structure was investigated by inserting a-AlN and a-Al₅N₃O₃ between a-Al₂O₃ and GaN(0001) substrate. The DOS curves revealed midgap and band-edge states, caused by Al-Al bonds at the oxide/amorphous nitride interface, Ga-Al bonds at the amorphous nitride/GaN interface, and under-coordinated Ga atoms forming no bonds to the a-AlN oxide.
Much attention has been given to using SiGe as a channel material due to its high hole mobility and the facility to deposit films under tensile (Si-rich substrate) or compressive (Ge-rich substrate) stress thereby enhancing electron and hole mobility. We have performed a set of comprehensive DFT-MD simulations of SiGe using different surface terminations (Si or Ge) and various oxides (a-HfO₂, a-Al₂O₃, a-TiO₂) such as a-Al₂O₃/SiGe(Si-Term), a-Al₂O₃/SiGe(Ge-Term), a-Al₂O₃ /SiGe(110), a-HfO₂/SiGe(Si-Term), a-HfO₂/SiGe(Ge-Term), a-TiO₂/SiGe(Si-Term), and a-TiO₂/SiGe(Ge-Term) stacks. The simulated interfaces were analyzed to investigate structural and electronic properties. Band-decomposed charge density simulations were performed to localize sources of some midgap or band-edge states.

As silicon technology node continues to scale downwards aggressively in the sub-100 nm regime, increasing challenges emerge for both active and passive components on the chip. While the feature sizes of transistors and interconnects are scaled at every node, and the speed of transistors continues to increase, propagation delays due to increase in interconnect resistance have become the dominant chip performance-limiting factor [1]. Further, the current interconnect materials, Cu and W, face reliability challenges resulting from electromigration at higher current densities [1]. Several materials such as carbon nanotubes (CNTs), graphene, nanoribbons, and Ag nanowires are being considered as potential replacements for Cu and W in via interconnects, due to their superior electrical and mechanical properties [1]. However, before they become truly viable replacement candidates, key roadblocks such as high contact resistance and high processing temperature must be addressed. In particular, CNT is most promising to replace Cu and W in vias due to its ultra-high current capacity and its filling ability in high aspect-ratio structures. While most of the research on study of CNTs has been focused on lowering the growth temperature for process integration [2] or finding a suitable metal for via top contact [3], there are limited reports on evaluating the performance of CNTs and comparing it with those of Cu and W as the feature size scales downwards in the sub-100 nm regime.
Based on our recent work on resistance measurements of CNT vias with widths ranging from 150 nm to 60 nm [4], we have compiled an extensive comparison of reported results. These results on CNT vias are also compared with their counterparts for Cu and W. We have demonstrated that CNT via performance is beginning to approach that of W, though more improvements in CNT growth and contact resistance are still needed to be truly competitive. The lowest measured resistance for a 60 nm-wide, 130 nm-high CNT via is 150 #8486;. Statistical analysis has been performed to yield a best projected resistance of 295 #8486; for a 30 nm-wide CNT via, five times its W counterpart. Such improvements will eventually enable functionalized CNT via interconnects for next-generation IC technology nodes to be within reach.
[1] International Technology Roadmap for Semiconductor 2013 Edition, available online at www.itrs.net
[2] Vollebregt et al "Carbon nanotube vias fabricated at back-end of line compatible temperature using a novel CoAl catalyst," IEEE Interconnect Technology Conference (IITC), 2013, pp.1,3,
[3] Chiodarelli et al., "Carbon nanotube interconnects: Electrical characterization of 150 nm CNT contacts with Cu damascene top contact,"IEEE Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), pp.1,3,
[4] C. Zhou, A.A. Vyas, P. Wilhite, P. Wang, M. Chan, and C.Y. Yang, “Resistance Determination for Sub-100nm Carbon Nanotube Vias,” submitted for publication.

Spin transfer torque random access memory (STT-RAM) is regarded as a promising non-volatile alternative to SRAM cache memory and DRAM, since STT-RAM warrants high density, high speed and ultimate scalability. However, the large current densities are required especially for high speed writing. In addition, erroneous writing by the reading current can also occur, as writing/reading currents share same path. Recently, the bipolar switching the magnetization of ferromagnet layer induced by an in plane current via spin orbit torque (SOT) provides an exciting approach to the development of low power dissipation memory and logic devices. Strong SOT can be generally afforded in the metal oxide/ferromagnet/heavy metal heterostructues with large perpendicular magnetic anisotropy (PMA), which is beneficial for high thermally stability. However, the main obstacle for practical implementations of perpendicular switching of magnets with such structures is the necessity to apply a magnetic field to assist SOT-driven switching, due to symmetry reasons. A tilted anisotropy breaks the symmetry of the problem and makes it possible to switch the magnet deterministically without external magnetic field[1,2]. Here we discuss how to precise control the anisotropy tilt angle, the method is to couple the perpendicular magnetic anisotropy (PMA) hard layer (Co/Pt) with an in-plane soft layer (IMA, CoFeB). Due to the competition between the PMA and IMA, the tilted angle can be tuned by varying thickness of IMA. The stack of Pt(5 nm)/Co (1 nm)/CoFeB ( x nm)/MgO (2nm) (x varied from 0 to 1 nm) was deposited by magneto-sputtering system. The magnetic properties were investigated by vibrating sample magnetometer (VSM). The electric transport of microscale devices comprised of that stack were also studied by our probe station with electromagnet.
Reference:
[1] Kwaku Easona, Seng Ghee Tana, Mansoor Bin Abdul Jalil, Jun Yong Khoo, Bistable perpendicular switching with in-plane spin polarization and without external fields, Phys. Rev. A 377, 2403-2407 (2013)
[2] Long You, OukJae Lee, Debanjan Bhowmik, Dominic Labanowski, Jeongmin Hong, Jeffrey Bokor, Sayeef Salahuddin, Switching of perpendicular nanomagnets with spin orbit torque without an external magnetic field by engineering a tilted anisotropy, http://arxiv.org/abs/1409.0620ena.

We present results from a resistive switching study of 30 - 40 nm thick layers of insulating silicon-rich silica sandwiched between conductive electrodes. A voltage applied across the switching layer drives the drift and diffusion of oxygen ions and, in turn, switches the material from a highly insulating state to a conductive state with a difference in resistance of up to three orders of magnitude. Device resistances may subsequently be read with a small bias voltage without inducing further changes. Due to the non-volatile nature and readability of these states, such devices may be used to store binary data. Additionally, the use of silica as a switching material provides a facile means of integration into existing CMOS infrastructures. The physical processes that occur during changes in resistance are highly dynamic, ranging from the movement of ions to measurable structural deformations. The collective result of such changes is the formation of a filament-like conductive pathway that bridges the switching layer. We use atomic force microscopy, x-ray photoelectron spectroscopy and secondary ion mass spectroscopy to characterise the conductive bridge formation. From these measurements we propose a model for filamentary switching that allows us to better understand the requirements for integrating this technology into consumer devices.

The last few years have seen a growing interest for monolithic integration of III-V materials within a silicon platform. Electrical and optical properties of III-V materials (high carrier mobility, direct gaphellip;) could be combined with the existing knowledge in silicon technologies to increase the integrate circuits performances. In nano-electronics, this could lead to an alternative for building low power MOS transistor channels. Other applications in opto-electronics could create new features by integrating high efficiency light transmitters and receivers. Integration of III -V materials on silicon could be obtained by two ways. In the first one, the layers or devices are fabricated on a III-V substrates and then transfer on a Si substrate. In the second one, hetero-epitaxy of III -V materials on silicon is proposed it presents many technological challenges. High density of crystalline defects (dislocations, antiphase domains, twins, and stacking faults) due to the difference in lattice parameter and polar / non-polar interface between the two materials, are issues that need to be addressed.
We present a study on the nucleation and growth of GaAs, GaP, epitaxially grown on Si 300 mm substrate by MOCVD on an Applied Materials tool. The results obtained on nominal and offcut wafers will be shown. Then InGaAs quantum wells are grown between AlGaAs barriers. The morphology of the layers is characterized by SEM and AFM and the abruptness of the junctions is addressed by SIMS. The physical properties of the InGaAs quantum wells are characterized by photoluminescence and cathodoluminescence. They are compared with the one obtained by direct epitaxy on GaAs or InP substrates. At the end, high k dielectric is deposited on top of the InGaAs layers and capacitors are fabricated. The first electrical characterizations show a D_it of around 10¹² cm^-2.

Ionizing radiation in space can damage electronic equipment, corrupting data and even disabling computers. Radiation resistant (rad hard) strategies must be employed to prolong the usefulness of electronics in space. Currently, several strategies are used to improve radiation resistance in circuits. Devices can be designed to minimize radiation effects through the use of silicon-on-insulator (SOI) processing, or thin oxides in the case of CMOS transistors. Protection diodes and clamping circuits can be used to cap the effect of an ionizing event. Finally, redundant wiring and error correction circuits can be used to bypass or mitigate damage. However, most of these strategies do not affect the memory cell itself, which must also be radiation tolerant. Resistive memory is a promising new form of memory that appears to be resistant to radiation. Hafnium oxide-based resistive memory (ReRAM) has been shown to have some degree of resistance to radiation damage. However, multiple ReRAM materials must be tested to determine the general rad-hard properties of ReRAM. Tantalum oxide is a leading ReRAM material, but has not been thoroughly investigated for radiation resistance. Therefore, this work will eventually result in a comprehensive study of the radiation resistance of tantalum oxide ReRAM.
This study serves as a foundation for future radiation experiments, investigating the mechanism of radiation damage and resistance in ReRAM devices. Fabrication of tantalum oxide films and devices was performed in a Kurt Lesker PVD75 sputtering system, by reactive RF sputtering. Oxide composition was controlled by varying the oxygen concentration in an Ar atmosphere during sputtering. Our system is capable of varying oxygen concentration during deposition, yielding a gradient of oxide composition in our devices. X-ray photoelectron spectroscopy (XPS) was used to confirm the formation of a sub-stoichiometric tantalum oxide (TaO_x). Additionally, the effect of oxygen getter layers was investigated (Ti, Hf, Ta, Al). Ongoing electrical testing shows distinct forming and repeatable switching of these devices. In addition, ellipsometry (150nm to 1700nm) was performed to investigate film thickness, surface roughness, bandgap, and optical properties of the films. Rutherford backscattering (RBS) was used in conjunction with XPS to attempt to identify different sub-oxides within the films (TaO₂, Ta₂O₃, etc.). Finally, X-ray diffraction was performed to investigate the crystallinity of the films. The effect of these properties on switching performance is the subject of ongoing investigation. This comprehensive study of TaO_x devices, and the effect of the stoichiometric composition of the oxide, is a crucial step toward understanding the effects of radiation on ReRAM devices. Additionally, our results correlating material properties to switching characteristics will be of use in future tantalum oxide studies, and to further understand switching properties of ReRAM in general.

Layered transition metal dichalcogenides (TMDs) have emerged as a potential alternative channel material for ultra-thin and low power nanoelectronics. Highly tunable and unique electronic properties of TMDs made them promising novel materials for various other applications as well. However, in order to realize the superior performance of TMD based devices, the physical and chemical properties need to be understood, in particular their stability under different chemical environments. A detailed comparative analysis of the air stability (i.e., oxygen interaction) of different TMDs is still lacking. We have examined various TMD stabilities in air and found them different from graphene which is stable in air. The changes in the electronic properties with air exposure were studied using density functional theory (DFT), Kelvin probe, and photoelectron emission in air. The results reveal that transition metal sulfides are kinetically more stable than selenides in air, but all TMDs are thermodynamically unstable against oxidation. Furthermore, it is shown that TMD surface defects function as facile oxidation sites impacting their air stabilities. These findings provide helpful guidance to controlled exfoliation and device fabrication processes.
This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA. It was also supported partially by National Council of Science and Technology, Mexico (CONACyT), project NL-2010-C33-149216 and Southwest Academy of Nanoelectronics (SWAN) center. DFT calculations were performed using Texas Advanced Computing Center (TACC).

The InGaAs high mobility channels are vowed as serious candidates for alternative channel materials for sub-10 nm technology nodes urging studies for analogous contacts to the dominant silicide contacts in the Si technology mainstream. The Ni-InGaAs (nickelide) contact technology has been demonstrated as a suitable self-aligned contact technology for InGaAs channels with record small specific contact resistivity. However, the majority studies on nickelide contact formation were conducted on planar InGaAs films and little studies focused on the contact metallurgy specific in nanoscale InGaAs nanowire or Fin channels. Here, we utilized a novel wafer bonding technique to transfer thin (50 nm) In_0.53Ga_0.47As layers onto SiO₂/Si substrates and Si transmission electron microscopy (TEM) frames. InGaAs Fins with variable widths, lengths, and orientations were fabricated through a combination of electron-beam lithography and top-down dry etching steps, followed by Ni contact deposition. Rapid thermal annealing and in-situ TEM thermal heating cycles were conducted to react Ni with the InGaAs channel and deduce the reaction kinetics, dynamics, and resultant nickelide and interface structures. The nickelide phase was found to gradually extend into the InGaAs fin channels, introducing a 32% ± 7% height increase to the channels with negligible lateral expansion. The morphology of formed nickelide phase strongly depended on the orientation of fin structures, as we observed sharp and abrupt nickelide-InGaAs interfaces for <110> oriented fin channels, while rough interfaces with multiple facets in <100> oriented ones. Systematical measurements of the length of nickelide segments according to different annealing times, temperatures, and fin widths, revealed a Ni diffusion limited kinetic growth process, which agrees well with the derived equations from a kinetic competition model. A transition from surface diffusion limited kinetic process to volume diffusion limited one was reported for the first time, related to the increase of InGaAs fin widths. We extracted a surface diffusion coefficient of 1.3x10^-15 ~ 1.5x10^-15m²/s at a reaction temperature of 250 °C, which is ~5 times larger than the extracted volume diffusion coefficient. The crystalline structure analysis with TEM revealed a hexagonal lattice of formed nickelide phase, adopting a NiAs (B8) structure. Cross-sectional TEM measurements were achieved by focus ion beam (FIB) cut along the fin channels, showing a slanted nickelide-InGaAs interfaces towards the base, which is possibly induced by the stress from underneath dielectric layers. These results contrasted with the conventional contact metallurgy studies in nanowires with free surface, and the detailed structure, interface and reaction dynamics will be discussed.

In this talk, we report the observation of RTN on top-down fabricated highly scaled InGaAs GAA MOSFETs. RTN and low frequency noise were systematically studied on InGaAs GAA MOSFET with various gate dielectrics, channel lengths and nanowire sizes. Mobility fluctuation is confirmed to be the source of low frequency noise, showing 1/f characteristics. Low frequency noise was found to decrease as channel length scaling down from 80 nm to 20 nm, indicating the near-ballistic transport property of highly scaled InGaAs GAA MOSFET.

GaN High-Electron Mobility Transistors (HEMTs) are well on their way to revolutionizing RF, microwave and millimeter-wave communications and radar systems. GaN FETs are also uniquely poised to have a disruptive impact in electrical power management. In all these applications, device reliability remains a significant concern. As the field has expanded, great progress has recently taken place in understanding GaN transistor degradation, especially under high-voltage stress. Detailed electrical studies coupled with comprehensive failure analysis involving a variety of techniques have revealed a rich picture of degradation. Early studies showed that high voltage degradation of GaN HEMTs was characterized by a critical voltage (V_crit) at which the device gate current abruptly increases. For stress voltage beyond V_crit, prominent degradation was observed in the drain current and other electrical parameters of the device. More recently, it has been shown that degradation in the gate current can occur for voltages below the critical voltage suggesting that stress time is a key variable in degradation. Cross-section TEM and planar imaging techniques have shown that high-voltage stress induces prominent structural defects such as grooves, pits and cracks in the GaN cap and AlGaN barrier at the edge of the gate. The evolution of these defects correlates well with that of electrical degradation. Recently, a similar pattern of degradation has been observed under high-power DC and RF stress, although not in a consistent way. A significant recent finding is the role that moisture plays in the formation of these structural defects. This suggests a path for mitigation. Separately from device degradation, a significant anomaly affecting GaN transistors is electron trapping which can severely upset device operation on a wide time domain. This talk will review recent research on the electrical reliability and trapping of GaN HEMTs.

As silicon-based complementary metal-oxide-semiconductor (CMOS) technology obviously approaches its physical limits, a need for its replacement with other materials such as GaAs and In_xGa_1-xAs for high mobility and scalable logic devices has emerged. However, large source/drain (S/D) spacing induced by annealing process to make ohmic contacts obstructed the scaling of III-V devices. Also, Fermi level pinning at metal/semiconductor interfaces caused by metal-induced gap states (MIGS) leads to high contact resistivity. The metal-interlayer-semiconductor (MIS) structure in order to prevent MIGS can&’t settle the Fermi level pinning perfectly by reason of high interface state density at the interlayer-GaAs substrate interfaces. Therefore, GaAs surfaces need to be passivated for Fermi level unpinning.
Sulfur passivation, which has been used widely, can suppress oxidation and passivate dangling bonds on the GaAs surface, but it cannot completely decrease interface states between the interlayer and the semiconductor for MIS structure. Germanium is greatly suitable for GaAs surface passivation because not only can it suppress surface defects of GaAs substrate, but also has similar lattice constant and thermal expansion coefficient to GaAs. Furthermore, we can unpin the GaAs Fermi level by inserting Ge interfacial passivation layer. To investigate Ge passivation effect, we designed samples of three different structures: Ti/ZnO/Ge/GaAs, Ti/ZnO/GaAs, and Ti/Ge/GaAs, all GaAs (~2×10¹⁸ cm^-3) substrates having been passivated by (NH₄)₂S.
All samples resulted in lower contact resistance than that of Ti/GaAs with the Ti/ZnO/Ge/GaAs sample having the lowest contact resistance. The Ge passivation only cannot block the MIGS, and the ZnO interlayer only cannot prevent surface defects. However, the MIS structure with Ge passivation can effectively reduce both MIGS effect and interface state density, achieving ~300 × reduction in contact resistivity compared to the Ti/GaAs sample. As a result, the effect of Ge passivation on contact resistance reduction for MIS structure is well demonstrated.

III-V semiconductors are promising candidates to replace Si channels in future high performance MOS devices. High quality gate dielectrics on III-V materials must have a high dielectric constant, sufficient band offset for low leakage current, and low interface trap state density (D_it). Achieving low D_it has been a major challenge for high-k/III-V interfaces. We have recently shown that in-situ plasma-based surface preparation treatments in atomic layer deposition (ALD) can achieve D_it in the low 10¹² cm^-2 eV^-1 range for gate stacks with high-k HfO₂ and ZrO₂ dielectrics on In_0.53Ga_0.47As [1,2]. Such gate stacks can be scaled to achieve accumulation capacitance densities exceeding 3.5 mu;F/cm² at 1 MHz (~ 3 nm physical thickness). Further scaling has proven difficult, due to high leakage currents and the presence of an Al-oxide interface layer with a low dielectric constant. Here we report on the use of higher-k Ti-oxides to replace the low-k Al-oxide interface layer. Such layers are obtained by a pre-deposition cleaning process that consists of cycles of nitrogen plasma and tetrakis(dimethylamino)titanium pulses [3]. In combination with ZrO₂ and/or HfO₂ ALD gate dielectrics, this process gives rise to extremely scaled gate stacks with accumulation capacitance densities of more than 5 mu;F/cm² at 1 MHz, low frequency dispersion in capacitance vs. voltage curves, low D_it, and low leakage currents. The chemical, physical, and electrical properties of Ti-oxide based interfacial layer are discussed. We also discuss the mechanisms by which low leakage is obtained despite the small band gap and conduction band offset between the Ti-oxide interface layer and the channel, and the role of interface dipoles in determining the properties of the gate stacks. Results for both n- and p-type In_0.53Ga_0.47As channels will be presented.
References
V. Chobpattana, T. E. Mates, W. J. Mitchell, J. Y. Zhang, and S. Stemmer, J. Appl. Phys. 114, 154108 (2013).
V. Chobpattana, T. E. Mates, J. Y. Zhang, and S. Stemmer, Appl. Phys. Lett. 104, 182912 (2014).
V. Chobpattana, E. Mikheev, J. Y. Zhang, T. E. Mates, and S. Stemmer, J. Appl. Phys. 116, 124104 (2014).

Atomic layer deposition (ALD) has been established as the main technique for creating MOS structures based on III-V semiconductors, which are highly promising both in planar and in nanowire geometry [1]. In order to achieve superior device performance, a precise control and profound knowledge of the semiconductor/oxide interface is crucial, but not fully reached yet. One of the great challenges is to characterize the chemical reactions taking place at the interface between the III-V semiconductor, its native oxide, and the high-k dielectric material during the ALD process. X-ray photoemission spectroscopy (XPS) has successfully been used to investigate this interface before and after individual steps of the ALD reaction [2,3], but was until now limited to ultrahigh vacuum conditions.
Here I present ambient pressure XPS studies of the atomic layer deposition of HfO₂ on InAs, using tetrakis(dimethylamino)hafnium (TDMA-Hf) and water precursors: By performing subsequent half-cycle steps of the ALD process within the reaction cell of an ambient pressure XPS system [4], we were able to monitor the slowed down ALD reaction by XPS and thus obtain fully in-situ and real-time XPS measurements of the high-k deposition on III-V semiconductors.
From the time-resolved investigation of the self-cleaning effect during ALD, we reveal several subsequent steps in the removal of different native As-oxides and the reduction of In-oxides. Furthermore, based on the observations during initial TDMA-Hf deposition, I will discuss separate phases of precursor chemisorption followed by precursor dissociation and ligand exchange reaction, which also depend on sample temperature. Accordingly, the surface chemistry of the ALD process seems to be more complex than previously expected.
[1] Johansson et al., IEEE EDL 35, 518 (2014)
[2] Timm et al., Appl. Phys. Lett. 97, 132904 (2010)
[3] Timm et al., Appl. Phys. Lett. 99, 222907 (2011)
[4] Schnadt et al. J. Synchrotron Radiat. 19, 701 (2012)

III-V semiconductor channels are one way to continue CMOS scaling to higher mobility substrates. The problem has been to passivate their interfaces effectively. Progress followed in-situ XPS studies of ALD growth of oxides [1,2], and a better understanding of the nature of interface defects [3]. Al₂O₃ based gate oxides gave good performance, partly due to their diffusion barrier properties and partly because trivalent oxides allow valence matching across the III-V interface [3]. However, Heyns [4] noted that Al₂O₃/III-V stacks have a lower overall reliability, due to more border traps. Various groups [5-7] found that nitridation of Al₂O₃ gate oxides would reduce D_it values. Here we study the origin of this effect.
Lin [3] found that for GaAs/oxide interfaces the As-As bond gave states in the upper gap and As dangling bonds gave states near the valence band maximum (VBM). We find that for AlN interfacial monolayers, any N-N bonds would spontaneously break, leaving only N dangling bonds (DBs). Nitrogen DBs give states at least 2 eV below the VBM, well away from the gap. These calculations are repeated for each III-V material, including pFET antimonides. Nitrogen states always lie well below VBM.
We find that the advantage of AlN interlayers is that they have a lower density of border traps. We find that O vacancies in Al₂O₃ can give 4 transition states across its band gap, some lying within the III-V gap. In contrast, the N vacancy in AlN gives no states within the III-V gap. Thus AlN will give lower trap densities. AlN also retains the diffusion barrier properties of Al₂O₃. AlN has fewer defect levels because its anion site, N vs O has higher symmetry. N has a tetrahedral site, so that its vacancy has only A₁ and triply degenerate T₂ levels with a wide separation between them, with the T2 state above the III-V conduction band edge. On the other hand, the O site in theta;-Al₂O₃ has a low symmetry. This breaks the T₂ state into 3 separate defect states, some lying in the III-V gap.
1 M L Huang, et al, APL 87 252104 (2005)
2 C L Hinkle et al, APL 92 071901 (2008)
3 L Lin, J Robertson, APL 98 082903 (2011)
4 M Heyns, MRS Spring (2014)
5 V Chobpattana, et al, APL 102 022907 (2013)
6 T Aoki, et al, APL 105 03513 (2014)
7 Y Guo, L Lin, J Robertson, APL 102 091606 (2013)

A broader range of MOSFET channel materials allowing better carrier confinement and mobility could be employed if a universal control monolayer (UCM) could be self-limiting CVD or ALD deposited on multiple materials and crystallographic faces. Si-OH is a leading candidate for use as the UCM because silicon uniquely bonds strongly to all crystallographic faces of In_xGa_1-xAs, In_xGa_1-xSb, In_xGa_1-xN, SiGe, and Ge. The Si-OH monolayer could be formed by self-limiting CVD or ALD deposition of an Si-H layer which can be functionalized with an oxidant to create the UCM Si-OH layer. The Si-H or Si-OH monolayer would be electrically passive if the bonding structure results in a charge balanced surface (i.e. obeys the electron counting model) because the Si-H or Si-OH monolayer would remove all dangling and dimer bonds. This study focuses on depositing a saturated Si-H monolayer via two separate self-limiting processes on InGaAs(001)-(2x4). XPS in combination with STS/STM were employed to characterize the electrical surface properties of the saturated Si-H layers on InGaAs(001)-(2x4). Density Functional Theory (DFT) modeling indicates missing dimer and ideal unit cells of the InGaAs (001)-(2x4) surface are electrically passivated by Si-H_x.
Self limiting CVD is a self limiting dose of the reducing ALD precursor; it is self limiting since reductants do not react with substrate back bonds. For the 375°C self-limiting CVD process, a decapped In_0.53Ga_0.47As(001)-(2x4) surface was dosed with 300 MegaLangmuir Si₃H₈ at 375°C. STM images of the (2x4) surface following the saturated Si₃H₈ dose at 375°C shows Si-H_x absorbs in a commensurate structure with average row spacing nearly identical to the (2x4) surface at 1.5 nm, consistent with III-V dangling bond elimination. A second process was tested using an ALD method. In this second process, the (2x4) surface was dosed with 21 MegaLangmuir Si₂Cl₆ at 400°C. The surface is terminated by SiCl_x and 500 Langmuir of atomic hydrogen is pulsed at 400°C to remove -Cl and terminate the surface with SiH_x. For both processes, the XPS spectra following the saturated Si₃H₈ or Si₂Cl₆ dose shows the increase of the silicon 2p peak and decrease in the gallium 3p substrate peak, indicative of saturating coverage. Complete saturation is determined to occur once further dosing with Si₃H₈ or Si₂Cl₆ leads to no further increase in the silicon 2p or decrease in gallium 3p peak areas. Both processes employ high pressure pulses which protect from surface carbon and oxygen contamination. The Si-H_x surfaces achieved by both processes show identical STS results with the surface Fermi level (E_F) shifting from the valence to the conduction band for p-type vs n-type samples consistent with an unpinned E_F. DFT simulations are in direct agreement with STS results showing the surface E_F remains unpinned, as the modeling indicates there is charge neutrality found in both the missing dimer and ideal (2x4) unit cells passivated by Si-H_x.

For future high performance III-V n-channel MOS devices, In_0.53Ga_0.47As is a promising material for the channel due to its high electron mobility. Atomic layer deposited (ALD) Al₂O₃ has a large conduction band offset to InGaAs and can form a low defect-density interface with InGaAs.¹ Therefore, Al₂O₃ has received attention as either a candidate dielectric layer for InGaAs nMOSFETs, or as a large band-offset interface layer interposed between the InGaAs channel and a higher-k dielectric such as HfO₂.² Apart from the well-known oxide/InGaAs interface charge traps that may pin the Fermi level of the channel, traps in the oxide layer, called border traps, may also reduce the charge in the channel and thus degrade the on-state performance of InGaAs MOSFET devices. In this presentation, we study the effects of various approaches to reduce the border trap density, such as variation of ALD temperature, post-gate metal forming gas (5% H₂/95% N₂) anneals (FGA).
Experimental methods employed include quantitative interface trap and oxide trap modeling^{3, 4} of MOS capacitor data obtained over a range of frequencies and temperatures. With the application of these models, we find that MOS capacitors fabricated using trimethylaluminum (TMA)/H₂O at an ALD temperature of 120°C have a considerably lower border trap density (N_bt) while maintaining a similarly low interface trap density (D_it) compared to samples prepared with a more standard 270°C Al₂O₃ ALD temperature. Large-dose TMA exposure (pre-dosing) of the InGaAs(100) surface prior to Al₂O₃ ALD is also found to be an important step to guarantee stable electrical quality of the low temperature-deposited samples. To understand the nature of this ALD temperature effect, composition and bonding characterization methods such as XPS and SIMS are employed to probe the origin of the N_bt variation as a function of the structure of the Al₂O₃ layer. Besides altering the ALD temperature, the impact of other treatment methods on the N_bt, such as variations of H₂/N₂ forming gas anneal time and temperature, and application of bias-temperature stress, will also be discussed.
References
1. J. Ahn, T. Kent, E. Chagarov, K. Tang, A.C. Kummel, and P.C. McIntyre, Applied Physics Letters 103, 071602 (2013).
2. V. Chobpattana, T.E. Mates, W.J. Mitchell, J.Y. Zhang, and S. Stemmer, Journal of Applied Physics 114, 154108 (2013).
3. H. Chen, Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2383 (2012).
4. Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2100 (2012).

The increasing integrated circuits power consumption constitutes a major showstopper for further downscaling silicon MOSFET devices. To tackle this issue, a possible way is to replace the channel made of silicon or silicon germanium alloys by high mobility arsenic based III-V materials such as InGaAs. It offers the possibility to operate at lower voltage (V_dd), and hence to strongly decrease the dynamic power consumption as it scales as V²_dd. Two architectures for III-As integration as a MOSFET channel are foreseen: fully-depleted III-As on insulator and FinFET. Nevertheless, the introduction of these materials in the existing processes faces many challenges: channel/high k interface control, contact resistance, and high crystalline quality channel material. The last issue is investigated using two main paths: layer transfer from a III-V substrate and direct growth on silicon substrate. Direct epitaxy of III-V on silicon faces many challenges: a high threading dislocation density due to a strong lattice mismatch (4% for GaAs and 11% for InAs) and antiphase boundaries caused by the difference in polarity between III-V and Si. Also, the thermal expansion coefficient difference between these two materials is limiting the total thickness of III-V that can be grown on Si.
We focus on the direct growth of III-As and III-P compounds on patterned Si(100) 300 mm substrates. GaAs, InP and InGaAs layers are grown in an Applied Materials MOCVD tool. TMIn, TMGa and TMAl are used as group III elemental precursors whereas TBAs and TBP is used as group V elemental precursors. The structural and the physical properties of GaAs, InP, InGaAs, AlGaAs and InAlAs layers grown on patterned Si(100) wafers are studied by FIBSTEM, TEM, SIMS, µPL and cathodoluminescence (CL). InGaAs quantum wells, with In composition ranging between 10 and 53% were selectively grown on GaAs and/or InP buffer and exhibited room temperature photoluminescence. Low temperature CL mappings revealed a strong non-uniformity of luminescence along the cavity lines. We combined these observations with localized cross-sectional TEM analysis in order to identify the defects responsible for the luminescence extinctions.

Transition metal dichalcogenides (TMDs) are well recognized to be a promising material for tribology and opto- and nano-electronic as well as biosensing and photocatalysis. The lifetime of devices TMD-based is limited when the material is kept at ambient atmosphere. We studied the reactivity of several TMDs using X-ray photoelectron (XPS), Kelvin probe and photoelectron emission in air with a support of density functional theory (DFT). Six TMDs were utilized on this study: MoS₂, WS₂, WSe₂, MoSe₂, HfSe₂ and HfS₂. Our results suggests that the sulfides are more stable than the selenides with respect to oxidation, and the TMDs from group VI (Mo, W) are more stable than group IV (Hf). The investigation of the MoS₂ crystals from different sources (geological and vapor transport synthesis) shows that the workfunction changes between 4.85 and 5.2 eV. Moreover, the air stability varies from one sample to another; this variability is assigned to the presence of intrinsic defects on both natural and synthetic MoS₂ surface as already reported by our previous work [1-2]. In conclusion, we will show that the degree of reactivity on TMDs is highly depends upon (i) the number of electrons in the d-orbital; group IV vs. group VI, (ii) the chalcogen element; sulfur (period 3) vs. selenium (period 4), and (iii) the structural topology.
This work is supported in part by the SWAN Center, a SRC center sponsored by the Nanoelectronics Research Initiative and NIST. It is also supported in part by the Center for Low Energy Systems Technology (LEAST), one of six centers supported by the STARnet phase of the Focus Center Research Program (FCRP), a Semiconductor Research Corporation program sponsored by MARCO and DARPA.
[1] S. McDonnell, R. Addou, C. Buie, R. M. Wallace and C. L. Hinkle Defect-dominated doping and contact resistance in MoS₂ACS Nano8 2880-2888 (2014)
[2] R. Addou, Robert M. Wallace et al. Microscopy and spectroscopy characterization of intrinsic defects on natural MoS₂ (in preparation, 2014)

Two-dimensional transition metal dichalcogenides (TMDs) are currently considered as potential channel material in the beyond Si-CMOS device structures¹.The electronic and optoelectronic properties of MoS₂ have been extensively studied in recent years. Moving forward into the exploration of other members in the TMD library, several efforts have focused on studying WSe₂, where field-effect mobility (mu;_FE) values up to 500 cm²/Vs have been reported². Following these efforts, MoSe₂ has been implemented in FETs, exhibiting a promising performance (i.e. mu;_FE 150-200 eV) according to recent reports³. Additionally, it has been demonstrated that the mu;_FE of TMDs based FET can be increased by depositing a high-k dielectric on top of the two-dimensional channel⁴. However, when HfO₂ or Al₂O₃ are deposited by atomic layer deposition (ALD) on the bare MoS₂ surface, these high-k dielectrics exhibit island-type growth⁵ resulting in non-continuous films. In order to enhance the high-k film uniformity and coverage, UV-O₃ pre-treatment on the inert MoS₂ surface prior to ALD of Al₂O₃ was proposed⁶. Such pretreatment generated an oxygen functionalized MoS₂ surface, which provided nucleation sites for a uniform ALD growth.
In this work, the reactivity towards oxygen functionalization upon UV-O₃ exposure of the MoS₂, MoSe₂ and WSe₂ surfaces analyzed in-situ by XPS will be presented. In correlation, the oxygen interaction with these TMDs surfaces was studied by density functional theory (DFT). The impact of the presence of surface oxides generated on MoSe₂ and WSe₂ after UV-O₃ exposure on the interfacial chemistry during high-k dielectric deposition by ALD was evaluated by XPS. It was found that the surface oxides on MoSe₂ and WSe₂ were reduced by the ALD process (“self-cleaning effect”). The effectiveness of the oxide reduction on these TMDs will be discussed and correlated with the relative oxide stability. Significant differences in HfO₂ nucleation between UV-O₃ treated MoSe₂ and WSe₂ will be demonstrated by means of topography and interface imaging by atomic force microscopy and transmission electron microscopy, respectively. Finally, it will be shown that HfO₂ growth and uniformity on the UV-O₃ treated MoSe₂ and WSe₂ was improved in comparison to the non-treated TMDs surfaces.
This work is supported in part by the SWAN Center, a SRC center sponsored by the Nanoelectronics Research Initiative and NIST and by the LEAST Center, one of six centers supported by the STARnet phase of the Focus Center Research Program, a Semiconductor Research Corporation program sponsored by MARCO and DARPA.
¹Jena, D. Proc. IEEE 101 1585-160 (2013).
²Podzorov, V., et al. Appl. Phys. Lett. 84, 3301 (2014).
³Pradhan, N.R., et al. ACS Nano, 8 (8), 7923-7929 (2014).
⁴Bao, W. et al. Applied Physics Letters 102, 042104 (2013).
⁵Yang, J. et al. ACS Appl. Mater. Interfaces, 5, 4739minus;4744 (2013).
⁶A. Azcatl, et al. Appl. Phys. Lett. 104, 11, 111601 (2014).

In this work, we demonstrate the high-quality growth of tungsten-based transition metal dichalcogenide thin films (WSe₂, WTe₂) grown by molecular beam epitaxy (MBE). The relaxed lattice-matching criteria of van der Waals epitaxy (vdWE) has allowed for layered, crystalline growth with atomically abrupt interfaces on substrates with inert hexagonal symmetry such as highly ordered pyrolytic graphite (HOPG) and MoS₂. Here, we report the investigation of substrate temperature and flux on the nucleation and quality of the grown TMDs to enable larger-area, continuous 2D layers. Structural and chemical characterization as well as experimentally determined band alignment of the WSe₂ and WTe₂ was conducted via X-ray diffraction (XRD), transmission electron microscopy (TEM), scanning tunneling microscopy/spectroscopy (STM), X-ray photoelectron spectroscopy (XPS), and Raman spectroscopy. A comparison between these W-based dichalcogenides and Mo and Hf based TMDs will also be discussed. These grown materials, in conjunction with other 2D materials (e.g. h-BN), show significant potential for fabricating all-2D materials based heterostructures with tunable alignments for a variety of nanoelectronic and optoelectronic applications.

A number of 2D materials are under investigation as potential candidates for materials in beyond CMOS applications. In addition to graphene, materials such as transition metal dichalcogenides (TMDs) and phosphorene have been examined for field effect devices with promising results. However, the detailed understanding and control of the interfaces of these materials with dielectrics, contacts, and even the environment requires attention. This talk will present a review of our recent studies of these materials systems in this context using in situ deposition and characterization methods we have developed for similar studies of conventional CMOS materials such as Si, Ge, III-V and III-N materials.
This work is supported in part by the the Center for Low Energy Systems Technology (LEAST), one of six centers supported by the STARnet phase of the Focus Center Research Program (FCRP), a Semiconductor Research Corporation program sponsored by MARCO and DARPA, and the SWAN Center, a SRC center sponsored by the Nanoelectronics Research Initiative and NIST.

2-D materials are single or trilayer networks of atoms, such as carbon, hBN, and MoS₂. The 2D materials are attractive for future electronic devices because the materials provide ballistic transport of charge carriers as well as carrier confinement. These novel devices require ultrathin and defect-free dielectric layers as gate or channel insulators. However, 2D semiconductors such as graphene, boron nitride, and some metal dichalcogenides (MDCs) are un-reactive, thus the dielectric layer selectively nucleates on defect sites or step edges. In the conventional atomic layer deposition (ALD) process on graphene or other 2D semiconductors, such non-uniformly grown oxides can create large leakage currents in 2D semiconductor based device.
In order to deposit high quality dielectric layers on 2D semiconductors, metal phthalocyanine layers have been employed. TiOPc monolayers were deposited on HOPG surfaces by organic molecular beam epitaxy or solution phase deposition. After deposition, TiOPc forms a monolayer with only few defects, and the crystal structure has four-fold symmetry. ALD pulses of TMA and water were introduced in-situ onto TiOPc/HOPG to investigate nucleation of Al₂O₃ on the TiOPc monolayer. After exposure of the TiOPc monolayer to 1 ALD pulse cycle, aluminum oxide was deposited uniformly on the TiOPc layer and the band gap of surface increased from 1.7 to 2.7 eV, while the conductance decreased. DFT calculations show the TiOPc molecule has multiple react sites with precursors of Al₂O₃. Consequently, TiOPc can induce a subnanometer nucleation for dielectric layers on 2D semiconductors. By combining scanning tunneling microscopy and DFT calculations, the insulating property and growth mechanism of subnanometer dielectric layer have been elucidated.

The recently developed ability to grow layers of transition metal oxides with the atomic precision by means of physical vapor deposition has led to discovery of many fascinating phenomena that cannot be easily realized in bulk materials and to integration of these oxides on semiconductors. In this talk I will review the recent progress in integrating ferroelectric films with Si and Ge, and their potential applications in electronics and nanophotonics. I will also talk about potential applications of perovskite oxide heterostructures. Heterostructures described in the talk were grown by molecular beam epitaxy (MBE), when possible, chemical routs were tested via atomic layer deposition (ALD). Design of the structures and analysis of the experimental results were aided by density functional theory (DFT).

In this study, we report a new route to modify the carrier density in complex oxides by extreme electron doping with hydrogen/lithium/magnesium intercalation. By reversibly doping a rare earch nickelate, SmNiO₃, with different ions and changing the filling of Ni e_g orbitals, we found a new insulating phase characterized by strong electron correlation. The phase transition is manifested by a more than eight orders of magnitude decrease in conductance and a large increase in the electronic band gap, as evidenced by transport and optical properties. XPS, XRD and TEM studies indicate that the phase transition involves the shift in the valence state of Ni while the parent framework remains unchanged. We then utilize this phenomenon to mimic spike-timing-dependent plasticity in a synaptic transistor. This study presents a new way to induce extremely large number of carriers in complex oxides through intercalation. The extreme sensitivity of electrical properties to defects in correlated oxides may make them particularly suitable for neuromorphic devices.

Diamond is a semiconductor with extreme and unique properties which are well known for power electronics applications. The recent development of phosphorus doping to obtain n-type character has enabled research on a range of power electronic applications. This study is focused on understanding the properties of dielectric layers on P-doped diamond epitaxial layers. The specific goal of this research is to use XPS and UPS to determine the band alignment of the dielectric layers on diamond and to measure the band bending in the diamond. The P-doped diamond layers are grown on (100) single crystal diamond substrates, and doping densities of ~1E18 cm-3 have been achieved. The ALD layers of HfO₂, Al₂O₃, and SiO₂ will be grown by plasma enhanced ALD. The band offsets and band bending are measured by in situ XPS and UPS and results are related to possible device structures.

Cation-based resistive memory cells [1] (ECM or CBRAM) often exhibit changes of OFF or intermediate resistance values over time and even ON states can be completely lost in certain cases. The stability of these resistance states and the time until resistance loss strongly depends on the materials system. Also both memory cells and complementary resistive switches [2] suffer from the necessity of a destructive read-out procedure increasing wear and reducing read-out speed.
On the basis of electrical measurements and chemical analysis we found a viable explanation for the volatile resistance states (VRSs) in Ag-GeSx-based electrochemical metallization memory cells and identified a technological application in the field of crossbar memories[3].
The VRS can be addressed from a HRS by applying a subcritical voltage that is large enough to decrease the resistance significantly, but at the same time small enough not to trigger a LRS. After the application of the read pulse, the memory cells returns with a certain relaxation time self-activated to an HRS. This feature was commonly treated as an undesired side effect, but can be explained by taking into account the nanobattery effect[4], the microstructure of the filament and of the surrounding electrolyte[5]. Beside the situation at the HRS with no filament and the situation at the LRS with a full grown filament in ohmic contact with both electrodes, a third state called VRS exists.
From our analysis we deduced a solution to use the VRS as an inherent selector mechanism without the necessity for additional selector devices. The VRS approach also enables the non-destructive read-out of complementary resistive switches.
References:
1. I. Valov, M. Kozicki. Cation-based resistance change memory. J. Phys. D: Appl. Phys, 46, 074005 (2013)
2. J. van den Hurk, E. Linn, H. Zhang, R. Waser, and I. Valov. Volatile resistance states in electrochemical metallization cells enabling non-destructive readout of complementary resistive switches. Nanotechnology, 25, 425202 (2014)
3. E. Linn, R. Rosezin, C. Kügeler and R. Waser. Complementary resistive switches for passive nanoscrossbar memories. Nature Mater, 9, 403 (2010)
4. S. Tappertzhofen, E. Linn, R. Rosezin, U. Böttger, R. Waser and I. Valov. Nanobattery effect in RRAMs - implications on device stability and endurance. IEEE Electron Device Lett, 35, 208 (2014)
5. I. Valov, E. Linn, S. Tappertzhofen, S. Schemelzer, J. van den Hurk, F. Lentz and R. Waser. Nanobatteries in redox-based resistive switches require extension of memristor theory. Nature Comm, 4, 1771 (2013)

Resistive random access memory (RRAM) is a promising candidate for next generation data storage due to its potential for performance, scalability and compatibility with CMOS processing. The switching of metal oxide films (HfO_x, TiO_x, AlO_x) has been studied [1] and several mechanisms proposed for the formation of low resistance pathways of such films [2,3]. However, the performance of the memory device is also dependent on the contact resistance, especially at sub-5 nm dimensions [4]. Measuring the contact resistance in highly resistive films is challenging due to low current levels, variability and interface ionic migration. Similar studies exist for phase change materials such as Ge₂Sb₂Te₅ (GST) [5,6] but a comprehensive study for the more resistive metal oxide based RRAM materials is still lacking.
In this study, we introduce a methodology to measure highly resistive thin films and their interfacial electrical resistances. We carry out low current four-probe measurements to measure contact resistance with a Cross Bridge Kelvin [6] structure. The overlap parameter for the structure is ~100 nm to enhance the signal-to-noise ratio for the low-current level typically used in these resistive devices. This allows accurate extractions of contact resistance and film resistivity for structures with specific contact resistance values greater than 100 mu;Omega;middot;cm² and underlying film resistivity value above 10 Omega;middot;cm. Circular transfer length measurements (TLM) are carried out with a Ti/Pt contact stack on 20 nm HfO₂ films prepared via atomic layer deposition (ALD) and sputtered GST films - yielding specific contact resistivity values of 7.5 Omega;middot;cm² and 3.2 x 10^-4 Omega;middot;cm² at room temperature, respectively. For RRAM films which involve ion migration in the bulk and at the metal oxide interfaces, we utilize a Greek Cross [7] structure for sheet resistance measurement to avoid the injection effect at the interface.
We find transfer lengths for contacts to HfO₂ to be in the range of 200 nm and for amorphous GST in the range of 4 mu;m at room temperature. Linear TLM structures with metal line widths below 200 nm are also fabricated and measured for stoichiometric ALD HfO₂ and sputtered HfO_x films, to extract the carrier mobility under the metal contact [8]. This measurement platform can be used to precisely measure the interfacial and bulk characteristics for highly resistive films. It is also a useful tool in exploring the switching mechanism, as a single electrode-memory bit interface can be measured accurately, with low current and low noise measurement capability.
[1] H.-S.P. Wong et al, Proc. IEEE (2012)
[2] R. Waser et al, Adv. Mater. (2009)
[3] D. Ielmini, IEEE-TED (2011)
[4] C.-L. Tsai, E. Pop, et al ACS Nano (2013)
[5] S. Savransky, I. Karpov, MRS Proceedings (2008)
[6] D. Roy et al. IEEE-EDL(2010)
[7] S. Enderling et al, IEEE-TSM (2006)
[8] D. Schroeder, 3rd ed. (2006)

Transition metal oxide based resistive switching devices (TMO-RRAM) have been widely studied for next generation data storage technology and neuromorphic computing applications due to the great memory characteristics and the adaptation response ability similar to the synapses [1-4]. For the data storage or neuromorphic computing system applications, different device performances are needed. To achieve the targeted performances, the optimization design on the materials including resistive switching and electrode layers are required based on the physical understanding on the resistive switching effects in TMO-RRAM. In this talk, the critical physical effects correlated with resistive switching behaviors in TMO-RRAM will be addressed [5,6]. Based on the understanding on the physical mechanisms of the critical physical effects, the material-oriented methodology is developed for the design and optimization of TMO-RRAM devices [7]. The optimized HfOx- and TaOx-based RRAM devices are designed and demonstrated for the targeted device performances [7, 8]. The optimization design guideline is presented for the engineering of materials and structures of HfOx- and TaOx-based RRAM devices.
References:
[1] A.Sawa, “Resistive switching in transition metal oxides”. Mater. Today. , 11, p.28, 2008
[2] H. -S. P. Wong, et al, “Metal-Oxide RRAM,” Proc. IEEE, 100, p.1951, 2012
[3] K. H. Kim, et al, “A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications”, Nano lett., 12, p.389, 2012
[4] S. Yu et al, “A Low Energy Oxide-Based Electronic Synaptic Device for Neuromorphic Visual Systems with Tolerance to Device Variation”, Adv. Mater. 25, p. 1774, 2013
[5] B. Gao et al, “Oxide-Based RRAM: Unified Microscopic Principle for both Unipolar and Bipolar Switching”, IEEE Tech. Dig. IEDM 2011, p.417.
[6] D-H. Kwon et al, “Atomic structure of conducting nanofilaments in TiO₂ resistive switching memory”, Nat. Nano., 5, p.148, 2011
[7] B. Gao, et al, “A Novel Defect-Engineering-Based Implementation for High-Performance Multilevel Data Storage in Resistive Switching Memory,” IEEE Tran. T-ED, 60, p. 1379, 2013.
[8] B. Gao, et al, “Ultra-Low-Energy Three-Dimensional Oxide-Based Electronic Synapses for Implementation of Robust High-Accuracy Neuromorphic Computation Systems”, ACS NANO 8, p. 6998, 2014

There is presently an extensive effort to develop non-volatile resistive random access memories (RRAM) based on transition metal oxides [1-4]. These generally work by the formation of a conductive filament of oxygen vacancies between the two electrodes. In one model, the ‘hour glass model&’ [2], the oxygen vacancies migrate between two ‘reservoirs&’, allowing the filament neck to increase or decrease in size during the SET and RESET process. HfO2, TiO2, Ta2O5, and Al2O3 are the typically used oxides, together with a scavenging metal that allows the vacancy creation process during the initial filament forming process. However, there has been no clear materials selection criteria given in terms of how to maximize memory endurance or retention lifetime.
Here, we determine the standard operating conditions in terms of O chemical potential and Fermi energy. It is shown how the choice of scavenger metal can be used to fix the O chemical potential. This then fixes the O vacancy formation energy, because that formation energy varies between ~6.1 eV at pO2 = 0 eV, to ~ 0.2 eV at for example the Hf/HfO2 equilibrium potential pO2 = -5.8 eV. Setting this formation energy then ensures that the total number of O vacancies is conserved during memory cycling, maximizing endurance, and stops formation of any O interstitials. Choice of the O chemical potential/scavenging metal allows the endurance and retention time to be optimized. The various migration energies and charge state energies are calculated for the oxides. It is argued that Ta2O5 has the preferred properties, having lower migration energies, charge state energies at the preferred Fermi energies, and having a wider stability zone of its amorphous phase than HfO2. On the other hand, TiO2 has sub-oxide phases which complicate electrode processes, while Al2O3 has too high defect formation and migration energies. It can only be used as an oxide modifier.
1. R Waser, et al, Adv Mats 21 2632 (2009)
2. R DeGraeve, et al, Tech Digest VLSI (2013)p8.1; Tech Digest VLSI (2012);
3. S Clima et al, APL 100 133102 (2012)
4. J J Yang et al, Nature Nanotechnol 3 429 (2008)
5. L Goux et al, ECS Solid State Lets 3 Q79 (2014)

Resistive RAM (ReRAM) is one of the leading non-volatile memory candidates due to many promising performance metrics and easy integration with CMOS technology [1]. ReRAM often uses memristors made from transition metal oxides, which are often described as being in one of two states, either high- or low-resistance. However, the state of a given memristor is a continuum of resistance values, demonstrated with TaO_x by applying voltages with compliance currents [2]. HfO_x devices have been programmed into distinct resistance bands using only voltage pulses [3]. In this work, we are assessing switching variability present in TaO_x memristors to determine suitability for multi-level applications. Currently, memristors from a single wafer have been tested. In the full paper, we will characterize the switching variability of memristors from different wafers with varying stoichiometry.
Automated wafer level testing was performed on multiple devices that cycled them repeatedly, using a feedback algorithm to ensure that they reached a certain resistance threshold (< 3 kOmega; for the set operation, and > 10 kOmega; for the reset operation). The voltage at which the resistance threshold was crossed was recorded. Based on these results, a series of 100 set and reset operations were performed with the feedback removed for the set operation and then repeated with feedback removed from the reset operation. The resistance range for the set operation increased by 1.68 and the reset range decreased slightly. Another device was programmed to three different high resistance states using the same technique. The three high resistance states had ranges of 8-22 kOmega;, 21-70 kOmega;, and 60-267 kOmega;. Without feedback the ranges were 5.5-14 kOmega;, 15.5-42 kOmega;, and 46-161.5 kOmega; (with one outlier of 31.5 kOmega;). These resistance bands can overlap, so the variability will be characterized across multiple devices and programming pulses will be tuned to achieve more distinct resistance levels.
The feedback algorithm helps to assess device suitability for multi-level applications and provides data on the typical switching voltages. The removal of feedback simplifies the usage of memory and should prolong endurance since the number of cycles applied per operation is reduced. Applying this technique to wafers produced with varying stoichiometry will allow us to optimize the processing conditions for TaO_x devices for various metrics, such as minimum variability and multi-level suitability.
References
[1] P. R. Mickel, et al., Mod. Phys. Lett. B, vol. 28, no. 10, p. 1430003, April 2014.
[2] T.-W. Lee and J. H. Nickel, IEEE Elec. Dev. Lett., vol. 33, no. 10, pp. 1456-1458, Oct. 2012.
[3] S. Yu, et al., Appl. Phys. Lett., vol. 98, pp 103514, 2011.
Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy&’s National Nuclear Security Administration under contract DE-AC0494AL85000

For more than 50 years, the capabilities of Von Neumann-style information processing systems — in which a "memory" delivers operations and then operands to a dedicated "central processing unit" — have improved dramatically. While conventional wisdom says that this remarkable history was driven by ever-increasing density (Moore's Law), the actual driver was Dennard's Law: the amazing realization that each generation of scaled-down transistors would actually perform better, in every way, than the previous generation. Unfortunately, Dennard's Law terminated some years ago, and as a result, Moore's Law is now slowing considerably. In a search for ways to continue to improve computing systems, the attention of the IT industry has turned to Non-Von Neumann algorithms, and in particular, to computing architectures motivated by the human brain.
At the same time, memory technology has been going through a period of rapid change, as new nonvolatile memories (NVM) — such as Phase Change Memory (PCM), Resistance RAM (RRAM), and Spin-Torque-Transfer Magnetic RAM (STT-MRAM) — emerge that complement and augment the traditional triad of SRAM, DRAM, and Flash. Such memories could enable Storage-Class Memory (SCM) — an emerging memory category that seeks to combine the high performance and robustness of solid-state memory with the long-term retention and low cost of conventional hard-disk magnetic storage.
However, such large arrays of NVM can also be used in non-Von Neumann neuromorphic computational schemes, with device conductance serving as the plastic (modifiable) “weight” of each “native” synaptic device. This is an attractive application for these devices, because while many synaptic weights are required, requirements on yield and variability can be more relaxed. However, work in this field has remained highly qualitative in nature, and slow to scale in size.
In this talk, we discuss our recent work on scaling NVM-based neural networks in size while quantitatively assessing engineering tradeoffs [1]. We demonstrate a 3-layer neural network of 164,885 synapses, each implemented with two PCM devices, trained on a subset (5000 examples) of the MNIST database of handwritten digits. A weight-update rule compatible for NVM+selector crossbar arrays is presented, as well as a “G-diamond” concept that illustrates problems created by nonlinearity and asymmetry in NVM conductance response. A neural network (NN) simulator matched to the experimental demonstrator allows extensive tolerancing. NVM-based Neural Networks are found to be highly resilient to random effects (NVM variability, yield, and stochasticity), but highly sensitive to “gradient” effects that act to steer all synaptic weights. Low “learning-rate” is shown to be advantageous for both high accuracy and low training energy.
[1] G. W. Burr, R. Shelby, C. di Nolfo, J. Jang, R. Shenoy, P. Narayanan, K. Virwani, E. Giacometti, B. Kurdi and H. Hwang, "Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element," IEDM Technical Digest, page 29.5, (2014).

Resistive Random Access Memories are among the most promising candidates for next generation non-volatile memory.[1-4] Transition metal oxides such as HfOx, TiOx and TaOx crystallized a lot of attention due to their CMOS compatibility. Further, these materials do not require the inclusion of extrinsic conducting defects since they operate based on intrinsic ones (oxygen vacancies - V_O). Using Density Functional Theory and bond-boosted Accelerated Ab Initio Molecular Dynamics (AIMD) techniques,[5] we evaluated the thermodynamics of the defects formation and the kinetics of diffusion of the conducting species active in transition metal oxide RRAM materials.[6,7] Here we report the gained insights built based on the thermodynamics at the Top Electrode, Insulating Matrix and Bottom Electrode interfaces. These are used to design a proper defect reservoir (so-called Oxygen Exchange Layer OEL), which is needed for a low-energy reliable switching device. It has also a direct impact on the retention of the Low Resistance State due to the resulting thermodynamic driving forces. The kinetics of the diffusing conducting defects in the IM determine the switching dynamics and resistance retention. The interface at the Bottom Electrode has a significant impact on the low-current operation and long endurance of the memory cell. Our first-principles findings are confirmed by both experimental measurements and stochastic model simulations.[8]
[1] Z. Wei et al., 2011 IEEE International Electron Devices Meeting, 31.4.1 (2011)
[2] S. Shyh-Shyuan et al., 2009 IEEE Symposium on VLSI Circuits, 82 (2009)
[3] L. Seung Ryul et al., 2012 IEEE Symposium on VLSI Technology, 71 (2012)
[4] B. Govoreanu et al., Ext. Abstr. SSDM Conf.,Nagoya, Japan, 1005 (2011)
[5] R. A. Miron and K. A. Fichthorn, J. Chem. Phys. 119, 6210 (2003)
[6] S. Clima et al., App. Phys. Lett. 100, 133102 (2012)
[7] L. Goux et al., 2012 IEEE Symposium on VLSI Technology, 69 (2012)
[8] R. Degraeve et al., 2012 IEEE Symposium on VLSI Technology, 75 (2012)

Devices based on the field-driven migration of metal inclusions (such as resistive switching or memristive devices) have attracted broad interest recently and have shown great potential as a disruptive technology for a number of applications including nonvolatile memory, logic, and neuromorphic computing. The resistive switching effect is normally attributed to filament formation caused by the movement of metal inclusions in the insulating dielectric film. However, a critical question was raised regarding the fundamental, microscopic origin of the growth and migration of the nanoclusters inside dielectrics¹, and whether the different and seemingly contradicting experimental results can be reconciled within the same theoretical framework. Here we directly reveal the microscopic origin of the dynamic growth and migration processes of various metal nanoclusters (Ag, Cu, Ni, Pt) in dielectrics and show that the field-driven migration is a universal behavior, even for inert metals such as Pt². We show the different migration modes can be explained in the electrochemical model framework, driven by both thermodynamic and kinetic factors. Specifically, we show that in conventional macroscopic insulators the metal clusters can be treated as bipolar electrodes, and can dissolve from their original locations and nucleate and redeposit at new positions closer to the counter electrode in a process driven by the competing electrochemical processes occurring at the two polarized sides. We show this fundamental process can be used to explain the diverse filament growth modes observed experimentally^1,3, and predict and verify the growth modes at different limiting cases, mainly controlled by the kinetic factors including ion mobility and redox rates, therefore reconciling the different experimental results obtained earlier within a generalized theoretical framework². By tuning kinetic factors we further show different nanocluster dynamics can be observed in the same device, leading to transition between different filament growth modes. These findings can be readily expanded to material and device systems where controlling the metal inclusion dynamics (or avoiding such) is critical and will have significant theoretical and practical impacts.
References
1. I. Valov and R. Waser, Adv. Mater.25, 162-164 (2013).
2. Y. Yang, P. Gao, L. Li, X. Pan, S. Tappertzhofen, S. Choi, R. Waser, I. Valov, and W. D. Lu, Nat. Commun. 5, 4232 (2014).
3. Y. Yang, P. Gao, S. Gaba, T. Chang, X. Pan, and W. Lu, Nat. Commun. 3, 732 (2012).

Resistive random access memories based on Redox phenomena (ReRAM) have gained much attention for the future use as nonvolatile information storage due to their good scalability, high endurance and fast switching kinetics (1),(2). ReRAM cells basically consist of a metal-insulator-metal structure with the information being retained in form at least two different resistive states, hereinafter called LRS (low resistive state) and HRS (high resistive state).
The devices characterized in this work belong to the VCM (valence change mechanism) class of resistive switches, that is characterized by a migration of mobile donors, here: oxygen-vacancies, and a corresponding valence change of the cation-sublattice. During an initial electroforming step an oxygen-vacancy rich, and therefore highly conductive, nano-sized filament evolves in the oxide layer (1). By the application of bipolar voltage signals the length of the filament can be modulated and the device can be switched between the two states (1),(2). The switching from the HRS to the LRS is called SET. During the SET the oxygen vacancies are attracted by a negative voltage bias to the active electrode, thereby leading to a conductive path between the electrodes. By the application of a positive voltage the oxygen vacancies are repelled from the active electrode thus rupturing the filament. This process is called RESET and leaves the device in the HRS. It is essential for nonvolatile memories to overcome the “voltage-time dilemma”, i.e. the discrepancy of high retention at low read voltages and very fast switching at only moderately higher write voltages (3). For the VCM class of ReRAM this dilemma is solved by the highly nonlinear SET and RESET kinetics. The analysis of this nonlinearity is essential for understanding the physical processes underlying the resistive switching (4),(5).
In this paper we present a study of the switching kinetics of SrTiO₃ based resistive switches covering up to 12 orders of magnitude on the timescale. The cells used for this study are microstructured Ti/SrTiO₃/Pt cells and Pt/SrTiO₃/TiN nano-crossbars. A pulse scheme is used to cycle the cells thereby monitoring the transient currents for a precise analysis of the SET and RESET transitions. Through varying the pulse width and amplitude the influence of the applied voltage on the switching kinetics is studied between 10 ns and 10⁴ s. The results are supported by the model proposed in (5). Taking the pre-switching currents into account, a power dependency of the SET is found that emphasizes the importance of local Joule heating for the nonlinearity of the switching kinetics.
(1) R. Waser, R. Dittmann et al., Adv. Mater., 21, 2632 (2009)
(2) Myoung-Jae Lee, Chang Bum Lee et al., Nat. Mater., 625 (2011)
(3) H. Schroeder, V. V. Zhirnov et al., J. Appl. Phys., 107, 054517/1 (2010)
(4) S. Menzel, M. Waters et al., Adv. Funct. Mater., 21, 4487 (2011)
(5) K. Fleck, U. Böttger et al., IEEE Electron Device Lett., 35, 924 (2014)

Redox-based resistively switching thin films have attracted great attention for the potential use in future nonvolatile information storage; a so-called ReRAM. By applying appropriate voltages, a ReRAM cell can be switched between a high resistive state (HRS) and a low resistive state (LRS). Since multiple resistance state can be programmed, multiple bits can be potentially stored in one memory cell (1, 2).
One class of oxide resistive switches relies on the electrochemical metallization mechanism (ECM) also known as conductive - bridging RAM (CBRAM). ECM cells consist of an active silver/copper electrode an ion conducting layer, e.g. TaOx or AgI, and an inert electrode. The ECM mechanism relies on the electrochemical growth/dissolution of an Ag/Cu filament within the ion conducting layer. To switch the ECM cell to the LRS (SET operation) a positive voltage needs to be applied to the active electrode, whereas a negative voltage is required to RESET the cell to the HRS. By tuning the current compliance during SET different LRS can be achieved which are represented by varying tunneling gaps between the growing silver/copper filament and the active electrode (3, 4).
The modeling of ECM cells is crucial for the understanding of the switching mechanism, variability and failure mechanism. In this paper a kinetic Monte Carlo simulation model is presented that enables to relate microscopic processes, e.g. single hopping events, to macroscopic switching properties. It includes the electrochemically driven growth/dissolution of the filament as well as electron tunneling. Furthermore, the influence of the mechanical stress and the applied voltage on the filamentary growth is investigated. Our simulation results indicate that the dimensions of the growing filament depend on the applied voltage. In addition, the mechanical stress that builds up during growth facilitates a cylindrical filament growth.
It is shown that the simulation model can reproduce the reported switching kinetics, switching variability and multilevel capabilities of ECM devices. In particular, the nonlinear switching kinetics is determined by three different processes depending on the voltage regime: (i) nucleation, (ii) electron-transfer reactions, and (iii) ion hopping transport.
(1) R. Waser, M. Aono et al., Nat. Mater., 6, 833 (2007)
(2) J. J. Yang, D. B. Strukov et al., Nat. Nanotechnol., 8, 13 (2013)
(3) S. Menzel, U. Böttger et al., J. Appl. Phys., 111, 014501/1 (2012)
(4) S. Menzel, S. Tappertzhofen et al., PCCP, 15, 6945 (2013)

A "memristor" (or "memory resistor") is a Metal-Insulator-Metal (MIM) resistor whose resistance value depends on its past electrical history, i.e. its current-voltage characteristic (I-V) displays a hysteresis loop. In recent years, a large amount of research has been devoted to memristors, focusing on their application to microelectronic non-volatile memories (RRAM - Resistive Random Access Memory). Depending on the nature of the oxide as well as the metallic electrode, the switching is based on a unipolar thermochemical mechanism, a bipolar valence change mechanism, as well as a bipolar electrochemical metallization mechanism. For all these devices, yields and cyclability strongly depends on oxide, metal and interface. In the last five years, we studied HfO₂ based RRAM which is a good candidate for embedded non-volatile memories since it can offer high density, high speed and low power consumption [1-3].
While investigating HfO₂ RRAM we found that, upon voltage biasing, not only does the resistance changes, but the capacitance also varies. This also has been recently observed by other groups [4-7]. In other words, both the real and imaginary part of the impedance can be controlled by the voltage bias. Moreover, the impedance state is non-volatile (memory function). This defines a “memory impedance”, or “mem-impedance”, which extends the concept of memristor to include the more general impedance. Memory impedance devices (mem-capacitors and mem-inductors) were recently theorized and their potential applications reviewed [8].
In this presentation we will show that it is possible to vary the capacitance over a very broad range, from positive values down to negative values. In other words, it is even possible to get an inductive behavior for the MIM device. By comparison, commercial varactors do not provide the possibility to tune the resistance while the change in capacitance is limited for SONOS structures. Here both the resistance and capacitance can be tuned at the same time. These distinct properties make mem-impedances a new class of devices. At present, the physical origin of capacitance variation is an open question. One hypothesis is that conduction paths, which lead to resistance switching, are the same which lead to capacitance decrease (though the inductive behavior of conduction paths). This will be discussed in this presentation.
[1] Ch. Walczyk et al, J. Vac. Sci. Technol. B29 (2011) 01AD02-1
[2] P. Gonon et al, J. Appl. Phys.107 (2010) 074507
[3] V. Jousseaume et al, Solid-State Electronics58 (2011) 62-67
[4] C.H. Cheng et al, IEEE Electron Device Letters32 (2011) 1749
[5] S. Liu et al, J. Appl. Phys. 100 (2006) 056101
[6] S-C. Na et al, Appl. Phys. Lett.104 (2014) 123503
[7] L. Quingjiang et al, Sci. Rep. 4 (2014) 4522
[8] Y.V. Pershin et al, Advances in Physics60 (2011) 145

In this presentation, we will report (1) our latest approach to reduce the dislocation density in heteroepitaxially grown Ge to 10⁵ cm^-2 level, (2) temperature-dependent optical characterization and transistor performance, and (3) a new approach to create a responsive SiGe substrate to form a 2D array of Ge quantum dots as a basis for future transistor architecture. Our recent growth technique takes advantage of oxygen-precipitate-induced dislocation reduction in n-type Ge, where the dislocation density is reduced to the 10⁵ cm^-2 level. This result contrasts with 10⁷ cm² level observed in p-type Ge grown on Si by the same procedure. For n-type Ge, we observe accumulation of n-type impurity (phosphorus) near the oxygen precipitates that exist near the Ge-Si interface, whereas we do not observe oxygen precipitates or p-type impurity (boron) accumulation in p-type Ge. This observation supports that n-type impurities stabilize the formation of oxygen precipitates that are known to lock dislocations from propagating. As a stringent test of the dislocation reduction, we have fabricated and characterized high-carrier-mobility MOSFETs on Ge-on-Si (GoS) substrates. The effective mobility µ_eff in p- and n-MOSFETs is 401 and 940 cm²/V-s (82 and 30% improvement from Si), and the subthreshold slope is 100 and 200 mV/decade, respectively. Consistent with the improved crystalline quality, we also observe photoluminescence (PL) from n-type Ge with 0.8% tensile strain, where the pronounced PL intensity indicates bandgap shrinking at the #1043; band-edge. Going beyond epitaxial engineering and device fabrication, we demonstrate a scalable path to create a 2D array of Ge quantum dots on responsive SiGe substrates based on elastic mechanical deformation and subsequent SiGe compositional redistribution. For large-scale manufacturing of single-electron transistors, we show that a spatially structured elastic compressive stress to the SiGe substrate with proper thermal annealing leads to a compositional redistribution of Si and Ge in the near-surface region of SiGe substrates, forming a 2D array of Ge-depleted nanoscale regions. A study is currently underway to expose the compositionally altered SiGe surface Ge beam to form Ge quantum dots.

One of the most critical issues for Ge/III-V MOSFETs, which have been regarded as a promising CMOS structure under sub 10 nm regime, is formation of superior gate stacks satisfying the requirements of thin equivalent oxide thickness (EOT) and excellent MOS interface quality enabling high channel mobility and low S factor. As a result, MOS interface control engineering is of paramount importance. In this presentation, we focus on viable III-V/Ge gate stack technologies by using ALD high-k films for realizing these requirements. The impact of the MOS interface properties on the MOS channel mobility is also addressed.
As for Ge gate stacks, we present ultrathin EOT Al₂O₃/GeO_x/Ge and HfO₂/Al₂O₃/GeO_x/Ge gate stacks, fabricated by a plasma post oxidation method, and the electrical properties of n- and p-MOSFETs using these gate stacks. HfO₂/Al₂O₃/GeO_x/Ge gate stacks with EOT of 0.76 nm have yielded (100) Ge p- and nMOSFETs with high peak mobility of 546 cm²/Vs and 690 cm²/Vs, respectively. We have evaluated limiting factors of electron and hole mobility in Ge n- and p-MOSFETs. It is found in a high N_s region that the Ge MOS channel mobility is significantly degraded by surface roughness scattering as well as trapping of free electrons holes into interface states inside the conduction and valence bands. The mobility in the high N_s region can be improved by reduction in surface roughness through a layer-by-layer plasma oxidation process. Also, atomic Deuterium annealing can reduce Dit inside the bands, resulting in higher effective mobility.
As for InGaAs gate stacks, the insertion of 0.2-nm-thick ultrathin Al₂O₃ inter-layer can effectively improve the HfO₂/InGaAs interface properties, resulting in 1-nm-thick CET HfO₂/Al₂O₃/InGaAs MOS gate stacks with low gate leakage of 2.4×10^-2 A/cm². As similar to Ge, on the other hand, electron trapping in interface states inside the conduction band of InGaAs also significantly reduces effective mobility in in high N_s. It is shown, on the other hand, ALD La₂O₃ gate stacks can yield lower Dit than the Al₂O₃ ones, indicating that La₂O₃ can be a promising high k material for III-V gate stacks. As for GaSb gate stacks, much higher Dit of Al₂O₃/GaSb MOS interfaces than that of Al₂O₃/InGaAs MOS interfaces severely degrades the device performance. Any thermal processing significantly is observed to increase D_it at Al₂O₃/GaSb interfaces. It is shown that InAs passivation can effectively improve the MOS interface properties and the thermal stability. 2.5-nm-thick InAs passivation can provide the peak hole mobility of 159 cm²/Vs for Al2O3/InAs/GaSb pMOSFETs.

We demonstrate the growth of crystalline strontium titanate, SrTiO₃ (STO), and strontium hafnate, SrHfO₃ (SHO), directly on Ge via atomic layer deposition (ALD). Both STO (a ~ 3.905 Å) and SHO (a ~ 4.069 Å) have good lattice match to the Ge (001) surface (a/radic;2 ~ 3.992 Å), yielding a ~2.2% tensile and ~1.9% compressive strain in the epitaxial film, respectively. After thermal deoxidation, the Ge substrate is transferred in vacuo to the deposition chamber where a thin film of STO / SHO is deposited by ALD. Following a post-deposition anneal, the perovskite film becomes crystalline with epitaxial registry to the underlying Ge (001) substrate. The 2×1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. In situ x-ray photoelectron spectroscopy confirms stoichiometric films with no GeO_x formation or carbon impurities. The STO and SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy.
Capacitor structures using the crystalline STO dielectric show a high permittivity (k~90), but also high leakage current (~10 A/cm² at +1 eV). The unfavorable conduction band offset (and high leakage current) of STO on Ge is circumvented by growing the Hf-based perovskite, SHO. The SHO films have favorable electronic properties, with satisfactory band offsets with Ge (> 2 eV), low leakage current (< 10^-5 A/cm² at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k~15). The interface trap density (D_it) is estimated to be ~2-5 × 10¹² cm^-2 eV^-1 under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ~650 °C, which may contribute to the observed D_it value.
In efforts to improve electrical performance of the crystalline perovskite dielectric, including leakage current, permittivity, and D_it, we have recently studied crystalline SrHf_xTi_1-xO₃ (SHTO) grown directly on Ge by ALD. SHTO benefits from a reduced leakage current over STO and a higher permittivity than SHO. The SHTO films crystallize at a relatively lower temperature than SHO (600 °C vs. 650 °C), which limits the formation of hafnium germanide. In addition, the lattice constant of SrHf_xTi_1-xO₃ (x~0.5) is estimated to be 4.014 Å, yielding minimal (~0.6%) compressive strain in the epitaxial film. By minimizing the epitaxial strain and maintaining an abrupt interface, the SHTO films are expected to reduce D_it at the oxide-Ge interface. We will report our recent results on the growth, characterization, and electrical performance of epitaxial SHTO films on Ge for next-generation high-k dielectric applications, and compare them against STO and SHO films grown directly on Ge(001).

Germanium (Ge) is a promising semiconductor material to be used in hole current-carrying devices due to its better transport properties in comparison with silicon (Si). However, finding a suitable passivation strategy is still a challenge for Ge-based devices. Passivation strategies usually involve the formation of a thin layer on the top of Ge (usually Ge oxides or oxynitrides) followed by the deposition of a high dielectric constant material (HfO₂, for example). The resulting stack can be further annealed in order to heal defects formed during the deposition process. Tailoring the effects of such annealings is mandatory to conveniently modify the physico-chemical and, consequently, electrical properties of the resulting structure. Post-deposition annealings (PDAs) can be performed after the formation of metallic electrodes on the top of the dielectric which can modify the reactivity of the annealing gas. Pt/HfO₂/Ge stacks evidenced reduced interface trap densities following oxygen treatments [Henkel et al., Appl. Phys. Lett. 97 (2010) 152904]. Comparison with bare samples annealed in oxygen (without the Pt layers) confirmed the role played by the electrode. In the present work, we investigated O incorporation in Pt/HfO₂/Ge stacks aiming at understanding the role of the Pt layer in the physico-chemical modifications of this structure following PDA in O₂. PDAs were performed with oxygen enriched in the ¹⁸O isotope (¹⁸O₂). Depth profiling of this isotope with subnanometric depth resolution enabled the identification of incorporation sites and transport mechanisms. Results were compared with counterpart structures prepared on Si. HfO₂ deposited on Ge constitutes a diffusion barrier for molecular O₂, preventing pronounced substrate oxidation during PDAs in O₂. The supply of atomic oxygen (able to diffuse through HfO₂) is a function of temperature and the number of available O₂ dissociation sites in HfO₂ [Goncharova et al., Appl. Phys. Lett. 89 (2006) 44108]. O transport promotes exchange of this element in the HfO₂ lattice. The extent of oxidation of the underlying Ge depends on the amount of O reaching the HfO₂/Ge interface. Deposition of a top Pt layer promotes a more efficient O₂ dissociation, raising the net flux of incoming O in HfO₂. This process is followed by a higher O exchange in HfO₂ and a higher O supply at the HfO₂/semiconductor interface. In the case of Ge, the more defective nature of its oxide (in comparison with SiO₂) promotes the consumption of O. Thus, oxidation of the Ge substrate is higher than that of bare HfO₂ samples. The different nature of thermally grown oxides on Si and on Ge have direct influence in the resulting physico-chemical modifications of the stacks prepared on these semiconductor materials.

Commercially available gate-first high-k/metal gate dual channel (Si nFET, SiGe pFET) CMOS technologies incorporate ‘metal-inserted poly-Si stack&’ (MIPS) gate electrodes in which amorphous or polycrystalline Si (a-Si or poly-Si) on a nitride work function metal such as TiN serves as a barrier against external oxygen ingress during junction activation and is then alloyed to form a low-sheet-resistance silicide such as Ni(Pt)Si_x. Supplanting this alloy-based stack with a deposited gate would facilitate semi-self-aligned (‘borderless&’) source/drain (S/D) contact formation and thus continued pitch scaling [1]. Prior deposited full metal gates (FMG) have employed tungsten as a low-resistivity layer, but oxygen down-diffusion through the W in the absence of a-Si has been a challenge.
We evaluate deposited gates incorporating low-resistivity, oxygen-blocking titanium silicide. We discuss (i) a simple TiSi_x/TiN FMG, and (ii) TiSi_x/a-Si/TiN ‘hybrid metal gates&’ (HMG) or ‘deposited MIPS&’ (DMIPS) which would retain the bottom a-Si/TiN element from conventional alloyed MIPS. Silicide phases and thermal stability during rapid thermal anneals are studied by in situ synchrotron X-ray diffraction (XRD) and sheet resistance (R_s) measurements, SEM, TEM, STEM-EDX, etc. Device integrity and performance are evaluated using low-gate-height (~30 nm) gate-first Si channel nFETs and SiGe channel pFETs with HfO₂-based gate dielectrics and >1000°C anneals.
We first show that TiSi_x/TiN FMG with Si-rich TiSi_x crystallize in the desirable low-resistivity C54-TiSi₂ phase, are thermally stable during gate-first processing, and successfully block oxygen. We thus demonstrate a capacitance-equivalent thickness in inversion (T_inv) of 1.11 nm, corresponding to an equivalent oxide thickness (EOT) of about 0.7 nm. Silicon channel nFET and silicon germanium channel pFET parametrics are similar to those of control devices utilizing a conventional a-Si/TiN gate, while providing superior gate sheet resistance.
By contrast, TiSi_x/a-Si/TiN HMG suffer lateral phase segregation during the anneal, resulting in side-by-side MIPS and C54-TiSi_x/TiN FMG regions and thus elevated R_s. While this remarkably leaves long-channel device performance essentially unaffected, it would be unacceptable in short-channel transistors. We newly establish that segregation occurs for a wide range of a-Si film thicknesses and deposition processes, suggesting that in order to stabilize the stack, the silicide layer may have to be modified instead. We evaluate Ta incorporation, known to promote C54-TiSi₂ phase formation [2] and thermal stability on poly-Si [3]. We find that lightly Ta-doped Ti(Ta)Si_x/a-Si/TiN indeed exhibits superior thermal stability and is promising for gate-first device integration.
[1] S.-C. Seo et al., Proc. VLSI, p. 36 (2011)
[2] C. Cabral, Jr., et al., Appl. Phys. Lett. 71, 3531 (1997)
[3] J. S. Choi et al., J. Appl. Phys. 74, 1456 (1993)

To improve advanced CMOS performance, mobility boosters have to be used. For example, for Fully Depleted SOI (FDSOI), strained Si-On-Insulator (sSOI) wafers using Smartcut^TM have been developed to improve nMOSFETs. We propose here another approach to create sSOI starting from SOI wafers by transfer of lattice parameter from a relaxed Si_0.7Ge_0.3 to the Si layer.
The process is divided in four steps: i) a Si_0.7Ge_0.3 epitaxy of 40 nm on SOI with 9 nm thickness Si; ii) an amorphization by Si implantation at 25 keV with 2.5 x 10¹⁴ at/cm² (tilt 0°) of the Si layer and the lower portion of the SiGe layer; iii) a recrystallization by thermal annealing at 850 °C, 10 s under N₂ atmosphere, and; iv) SiGe selective etching using HCl. The stress induced in the Si thin film in memorized turning the initial SOI into sSOI. High Resolution X-Ray Diffraction (HRXRD) and cross-sectional Transmission Electron Microscopy (TEM) were used to characterize the microstructure of the layers. Strain and stress evolutions throughout the process were determined using Raman spectroscopy and wafer bow measurements.
Firstly, HRXRD profiles and Raman spectra allow us to confirm the compressive stress (- 1.94 GPa) of the initially compressively-strained Si_0.7Ge_0.3 layer.
Secondly, the implantation induced an amorphization in depth of the Si layer and most part of the SiGe while keeping a thin monocrystalline seed at the surface. It can relax and recover is own lattice parameter. That is confirmed by HRXRD which shows SiGe fringes loss which corresponds to a significant amorphization of the SiGe layer. The presence and the thickness of a top crystalline seed have been then determined by TEM micrograph (around 6 nm). This amorphization involves also a stress relaxation of the SiGe layer (around -100 MPa) calculated from wafer bow measurements.
For the third step, the amorphized layers have recrystallized with a dedicated annealing step. HRXRD and TEM characterizations both confirm recrystallization and relaxation of the SiGe layer. The relaxed top seed imposed its own lattice parameter to the amorphous SiGe and Si layers, which turn into relaxed SiGe and tensile Si respectively.
Finally, after SiGe selective etching, according to Raman spectroscopy, the 9 nm Si layer exhibits a large tensile stress with + 1.6 GPa.
In summary, we report here the fabrication of a tensile Si (sSOI), starting with SOI substrate. The process divided in four steps (epitaxy, implantation, anneal and SiGe etching) have been analyzed by using HRXRD, TEM, Raman spectroscopy and wafer bow measurements. We demonstrate here tensile sSOI with a 9 nm Si exhibiting a stress of + 1.6 GPa corresponding to 80% of lattice parameter transfer from a relaxed Si_0.7Ge_0.3 to the Si layer.

Silicon Germanium (SiGe) is a promising candidate for FinFET channels, sources, and drains due to its high mobility and utility in strain engineering. Since FinFETs are composed of three-dimensional structures utilizing multiple crystalline planes, the cleaning and passivation must provide uniform and clean surfaces in each plane to combine high mobility with low interface trap density (Dit). In this study, passivation and functionalization of SiGe(100) and (110) surface are discussed, using Scanning Tunneling Microscopy (STM), Scanning Tunneling Spectroscopy (STS), X-ray Photoelectron Spectroscopy (XPS), and Capacitance-Voltage (C-V) curve.
The SiGe(100) is dimer terminated while the SiGe(110) is dimer-free leading to differences in surface stoichiometry and surface order. STM and XPS measurements indicate that clean (100) is mostly terminated with Ge atoms with a uniform and well-ordered structure while (110) is terminated with both Si and Ge atoms and lower surface order. The clean SiGe sample was dosed at room temperature with a saturation dose of H₂O₂(g) leaving the SiGe surface terminated with an ordered monolayer of only Ge-OH sites on (100) and Ge-OH and Si-OH sites on (110). STS measurements indicate the clean n-type (100) surface is unpinned while on the HOOH dosed SiGe(100) the Fermi level is shifted to near the valence band edge due to the large surface dipole when the surface is passivated with Ge-OH bonds. In comparison, the clean (110) surface is pinned mid gap between the valence and conduction band edge due to adatom dangling bonds while the HOOH dosed p-type SiGe(110) is shifted to near the valence band edge after passivation with Si-OH and Ge-OH bonds . In order to understand the thermal stability of monolayer of hydroxyls on the surface, the surfaces were annealed to 300°C and XPS measurements verify that oxygen does not desorb from the surface and remains in the form of Si-OH or SiO_x species on both (100) and (110). XPS also indicates that strong affinity between Si and oxygen is pulling Si atoms toward the surface to bond with oxygen or hydroxyls while pushing Ge atoms into the subsurface during the annealing. TMA was subsequently dosed on the HOOH/SiGe(001) and HOOH/SiGe(110) surfaces forming an ordered monolayer of Al-O-Si bonds. STS indicates this unpins the Fermi level on both surfaces, leaving an electrically passive ordered layer which serves as an ideal template for further high-k ALD.

The interface between high-k gate oxides and SiGe channel is crucial for EOT scaling and carrier transport of SiGe MOSFETs. In this work, SiGe substrates with a range of Ge compositions are characterized by both soft x-ray synchrotron photoelectron spectroscopy (PES) and x-ray reflectivity (XRR) measurements at SSRL to determine the surface and interface components. SiGe-MOSCAPs are fabricated using a HF/H₂O surface clean cycles prior to gate dielectric ALD and we then investigate H₂O₂/HF cleans to produce a less defective interface.
Soft x-ray synchrotron PES was performed at SSRL Beamline 8-1a with photon energies of 60eV to 200eV. We first characterized the as-received SiGe surfaces with bulk Ge compositions 35%, 45%, 50% and 70%. Both SiO_x and GeO_x PES peaks are detected, and the intensities of both Si 2p and Ge 3d substrate peaks decrease with higher bulk Ge composition. Angle-resolved PES results for Ge 3d and corresponding to GeO_x peaks suggest that the GeO_x is concentrated beneath a top surface SiO_x. The initial analysis yielded some conclusions about the pre-cleaned surface composition: The SiO_x-GeO_x oxide layer at the top surface is inhomogeneous, being SiO_x rich near the surface and GeO_x rich near the substrate. The composite oxide layer is thicker for higher Ge composition. A Ge-rich layer is sandwiched in between the top oxide layer and the SiGe substrate.
XRR measurements were performed at SSRL Beamline 2-1 with a grazing incidence angle from 1 to 5 degrees. Al₂O₃ layers were deposited by ALD on SiGe substrate (with 45% Ge) using a TMA-H₂O process at 250#730;C. It was found that the addition of H₂O pre-pulsing lowers the interface roughness between Al₂O₃ and the SiGe surface, however the interface roughness appears to be insensitive to the number of ALD cycles The XRR analysis also reveals that the interfacial layers are comprised of non-stoichiometric oxides of Al, Si & Ge, which are in agreement with the PES data.
Clean cycles using HF 2%/DI water appears to leave an almost oxide-free surface. However, C-V curves from Pt/TiO₂/Al₂O₃/Si_0.5Ge_0.5 MOSCAPs after forming gas anneal (FGA) exhibit frequency dispersion and a large D_it feature in weak-inversion. These C-V features may result from poor initial chemisorption of TMA and/or H₂O on a clean SiGe substrate. H₂O₂/HF cyclic cleans were also examined to change the surface composition in order to avoid chemisorption issues. Soft x-ray synchrotron PES results show that after H₂O₂/HF clean, there is a thin GeO₂ layer on top and the initial surface SiO_x is changed to stoichiometric SiO₂ under the GeO₂. The top GeO₂ layer exhibits quite facile initial TMA chemisorption. To validate the H₂O₂/HF clean process, SiGe p-type MOSCAPs with Pt/TiO₂/Al₂O₃/Si_0.5Ge_0.5 gate stack were fabricated with an identical ALD method based on HF/H₂O₂ cyclic pre-ALD clean. Significantly lower D_it response was observed in C-V plots than does HF/DI-H₂O cleaning suggesting an improved clean process using H₂O₂/HF.

Silicon-Germanium has shown a great promise to be used in the future CMOS technology combining the high hole and electron mobility of Ge with the ability to have both tensile and compressive strain by fabrication of alloys of higher and lower Ge content. In contrast to Si, SiGe native oxide is a combination of SiO₂ and GeO₂, generally denoted by SiGeOx which has low interface quality and stability in comparison with SiO₂ due to the presence of the GeOx. Therefore, instead of thermal oxide growth, it is necessary to employ atomic layer deposition (ALD) for gate oxide deposition in SiGe MOS devices. Furthermore, scaling SiGe devices is crucial in its future application and ALD growth of high-k oxides with small equivalent oxide thickness (EOT) such as Al₂O₃, HfO₂ and TiO₂ on SiGe is favorable. The present study determines the effect of the ALD temperature on Al₂O₃ bulk and Al₂O₃/SiGe interface quality in terms of oxide leakage and interface and near-interface trap density. MOS capacitors fabricated by Al₂O₃ ALD at 120, 200 and 300 °C, have been compared by capacitance-voltage (C-V) and current-voltage (I-V) measurements. Upon increase in ALD temperature, maximum capacitance in C-V measurements decreased consistent with larger equivalent oxide thickness as a result of interfacial SiGeOx formation. Al₂O₃ ALD at 120 ^°C resulted in smaller positive flat-band-voltage relative to the oxide deposited at 200 and 300 °C suggesting lower positive fixed or trapped charge in the oxide. Interface trap capacitance to the maximum capacitance ratio did not significantly change as a function of ALD temperature consistent with the formation of a high quality interfaces between Al₂O₃/SiGe with formation of an SiO₂ interlayer. Thickness of SiGeOx interfacial layer will be measured as a function of Al₂O₃ ALD temperature using angle-resolved X-ray photoelectron spectroscopy (AR-XPS).

With the recent physical demonstration of memristive-based devices, low-power two terminal devices with memory and learning functions have advanced electronics and computing. In memristive devices, typically slow moving ions are coupled with fast moving electrons. Ionic motion affords memory, with electronic current as the output signal. Here, we present fully ionic memory devices in which protons (H⁺) provide both memory and output signal. We describe the development of 1D and 2D grid-based memory elements. These devices function by storing and passing protons between adjacent palladium bits, in a mechanism similar to electron transfer in a CCD. This transfer allows for the serial measurement of parallel analog inputs. Digital input or output can easily be accomplished by assigning logic values to threshold values of proton concentration. Energy consumption is dependent on device volume: the current 10µm x 30 µm device consumes 35 µJ per switching operation, but a 40nm x 40nm bit is expected to consume less than 50fJ.

In_0.53Ga_0.47As is considered as one of the most attractive semiconductors for high electron mobility channels complementary metal oxide semiconductor transistors. Fixed charges and traps (e.g. border traps) within the oxide layer, and trap states produced by defects at the Al₂O₃/InGaAs interface were found in many studies of Al₂O₃/InGaAs gate stacks. Post oxide deposition annealing and post metal deposition annealing help in improving the quality of the Al₂O₃/InGaAs system by reducing the above mentioned traps and charges.
In this study the effect of post metal deposition annealing on the effective work function (EWF) in metal/Al₂O₃/InGaAs gate stacks was investigated. Al₂O₃ was deposited by thermal atomic layer deposition (ALD) using a standard trimethylaluminum/H₂O process on n-type InGaAs(100) substrates. The samples were then annealed at 400°C for 30 min in vacuum (P<10^-7 Torr). Various metals were deposited by electron beam evaporation or thermal evaporation through a shadow mask to be used as the gate metal. The samples were then annealed again at 400°C for 30 min in vacuum (P<10^-7 Torr). Various techniques including high resolution transmission electron microscopy, time-of-flight secondary ion mass spectrometry (TOF-SIMS), and electrical measurements were utilized to analyze the MOS samples.
In order to calculate the EWF of the different metals we measured the flat-band voltage (V_FB) in different oxide thickness (t_ox) samples and plotted V_FB vs. t_ox curves. We found a significant difference between the extracted EWF and the reported vacuum work function (VWF) values. The EWF of high VWF metals (such as Pt) decreased while the EWF of low VWF metals (such as Al) increased.
TOF-SIMS measurements showed that after the post metallization annealing, Indium was found at the metal/Al₂O₃ interface. We suggest that this accumulation of Indium causes the Fermi level pinning. The interface traps in the Indium rich interface can be charged or discharged according to the difference between the charge neutrality level of the Al₂O₃ and the Fermi level of the metal, thus explaining the convergence of the EWF values to the range of 4.8-5.2 eV.

In 2003, a key scaling limit of the physics underlying the current computer switch technology, the complementary metal oxide semiconductor (CMOS), was reached. The consequence is that line voltage is fixed at about 1 V and computer clock speeds are now frozen. A general mechanism to circumvent the physical limits of CMOS is referred to as transduction; an input voltage is transduced into a degree of freedom internal to the device, which is then transduced back into voltage. This effect serves to circumvent electrostatic gating physics of CMOS which no longer scales, allowing, in principle, the development of very fast, low voltage devices.
We have invented a transduction based post-CMOS device based on piezoelectrically driven metal insulator transitions [1-2]. An input voltage pulse activates a nanoscale piezoelectric element (PE) which transduces input voltage into an electro-acoustic pulse that in turn drives an insulator to metal transition (IMT) in a nanoscale piezoresistive element (PR); the transition effectively transduces the electro-acoustic pulse back to voltage - mechanical contact is continuous, distinguishing the concept from NEMs and avoiding its breakdown mechanisms. Using the known properties of bulk materials, we predict using modeling that the PET achieves multi-GHz clock speeds with voltages as low as 0.15 V and a large On/Off switching ratio (~10⁴) suitable for digital logic [1-2].
Exceptional PET device performance is enabled by the properties of two key materials, a relaxor piezoelectric for the PE and a rare earth chalcogenide piezoresistor for the PR - provided the materials exhibit nearly bulk properties at the nanoscale. Thus it is critical to investigate materials scaling using a combined theoretical/experimental approach. In this lecture, the development of thin film piezoresistive and piezoelectric materials and patterned structures, and associated characterization tools is presented, along with the theoretical models that yield insight into their behavior [3-6]. Lastly integration of these novel materials into 3 evolutionary generations of PET devices, and subsequent device characterization, is briefly given [7] to show that an experimental proof of concept, piezoelectrically driven cycling of an IMT in a piezoresistor, has been achieved.
1. D.M. Newns, B.G. Elmegreen, X.-H. Liu, G.J. Martyna, Adv. Mat.24, 3672 (2012).
2. D.M. Newns, B.G. Elmegreen, X.-H. Liu, G.J. Martyna, MRS Bulletin37, 1071 (2012).
3. M. Copel et al, Nano Lett. 13, 4650 (2013).
4. Z. Jiang, M.A. Kuroda, D.M. Newns, G.J. Martyna et al, Appl. Phys. Lett. 102, 193501 (2013).
5. M.A. Kuroda, Z. Jiang, Michael Povolotskyi, Gerhard Klimeck, Dennis M. Newns and G.J. Martyna, Phys. Rev. B. submitted (2014).
6. R. Keech, S. Shetty, M. A. Kuroda, X-H Liu, G.J. Martyna, D.M. Newns, and S. Trolier-McKinstry, J. Appl. Phys.115, 234106 (2014).
7. P.M. Solomon, B. Bryce, M. Copel, T. Shaw, G.J. Martyna, D.M. Newns et al, in preparation (2014).

Electrostatic gating of oxide-based two dimensional electron gases (2DEG) is an exciting pursuit, given the wealth of novel phenomena recently discovered in these systems. A particularly challenging aspect is the necessity to control extremely large charge carrier densities: an interface, such as RTiO₃/SrTiO₃, with a polar discontinuity contains 3middot;10¹⁴ cm^-2 electrons. This requires very high-k gate dielectrics with permittivities (ε_r) above 100. SrTiO₃ has a bulk ε_r of 300, which can be increased above 1000 by epitaxial strain or by alloying with Ba. SrTiO₃ thin film structures exhibit, however, severely reduced ε_r due to a combination of interface layers, suppression by electric fields, and sensitivity to structural defects. Moreover, structures that incorporate these 2DEGs with ferroelectric BaTiO₃ may exhibit negative capacitance effects, investigated for decreasing sub-threshold voltage swing in field effect devices below 60 mV/decade, while at the same time providing excellent capacitance and polarization/channel carrier density matching.
Here, we present a systematic study of dielectric response of SmTiO₃/SrTiO₃/Pt structures that have a high-density 2DEG at the SmTiO₃/SrTiO₃ interface. Increasing the SrTiO₃ thickness is found to result in an increase of the effective dielectric permittivity of the gate from 27 to 372. We present a simple lumped circuit model that quantitatively explains the experimental observations and that accounts for the contributions of an interfacial layer at the Pt electrode, the electric field in the vicinity of the 2DEG, and the epitaxial strain. We also discuss the DC leakage characteristics, which are shown to be optimized around a SrTiO₃ thickness of 60 nm. Significant degradation in the low and large thickness limits is explained with direct tunneling and dislocation formation, respectively. We will discuss how this model can be used as a guideline for design of field effect devices incorporating SrTiO₃ or related insulators with very high dielectric permittivities. In particular, we will focus on strategies for maximizing charge modulation in high carrier density material systems. We will also present dielectric response data for 2DEG/insulator/ferroelectric/metal stacks, i.e. SmTiO₃/SrTiO₃/BaTiO₃/Pt, and quantitative models for the capacitance density as a function of BaTiO₃ thickness, which is a common approach to establish negative capacitance effects. It is shown that a model that accounts for all contributions discussed above is extremely important in order to distinguish true negative capacitance effects from the plethora of other factors that can give rise to a non-trivial thickness dependence of the capacitance.

Mott metal-insulator transitions have attracted considerable interest for novel switching devices as they possess unique properties such as charge gain that have implications on device properties such as scaling, cut-off frequencies, and subthreshold slopes. For such applications, the transition must be controlled with an applied electric field. In this presentation, we will discuss experimentally observed metal insulator transitions in two different thin materials systems, namely the rare earth nickelates and thin, high-electron-density SrTiO₃ quantum wells embedded in rare earth titanate Mott insulators. We show that different mechanisms can give rise or contribute to metal-insulator transitions in these systems, including disorder, film strain, interfacial effects, structural modifications and coupling to the lattice, in particular oxygen octahedral tilts. We will discuss the challenges and approaches for electric-field control of the transition, in particular the need to control very large carrier densities. We also demonstrate the effect of electric fields on modifying strong electron correlation phenomena in these materials.
This work was performed in collaboration with Evgeny Mikheev, Patrick Marshall, Santosh Raghavan, Adam Hauser, Jim Allen, Jack Zhang, Leon Balents, Junwoo Son, and Siddharth Rajan.

A new research direction in the current era of “post Si CMOS” is the pursuit of emergent quantum matters in realization of exotic quantum phenomena, thus to develop a “paradigm shift” technology in pushing computer speed and power consumption beyond current limitations. The new states of low-D quantum matters, typified by topological insulators (TI), have recently drawn unparalleled attentions worldwide due to their extraordinary physical properties and potential applications in dissipationless spintronics and quantum computing. The helical spins of the TI surface states plus the unique spin-momentum locking feature may be exploited in giving rise to a host of novel spintronic devices with much higher spin-charge conversion efficiency, crucial for effective pure spin current generation to realize spin logics and circuits in future. In light of the exciting prospect, we have recently undertaken investigations of TI thin films and heterostuctures intended for spintronic applications. High quality 3-D TI films of Bi₂Se₃ and Bi₂Te₃ were obtained by van der Waals epitxy, and the surface states displayed distinct Dirac cone features confirmed by ARPES and STS, as well as weak antilocalizations observed in low-T transport. TI/FM and TI/FI magnetic heterostructures have been fabricated, and pure spin current is generated by the dynamical spin pumping method, and detected by the inverse spin Hall effect. Very strong spin-charge conversion was observed, with a typical charge current density J_c about 3-5 times higher than those of Fe₃Si/NM and Fe₃Si/GaAs bi-layers. The remarkable enhancement of J_c in TI/FM heterostucture is attributed to strong spin-orbit coupling inherent of TIs. In addition, we also demonstrated a large electrical field effect via a back gate, paving new ways of exploiting this new quantum matter for pure spin current generation and manipulation.
*The work is done in collaboration with C. N. Wu, Y. T. Fanchiang, H. Y. Hung, H. Y. Lin, C. Y. Wang, Yuchi Liu, Dept. of Physics, National Tsing Hua University, Hsinchu; Prof. Minghwei Hong, Dept. of Physics, National Taiwan University, Taipei; Dr. Jau Yin Lin, CCMS, NTU; Dr. Shang-fan Lee, Institute of Physics, Academic Sinica, Nangkang; and Dr. T. W. Pi of NSRRC, Hsinchu, Taiwan.

Nanoelectromechanical (NEM) switches were identified by the ITRS as a low-power "beyond CMOS" technology. However, the reliability of the contact interface currently limits the commercialization of NEM switches, as the electrical contact has to be able to physically open and close up to a quadrillion (10¹⁵) times without failing due to adhesion (by sticking shut) or contamination (reducing switch conductivity). These failure mechanisms are not well understood, and materials that exhibit the needed performance have not been demonstrated. Thus, commercially viable NEM switches demand the development of novel contact materials along with efficient methods to evaluate the performance of these materials.
We are developing novel contact material candidates that are highly conductive, minimally adhesive, chemically inert, mechanically robust, and amenable to CMOS fabrication processes. One promising candidate material is platinum silicide (Pt_xSi). The controlled diffusion of thin films of amorphous silicon and platinum allowed us to tune the chemical composition of Pt_xSi over a wide range (1xSi of multiple stoichiometries in comparison with pure Pt. These experiments showed that the platinum-rich silicide phase (Pt₃Si) may be an ideal contact material for NEM switches due to its desirable combination of mechanical robustness with metal-like conductivity. We also demonstrate that Pt_xSi can be used to release NEM switches with a self-formed gap caused by interfacial separation driven by shrinkage-induced tensile stress.
To assess contact material candidates under NEM switch-like conditions, we developed a novel, high-throughput electrical contact screening method based on atomic force microscopy (AFM) that enables billions of contact cycles in laboratory timeframes. We compared the performance of self-mated and dissimilar single asperity Pt and Pt_xSi contacts under forces and environments representative of NEM switch operation and cycled up to two billion times. The contact resistance increased by up to six decades due to cycling-induced growth of insulating tribopolymer in the case of Pt-Pt contacts whereas Pt_xSi exhibited reduced tribopolymer formation. Additionally, we found that the original conductivity can be recovered by sliding of the contact, which essentially leads to the displacement of the tribopolymer thus suggesting a route for mitigating contamination-induced failure.

The Boltzmann distribution of electrons poses a fundamental barrier to lowering energy dissipation in conventional electronics, often termed as Boltzmann Tyranny[1-5]. By replacing the gate insulator with a negative capacitance oxide in a field effect transistor, the subthreshold swing can be reduced below the fundamental physical limit of 60 mV/dec, thereby overcoming the tyranny[1]. In this talk, we will discuss the design methodology of ferroelectric (FE) negative capacitance FETs (NCFETs) based on the concept of capacitance matching[6,7]. In the first part of the talk, we will compare different device structures, namely bulk, SOI and double gate FinFET and discuss how a hysteresis free operation of NCFET can be obtained. We will shed light on the beneficial effects of the overlap capacitances for capacitance matching.
In the second part of the talk, we will focus on the choice of ferroelectric materials that could lead to an ideal capacitance matching in a NCFET structure. We have recently reported a direct measurement of negative capacitance in a thin, single crystalline ferroelectric film of Pb(Zr_0.2Ti_0.8)O₃, by constructing a simple R-C network and monitoring the voltage dynamics across the ferroelectric capacitor[8]. Furthermore, a number of negative capacitance materials have been identified [9-11] and sub-60 mV/dec transistors employing the negative capacitance effect have been reported [12-14]. Based on these experimental reports, we will discuss material exploration and the possibility of designer ferroelectrics for NCFETs.
References:
1. Salahuddin, S., Datta & S. Nano Lett. 8, 405-410 (2008).
2. Zhirnov, V. V. & Cavin, R. K. Nature Nanotechnology3, 77-78 (2008).
3. Theis, T. N. & Solomon, P. M. Science327, 1600-1601 (2010).
4.Theis, T. N. & Solomon, P. M. Proc. IEEE98, 2005-2014 (2010).
5. Ionescu, A. M. & Riel, H. Nature479, 329-337 (2011).
6. Yueng, C. W., Khan, A. I., Salahuddin, S & Hu, C. Proc. VLSI Tech. Symp 2013.
7. Khan, A. I., Yeung, C., Hu, C & Salahuddin, S. Proc. Intl. Electron Devices Meeting(IEDM), 2011.
8. Khan, A. I., Chatterjee K., Wang B., Drapcho, S., You, L., Rayan, C., Bakaul, S. R., Ramesh, R. & Salahuddin, S. Nature Materials (accepted).
9. Khan, A. I. et al. Appl. Phys. Lett. 99, 113501-3 (2011).
10. Appleby, D. J. et al.Nano Lett.14, 3864-3868 (2014).
11. Gao, W. et al. Nano Lett. 14, 5814-5819 (2014).
12. Rusu, A., Salvatore, G. A., Jiménez, D., Ionescu, A. M. Proc. Intl. Electron Devices Meeting (IEDM), 2010.
13. Then, H. W. et al. Proc. Intl. Electron Devices Meeting (IEDM), 2013.
14. Cheng, C. H. and Chin, A. IEEE Electron Dev. Lett. 35, 274 (2014).

Tunnel field effect transistors (TFETs) have generated much interest in the pursuit of energy-efficient electronics due to their potential to surpass the classical subthreshold-slope limit of 60 mV/decade, allowing them to switch at much lower voltages. Heterojunctions with a broken gap (type-III) or a small staggered gap (type-II) have become promising candidates for TFETs because they are predicted to provide steep subthreshold slopes limited only by the steepness of the band-edges of the material, while providing enough current for high speed operation. However, experimental results to date have not demonstrated subthreshold swings that are steeper than the classical limit. To solve this, it is necessary to understand how sharp the band-edges can be in such materials in the presence of realistic imperfections.
We have studied this for some of the most commonly proposed materials systems: InAs/GaSb (type-III) and InGaAs/GaAsSb (type-II), which we have grown via MOCVD. Two-terminal measurements are used to reveal the steepness of the band-edges and to predict an ideal subthreshold slope that is intrinsic to the material interface. We find that these interfaces are prone to the formation of misfit dislocations due to strain buildup of intermixed compositions. I-V measurements show that these dislocations, along with point defects, result in less sharp band-edges and poorer predicted subthreshold swings. We propose that point-defects gettered by dislocations lead to defect states near the band edge that lower steepness, as well as strain fields and charge that cause band alignment to change across the interface. We have identified techniques to control these defect densities, including growing the III-Sb layer at the top to prevent As-Sb swap, purposely straining III-Sb layers, and lowering growth temperature near the interface to suppress intermixing. We have also employed annealing to allow lower and/or more uniform point defect concentrations and more uniform intermixing. We show that this can obtain considerably improved steepness.
Low temperature measurements reveal that steepness is not a function of temperature, even in devices that show no observable defects in cross-section TEM, indicating that in all cases, the sharpness of tunneling is limited by materials defects and inhomogeneity. Furthermore, our temperature-independence in two-terminal measurements indicate that most published TFET devices, which show a strong temperature dependence of subthreshold slope, are likely overpowered by thermally-activated parasitic effects originating from the gate oxide and channel. Our results indicate that the design of TFETs need to be modified to mitigate such parasitic effects. Furthermore, even in the absence of such parasitics, the material quality likely limits the ultimate performance of band-edge switching in TFETs, and further control of materials or a change in design is required in order to perform better than the classical limit.

The heterovalent ZnTe/InAs junction has a straddling band alignment with a conduction band discontinuity of 1.65 eV and a valence band offset of 0.26 eV. This alignment is appealing for the gate stack of an InAs-channel metal-oxide semiconductor field-effect transistor (MOSFET) and for the InAs-channel tunnel FET. Researchers have demonstrated bulk ZnTe/InAs heterojunction grown epitaxially and showed preliminary transport properties. However there are few reports of current-voltage and capacitance-voltage measurements for heterojunction between thin ZnTe layers and InAs. Also data is lacking to make an assessment of this heterojunction and the use of it in MOS gate stacks. This paper provides the first physical and electrical characterization of thin ZnTe/InAs and ZnTe/InAs MOS structures grown by molecular beam epitaxy (MBE). To study the transport and interface properties, thin ZnTe layers with thicknesses ranging from 2 to 15 nm were grown on InAs substrates. Cross-sectional transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) were used for interface inspection and analysis. TEM and STEM confirmed the layer thicknesses of ZnTe/InAs interfaces, which were found to be single-crystal and flat with RMS roughness less than 0.4 nm. The TEM/STEM analysis shows that ALD of Al₂O₃ consumes ZnTe during the deposition. ZnTe/InAs diode structures as well as HfO₂/Al₂O₃/ZnTe/InAs capacitor structures were fabricated and tested. Current-voltage (I-V) measurements were performed on metal/ZnTe/InAs structures versus temperature from 77 to 400 K. From the temperature dependence and the electric field-dependence of the I-V characteristic, the transport mechanisms in these heterostructures have been analyzed. Frenkel-Poole conduction is found to be the dominant transport mechanism at high temperature (above -70 °C) and at a bias of 0.2 V. A dielectric bilayer of HfO₂ and Al₂O₃ was deposited in a Savannah 100 atomic layer deposition (ALD) system at 400 °C with HfO₂ and Al₂O₃ thicknesses of 4.5 nm and 2.5 nm respectively. Te cap layer was in-situ deposited to protect the interface and was removed before the ALD dielectric deposition. Addition of the HfO₂/Al₂O₃ bilayer to the ZnTe/InAs capacitor structures reduces the current density from around 1 µA/mu;m² to less than 1×10^-6 µA/mu;m² at 1 V, and makes capacitance-voltage (C-V) measurements possible. Based on the C-V results, the density of interface traps (D_it) was extracted for HfO₂/Al₂O₃/ZnTe/InAs structures using the conductance method. In the best case, a D_it of approximately 1×10¹¹ cm^-2eV^-1 was obtained. As a control the HfO₂/Al₂O₃ bilayer was also grown on InAs with 0 nm ZnTe (consumed from 2 nm ZnTe during ALD process). This heterostructure showed a higher D_it, 8×10¹¹ cm^-2eV^-1, reducing to 4×10¹¹ cm^-2eV^-1 after forming gas annealing at 350 °C for 30 minutes. These D_it values are comparable to the best values reported for In(Ga)As channel devices.

With the introduction of new memory concepts such as resistive switches [1,2] and 3D architectures as 3D-NAND [3], the characterization of the conduction paths in such 3D nano-sized volumes is becoming of paramount importance. Whereas standard approaches are primarily 2D, we present in this work conductive atomic force microscopy (C-AFM) tomography as a concept for three-dimensional characterization with nm spatial resolution [4]. C-AFM is based on a 2D contact-mode AFM using a (biased) conductive tip and a current amplifier in series to the tip. The resulting information contains the 2D-topography as well as the 2D-distribution of the conduction paths. In C-AFM tomography we extend this method to 3D by combining the high lateral-resolution conductance mapping with a controlled material removal during tip scanning. To accomplish the latter part we make use of conductive, wear-resistant diamond-tips. The hardness of diamond is exploited to physically remove (scraping) material during the scan. We slice in a controlled manner (nm steps) through the sample collecting C-AFM slices at different depths. The consecutive planar C-AFM current images are then stacked and interpolated for the formation of the 3D tomogram. In this paper we discuss its application for resistive switching devices whereby our technique enables the observation of the conductive filament in the ON and OFF states, its evolution during set/reset operations and its relation to the characteristics of the memory device. We also demonstrate the application to 3D-Nand devices, highlighting the current conduction paths depending on the process conditions. Finally we demonstrate the insight to be gained from C-AFM tomography when applied to failure analysis on memory devices.
Ref.
[1] R. Waser et al. Adv. Materials, 2009. 21: 2632.
[2] J. Zahurak et al. In IEDM Tech. Dig. 2014.
[3] H. Tanaka et al., VLSI Symp. 2007, pag. 14.
[4] U. Celano et al., Nano Lett. 2014, 14, 2401-2406.

The fabrication of high quality metallic contacts to carbon nanomaterials such as carbon nanotubes and graphene is challenging. There are several compatibility issues between conventional lithography and carbon nanomaterials. For example, the use of resist coatings which are very hard (if not impossible) to remove during development and lift-off, resulting in poor quality contacts due to the presence of resist residue between the contacts and carbon nanomaterials. This motivates the development of a ‘bottom-up&’, direct-write, resist-free contacting method.
We developed the direct-write atomic layer deposition (ALD) technique to enable contacting carbon nanomaterials by high-quality ALD materials without the use of conventional lithography. In direct-write ALD, first a very thin seed-layer (< 0.5 nm) is deposited by Pt electron-beam induced deposition (EBID) in the shape of the desired contact pattern. Next, an area-selective Pt ALD process is used to convert the seed layer into a pure Pt contact. In this way the patterning capability of EBID is combined with the material purity of ALD to form virtually 100% pure Pt patterns (resistivity of 12 mu;Omega; cm) with a resolution down to 10 nm^[1].
Single-walled carbon nanotubes field effect transistors (CNTFETs) were fabricated using Pt direct-write ALD to deposit the contacts. The CNTFETs typically show good unipolar p-type behavior with on/off ratios of 10⁵ - 10⁶ and very low conduction in the n-type branch. Transfer characteristics of a set of ~ 30 CNTFETs show that contacts patterned by direct-write ALD are of similar quality as Pd contacts patterned by conventional techniques. This is an improvement over previous reported results on Pt contacts, which typically show low quality contacts (despite the higher work-function of Pt compared to Pd) due to a poor wetting interaction with the carbon nanomaterials.
Similarly, graphene transistors were fabricated by direct-write ALD of Pt on large-area CVD graphene. Device areas were isolated by cutting the graphene directly with a Ga focused ion beam (FIB). First results from sub-optimal devices show a very low contact resistance down to (40 ± 30) Omega; and a contact resistivity of ~240 Omega; mu;m² which indicates high quality contacts.
In summary, carbon nanotube and graphene devices were fabricated by direct-write ALD of Pt. By avoiding the use of conventional lithography and resist coatings, high quality Pt contacts were fabricated resulting in improved device performance for CNTFET devices and low contact resistance in graphene devices.
[1] A.J.M. Mackus et al., Nanoscale4, 4477 (2012)

Single-walled carbon nanotubes (SWNTs) have been widely studied for their applications in transistors and logic circuits due to their excellent electronic properties. However, as-synthesized SWNTs are mixtures of semiconducting SWNTs and metallic SWNTs, hindering their practical deployment in semiconductor-based electronics. Sorting of SWNTs by conjugated polymers (e.g. polythiophene) is of particular interest because of its simplicity, high selectivity and high-yield. Here, we demonstrated the use of high-mobility n-type (electron-transporting) polymer for sorting of high-purity semiconducting SWNTs. The high selectivity of semiconducting SWNTs with n-type polymer is confirmed by Raman spectroscopy, dielectric force spectroscopy and transistor characterizations. In addition, our selected SWNTs have large-diameters than polythiophene-sorted SWNTs and hence are more desirable for electronic applications. Furthermore, by using high-mobility n-type polymer for sorting, we achieved ambipolar SWNT transistors with enhanced electron transport in comparison to polythiophene-sorted SWNTs, even on the flexible substrate. As a result, the ambipolar transistor characteristic allows the fabrication of negated AND (NAND) and negated OR (NOR) logic circuits from the same set of transistors, without the need for doping. The use of n-type polymer for sorting semiconducting SWNTs as well as using the resulting ambipolar SWNT transistors for CMOS-like logic circuits greatly simplify the fabrication of flexible SWNT logic circuits.