Silicon carbide metal oxide semiconductor field effect transistors have enormous promise in high power and high temperature applications. However, the great promise of this technology remains somewhat limited because of materials physics problems at and very near the SiC/SiO2 boundary. Electrically active defects, interface traps and near interface traps limit device performance. The creation and/or activation of such defects when devices are operated at elevated temperature can lead to significant threshold voltage instabilities. Electron paramagnetic resonance (EPR) has the analytical power to provide fairly detailed information about the physical nature of trapping centers in semiconductors and insulators. Unfortunately, the sensitivity of conventional EPR is about 10^10 defects, a number too large to allow for the study of defects within an individual transistor. However, electrically detected magnetic resonance (EDMR) via spin dependent recombination (SDR) provides essentially all of the analytical power of conventional EPR and, in addition, specifically sensitive only to defects which directly affect device operations. SDR/EDMR sensitivity can be ten million times higher than that of conventional EPR, thus allowing sensitive measurements in single transistors. We have utilized SDR/EDMR to investigate defect centers on both the SiO2 and SiC side of the SiC/SiO2 interface. We detect silicon vacancy centers on the SiC side of the interface and a hydrogen complexed oxygen deficient silicon on the oxide side of the interface in almost all of the devices we have investigated. The densities of both defects are greatly reduced by NO anneals. We observe the creation or activation of multiple defect centers when devices are subjected to high temperature operation (between 130C and 190C). These defects involve oxide E&’ centers, likely holes trapped in oxygen vacancies, and hydrogen complexed defects of as yet unknown structure.

SiC has been widely studied for a range of applications, especially as a semiconductor for high-temperature, high-field, and high-power electronics. Understanding the oxidation mechanism is important as it controls the properties of both the oxide and the semiconductor/oxide interfaces. Much of the present understanding of thermal oxidation has been gained from extensive studies of the oxidation of Si, which produces the same oxide - SiO₂, as in SiC oxidation. For Si oxidation under normal conditions (700 to 1300°C), molecular oxygen, which is the most abundant oxygen species at the oxide/semiconductor interface due to its highest stability and largest diffusivity in SiO₂, has been identified as the oxidant.
It has been widely assumed that the oxidation of SiC at temperatures below 1200°C, as in most applications, is also dominated by molecular oxygen as in the case of Si, since the oxide is the same. However, it has not been possible to explain the oxidation data on SiC in a satisfactory way using this assumption [1,2]. For example, the diffusion-limited oxidation rate and its activation energy, which are independent of crystal-faces in Si, show strong face-dependence in SiC, and their values at the Si-face of SiC cannot be explained by the diffusion of molecular oxygen.
In this talk, we present a systematic study of the oxidation of SiC [3]. We first scrutinize the long-held perception on the nature of the active oxidant by analyzing a wide-range of available data on SiC oxidation, showing that a different mechanism must be at play. We then report results of pertinent first-principles calculations and use them to elucidate the oxidation mechanisms. We find that for the Si-face SiC, the last layer of the oxide is very tight and inhibits the incorporation of molecular oxygen at the interface, but allows atomic oxygen, resulting in an atomic oxygen mechanism despite the abundance of molecular oxygen in the oxide. This is the first example of the minority oxidant species dominating the oxidation kinetics and is in direct contrast to the prevailing assumption in the field. For the C-face SiC, we find that the interface inevitably contains a high density of defects, which can crack molecular oxygen and thus facilitate a molecular mechanism. These conclusions are checked against a range of experimental data, including the face-dependence, activation energies, growth rate, pressure dependence, and results of double- and triple-oxidation experiments. Finally, we compare SiC oxidation to Si and propose a generic rule of how interface bonding controls the oxidation mechanism [3].
References
1. I. Vickridge, J. Ganem, Y. Hoshino, and I. Trimaille, J. Phys. D 40, 6254 (2007).
2. V. Presser and K. G. Nickel, Crit. Rev. Solid State Mater. Sci. 33, 1 (2008).
3. X. Shen, B. R. Tuttle, and S. T. Pantelides, J. Appl. Phys. 114, 033522 (2013).
Acknowledgement
This work was supported by NSF under grant # DMR-0907385 and XSEDE grant # TG-DMR100022.

The reduction of the density of traps (Dit) in the SiO2/4H-SiC interfacial region allowed commercially available SiC MOSFETs recently. However, the nature of the defects responsible for the electrical degradation in the SiO2/SiC interfacial region due to thermal oxidation is still not completely understood.
Concerning SiC oxidation, a non abrupt interface between SiO2 films and SiC was revealed by nuclear reaction profiling (NRP), differently from the case of Si oxidation. Moreover, residual compounds on the SiC surface after the removal of the oxide film were observed by nuclear reaction analysis (NRA), exhibiting different properties when using Si or C face terminated substrates. These compounds were not observed in the Si case, being probably related to the presence of silicon bonded to oxygen and to carbon in different stoichiometries, named silicon oxycarbides (SiCxOy). Nevertheless, the influence of their presence in the electrical properties was not yet investigated.
In order to elucidate how these residual compounds and how the SiO2/4H-SiC interfacial region thickness, determined by NRP, influence the electrical properties of the SiC MOS structures, more investigations were necessary. In this work, we investigated the relation between these characteristics, obtained by nuclear reaction analyses, and the modification in the electrical properties induced by the thermal growth parameters oxidation time and oxygen pressure. Thus, we expected to achieve a better understanding on the SiC thermal oxidation and on the origin of the electrical defects present in the SiO2/SiC interfacial region. To achieve these goals, different subatmospheric oxygen pressures (of 18O2, enriched in the 18O isotope) and oxidation times were used to thermally grow thin Si18O2 films on 4H-SiC substrates. Samples were probed by NRA to determine the total amount of oxygen incorporated before and after the removal of the Si18O2 film by HF etching, and by NRP to determine its depth distribution. Current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed in Al/SiO2/4H-SiC MOS structures and correlated with the other results.
Although the oxidation parameters investigated affected the total amount of oxygen incorporated and the electrical degradation in MOS structures, they did not affect the amount of residual compounds after HF etching or the SiO2/4H-SiC interfacial region thickness. Such results corroborate the idea that the origin of the electrical degradation is in the interaction of SiC oxidation by-products with the SiO2 film.
Acknowledgments: The authors would like to acknowledge INCTs Namitec and Ines /MCT, CNPq/MCT, CAPES, and FAPERGS.

Nowadays, the key point of high performance and efficiency of 4H-SiC-based power MOSFETs is electrical properties of 4H-SiC/SiO2 interface. Gate oxide formation by conventional thermal oxidation in dry oxygen inevitably leads to high density of interface traps (Dit) due to carbon clusters and so-called near interface traps (NIT). This results in significant reduction of electron mobility in the channel of 4H-SiC MOSFET and low efficiency of the device. The most widely used approach of interface traps passivation is introducing of nitrogen to the 4H-SiC/SiO2 interface by using nitrous ambient (NO, N2O) either during oxidation [1] or post-oxidation annealing [2,3,4]. In this work we introduced nitrogen to the 4H-SiC/SiO2 interface by deposition of thin silicon nitride layer followed by deposition of SiO2 and subsequent over-oxidation in dry oxygen and investigated electrical properties of the resulting gate oxide. Oxidation process of the gate stack can be considered in two steps: over-oxidation of silicon nitride and subsequent oxidation of thin 4H-SiC layer. Nitrogen, released during silicon nitride oxidation, incorporates at the 4H-SiC/SiO2 interface.
We fabricated MOS devices, so-called inversion-channel MOS devices with electron source (n+ implanted rings) and lateral MOSFETs on 4H-SiC (0001) commercial wafers with p-type epilayers. Three different silicon nitride / silicon oxide gate stacks with various thickness of SiO2 layer (40, 45, 50 nm) were deposited by PECVD method in order to reveal effect of under-oxidation and over-oxidation of the silicon nitride layer on electrical characteristics of the gate dielectric and 4H-SiC/SiO2 interface. Oxidation step was done in dry O2 at 1250 C for 52 min. In addition, the devices with thermally grown gate oxide in dry O2 ambient were fabricated as a reference point for this study.
C-V, G-V, I-V and time zero dielectric breakdown (TZDB) measurements were performed on MOS and inversion-channel MOS devices. Using of inversion-channel MOS devices allows electrical characterizing of the gate oxide and 4H-SiC/SiO2 interface in inversion mode. Field effect mobility values were calculated from transfer characteristics taken on lateral MOSFETs.
We have demonstrated that nitrogen introduced at the 4H-SiC/SiO2 interface by deposition of thin silicon nitride layer effectively passivates interface traps in vicinity of conduction band edge. Increase of the field effect mobility as compared to mobility in channel of MOSFET with gate oxide grown in dry oxygen was observed.
[1] D. Okamoto et al, IEEE Electron Device Lett. 31, 710 (2010)
[2] L.K. Swanson et al, Appl. Phys. Lett. 101, 193501 (2012)
[3] H. Li et al, Appl. Phys. Lett. 70, 2028 (1997)
[4] G.Y. Chung et al, Appl. Phys. Lett. 76, 1713 (2000)

SiC power devices can handle large power and high frequency switching beyond the Si power devices. Typical full-SiC power modules are composed of both SiC-MOSFETs and SiC-SBDs to suppress the degradation of Ron of SiC-MOSFET during the bipolar reverse-current flow while there will be unfavorable consequences such as increased material cost, larger area, and larger wiring inductances. Panasonic has proposed the SiC-DioMOS which successfully integrates the unipolar reverse diode without any increase of chip size from the original DIMOS transistor. The SiC-DioMOS utilizes the highly-doped n-type epitaxial channel under the MOS gate for the FET channel and also for the reverse conduction path of the diode. Thickness and concentration of the highly-doped n-typed channel are carefully designed to achieve reasonable V_th of the MOSFET and Vf0 barrier constituting the diode current. The MOSFET and also the MOS-channel diode completely operate under unipolar mode. The SiC-DioMOS with BV_ds =1700V, Ron=20mOmega;#12289;V_th=4.5V, V_f0=0.8V is successively fabricated using the state-of-the-art epitaxial-growth technique. Fast switching of t_r=58ns and t_f=13ns is confirmed. The SiC-DioMOS meets practical standards for safety operation of high-power fast switching without SiC-SBD.
Even though SiC power devices verify adequate power-electronics performance, they include a lot of defects in the active area. The electrical characteristics/reliability affected by the defects need to be understood to establish the growing SiC-power-electronics supply chain and mass production. FUPET has put steady effort to establish the Integrated Evaluation Platform (IEP) for the SiC wafers and epitaxial films under “Novel Semiconductor Power Electronics Project Realizing Low Carbon Emission Society” supported by METI and NEDO in Japan. The IEP consists of the observation-recognition system, and the electrical characteristics/reliability analyses providing the data from the TEG electrodes affected by the recognized defects. Every simple characteristics of each defect are accumulated and analyzed statistically. For example, the IEP provides the reliability TDDB-Q_bd-test affected by the defects. The Q_bd shows three discrete universal distributions (D1>D2>D3). D1 distribution with highest Q_bd is observed on the flat surface without step bunching and defects. D2 distribution with lower Q_bd, was observed on the bunched-step lines. The severe step-bunching and some of the large defects (such as down falls and triangular defects) degrade the Q_bd into the worst D3. Small defects of TSD and TED scarcely affect the Q_bd. The quantitative statistical-probability data accumulated on the IEP may enable the prior-to-fabrication evaluation of the wafers to promote the device production.

The mechanism of nitric oxide (NO) post-oxidation annealing, the most established passivation method for improving the quality of the interface between silicon carbide (SiC) and silicon oxide (SiO₂), is not yet completely understood. In the present work, ~ 65-nm SiO₂ was thermally grown at 1150^oC and 1 atm with the O₂ flow rate of 500 sccm on (000-1) carbon face (8^o-miscut) and (0001) silicon face (4^o-miscut) 4H-SiC samples. The samples then underwent the NO passivation at temperatures ranging from 1000^oC to 1175^oC at 1atm with the NO flow rate of 577 sccm for different periods of time (15-min through 360-min). X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS) were employed to reveal the nitrogen areal concentration at the SiC/SiO₂ interface. Prior to XPS the oxides were etched in ~7% HF, and previous measurements have shown that the etch does not remove the interfacial nitrogen. Nitrogen areal concentrations versus time at different temperatures on both faces were analyzed using first-order kinetics models, including a term that allowed for the oxygen induced loss of nitrogen. Surprisingly inclusion of nitrogen loss led to unphysical results (negative activation energies) and was not included in the final analysis. Using a simple first-order up-take model, the activation energies for nitrogen incorporation, 3.2eV on silicon-face and 1.8eV on carbon-face, were extracted. These values are close to the activation energies extracted from Deal-Grove-like analyses of the oxidation process. Comparison of the nitrogen up-take rates with oxidation rates from previous reports on both faces also demonstrates that nitrogen incorporation is closely related to the oxidation process. These results provide new insights of the nitrogen inclusion process and its quantification. In particular, the results suggest that simultaneous oxidation and nitridation is critical for the nitrogen induced improvement of the SiC/SiO₂ inversion channel mobility.

SiC MOS devices are expected to play a leading role in next generation power MOSFETs due to their large bandgap and high thermal conductivity. Oxide-SiC interface trap passivation using nitric oxide (NO) annealing has been critical for commercially viable SiC MOSFETs. Even with NO passivation, the mobility is limited [1]. Introduction of phosphorus (P) at the interface both passivates traps and counter-dopes at the interface [2], and has shown a greater increase in field effect mobility than nitrogen, but it is unstable under biased temperature stress conditions [3]. In this work, Antimony (Sb), from the same periodic column as nitrogen and phosphorus, is examined for similar passivation and counter doping effects.
This presentation will focus on processes and results using Sb counter doped implanted-channel 4H-SiC lateral MOSFETs. Sb is implanted into SiC before thermal oxidation. After implantation, the sample is annealed at 1550°C for dopant activation (Sb as well as N source-drain implants). Then, the gate oxide is grown. Mo is sputter deposited for the gate metal. Sputtered Ni is employed for the source and drain contacts followed by an 800°C ohmic contact formation anneal. Companion MOS capacitors are processed alongside the MOSFETs. A second Sb sample is processed using the above procedure, except that it experienced an additional annealing in NO after the gate oxide growth (Sb+NO).
Extremely promising results have been obtained using both processes. Peak channel field effect mobilities for Sb and Sb+NO devices are 80cm²V^-1s^-1 with a positive threshold voltage, which is a significant improvement over the standard NO process. Mobilities decrease for both processes at higher oxide electric fields, but the Sb+NO mobility remains substantially higher (~50 cm² V^-1 s^-1) than the Sb only and the standard NO mobility at all applied fields up to 2.5MV/cm. Temperature dependence suggests that the mobility improvement is due to a surface counter doping mechanism for the ‘Sb only&’ process. The additional improvement due to NO may be attributed to interface and near-interface trap passivation. Preliminary results indicate neither short-term instability nor gate reliability problems, as opposed to P passivation, which is extremely exciting. These preliminary results are very promising for application to next-generation SiC power MOSFETs and other MOS devices. This presentation will discuss these results in detail in the context of current state-of-the-art SiC oxide processing methods.
[1] S. Dhar, L. C. Feldman, K. C. Chang, Y. Cao, L. M. Porter, J. Bentley, J. R. Williams, J. Appl. Phys. 97, 074902 (2005).
[2] G. Liu, A. C. Ahyi, Y. Xu, T. Isaacs-Smith, Y. K. Sharma, J. R. Williams, L. C. Feldman, S. Dhar, Electron Device Lett., 34, 181 (2013).
[3] Y. K. Sharma, A. C. Ahyi, T. Isaac-Smith, A. Modic, M. Park, Y. Xu, E. L. Garfunkel, S. Dhar, L. C. Feldman, J. R. Williams, Electron Device Lett., 34, 2 (2013).

Silicon carbide (SiC) MOSFETs show great promise in high power and high temperature applications. SiC MOSFET technology has been limited in part by electrically active defects at or very near to the SiC/SiO2 interface. Previously, our group has studied the 4H SiC/SiO2 interface via electrically detected magnetic resonance (EDMR) at X band (~9.5 GHz) and found a ubiquitous performance limiting defect in nMOSFETs, the silicon vacancy [1,2]. We have extended our earlier EDMR measurements from original room temperature X band studies to include: (a) elevated temperatures, up to 190C and (b) various EDMR frequencies from 220 MHz to 16 GHz. We have also greatly extended the range of devices explored from lateral n-MOSFETs to include lateral pMOSFETs and n-DMOSFETs. Our new measurements demonstrate that multiple defects play important roles in device performance and show that elevated temperature creates or activates new defect centers. Our results also suggest that SiC/SiO2 interface disorder may contribute to low effective channel mobilities, at least in pMOSFETs. Both n- and p- LMOSFET EDMR spectra are dominated by a relatively narrow isotropic line with a g asymp; 2.0028, due to the silicon vacancy, however, new measurements show additional strong side peak structure in the p-LMOSFETs and multiple changes in the spectra at elevated temperature. Utilizing low-frequency EDMR (350 MHz), we clearly resolve two strong isotropic side peaks separated by about 11 Gauss. We attribute these side peaks to a hydrogen-complexed E-prime defect called the 10.4 Gauss doublet; likely a hole trapped in an oxygen vacancy [3]. NO anneals, in all cases surveyed, greatly reduced the 10.4 Gauss doublet EDMR signal and the silicon vacancy signal. However, a reduction in their number does not coincide with an improvement in pMOSFET mobilities. This result is very different from the case of nMOSFETs. In nMOSFETs, the NO anneal consistently reduces the interface-sensitive EDMR silicon vacancy signal and 10.4 Gauss doublet signal by more than an order of magnitude and increases the nMOSFET effective channel mobility by more than one order of magnitude. In pMOSFETs, the NO anneal reduces the EDMR response by a factor of about 30 for both defects, but increases the mobility only by a factor of 1.1. Our variable frequency EDMR measurements may provide insight into this surprising result. One possible cause of low channel mobility in pMOSFETs could be disorder at the SiC/SiO2 interface region. Disorder within a crystal will introduce a frequency dependent spectrum broadening on the g-tensor. We compare EDMR measurements made at X band and low-field and consistently observe a large change in line width, almost certainly a direct measure of disorder on the SiC side of the SiC/SiO2 interface.
[1] C.J. Cochrane, et al., Appl. Phys. Lett. 102, 193507 (2013)
[2] C.J. Cochrane, et al., Appl. Phys. Lett. 100, 023509 (2012)
[3] P.M. Lenahan and J.F. Conley, Appl. Phys. Lett. 62, 40 (1993)

An overview will be given of the progress in developing the CH₃Cl-based technique for the regular-temperature and low-temperature (down and below 1300°C) epitaxial growth of 4H-SiC. The interest in using a chloro-carbon precursor instead of the traditional hydrocarbons was dictated by (1) a desire to find an alternative to HCl or SiH_xCl_y for bringing Cl in the system to fight homogeneous nucleation of Si in the gas phase and (2) an expectation that intermediate Cl-containing products of chloro-carbon decomposition may be significantly different compared to other precursor systems, which would enable more favorable surface reactions.
When CH₃Cl was used in combination with SiH₄, the supply of Cl from the CH₃Cl precursor was insufficient to significantly suppress homogeneous nucleation both in the 1600-1700°C temperature range and at low temperatures. Even at the optimized growth conditions, specular epilayer surface morphology could be achieved with the growth rate of no more than 2.5-3 mu;m/h at 1300°C. It was expected that by solving the problem of the homogeneous nucleation, the full potential of the chloro-carbon precursors could be explored. The straightforward approach was to supplement the chloro-carbon precursor with HCl or use chloro-silane precursor instead of SiH₄.
At 1500-1600°C, the use of the CH₃Cl+SiCl₄ precursor system brought improvements qualitatively similar to those obtained with some other chlorinated precursor systems - complete suppression of the homogeneous nucleation and ability to achieve growth rates above 100 mu;m/h. However, noticeable advantages of this precursor system compared to HCl-assisted growth as well as various chlorinated-silicon precursors have been revealed.
The role of CH₃Cl in providing improvement mechanisms at 1300°C beyond partial suppression of the homogeneous nucleation in the gas phase was investigated. The CH₃Cl and C₃H₈ precursors, with SiCl₄ as the silicon precursor in both cases, were compared. The main evidence of the superiority of CH₃Cl was in a much wider C/Si window for the degradation-free growth. The differences between the chloro-carbon and hydro-carbon growth could not be explained using a thermodynamic analysis of the stability of the condensed phase. The improvement was attributed to the surface reaction kinetics, different surface diffusivities and different sticking coefficients of the dominating products of the chloro-carbon decomposition. The effect of increasing Cl/Si ratio in the CH₃Cl+SiCl₄ growth at 1300°C (by adding HCl) was also investigated.
A few important steps taken towards device applications will be reviewed, including (1) heavy N₂ and Al doping, (2) semi-insulating behavior via in-situ vanadium doping, (3) low-temperature selective epitaxial growth and (4) growth of high-purity drift regions by conducting the low-temperature growth at further reduced pressure.

In this study we focused on the development of a chlorinated epitaxial growth process to meet the requirements on material quality and process efficiency/reproducibility of 4H-SiC epi material. The main emphasis has been on obtaining device quality 100 µm thick epilayers with a smooth surface and low defect density while maintaining a high growth rate of 100 µm/h on 4-degree off-cut 4H-SiC 4-inch diameter wafers. Further investigations of the epilayers were made to study the influence of growth parameters on in-grown stacking faults, surface morphological defects such as surface step-bunching, triangular defects and ratio of basal plane dislocation conversion into threading edge dislocations.
A hot-wall CVD reactor with gas foil wafer rotation and TaC coated graphite susceptor was used for the growth process. Trichlorosilane (SiHCl3) and propane (C3H8) were used as source gases together with hydrogen as carrier gas. The growth was performed in the temperature range of 1580-1670 C at 100 mbar pressure, C/Si ratio = 0.8-1.2 Cl/Si ratio = 3-5 and Si/H2 = 0.038-0.45%. In-situ surface preparation of the substrates was performed during the temperature ramp up and for 10 min at the growth temperature using a flow of 200 ml of HCl.
Silicon evaporation from the susceptor during temperature ramp up and substrate surface preparation shows negative affect on the quality of epilayer and significantly enhances the surface roughness and density of epitaxial defects. A linear increase in growth rate with increasing Si/H ratio is observed until 80 µm/h. However, further increase in the flow rate of source gases results in the formation of high density of defects together with Si-droplets and no further increase in the growth rate. In order to dissolve Si droplets additional Cl was added into the growth process in the form of HCl. An optimized Cl/Si ratio of 5 enhanced the growth rate to 102 µm/h. Growth conditions were optimized to obtain smooth surface without surface step-bunching and low surface defect density at a growth rate of 100 µm/h. Reproducibility of the growth process regarding the growth rate (100 µm/h), controlled n-type doping (3 x 1015 cm-3), surface roughness (< 1 nm) and surface defect density (< 1 cm2) was checked for 10 growth runs. 100 µm thick epilayers were grown with controlled doping of 3 x 1015 cm-3 at a growth rate of 100 µm/h during 1h growth. Basal plane dislocaiton conversion ratio during growth was estimated using a combination of KOH etching and polishing together with counting of basal plane dislocations related etch pits in the epilayer and substrate using optical maping. A high conversion efficiency (>99%) is observed in 4-degree off-cut grown epilayers. Further enhancement was achieved through optimization of starting growth conditions. Detailed investigations of the influence of in-situ substrate surface preparation and growth rate on conversion rate will be presented.

The performance of commercially available silicon carbide (SiC) power devices is limited due to inherently high density of screw dislocations which are necessary for maintaining polytype during boule growth and to obtain commercially viable growth rates. Researchers at NASA Glenn Research Center have recently proposed a new bulk growth process based on axial fiber growth followed by lateral expansion for producing SiC boules with potentially as few as one screw dislocations (SD) per wafer [1]. To implement this novel growth technique, the lateral homoepitaxial growth expansion of a SiC fiber without introducing a significant number of additional defects is critical. At NASA Glenn Research Center, lateral growth expansion is being investigated by lateral growth of 4H/6H-SiC a/m-plane ‘pseudo-fiber&’ crystals (0.8mm x 0.5mm x 15mm) in a hot wall chemical vapor deposition (HWCVD) system [2]. The post-growth crystals exhibit hexagonal morphology with approximately 1500 mu;m of total lateral expansion. Preliminary analysis by synchrotron white beam x-ray topography (SWBXT) confirms that the lateral growth was homoepitaxial, matching the polytype of the respective underlying region of the pseudo-fiber seed [2]. Axial and transverse sections from the samples were characterized in detail using a combination of SWBXT, TEM and Raman spectroscopy to map defect types and distribution. X-ray diffraction analysis indicates the initial pseudo-fiber crystals contained stacking disorders and this appears to have been reproduced in the lateral growth sections. Analysis of the relative intensity for folded transverse acoustic (FTA) and optical (FTO) modes on the Raman spectra indicate the existence of stacking faults. Further, the density of stacking faults is higher in the pseudo-fiber crystal than in the lateral-grown material. Bundles of dislocations are observed propagating from the pseudo-fiber in m-axis lateral directions. g.b analysis reveals these are edge type basal plane dislocations that track the growth direction. Further analysis of the stacking faults to determine the stacking fault vectors are currently being carried out using HRTEM and the results will be correlated with SWBXT and Raman results. The implications of these results for implementing the novel growth process will be discussed.
References
[1] US Patent 7,449,065
[2] A. G. Trunek, et al, MATERIALS SCIENCE FORUM (2012), 717-720 (Pt. 1, Silicon Carbide and Related Materials 2011), 33-36.
Acknowledgement
Samples provided by NASA Glenn Research Center (collaborators: Andrew J. Trunek, Andrew A. Woodworth, Philip G. Neudeck and David J. Spry).

Minimizing defect density in 4H-SiC bulk crystal is a key issue to improve the performance of power devices designed on 4H-SiC substrate. Generally speaking, defects reaching the growth surface will extend into the homoepitaxial layer during epitaxy growth, potentially impacting device performance. In our previous studies [1-3], four kinds of stacking faults in the bulk crystal have been distinguished based on their contrast behavior differences in the images of synchrotron white beam x-ray topography. These faults are Shockley fault, Frank fault, Shockley plus c/2 Frank fault, and Shockley plus c/4 Frank fault. Our proposed formation mechanisms of these stacking faults involve the overgrowth of the surface outcrop associated with threading screw dislocations (TSDs) or threading mixed dislocations (TMDs) with Burgers vector of c+a by macrosteps and the consequent deflection of TSDs or TMDs onto the basal plane. Previous observations were made in horizontally cut wafers with transmission geometry setting of synchrotron x-ray topography. In this paper, further evidences are reported to confirm the proposed stacking fault mechanism. Observations are made in vertically cut slices with surface plane of {11-20} type. Several kinds of stacking faults are recognized and their contrast behavior agrees with those four kinds of stacking faults reported before. Direct observation is obtained of Shockley plus c/4 Frank stacking fault nucleating from the deflected TMD on the basal plane. The contrast from stacking faults on the basal plane in the axial slice is recorded with a tilted angel of the axis perpendicular to both the direction of incident beam and the axis of Brag angle. With this method of imaging, 3D information of the defect distribution in the crystal can be built.

Continuous progress in quality and cost effectiveness in 4H SiC epitaxy has facilitated the penetration of SiC based devices in the power electronics market. In order for the SiC technology to reach the next level of maturity, substantial improvement in the epitaxy defect density is crucial. Various types of defects have been observed in SiC epilayers, such as triangles, short-lines, or pits. These defects can form due to non-optimized epitaxy process or as a result of interaction between the epitaxy process and the substrate surface condition. Disregarding shape and origin, the epitaxy defects can negatively impact device performance and reliability. The presented work investigates the factors that impact the defect formation in epitaxy, with the purpose of finding paths to defect reduction in SiC epitaxy. The epitaxy process is conducted in a 10x100mm planetary CVD reactor scalable to 6x150mm capacity. The substrates are 100mm or 150mm 4° off-axis 4H SiC Si-face. The epitaxy defect density has been reduced to below 1cm-2, as a result of: a). continuously improved substrate quality; b). improved substrate surface polish and clean; c): improved epitaxy procedure. As the substrate quality is a critically enabling factor in epitaxy defect reduction, the first part of the paper will describe our continuous efforts in improving the crystal quality in 100mm and 150mm substrates. The dislocation density in the 100mm substrates has steadily decreased with current levels at ~ 102 cm-2 for TSD, ~ 103 cm-2 for TED and ~ 102 cm-2 for BPD. The approach of the 150mm substrate development is to leverage the learning from the 100mm crystal growth and to obtain high crystal quality from the start. The main part of this paper will present extensive investigation on the remaining defects still observed in the epilayers. One of these defects appears as short lines along certain crystallographic orientations, also known as V or Y defects [1]. If present, most of these defects are observed within 10mm of wafer edges, but a small number of them can also form at the wafer center. These short lines are associated with the partials of a stacking fault and can originate either from a TSD in the substrate or through the nucleation of a TSD at the epitaxy start [1,2]. Molten KOH etch and X-ray topography are utilized to understand the defect formation mechanism. The results of this investigation are expected to have a wider implication as it relates to understanding the dislocation behavior as they enter from the substrate into the epilayer.
[1] H. Wang, etc., invited poster, ICSCRM2013
[2] H. Tsuchida, etc., Journal of Crystal Growth 310 (2008), p.757

Silicon carbide is a material of interest for high-voltage and high-power switching device applications. Basal plane dislocations (BPDs) are a major concern for SiC bipolar devices as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes [1, 2]. Many researchers have investigated methods to reduce the BPD density by experimenting with pre-growth treatments [3-5], substrate orientation [6], growth parameters [6, 7] and growth interrupts [8]. This work investigates extended defects, morphology and lifetime in SiC epilayers grown on substrates offcut 2° toward the [11-20].
Epilayers were grown on 2° offcut substrates in a horizontal hot-wall reactor using the standard chemistry of silane (2% in H2) and propane. Hydrogen etching was conducted to determine the morphology of the substrate during the ramp to growth temperature, where the temperatures explored were 1400, 1450 and 1500 °C. Epilayers were grown at various growth rates of 1, 5 and 10 µm/hr. All other growth parameters were maintained at T = 1620 °C, P = 100 mbar and C/Si = 1.55. Some samples were grown with a 5 µm highly doped n+ buffer layer using ultra high purity nitrogen prior to low doped epilayers. Ultraviolet photoluminescence (UVPL) imaging was used to identify BPDs in the low doped epilayers. Time resolved photoluminescence measurements were performed to determine minority carrier lifetimes of the layers and Raman spectroscopy was used to analyze polytype inclusions. Surface roughness was measured by atomic force microscopy and the morphology was also characterized using Nomarski microscopy.
No step bunching was found when the temperature was raised to 1400 °C in H2 and cooled down immediately. However, intermittent step bunching formed when the temperature was raised to 1500 °C. When a 15 µm epilayer was introduced without a buffer layer, step bunching was observed and the surface roughness was 6.0 nm RMS. For comparison, a standard 4° offcut sample typically has 3.0 nm RMS for a 20 µm epilayer. Using UVPL, it was found that after 4 µm of epi, 90% of the BPDs had converted in the low doped layer as compared to 70% in a 4° offcut sample, indicating the conversion is faster in the lower offcut material. 3C-SiC inclusions were present in the epilayers and verified using Raman spectroscopy. Results of using a buffer layer to reduce BPDs and the resulting carrier lifetime of the epilayers will also be reported.

[1] J.P. Bergman, et al. Mater. Sci. Forum Vol. 353-356, 299 (2001).
[2] R.E. Stahlbush, et al., J. Electron. Mater. 31, 370 (2002).
[3] Z. Zhang, et al., Appl. Phys. Lett. 89, 081910 (2006).
[4] J.J. Sumakeris, et al., Mater. Sci. Forum 527-529, 529 (2006).
[5] H. Tsuchida, et al., Mater. Sci. Forum 483-485, 97 (2005).
[6] W. Chen and M.A. Capano J. Appl. Phys. 98, 114907 (2005).
[7] T. Ohno, et al., J. Cryst. Growth 271, 1 (2004).
[8] R. E. Stahlbush, et al., Jr., Appl. Phys. Lett. 94, 041916 (2009).

Silicon Carbide (SiC) has attracted much interest in power devices because of its outstanding material properties. SiC wafers with high quality and large diameter are required to accomplish the wide use of SiC devices. The control of internal stress in the crystal is one of the key technologies for growing high quality and large SiC crystals. The micro-Raman spectroscopy is considered to be an effective method to evaluate the internal stress of SiC crystal. The phonon deformation induced by the strain results in the shift of Raman spectrum. A liner correlation is shown between strain and frequency shift in the Raman spectrum. Previous works revealed the correlation between the stress and Raman shift on (0001) face of 6H-SiC crystal [1]. However, few experiments have been reported on 4H-SiC crystal. We investigated the correlations in 4H-SiC crystal and those on the other crystal face than (0001) face.
We prepared rod specimens of 4H- and 6H-SiC crystals with the size of 5mm×5mm×45mm. The rods were shaped with (0001) and (11-20) faces of SiC crystal. Uniaxial stress was applied to the specimen by four point bending test under measuring the micro-Raman spectroscopy. A strain gage was attached at the side of specimen to determine the stress at the point of measuring the Raman shift. The backscattering configuration micro-Raman system was employed in the present experiments. The 514.5nm argon laser beam was focused on the specimen to a spot size of 1 mu;m. The Raman shift was measured 5 times at every stress stage in order to estimate the co-efficient accurately. We calculated the stress from the strain gage assuming that the Young&’s modulus of SiC crystal was 450GPa. The experiment was performed on both (0001) and (11-20) faces of 4H- and 6H-SiC crystals.
We determined the co-efficient between uniaxial stress and Raman shift in SiC crystals.
The results on 4H-SiC crystal were described as follows,
on (0001) : Δnu;(cm-1)= -1.96×σ(GPa) for FTO(2/4)E2 around 777cm-1
on (11-20) : Δnu;(cm-1)= -2.08×σ(GPa) for FTO(2/4)E2 around 777cm-1
where Δnu;is the increase of frequency shift of Raman spectrum andσis the positive tensile stress.
The correlations on 6H-SiC crystal were also evaluated.
on (0001) : Δnu;(cm-1)= -2.70×σ(GPa) for FTO(2/6)E2 around 788cm-1
on (11-20) : Δnu;(cm-1)= -1.30×σ(GPa) for FTO(2/6)E2 around 788cm-1
We revealed the correlation of stress in SiC crystal and frequency shift in micro-Raman spectroscopy in this study. These results made it possible to evaluate the internal stress in 4H- and 6H-SiC crystals on (0001) and (11-20) faces quantitatively.
Acknowledgements: This work is supported by Novel Semiconductor Power Electronics Project Realizing Low Carbon Emission Society under METI / NEDO. We wish to thank Toray Research Center, Inc. for experimental support and valuable discussion.
[1] J. Liu and Y. K. Vohra, Physical Review Letters 72, 4105 (1994)

Currently, a 4° off-angle is the standard for 4H-SiC substrates. Off-angles produce anisotropy in devices such as trench metal-oxide-semiconductor field-effect transistors. If an epitaxial layer is grown on a substrate with a large off-angle, the trench side wall characteristics differ toward the off-direction, generating anisotropy of the channel mobility. A larger off-angle also reduces the number of wafers that can be sliced from a single ingot, especially in cases of large-diameter wafer fabrication. Thus, developing growth techniques for SiC homoepitaxial films on large diameter (>150 mm) 4H-SiC substrates with smaller (<4°) off-angles is essential. In this study, growth parameter effects in the growth of SiC epitaxial layers on 2° -off 4H-SiC (0001) wafers were investigated. The substrate used in this study was n-type (0001) 4H-SiC with a 2° off-cut toward <11-20>. N-doped SiC layers were grown on the substrates using a multiple-wafer (3 × 150 mm-diameter) horizontal low-pressure hot-wall chemical vapor deposition system. Two wafers (diameter: 76.2 mm) were aligned in a pocket (diameter: 150 mm) to cover the radial direction of a rotating wafer plate holder. Monosilane and propane were used as precursor gases in a hydrogen atmosphere. The surface morphology of the epilayer was observed with an inspection system using confocal optics with differential interference contrast. Epilayer thickness and carrier concentration were measured by conventional Fourier transform infrared spectroscopy and a mercury probe C-V method, respectively. In this study, we focused on growth conditions with higher growth temperatures and lower C/Si ratios than the conditions in our previous report (Tamura et al., ICSCRM 2013, We-P-4), in order to achieve a smoother surface, fewer surface defects, and better uniformity over the entire equivalent wafer area (150 mm) with good reproducibility. It was found that the C/Si ratio and temperature were the major parameters for suppressing extensive step bunching as well as for reducing the defect density. By increasing the temperature above 1710 °C, the surface became prone for generating extensive step bunching. By controlling growth temperatures to be as high as 1680 °C and reducing the C/Si ratio to be less than 0.9, extensive step bunching was suppressed and a smooth epi surface was obtained over the entire wafer. The surface triangle defect density was found to decrease from >10 cm^minus;2 to 0.5 cm^minus;2 by decreasing the C/Si ratio. Carrier concentration uniformity and thickness uniformity of 6.9% (sigma/mean) and 1.6% (sigma/mean), respectively, were obtained on an equivalent wafer size (150 mm), values which are suitable for practical use. Details will be presented in this conference. This work is supported by the Novel Semiconductor Power Electronics Project Realizing Low Carbon Emission Society under the New Energy and Industrial Technology Development Organization (NEDO).

A more effective n-type and p-type doping of P⁺ and Al⁺ ion implanted 4H-SiC materials, respectively, has been obtained by increasing the post-implantation annealing temperature up to 1950°C and above [1-2]. On these p-type materials ohmic contacts with specific resistance in the 10^-5 #8486;cm² range and dominated by field effect conduction have been obtained [3]. Moreover, Al⁺ implanted 4H-SiC p⁺-i-n diodes which pass from negative to positive temperature coefficient of forward current for identical implanted emitter but different post implantation process have been obtained [3]. These diodes show evidence for a defect activation in the n-type base which is dependent on the post implantation annealing process [4].
In this study, two families of P⁺ implanted vertical 6H-SiC n⁺-i-p diodes have been processed by all identical steps except the post implantation annealing: 1300°C/20min without C-cap and 1950°C/5min with C-cap. The two diode families have been characterized with static current voltage (I-V) measurements from -100 to +5V at different temperatures in the range of 25-290°C. Before the diode series resistance dominates, the I-V curves are featured by two exponential trends. At lower voltages, an ideality factor of 2 is extracted for both diode families. For increasing forward voltages the I-V curves of the two diode families show ideality factors higher than 1 and lower than 2, without passing through an ideality factor trend of 1. In particular, in this region, the 1950°C/5min diodes have an average ideality factor of 1.66 against a value of 1.44 of the 1300°C/20min ones. The more common interpretation of an ideality factor between 1 and 2 is a forward current due to equally important diffusion and recombination currents. Another possibility is the onset of an high injection condition at relatively lower voltages. In the light of past results, the 1950°C/5min emitters should have an electron density higher than the 1300°C/20min, which should favor a more intense minority carrier injection from the 1950°C/5min emitters. With increasing injected minority carriers the recombination current increases and this could account for the higher ideality factor of the 1950°C/5min diodes. Another possibility is that the post implantation annealing processes induce a status of recombination/generation center density and type in the p-type base that depends on the post implantation annealing parameters. A study of the trend of reverse current versus temperature for both the diode families should help for distinguishing between these two hypotheses. Such a study is in progress. First results show the evidence for a post-implantation-annealing dependent defect activation.
[1] R. Nipoti, et. al. , J. Electr. Mat. 41(3), 457 (2012).
[2] R. Nipoti, et. al., J. Mater. Res. 28(1), 17 (2013).
[3] R. Nipoti, et. al., IEEE Electron Dev. Lett.34, 966 (2013).
[4] U. Grossner, et al., proceeding of ICSCRM2013, Miyazachi, Sept. 29-Oct. 4, 2013 (accepted)

As a wide band gap semiconductor, silicon carbide (SiC) offers the possibility of electronic and sensing devices operating at much higher temperatures (> 600 °C) than the present-day silicon (Si) or silicon-on-insulator (SOI) technology. Bringing high temperature SiC sensors and electronics to fruition necessitates the identification of suitable contact metallizations, wherein ohmic contacts to p-type SiC have proved a greater challenge than contacts to n-type. However, simultaneous ohmic contact formation to p-type and n-type SiC has been demonstrated with tungsten-nickel alloys at 900 °C [1]. The lowest specific contact resistance (ρ_c) reported on p-type 6H-SiC was 1.5 x 10^-4 Omega;-cm² [1]. In this talk, electrical and materials characterization of tungsten-nickel contacts to p-type 4H-SiC will be discussed. Alloy compositions of 90 at.% W: 10 at.% Ni, 75 at.% W: 25 at.% Ni, and 50 at.% W: 50 at.% Ni were investigated on aluminum-doped 4H-SiC with dopant concentrations ranging from 2 x 10¹⁹ cm^-3 to 2 x 10²⁰ cm^-3. The ρ_c measurements were extracted by the transfer length method (TLM) after 1 h of annealing in argon gas at 1000 °C to 1200 °C. The most promising results were obtained from the W75:Ni25 alloy composition on SiC with a dopant concentration of 2 x 10²⁰ cm^-3 after annealing at 1100 °C; the average ρ_c from this specimen was 6.5 x 10^-6 Omega;-cm². X-ray diffraction showed different phase transformations depending on the composition of the alloys, including the formation of tungsten silicides, tungsten carbides, nickel silicides, and a ternary tungsten-nickel carbide phase. Auger electron spectroscopy (AES) depth profiles support the phase transformations observed using the microdiffractometer.
[1] Okojie R. S. et al., IEEE Electron Device Lett, Vol. 31, No. 8, pp. 791-793. August 2010.

One bottleneck for SiC mass production is the state of the art dicing technology - the mechanical blade dicing. Due to SiC material parameters like hardness and brittleness, dicing is only possible with very low feed rate in a range of approx. 2-10 mm/s and with high tool wear.
The Thermal Laser Separation (TLS) is a dicing technology based on a crack being guided through the wafer to be cut by thermally inducing a mechanical stress field inside the wafer. TLS is a two-step process comprising a first step of crack initiation done by an ablation laser with short pulses and a second step of cleaving done by laser-based heating and subsequent water spray cooling.
Fully processed 100 mm 4H-SiC JFET wafers including process control monitoring (PCM) structures inside dicing street were used to develop TLS suitable for dicing this kind of wafers. Previous experiments proved the applicability of TLS for cutting directly through back side metal layers as well as small PCM structures. However, it is not possible to separate wafers with large areas of metal on the front side of the dicing street. To ensure a reliable separation of the JFETs, the wafers were prepared using a pulsed ablation laser along the dicing streets to locally remove metal structures along the lines to be cut. In this case, an approx. 10 µm wide line was produced. TLS parameters suitable for separating SiC sample JFETs were successfully developed. TLS-diced JFETs do not show any chipping on the front side or on the back side. No delamination of back side metal occurs. TLS edges are smooth, except fracture markings, like river lines which occur due to crack propagation outside the crystallographic planes.
To evaluate the influence of the TLS process on the SiC device performance, SiC JFETs were prepared for electrical characterization: After dicing some SiC JFET chips were soldered on direct copper bonding substrates, wire-bonded and packaged. Additional, 5 devices were packaged and encapsulated with silicone gel. These assembled SiC JFETs were electrically characterized. The electrical characteristics meet the specifications and therefore demonstrate that the electrical properties of the SiC JFETs are not affected by the TLS dicing process.
With feed rates of 200 mm/s and above, TLS has the potential to significantly improve throughput for SiC dicing. The predetermined cleaving line was produced at a feed rate of approx. 50 mm/s. This feed rate will be increased during further research and development activities. There is no tool wear with the use of TLS and hence no risk of chip damage due to tool breakage which is most likely with mechanical blade dicing. Furthermore, blade wear is a major cost factor. So, with higher throughput and zero tool wear, TLS could improve productivity and reduce dicing costs compared with state of the art.
Within this paper, we demonstrated for the first time the industrial applicability of Thermal Laser Separation for fully processed 4H-SiC wafers.

Silicon carbide (SiC) has long been known as a robust semiconductor with superior properties to silicon for electronic applications. Consequently a tremendous amount of international activity has been on-going for over four decades to develop high-power solid state SiC electronics. While this activity has focused on the hexagonal polytypes of SiC, the only form that can be grown directly on Si substrates, 3C-SiC (or cubic SiC) has been researched for non-electronic applications such as MEMS and biosensors. In particular in our group we have pioneered several biomedical devices using 3C-SiC grown on Si substrates, and recently has been investigating the use of this novel material for clean energy applications. This invited paper will review nearly a decade of activity in this regard, with particular emphasis on the most promising applications: in-vivo glucose monitoring, biomedical implants for connecting the human nervous system to advanced prosthetics, and MEMS/NEMS research aimed at allowing for in-vivo diagnostic and therapeutic systems for advanced biomedical applications.

Silicon carbide (SiC) is an ideal material to meet the increasing demands of MEMS devices operation in harsh environments, including extreme temperature and pressure, intense radiation, chemicals and corrosion, etc. This is due to the superior mechanical properties and chemical inertness of SiC material. In “hybrid” SiC, with single or polycrystalline SiC film on Si substrate or SOI substrate, such as 3C-SiC, although the single-crystal SiC film can resist hostile conditions, the Si substrate and SiO2 spacer layer limit the actual range of operating conditions, and thermal expansion mismatch between SiC film and Si substrate affects the thermal coefficient of these MEMS devices. Therefore, single-crystal “all” SiC such as 4H-SiC with homoepitaxial SiC film on SiC substrate is the material of choice. It truly exploits SiC material properties, and provides MEMS devices true hardness to harsh operation conditions and capability of integrating with SiC high temperature electronic devices to realize integrated systems operating in extreme environments. In this study, 4H-SiC microactuator devices driven by electrostatic and photonic actuation were fabricated by a combination of plasma and electrochemical etching, and its dynamic characteristics related to applied voltage, ambient pressure and temperature were investigated. Feng Zhao acknowledges the support from National Science Foundation (ECCS-1307237 monitored by Anupama B. Kaul).

Epitaxial SiC films grown on silicon enable the fabrication of transducers that combine the desirable chemical/thermal stability, optoelectronic properties, and mechanical properties of silicon carbide with the simple low-cost techniques of silicon micromachining. However, residual stresses in such highly mismatched epitaxial films are a complex function of kinetic relaxation phenomena during film growth. This has led to inconsistent reports of varying tensile or compressive residual stresses which highlight the need for more accurate characterization.
We discuss the stresses present in epitaxial 3C-SiC membranes when pressurized to the point of fracture by bulge testing. The interfacial carbonization layer between SiC/Si is known to have a higher defect density, and we probe the resulting difference in fracture behavior seen by varying direction of pressurization. Furthermore, the carbonization layer is shown to be under highly compressive stresses by layer-by-layer wafer curvature characterization, revealing the presence of a stress gradient through the thickness of these membranes. In order to understand the fracture behavior in detail, we examine the stress state at fracture, which includes contributions from residual stresses, membrane stretching and bending, as well as stress concentration and film defects. While the stress gradient effect is masked during bulge testing, it is made clear in this analysis that engineering the stress gradient within epitaxial SiC films merits further study as a potential strategy for achieving increased fracture strength. Variation of the pressurizing medium (pH, aqueous salts, etc.) and application of environmental pretreatments further illustrates the capabilities of SiC membranes for MEMS technology.

Due to its exceptional stability, chemical inertness, and biocompatibility, silicon carbide (SiC) is a promising substrate material for applications in the fields of bioelectronics and biosensing. However, while advances in SiC growth and processing have paved the way for the utilization of SiC in high power and high temperature applications, only limited work has been devoted to establishing methods for the functionalization of SiC surfaces with biomolecules. In this context, nucleic acids immobilized on solid surfaces are of particular interest for many biotechnical applications such as microarrays and biosensors.

In this work, we demonstrate the controlled grafting of DNA and PNA oligonucleotides to SiC electrodes by applying a two-step functionalization procedure. First, self-assembled organophosphonate or organosilane monolayers are covalently bound to the SiC surface without introducing an oxide intermediate layer. These monolayers display a high degree of stability and are suitable for bonding single stranded oligonucleotides by using chemical conjugation techniques in a second step.
The structural and chemical properties of the nucleic acid-modified surfaces are quantitatively characterized by X-ray photoelectron spectroscopy and atomic force microscopy, revealing successful binding of both, DNA and PNA single strands to the SiC electrodes. In addition, electrochemical characterization methods are applied to study the electrical properties of the semiconductor-biomolecule interface in aqueous electrolytes. Cyclic voltammetry and frequency-dependent impedance spectroscopy measurements show that the presence of the oligonucleotides insulates the SiC substrate from the electrolyte and thereby increases the electron transfer resistance.
The results of this work demonstrate that SiC electrodes can be used to convert biological modifications into electrical signals in electrolyte solutions and that changes in the chemical and electronic behavior upon hybridization of complementary targets can be directly monitored.

A new two-fold nanosystem exploiting the simultaneous action of oxidative stress generated by self lighted photodynamic therapy1 and hyperthermia induced by radiofrequency magnetic fields2, is presented and discussed in view of possible deep cancer treatments. The nanosystem is based on SiO2/3C-SiC nanowires functionalized with tetraphenylporphyrins and superparamagnetic Fe3O4 nanoparticles3.
Fe3O4 nanoparticles (5 The best superparamagnetic properties are found for 8 nm nanoparticles which present a saturation value of the magnetic moment per unit volume of 60 emu/gr. The specific power absorption (hyperthermia) of the same nanoparticles (f=250 KHz, H=0.016 T) is around 4.3 W/g, a value which allows the cell to achieve in 1100 sec a final T >43 °C.
To verify the biocompatibility of the nanosystem, after optimizing the functional properties4,5, in-vitro tests on lung and human breast adenocarcinoma cells and human skin derma fibroblasts are carried out. The influence of concentration (0-100 mu;g/ml) and time (up to 72 hrs) on cell proliferation and death is studied. It is found that SiO2/SiC nanowires inhibit cell proliferation and induce necrosis only at concentrations >50-100 µg/ml. The Fe3O4 nanoparticles do not inhibit cell proliferation and do not induce death up to 100 mu;g/ml as well as oxidative stress up to 50 mu;g/ml.
The self lighted photodynamic effect is then tested on Lung adenocarcinoma cells after internalization of the complete nanosystem by an endocytosis process. After 72 hs from irradiation in an X-Ray radiotherapic linear accelerator at 6 Gy, the death of the 75% of cancer cells is observed6. Finally the hyperthermic effect on the same cells after the complete system internalization is also observed.
1. P. Yuzenas et al., Advanced Drug Delivery Reviews (2008) 60, 1600-1614
2. Van der Zee J., Annals of Oncology (2002) 13(8):1173-1184
3. G. Salviati et a., MRS Fall Meeting, (2012) Boston, MA Nov 25-30
4. F. Fabbri et al; Microscopy and Microanalysis (2010) 16(S2), 826-827
5. F. Fabbri et al., Nanotechnology (2010) 21 345702-345708
6. G. Salviati, EUROMAT 2013, Seville, Spain (2013) Sept 8-14

Bulk carbon nanotube (CNT) films and grapheme films form on silicon carbon (SiC) using a metal-catalyst-free thermal decomposition approach. In this work, the background vacuum pressure and temperature used in the decomposition process are varied to investigate their impact on the type and quality of carbon allotrope formed on the SiC substrate. The carbon nanostructure growth is performed using two approaches, both of which involve intense heating (1400-1700 deg C) and moderate vacuum conditions (10-2 - 10-5 Torr) without the aid of a carbon rich feed gases or metal catalysts commonly used in Chemical Vapor Deposition (CVD) growth approaches. The first growth method uses a conventional graphite resistance furnace capable of annealing wafer-scale samples over 1700 deg C under vacuum. Using this approach, post-growth characterization is performed using both scanning electron microscopy and Raman spectroscopy. The second growth approach uses a high-intensity laser to apply heating to a micro-meter scale spot size on the SiC substrate. The high-intensity laser heats the illuminated area of the SiC substrate while under vacuum conditions, resulting in a small-scale growth process similar to the conventional resistance furnace technique. Unique to this micro-scale approach is that in-situ Raman spectroscopy is performed yielding instantaneous characterization of the resultant carbon nanostructure from the thermal decomposition of the SiC substrate.
Given the arduous nature of the growth and characterization of films formed using the furnace based approach, this work focuses on using the laser-induced growth technique to refine ideal growth parameters of bulk nanostructure films. The laser-induced growth mechanism enables the impact of varied background vacuum pressures and temperatures to be evaluated in-situ, with the possibility to evaluate hundreds of parameter sets. This work reports the results and findings for various parameter sets implemented during growth, and provides insight into the physical mechanism influencing the growth process.

Nowadays the visible light spectrum is being used in the communication protocol Visible Light Communication (VLC). The technology uses fluorescent or LEDs to transmit signals which make VLC an available, easy communications medium because light-producing devices are used everywhere.
In this paper we propose the use of a multilayered pinpin device based on a-SiC:H to work as a photodetector operating in the pertinent range of operation for VLC (375 nm - 780 nm). In this paper we demonstrate the use of UV steady state illumination (present in the emission spectrum of fluorescent lamps) to increase the spectral sensitivity of a double pi&’n/pin photodiode beyond the visible spectrum. Increased sensitivity in the range of 400 nm-850 nm is experimentally demonstrated.
Optoelectronic characterization of the devices is presented and shows the feasibility of tailoring the wavelength and bandwidth of a polychromatic mixture of different wavelengths. The device consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n heterostructure with low conductivity doped layers, sandwiched between two transparent contacts. Optoelectronic characterization of the device with spectral response and I-V characteristics, with and without background illumination are presented.
Results show that the spectral current under UV front light irradiation (350 nm) increases with the background intensity in the 470nm-800nm range and decreases for low power wavelengths in the visible range. Under back irradiation the spectral current decreases for wavelengths higher than 550nm and strongly increases beneath them. The optical gains hasve opposite behaviors under front and back irradiations. Under front irradiation and low power intensity the gain is high and presents a well defined peak at 750 nm and strongly quenches in the visible range. As the power irradiation increases the peak shifts to the visible range an can be deconvoluted into two peaks one in the red range that slightly increases with the power density of the background and another in the green range that strongly increases with the intensity of the UV radiation. In the blue range the gain is much lower showing the filter properties of the device at different UV background intensities. Under back irradiation the gain is high in the violet/blue ranges and strongly quenches for higher wavelength whatever the intensity of the background.
Results show that, front background enhances the light-to-dark sensitivity of the medium, long and infrared wavelength channels and quench strongly the low wavelength, depending optical amplification on the background intensity. Back UV background has the opposite behavior; it enhances only channel magnitude in short wavelength range and strongly reduces it in the long ones.
A capacitive optoelectronic model supports the experimental results. A numerical simulation will be presented.

Silicon Carbide (SiC) has unique properties making it suitable for hard and protective coatings, optoelectronics and sensing. It is the most promising alternative to Si for electronics devices working at high power/high frequency or in harsh conditions [1]. A new perspective is now being pursued for SiC as material for biomedical applications [2], and SiC is expected to be one the most promising interface for Graphene-based electronics [3].
Despite the use of different growth approaches, SiC synthesis of high quality/low defects crystalline films still represents an open challenge [1]. In particular, SiC heteroepitaxy on Si is interesting for the cubic (3C) polytype synthesis, having potentially the best electrical properties. Molecular Beam Epitaxy (MBE) has demonstrated to be a viable approach to 3C-SiC/Si synthesis at ~1200 K, using buckminsterfullerene (C60) as C precursor [4]. The epitaxy is critically affected by three factors: high lattice/thermal mismatches between SiC and Si, the material processing temperature (T), typically higher than 1100 K, and Si diffusion through the SiC film, creating defects at the nano and micro-scale. Therefore, synthesizing SiC at lower T is highly desirable to reduce side-growth processes, film defectivity and high production costs.
In this work we demonstrate the room T (RT, 300 K) synthesis of nanocrystalline 3C-SiC on the Si(111)7×7 surface achieved by kinetic activation based on the Supersonic Molecular Beam Epitaxy (SuMBE) approach, where C60 translational kinetic energy (KE) reaches values up to tens of eV undergoing an aerodynamic acceleration in vacuum [5]. C60 sub-monolayer (ML) films have been deposited with two different precursor KEs of 30 eV (0.30 ML, 0.65 ML) and 35 eV (0.35 ML, 0.70 ML). The chemical/physical properties of the C60 films have been investigated by in-situ XPS and UPS, while ex-situ AFM and TEM microscopies have been used for morphology and structure analysis. Furthermore, we simulate the C60-Si(111)7×7 collision by Density Functional Theory (DFT) and we show that, to obtain the cage rupture at the observed kinetic energies, one needs to go beyond the Born-Oppenheimer (BO) approximation and use non-adiabatic molecular dynamics (NA-MD) to intertwine the electronic and nuclear motion.
Our study paves the way for the heteroepitaxy of complete 3C-SiC layers in a SuMBE codeposition scheme with different supersonic beams of Si and C precursors, as well as the synthesis on substrates that do not withstand high temperatures, e.g. plastic and polymers for applications like sensing and biomedicine.
[1] C.R. Jr. Eddy, D.K. Gaskill, Science 324, 1398 (2009)
[2] Silicon Carbide Biotechnology, (Ed. S.E. Saddow) Elsevier (2012)
[3] J.M.P. Alaboson, et al., Adv. Mater. 23, 2181 (2011)
[4] K. Sakamoto, et al., Phys. Rev. B 58, 13951 (1998)
[5] R. Verucchi, et al., Eur. Phys. J. B26, 509 (2002)

Transfer of 4H-Silicon carbide (SiC) layers to Si and more robust support substrates such as poly-SiC is a novel approach to achieve monolithic integration of power circuits with digital circuits and to cut down the cost of device quality SiC substrates. Hydrogen ion implantation assisted layer transfer method was used to exfoliate SiC and achieve uniform layer transfer to the above mentioned handle substrates. This study will highlight the lateral MOSFET fabrication and device characteristics on exfoliated 4H-SiC films. Further emphasis will be also given to reducing ion implantation damage during layer transfer process through hot implantations and damage recovery through chem-mechanical polishing of transferred SiC layers.
To obtain 1 µm thick layers of 4H-SiC, we implanted 180 keV H+ ions into SiC with 10 nm of thermally grown SiO2, followed by bonding of the implanted samples to other substrates, such as oxidized silicon, and then followed by thermal annealing that induce splitting off of the implanted layer at a depth equivalent to the projected range of the ions (at 180 keV it is 1.07 µm)[1]. Process optimization included investigating a range of ion implantation conditions such as ion dose and implantation temperature. The effects were analyzed using RBS ion channeling, optical transmittance spectroscopy, and SIMS. 300°C implantation led to the most complete exfoliation, while both higher (600°C) and lower (35 and -196C) implantations were less efficient in layer separation, as will be discussed in some detail in the presentation.
To facilitate fusion bonding of SiC films, oxide was grown or deposited on the handle substrates: Si or poly-SiC wafers. Post-splitting surface quality was characterized with AFM - a typical roughness of the surface of the donor wafer and of the exfoliated film were 2.0 - 5.0 nm RMS. A chem-mechanical polishing (CMP) process was developed by us that achieved sub-nanometer roughnesses (0.1 nm - 0.4 nm) on both surfaces. The transferred layer must be smooth enough for device fabrication, while the donor wafers need to be restored to the original smoothness so that the exfoliation process can be repeated, as this is the key to the reduced cost of SiC thin film electronics. CV characterization was used to evaluate the post-split electrical quality of the transferred layers and of the donor wafers.
[1] V. P. Amarasinghe, L. Wielunski, A. Barcz, L. C. Feldman, and G. K. Celler, ECS Transactions (The Electrochemical Soc., Pennington, NJ), Volume 50, Issue 7, 341-348 (2012),

In this report, a sacrificial oxidation treatment was applied to reduce reverse-voltage leakage current of 4H-SiC Schottky barrier diode, and mechanism of the leakage current was also discussed.Carbon vacancies in SiC form trap levels within bandgap, and increase of this trap density induce device degradation like carrier-life-time decrease. For curing of carbon vacancy, sacrificial high temperature oxidation treatments on SiC have been reported. In this work, the sacrificial oxidation was applied to reduce leakage current of SBD, and the leakage current mechanism was discussed.A sacrificial oxidation treatment was carried out on n-type 4H-SiC (0001) epitaxial layer at 1150°C for 400 min. The thickness of the epitaxial layer was 10 mu;m and its impurity density was 1×10^16 cm-2. Schottky barrier diodes with and without the sacrificial oxidation treatment were fabricated. At the bottom of the substrate, Ni metal was deposited by sputtering at the thickness of 100 nm. After the bottom Ni deposition, the sample was annealed by furnace annealing at 900°C for 5 min, and Ni silicide electrode was formed. At the top of the substrate, a field plate oxide film was deposited with APCVD. After a pattering of the field plate oxide, Schottky metal electrode was deposited at the thickness of 300 nm. After a pattering of the top electrode, the sample was annealed at 400°C for 5 min. The 12 and 19 SBD samples with and without the sacrificial oxidation treatment were prepared for measurements. At forward bias voltage, the measured current-voltage characteristics of the SiC SBDs with and without sacrificial oxidation treatment show the barrier heights of 1.80 and 1.81, and the ideality factor n of 1.03 and 1.13, respectively. At the SiC SBD without the sacrificial oxidation treatment, anomalous current was found near the forward voltage. The leakage current at reverse bias voltage was drastically decreased by the sacrificial oxidation treatment. At the sample without the sacrificial oxidation treatment, at the depletion electric field of 0.12 MV/cm, the leakage current reached over 1×10-6 A/cm2. On the other hand at the sample with the sacrificial oxidation treatment, at the depletion electric field of 0.20 MV/cm, the leakage current reached over 1×10-6 A/cm2. Poole-Frenckel analysis at various temperatures was carried out. For the sample with the sacrificial oxidation, the behavior of the leakage current can be explained by the Poole-Frenkel mechanism. On the other hand, for the sample without the sacrificial oxidation, the temperature dependency of the leakage current was relatively small and different from Poole-Frenkel plot. This results show the leakage current mechanism of the sample without the sacrificial oxidation was temperature-independent mechanism like Fowler-Nordheim tunneling current.

Thanks to its preferable physical properties, silicon carbide (SiC) is the most promising material for high-power, high-frequency and high-temperature devices. Like silicon, SiC can easily form SiO2 on its surface by thermal oxidation, which makes it feasible to use the current Si technology for the development of SiC devices. However, the defect density of the SiC/SiO2 interface is two orders of magnitude larger than that of Si/SiO2 interface, which is a critical issue for the development of 4H-SiC MOSFETs.
Though a large number of experimental and theoretical studies have been reported on the state of 4H-SiC/SiO2 interfaces, the formation mechanism for the high-density interface defects is still unclear. Last decade, C-based defects have been proposed such as homogeneous carbon excess around the SiC/SiO2 interface or carbon clusters like di-interstitial defects inside the SiC substrate. However, the more recent works do not support these conclusions and in addition propose the existence of various suboxides at the interface. Therefore, the mechanism of the defect formation remains controversial and needs further study.
In this presentation, we investigate the structural and chemical state of 4H-SiC/SiO2 MOSFETs interfaces by high resolution scanning transmission electron microscopy (HR-STEM) (0.1 nm) and spatially resolved electron energy loss spectroscopy (STEM-EELS). The Si-L edge (100 eV), C-K edge (284 eV) and O-K edge (532eV) were collected in the same spectrum. In particular, we consider the effect of nitrogen (N) implantation into the MOSFET channel region prior to thermal oxidation. For this purpose, our EELS study also focus on the Si-L edge fine structures (ELNES), which reflects the Si atomic bonding states to their neighboring elements.
Three n-channel MOSFETs were investigated after FIB sample preparation. Two MOSFETs were shallow implanted in the channel regions with a low and a high dose of N, respectively, and the third one was not implanted. Based on the relative compositions extracted from our EELS data, no C excess was evidenced for the three samples neither in the SiC substrate nor in the SiO2 gate oxide. However, modification of the Si-L ELNES was revealed and numerically exploited. In particular, fitting of the Si-L edge evolution across the interface with a linear combination of reference spectra (Si, SiC and SiO2) evidences the presence of a laquo; suboxide raquo; over a distance at the SiC/SiO2 interface. It implies a transition layer where the Si bonding is modified neither similar to SiC nor to SiO2. This transition layer, which is less than 2 nm in size (FWHM), seems to be smaller and less evident for the non-implanted sample compared to the implanted ones. These results will be commented with regard to electron mobility measurements previously published.
This work has been performed by the French-German Consortium MobiSiC and was supported by the Programme Inter Carnot Fraunhofer from BMBF (Grant Agreement 312483).

The effects of inhomogeneity in a Schottky diode include very large ideality factors, temperature and voltage dependent Schottky barrier heights (SBH) and ideality factors, and so-called ‘double bumps&’ in the turn-on characteristics. These are effects that are very common to all semiconductors [1], but are very commonly reported at the metal-silicon carbide interface [2,3], due at least in part to atomic terracing on the off-cut surface, and due to the surface material quality, which has a basal plane dislocation density typically two orders of magnitude higher than in Si, with other defects such as carrots, growth pits and micropipes also prevalent.
By taking I-V measurements of a Ni/SiC Schottky diode at 2 K intervals from 20 to 320 K, we are left with an IVT dataset which includes low ideality factors (n<1.01) at room temperature, excessively high (n>8), voltage dependent ideality factors at cryogenic temperatures.
We report for the first time, the results of a model that is able to accurately model, parameterise and fully fit the effects of interface inhomogeneity over such a wide temperature range. Usually confined to fitting single I-V plots, we show how the Tung's original interactive parallel conduction treatment of barrier height inhomogeneity [4] can be simplified for mass parameterisation.
The results of the fitting and modelling show a subtle shift in the origin and effects of inhomogeneity across the temperature range. Consider the inhomogeneous interface to be made up of numerous parallel, interacting conduction paths, or patches, each with an independent SBH. We show that at temperatures below 200 K, I-V plots with very high ideality factors are well described by an interface that is dominated by the resistive effects of a few patches of very low SBH, these being the apparent path of least resistance at the interface. Above 200 K, the current is more evenly distributed across the interface regardless of individual patch barrier energies, and hence a more homogeneous (lower ideality factor) I-V response is witnessed.
This work has contributed a simplified SBH inhomogeneity model that is applicable to any metal-semiconductor interface, and a better understanding of the complex interactions that occur at an interface that is so fundamental to many electronic devices.

4H-SiC have been accepted as an ideal substrate material for high power electronics due to its high thermal conductivity and excellent electrical properties. In our laboratory, 4H-SiC single crystals with different nitrogen doping concentration were grown by sublimation method. After processing, the standard 4H-SiC substrates were obtained. The carrier concentrations in 4H-SiC single crystals were measured by Raman spectroscopy and the nitrogen concentration were further calculated. The resistivities of 4H-SiC single crystals were measured by a non-contact resistivity testing system. The influence of nitrogen concentration on the resistivity of 4H-SiC single crystal was assessed. In addition, the structural qualities of 4H-SiC single crystals were investigated by high resolution X-ray diffractometry. The rocking curves of symmetric 004 and asymmetric 108 reflections were measured and the lattice constants of 4H-SiC single crystals were accurately determined. The effect of nitrogen concentration on the lattice constants was discussed.

The main objective of this study was to evaluate semi-insulating (SI) SiC material as a candidate for dielectric substrate for patch antennas, with a long-term potential for monolithic antenna integration on a SiC semiconductor chip. Computer-aided design of microstrip patch antennas operating at 10 GHz was conducted. Vanadium-doped SI SiC substrates were used as the dielectric substrate for the antennas. The dielectric properties of the SI SiC were found promising for antenna miniaturization and high antenna efficiency due to the high dielectric constant (ε_r asymp;10), low loss tangent (tanδasymp;10 ^-6), and low conductivity (σasymp;10^-5 S/m). Metal layers on the back and front surfaces of the SiC wafers served as the ground planes and patches respectively. The metal stack consisted of 1 kÅ Ti for adhesion, 1 kÅ Pt for a metal diffusion barrier and an oxygen barrier, and 3 µm Au for a low resistance wire-bondable layer. The fabrication sequence for patterning the front and the back side metal layers included the following steps. The metal layers were e-beam deposited over the front and backside of the sample. The metal patch was patterned with photoresist (PR) on the front side, and the entire backside was coated with PR. Two wet etches and a plasma etch were used for etching the metal layers. Return loss measurements were performed using an E8362B PNA network analyzer. A good agreement between the experimental results and the simulation was obtained at the band of operation (10 GHz), confirming that sufficient antenna functionality can be achieved when using SiC as the dielectric substrate. Co- and cross-polarized radiated fields for Phi;=0 and Phi;=90 cuts at 10 GHz were simulated. The antennas showed omnidirectional radiation characteristics for both cuts in the band of interest. Radiation efficiency of the antenna was over 96% through the entire band. It was concluded that SiC based patch antennas radiate as good as do the antennas fabricated with conventional RF materials such as FR4 and Rogers. In addition, the antennas had the gain around 2 dBi at 10 GHz, which is consistent with the conventional antennas of a similar size. A possibility of utilizing highly-conductive (heavily-doped) SiC epitaxial layers as the ground planes and radiating patches were investigated using computer simulations. The conductivity value for SiC patches was taken as 10⁴ S/m on the basis of the best experimental results obtained for the heavily doped SiC epitaxial layers grown by low-temperature epitaxial growth methods developed at MSU. The simulated values of the return loss of the full SiC antenna were compared to the antennas utilizing SiC dielectric with gold and PEC patches. The replacement of the metal patches with SiC significantly affected the antenna performance. The antenna operating frequency shifted to lower frequencies. In addition, it has been demonstrated that the antenna bandwidth significantly increases with the replacement of the gold layers with SiC material.

Graphitic carbon films have been used in the formation of ohmic contacts on n-Si [1] and high quality rectifying junctions on SiC [2]. The role of deposition conditions in determining the properties of the contacts to SiC remains unclear. In this paper, we examine the relationship between the deposition energy of carbon, the microstructure and the electrical characteristics of C/ n-SiC junctions. Films of carbon were energetically deposited onto 6H-SiC substrates using a near fully ionized carbon plasma in a filtered cathodic vacuum arc (FCVA) system. The average energy of deposition was varied by applying a bias to the conducting substrates of n-SiC. The low temperature (< 80 C) of deposition without the need for post-deposition annealing has allowed a simple lithographic patterning by lift-off. The test structures in a transmission line model pattern have been used to quantitatively measure the electrical properties of the contacts. By altering the deposition energy of carbon, it was possible to produce a continuous transition from ohmic to rectifying electrical contacts. The linearity of the contacts was also controlled by the nitrogen pressure during deposition. The residual stress in the carbon films deposited by FCVA has peaked at 100 V and then reduced with further increase in bias. The fraction of sp2 carbon in the films increased for biases greater than ~100V with a corresponding increase in electrical conductivity. 1. DWM Lau, DG McCulloch, MB Taylor, JG Partridge, DR McKenzie, NA Marks, EHT Physical Review Letters 100 (17), 176101 (2008). 2. Th Seyller, K V Emtsev, F Speck, K-Y Gao and L Ley, Applied Physics Letters 88, 242103 (2006).

Ion implantation is an important doping method during the course of SiC devices fabrication. We show how the growth of epitaxial graphene on Al ion-implanted SiC differs from the growth on the SiC surface, and also how it differs from the growth on Al ion-implanted SiC followed by pre-plasma treatment.
Samples used in this study was p-type epitaxial layer grown on n+-type SiC(0001) with off-orientation of 4°. Al ion was implanted into the SiC substrate with the energy range from 170 to 260 keV to form 300 nm-thick n-doped layer with Al concentration of 5 x 10¹⁹ /cm³, which is typical condition of our BJT transistor made of normal SiC devices. The implanted sample was processed by CF₄ plasma for 1 min with an RF power of 300 W at a pressure of 0.41 Pa, with a flow rate of 20 sccm. To remove the implantation induced damage and then activate the implanted dopant, the high temperature annealing was performed at the temperature of 1700oC for 30 min in Ar atmosphere. After the activation annealing, we used O₂ plasma treatment to remove graphite which was grown on SiC during annealing. And then, samples were annealed again at 1500 °C for 30min in 0.01MPa Ar gas flow to make a graphene film. The graphene films were characterized by AFM and Raman spectroscopy. The scan area of AFM and Raman mapping observation were 10 x 10 mu;m².
The Al ion implanted sample, which was processed by CF₄ plasma, showed small surface roughness of 3.49nm of meaning of root mean square (RMS), while the sample without CF₄ plasma treatment showed large surface roughness of 8.41nm. In Raman spectrum, strong D-band, G-band and 2D-band signals were detected on both samples after annealing at 1500 °C. Raman mapping (2D-FWHM) showed that the graphene on ion-implanted SiC treated by CF₄ plasma was more homogeneous than the one without CF₄ plasma treatment.

In general, conventional semiconductor detectors are severely limited by the operational temperature constraints and poor resistance in radiation damage, whereas Silicon Carbide (SiC) shows increased resistance to radiation particle and the capability to operate stable in elevated temperatures with its wide band-gap (~3.2 eV) and chemical / neutronical inactivity to compared silicon.
Therefore, SiC has attracted interests in radiation research due to their potential to be used in devices operating in high power ranges and high temperature space applications as well as neutron detectors. These applications may involve the integration of semiconductor devices into satellite systems in earth orbit, so as to operate for years in a radiation environment at widely varying temperatures.
In this study, SiC Schottky diodes were irradiated under neutron flunces and the changes in electrical characteristics were measured and compared to the charge control model to study the the radiation-induced changes in device properties.
We have fabricated SiC Schottky barrier diodes and a forward current of ~100 A/cm2 at a forward voltage of ~2.0 V and a blocking voltage of ~600V were demonstrated. SiC diodes are normally hardened to radiation effects compared to silicon devices and the fabricated SiC devices continued to function as diodes after radiation fluences of up to 3.1x1010 n/cm2 for 60 seconds.
For the electrical characterization, current-voltage (I-V) measurements were performed in a probe station with a Keithley 4200 semiconductor parameter analyzer. High temperature measurements were also performed in the temperature range of 25~300oC.
After the neutron irradiation, a slight positive shift in threshold voltage shift has been observed, which is attributed to charge damage in the SiC layer.The samples were subsequently annealed in a low-pressure (1x10-3 Torr) vacuum chamber at 350oC for 10min. The effect of annealing at elevated temperature has also been studied and the results are also compared with numerical simulations. The numerical simulations of pre- and post-irradiation results showed that the dominant parameter in the characteristics change may be the increase in trap concentrations, as the increased in reverse saturation current may be attributed to trap-assisted tunneling and the defects with an impurity element.

Graphene growth on SiC through thermal decomposition is a favorable approach for its feasibility of producing large-area graphene and compatibility with electronic device fabrication. Over the past several years, extensive studies have been conducted to understand the growth mechanism of graphene on SiC substrate, and the growth environment induced impacts on graphene formation and its structural and electrical properties. While most studies were focused on graphene growth on commercial bulk 4H and 6H-SiC (bulk SiC) substrates, a few reports address formation of graphene on epitaxial-grown 3C-SiC (epi-SiC) on silicon wafer which may open a new paradigm to integrate graphene into the main stream semiconductor industry.
Recently, graphene growth was demonstrated on 3C-SiC/Si as well as 3C-SiC/6H-SiC substrates. However, the required ultrahigh vacuum or high temperature (up to 1750oC) in these reports is too costly and incompatible with the silicon technology. In this work we performed a systematic study of growing graphene layers on epi-SiC/Si substrates in various experimental conditions. It turns out that the thickness of the epi-SiC layer, growth temperature, and environmental gas ambient are critical for the graphene growth. A thin epi-SiC layer, less than tens of nanometers, results in no carbon layer formation possible due to the lack of carbon resources. Decomposition at lower temperatures for prolonged time leads to formation of amorphous conducting carbons instead of graphene. Traces of water present in either a vacuum or argon environment facilitates the graphene formation on 3C-SiC/Si substrate at 1350oC. The grown graphene layers have been characterized using Raman spectroscopy, Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM) and Scanning Microwave Microscope (SMM), and compared with the graphene growth on bulk-SiC. The difference in correlation between the growth conditions and characteristics of grown graphene on the two SiC polytypes may provide the insight of surface chemistry and mechanism towards the formation of high-quality graphene.
Reference
1. C. Riedl, C. Coletti and U. Starke, J. Phys. D, 43 (2010) 374009.
2. A. Ouerghi, A. Kahouli, D. Lucot, M. Portail, L. Travers, J. Gierak, J. Penuelas, P. Jegou, A. Shukla, T. Chassagne, and M. Zielinski, Appl. Phys. Lett., 96 (2010)191910
3. L. Wang, S.Dimitrijev, J. Han, P.Tanner, A. Iacopi, and L.Hold, J. Crystal Growth, 329 (2011) 67-70
4. G. R. Yazdi, R. Vasiliauskas, T. Iakimov, A. Zakharov, M. Syva jarvi, and R. Yakimova, Carbon, 57(2013) 477-484.

In chemical and biomedical sensing, identification and quantification of analytes in water, blood or other carriers are very important. Various sensing methods have been developed, and among them, optical waveguide structure is considered very useful and its sensing properties can be significantly improved by surface plasmon resonance (SPR). For water based sensing medium, the optical waveguide sensors are desirable to operate in the visible light wavelength to overcome the large absorption coefficient of water in the near infrared range. Conventional silicon (Si) is not the choice of material for such sensors due to the strong absorption below the wavelength of 1.1 mu;m resulted from the narrow bandgap (Eg=1.12 eV). As a wide bandgap semiconductor, silicon carbide (SiC) is more desirable for such sensors with advantages of wide bandgap energy of Eg=3.2 eV (in 4H and 6H polytypes) and 2.2 eV (in 3C polytype), resulting in the transparent wavelength over visible and near-infrared range. Furthermore, SiC has excellent material properties especially the chemical inertness and biocompatibility, and SiC device fabrication is compatible with standard Si device fabrication which is desirable for manufacturing and on-chip integration. In this paper, we investigated SiC optical waveguide-based SPR sensors. Sensor structures with both single Au-layer configuration and Au-Ag bilayer configuration were studied to compare sensitivity and sensing resolution. The performance results, when combined with the advantages of SiC material, prove that SiC waveguide SPR sensor is very promising for chemical and bio sensing.

3C-SiC has a narrower bandgap than 4H-SiC but more isotropic electrical properties, and it since can be grown directly on a large area 6”/8” Si substrates via chemical vapour deposition (CVD) methods, it provides a more economical choice for intermediate power devices in electric vehicles [1,2]. But in order to avoid a poor 3C-SiC/Si interface in the vertical direction a very thick Si substrate has to be removed either by a mechanical polishing or chemical etching process. These processes are time consuming and not cost-effective. A lateral structure is much less prone to the electrical properties of the heterojunction (3C-SiC/Si) and as a result there is no need to remove the substrate. 2D finite element simulation results have shown that the use of a field- plate in a lateral Schottky diode design modifies the electric field around the corners and avoids early breakdown of the device. A maximum breakdown voltage of >1200V can be achieved with an epilayer of thickness <10µm. Also, this paper will discuss the influence of substrate doping/and thickness, the size and distance of field- plate (from the active area) on the electrical properties of the diode.
References
[1] http://www.i-micronews.com/upload/Rapports/Yole_SiC_Market_2013_Sample_report.pdf.
[2] G. L. Harris, Properties of Silicon Carbide, (IET, 1995).

4H-SiC holds great promise for demanding power electronics applications due to its excellent electrical and thermal properties. For applications above several thousand volts, bipolar semiconductor devices offer greater efficiency in the on-state due to the conductivity modulation effect. However, the degree to which conductivity modulation enhances the efficiency of such devices is heavily dependent on the carrier lifetime of the semiconductor material. Though carrier lifetimes up to 1 mu;s are typically reported in as-grown material [1], this has been found to be dramatically enhanced by thermal oxidation, which serves to eliminate the lifetime-killing carbon vacancy-related Z1/2 defect center in the material [2]. Unfortunately, in order to eliminate the Z1/2 center in the thick epilayers required for high voltage devices, long oxidation times are required, thus adding significant cost to the overall device fabrication process. For instance, such oxidation processes take over 50 hours when applied to a 10 kV, 100 mu;m thick epitaxial layer at a conventional temperature of 1300°C [3]. Furthermore, the oxidation process is typically followed by a separate argon (Ar) annealing process to eliminate the HK0 center that is generated during the thermal oxidation [4], adding further processing complexity and cost. As such, the application of thermal oxidation at higher temperatures is attractive, and is investigated in this work.
Epitaxial anode 4H-SiC PiN diodes have been fabricated with a n- drift region (110 mu;m doped at 6×1014 cm-3) and a p+ anode (1 mu;m doped at 1×1019 cm-3) grown on a Si-face 4° off-axis n+ substrate. After epitaxial growth, the wafer was laser-cut into 14 x 14 mm dies. After undergoing solvent- and acid-based cleans, these dies have undergone a high temperature oxidation process at temperatures ranging from 1300°C to 1600°C to enhance the carrier lifetime. Each oxidation was performed for 5 minutes. After the oxidation process and removal of the thermal oxide in dilute HF solution, individual devices were mesa-isolated, passivated with SiO2 and metallised using Ti/Al (anode contact) and Ti/NiV (cathode contact). An anneal was performed to improve the ohmicity of both contacts, then the devices were metallised again to facilitate wire bonding to direct copper bond (DCB) substrates. Forward I-V measurements carried out at 25°C showed that the differential on-resistance (ron,sp) decreased from a mean average of 12.2 Omega;-cm2 at 100 A/cm2 for the un-oxidized control sample to 8.4 Omega;-cm2 at 100 A/cm2 for the devices oxidized at 1500°C. The final paper will present the results of extended oxidation processes, as well as reverse recovery characteristics of the fabricated devices.
References
[1] T. Hiyoshi and T. Kimoto, Appl. Phys. Expr. 2 (2009) 041101
[2] S. Ichikawa et al, Appl. Phys. Expr. 5 (2012) 101301
[3] K. Kawahara et al. Mat. Sci. Forum 717-720 (2012) p.241
[4] T. Hiyoshi and T. Kimoto, Appl. Phys. Expr. 2 (2009) 091101

Much like varactors, the photosensitive capacitor (PSC) provides for continuously variable reactive tuning in RF circuitry. Unlike varactors, PSCs often do not require a DC bias voltage to operate. This is a major system advantage when interfacing directly to RF elements. Instead of using conductive wires or traces as control methods, an optical fiber can be used for control resulting in little to no perturbation in the surrounding EM field. Also, by using durable, high-high-temperature, very high Vbd semiconductors such as 4H-SiC we can greatly expand present day RF circuit capabilities into high power designs. Possible applications include reactive tuning of antennas and phase delay devices.
In this paper we present the experimental findings regarding the photocapacitance effect of Schottky barriers on bulk 8° off-axis HPSI 4H-SiC. We have fabricated several 1cm x 1cm square photocapacitor devices from the bulk material using metal-evaporated Ti/Au contacts in a simple planar parallel-gap geometry. IV curves were taken of the devices using a HP-4145B semiconductor parameter analyzer to ensure Schottky behavior at DC. The devices were then studied for series capacitance (Cs) and series resistance (Rs) using an HP-4284a LCR meter at 33 kHz, 66 Khz, and 1 Mhz under illumination of a below-bandgap 470 nm high intensity LED light source (Thor Labs model M470).
The resulting data demonstrates an increase in Cs and a drop in the Rs with increasing optical intensity incident on the device&’s gap. Series capacitance and resistance data points were taken at 33 khz, 66 khz, and 1Mhz, at a range of light intensities from 0.01 mW to 2.86mW with the largest capacitance changes seen at low frequency (33 kHz). At this frequency, Cs increases from its nominal value of 186.71 pF to 575.59 pF while Rs dropped from149.99 KOmega; to 22.39 KOmega;. The underlying phenomenon of the effect is suspected to be the light&’s interaction with the dominant deep level traps Z1/Z2 through Shockley-Read-Hall (SRH) recombination.Details of the experimental data will be provided along with an empirical model that is being developed to allow for device parameter extraction.

Nanoribbon structures have shown considerable potential for low leakage, and a high on/off current ratio with the low power consumption, due to its high surface-to-volume ratio, and small size. Also, Nano-ribbon structures have recently shown promise to enable high-density electronics as well as in high-performance sensors. SiC material has been proposed to replace conventional silicon devices which already are approaching the material limit in power electronics. SiC-based devices exhibit a high-temperature and high-power capabilities. The combination of the structural advantages of nanoribbon-based devices and the materials properties of SiC may result in devices with improved performance.
In this work, dual-gated 4H-SiC nanoribbon FETs have been fabricated by “top-down” approach and the characteristics of the fabricated devices have been studied at the elevated temperature.
We fabricated 4H-SiC nanoribbon FETs with channel thickness (tepi) of 100 nm. The starting materials are p-type 4H-SiC wafers (NA=1×1018 cm-3) with a n-type epilayer (ND=5×1017 cm-3).
The fabricated devices were examined by using field emission scanning electron microscopy (FE-SEM) and atomic force microscopy (AFM), respectively. Current-voltage I-V characteristics of the device were measured by using a Keithley 4200 semiconductor parameter analyzer for comparison at different temperature ranges from 300K to 523K. The experimental results have also been compared with numerical simulation results obtained from structures identical to those of the fabricated devices. In order to evaluate the back gate and top gate bias-dependent channel carrier modulation as a function of temperature, we extracted the channel cross-section profiles containing the on- and off-current density distribution.
We have successfully fabricated dual-gated SiC nanoribbon FET structures (tepi ~100nm) and typical SiC nanoribbon device shows ~2 times improved current degradation than that of the Si nanoribbon FETs at elevated temperatures (up to 523 K). And the pinch-off voltage of the fabricated FETs show a negative shift with the measurement temperature increases. The threshold voltage variation of the SiC nanoribbon FET is lower than that of the reference FET, which means the nanoribbon FETs are more stable at high temperature. These results suggest that the proposed SiC nanoribbon structures significantly improve the gate control at high temperatures and thereby making them promising for high-temperature sensing testbeds.

Silicon carbide (SiC) semiconductor devices for high power applications are now commercially available as discrete devices. Schottky diodes are offered since several years by both USA and Europe based companies. Active switching devices such as bipolar junction transistors (BJTs), field effect transistors (JFETs and MOSFETs) have also reached the market. The interest is rapidly growing for these devices in high power and high temperature applications. The main advantages of wide bandgap semiconductors are their very high critical electric field capability. From a power device perspective the high critical field strength can be used to design switching devices with much lower losses than conventional silicon based devices both for on-state losses and reduced switching losses.
This paper will give an overview of current state of the art device technology for SiC discrete devices and applications. The superior energy efficiency of SiC devices will be demonstrated and compared to its silicon counterparts. Recent developments in process technology for vertical very high voltage SiC bipolar devices will be presented and discussed.

Since the late 1990s, SiC planar DMOSFETs have been developed and recently commercialized. For voltage ratings between 600 V and 3 kV, the SiC MOS channel resistance is still a significant part of the total on-resistance due to the much lower inversion channel mobility on Si-face (0001) 4H-SiC than its theoretical value. To further improve the SiC MOSFET performance, trench-gate MOSFETs (UMOSFETs) have been actively investigated by several groups due to the advantages of a potentially higher MOS channel mobility along the (11-20) face, lack of the JFET region, and potentially higher channel density than that of the DMOSFETs. To further the development of trench gate devices, further research on the gate oxide processing and passivation are required, as these alternative SiC crystal faces.
In this report we present results comparing MOS capacitor and MOSFET properties of devices fabricated on Si-face (0001) and A-face (11-20) 4H-SiC. This allows a direct comparison of channel properties expected for DMOSFET versus UMOSFET devices. On Si-face, oxides have been either thermally grown or deposited by CVD, while on A-face the oxides have been deposited. For both cases, NO passivation anneals have been performed at temperatures ranging from 1175°C to 1300°C. Gate electrodes are B-doped poly Si, with Ni ohmic contacts to N+ source and drain regions. These lateral MOSFETs are all long-channel devices (Lg > 50 um).
We observe a MOSFET field-effect mobility ranging from of 18-34 cm²/Vs on the Si-face, dependent on the doping concentration. These devices have a channel mobility scaling with temperature as T^0.14, indicative of a channel mobility limited by coulomb scattering (shallow traps). On A-face SiC, the channel mobility after NO passivation is observed to be about 80 cm²/Vs, with a T^-0.71 temperature dependence, closer to the phonon-scattering limit (T^-2.5) indicating less interface traps are present near the conduction band. This >2x higher channel mobility would result in a substantial decrease in on-resistance hence power losses for 4H-SiC power MOSFETs, especially when the voltage rating is below 3 kV, and as such is very promising for trench channel device application. However, MOS I-V gate leakage indicates a very different oxide quality on each SiC face. For example, the Fowler-Nordheim (FN) barrier height for electron tunneling at the SiO₂/SiC interface is ~2.7 eV for oxides on Si-face SiC, while it is 2.4 eV or lower for oxides on A-face SiC. It is apparent that oxides on alternative crystal faces, although very promising in terms of channel mobility, require very different processing for property optimization.
Further results demonstrating the effects of hydrogen passivation anneal treatments, and the properties of lateral and trench devices as a function of temperature and gate stress, will also be presented.

The existence of gate oxide breakdown and various electrical and physical characteristic drifts in silicon carbide (SiC) power devices due to simultaneous bias stress and temperature conditions is well known. This topic has been the subject of much investigation recently, as the performance of available devices is being optimised [1,2,3]. However, very little work has been done on real commercially available devices to investigate the aging performances at temperatures much above 450 K, where many end users would like them to operate eventually. Furthermore, most existing work has focused on constant stresses, for device development reasons, and little work has been done using periodic stresses that are more representative of the application conditions, especially aging due to thermal cycling.

Our recent work has revealed quite serious aging issues. For example, we conducted the constant bias temperature stress (BTS) tests on commercially available SiC MOSFET devices and measured a 110% increase in gate threshold voltage (Vth) after a 30 minute +20Vdc gate bias at a temperature of almost 600 K. In the final paper, we will reveal and discuss our findings including measurement results from a selection of commercially available power device types for isothermal stresses compared to thermal cycling stress up to at least 600 K, in conjunction with periodic biasing. We will discuss the aging mechanisms, which ones can be screened out, and briefly introduce the state-of-the-art in device processing intended to mitigate these aging processes.

Finally, we know that most of these aging issues arise due to high interface trap density (Dit) [4]. As a result we have developed a new high temperature oxidation process that has led to the lowest Dit ever produced, without any passivation, to our knowledge [5]. Now we are in the process of evaluating the reliability of these oxides using MOS capacitors, by performing the classic time dependent dielectric breakdown (TDDB) tests. In the final paper, we will present the reliability of our high temperature oxide process for our capacitor structures and will also demonstrate the benefits of this process on the device ageing performance, including Vth drift, using our own device structures.

References
[1] K. Matocha et al., IEEE Trans. Elec. Devices, 55 (2008)
[2] C. Liangchun et al., IEEE Trans. on Devices and Mat. Reliability, 10 (2010)
[3] R. Kapler et al., Sandia National Laboratories report SAND2011-0099 (2011)
[4] C.J. Cochrane et al., Mat. Sci. Forum, 717-720 (2012)
[5] S.M. Thomas et al., ICSCRM (2013) to be published.

Owing to its properties silicon carbide (SiC) is an attractive candidate for high voltage and high temperature applications. Off-axis epitaxial SiC growth - although mature - introduces several defects. The major defects like basal plane dislocations (BPDs) may result in an increased forward voltage drop and bipolar degradation. This can potentially be avoided using on-axis homoepitaxial growth. We have designed and fabricated 10 kV 4H-SiC PiN diodes on on-axis substrates including lifetime enhancement.
A breakdown voltage around 13 kV was targeted to have some margins for process variations. The 3-zones JTE with accurate doses were optimized by using Sentaurus TCAD simulator to stabilize the breakdown voltage.
A thick n- layer (100 µm) low doped epitaxial layer was grown on the Si-face (0001) of 3-inch on-axis 4H-SiC wafer. Improving the surface morphology after growth of the n- layer was done by Chemo-mechanical polishing. Carrier lifetime was increased from 200 ns to 2 µs by carbon implantation followed by high temperature annealing at 1550 °C. A P++/P+ layer was regrown. The circular anodes with 3 different diameters (100, 200 and 400 µm) were formed by reactive-ion etching (RIE) with a photoresist mask. Three steps Al ion implantation were used to form the 3-zones JTE at room temperature. Activation annealing was done in Ar ambient at 1650 °C for 15 min with a carbon cap layer. To minimize the interface charges, a surface passivation layer was formed by 50 nm PECVD deposited SiO2 followed by post oxide annealing at 1100 °C for 3 hours in N2O ambient. Ni was used for cathode contact, while a triple layer Ni/Ti/Al was deposited for anode contact. Further rapid thermal annealing at 950 °C and 800 °C in Ar ambient was done to achieve ohmic contacts. 3 µm Al was deposited on the anode contact for current spreading and wire bonding.
The forward I-V characteristics shows a forward voltage drop (VF) of 3.38 V at 100 A/cm2 at room temperature with an ideality factor eta;=1.86. All fabricated diodes are working and 40% of them have a VF < 3.38 V. The forward I-V characteristics at elevated temperatures depicted a VF of 3.1 V at 200°C and 3.0 V at 300 °C which confirms the simulated results. It shows ΔVF=-1 mV/K due to bandgap lowering by temperature increasing. TLM structures were used to extract the contact resistivity for p-type contacts after annealing (8×10-4 Omega;.cm).
The reverse I-V characteristics were made for a few diodes while the sample was submersed in dielectric silicone fluid to avoid air sparking, and the diodes contacted by means of probe tips. We achieved a record for breakdown voltage more than 8.3 kV. It is the highest measured for on-axis 4H-SiC to our understanding. The diodes will be packaged and the reverse I-V characteristics will be done again, which will probably improve the breakdown properties. The bipolar degradation will be studied by stressing the diodes and switching characteristics are being done and will be presented.

Silicon Carbide devices can operate at much higher temperatures than Silicon devices, due to the significantly wider band-gap. These capabilities are expected to be required for certain drilling applications such as deeper oil, gas and geothermal wells, and also sensor interfaces in hot environments such as gas turbine parameter sensing. There may also be requirements in control systems for the new high power SiC components now becoming available. This paper provides a brief outline of a CMOS integrated circuit process which is being developed to operate at 300°C for significant periods of time. A 15v operating voltage was chosen to provide the necessary wide margins for operation over a wide temperature range. This process has been used to fabricate a range of simple logic circuits alongside a wide range of test transistors and other process characterisation structures such as resistors, capacitors, diodes and contact chains.
N-channel and P-channel transistor performance at room and elevated temperature is presented. Both channel types show the expected low values of field effect mobility, well known in SiC MOSFETS. This is due to the much larger defect state density present at the SiC/SiO2 interface compared with the Si/SiO2 interface, for example. However the performance achieved is easily capable of exploitation in CMOS digital logic circuits over a wide temperature range. In addition, long term reliability data for some structures such as resistors and contact chains will be summarised.
Data will also be presented for the performance of certain logic test circuits, such as a quad NAND gate, before and after long term bias temperature stress, and at temperature. Devices are packaged in conventional ceramic dual in line (DIL) packages, which are capable of 300°C operation. Alternatively, some test structures are mounted on custom ceramic hybrid substrates. A high temperature “micro-oven” system has been designed and built to enable testing of units assembled in either of these package types. This system heats a group of devices together to temperatures of up to 300°C, while keeping the electrical connections at much lower temperatures.
Finally, the initial performance of some new prototype circuits such as multiplexers, counters, and gate (or base) drivers will be presented.

Integrated Silicon Carbide (SiC) bipolar junction transistors (BJTs) have large potential for use in harsh environments. Thanks to the wide bandgap devices operate at 500 °C and beyond. Compared to MOSFET technology BJTs do not suffer from gate oxide degradation and hence are intrinsically more stable at elevated temperature. Previous work has demonstrated digital blocks in ECL topology. In this work we have designed RF transistors with a pad and emitter-base geometry layout suitable for S-parameter measurements and low-frequency noise studies. The BJTs were designed for low-voltage application, supply of 15 V, but have a breakdown voltage of around 65 V. The investigated devices featured an emitter width of 30 mu;m and either a double base contact or single sided base contact. The devices with different emitter-base geometry featured similar DC gain of about 80 at room temperature and about 30 at 200 °C. Scaled devices in a DC connection showed that the gain was maintained for smaller (15 mu;m) emitter geometries. Calibrated TCAD simulations indicated that further emitter and base geometry scaling would be beneficial for the RF performance. From S-parameters measured at room temperature a peak cut-off frequency f_T of 0.4 GHz was extracted for V_CB 2.0 V and 0.5 GHz for V_CE of 15 V. The strong f_T dependence on collector bias was caused by the internal forward biasing of the base-collector junction at high current, due to high collector epi resistance. The temperature variation of f_T was less than 20 % from room temperature to 125 °C. Extracted f_MAX values were about a factor of 4 lower than f_T values due to high access resistances. Low-frequency noise spectroscopy was performed at various bias points and for the different devices layouts. The noise dependence on the non-ideal base current was specifically adressed, by the directly measuring the base current noise using a transconductance amplifier.The noise spectra showed a well behaved 1/f-slope and no significant evidence of generation-recombination noise. In summary our low-voltage, integrated SiC BJT technology shows great potential for RF and low-noise applications and further optimization could target microwave frequencies above 1 GHz.

During the past years there has been considerable interest in systems able to record very low light levels in the ultraviolet range in severe conditions of use, as spatial and nuclear radiation environment. The advantage of Silicon Carbide (SiC) with respect to nitride alloys - the major wide band-gap semiconductor used today in industry - relies on three major points: a low residual doping for epitaxial layers, a high thermal conductivity and very good radiation hardness. It is then possible to use SiC for fabrication of devices able to operate under extreme conditions. Photodetectors based on SiC allow good wavelength selectivity in the UV range, without any optical filters. Last year, our team was investigating the characteristics of p⁺n photodiodes, where the p⁺ layer was produced by two different doping processes [1][2]: 4H-SiC n-type epilayers were either implanted with Aluminium by standard ion implantation at 27 keV, or with Boron by PULSION^TM system - B2H6 at 8 keV, in order to produce p⁺-type layer thicknesses of 30 and 10 nm, respectively. Each sample was then annealed in a specific furnace at 1700°C.
Today, we are going further in the characterization of these samples by performing spectral sensitivity measurements for several diode diameters (230µm, 320µm, 950µm), and at several temperature, from 23°C to 350°C. Our first results show that the diodes get the worst spectral sensitivity with the biggest diameter. This fact could be explained by the low homogeneity of actual SiC wafers. The temperature measurements exhibit a red shift when the temperature increases, as well as a supplementary UV shift and an increase of light induced current above 350°. The final paper will give more detailed measurements of temperature dependence of the spectral response, and exhibit the behavior of the photodiodes after strong irradiations (protons, 10MeV, 2.10¹¹ particles and electrons, 1MeV, 2.10¹² particles), aiming at proving the ability to work under harsh environments such as for space applications.
[1] L. Ottaviani, W. Vervisch, S. Biondo and O. Palais, Materials Science Forum 740-742(2013)
[2] S. Biondo and al, Materials Science Forum 717-720(2012)

Electrical Characteristics of Industry's first 650 V and 1200 V SiC Junction Transistors (SJTs) and Schottky Rectifiers, specially designed for operation up to 250°C are presented.
The 650 V-Class SJTs feature current gains (β) of 132 at 25°C, while values as high as 84 are obtained even at 250°C junction temperatures. At temperatures higher than 250°C, the current gain shows a desirable positive temperature co-efficient. Pulsed drain current measurements indicate an almost invariant current gain up to 800 A/cm2, at 175°C, which indicates the SOA boundary for pulsed high current operation of these SJTs. The blocking mode of the SJTs is characterized by low sub-5 mA/cm2 leakage currents at the rated blocking voltage, even at 250°C. The blocking voltages are solely limited by avalanche breakdown, which is confirmed by a positive temperature co-efficient of breakdown voltage. Temperature-invariant sub-100 ns switching waveforms are measured up to 250°C, which confirm the majority carrier operation mode of the SJTs even at such high temperatures.
The 1200 V Schottky Rectifiers feature reverse leakage currents of < 3 mA/cm2 up to temperatures as high as 300°C. GeneSiC&’s 1200 V/20A SHT rectifier offers a 10x reduction in leakage current and a 23% reduction in junction capacitance when compared to its nearest SiC Schottky rectifier competitor. In addition, these high-temperature Schottky (SHT) rectifiers demonstrate superior surge-current ratings, temperature-invariant low ideality factors < 1.2, and temperature-independent switching capability up to their rated junction temperatures.
Results from detailed static, switching and reliability characterization performed on 250°C-Class SiC SJTs and Schottky Rectifiers, including temperature-dependent avalanche energies, short circuit SOA, 10 mu;s and 10 ms surge current SOA will be presented in the full paper.

Silicon carbide (SiC) is a wide band gap semiconductor commonly used for power device but these last years it is became an attractive material for the conception of nuclear detectors. Indeed, compare with classical semiconductor, SiC detectors show themself very resistant to the radiation-induced damage.
In the framework of the I-SMART project, we developed three types of thermal and fast neutron detectors. Both of geometries are based on ion implantation of 10B as Neutron Converter Layer. The choice of boron 10 is explained by the relatively high thermal neutron cross section (3900 barns).
Mechanisms for detecting neutrons (Detection mechanism) are based on indirect methods where neutrons interact with 10B nucleus for example to produce charged particles (4He and 7Li nuclei). These charged particles lose energy in the detector and create a generation current of electron-hole pairs. In order to collect the electron-hole pair a p-n junction has been realized.
To validate devices, current-voltage measurements have been performed before and after irradiation.
For this work made in Dresden (Germany), the detectors have been tested under thermal and fast neutron irradiation and also at high/elevated temperature (300°-500°C). Three neutron sources have been used which are Cf-252 (2.15 MeV), AmBe (4.5 MeV) and Deuterium-Tritium (D-T) neutron generator (14.5 MeV). In order to limit interferences, diodes have been positioned in a Faraday box. To increase the signal perceived, a Fast Pre Amplifier and a Charge Sensitive Pre Amplifier have been created and tested in the framework of the I-SMART project.
Analyses reveal that SiC detectors, under irradiation and at elevated temperature, respond to neutrons showing consistent counting rates as function of external reverse bias voltages and radiation intensity.

In recent times, ever increasing attention has been devoted to trilayer graphene and its stacking and electric field dependent electronic properties. In nature, two stable forms of trilayer graphene are known to exist- i.e., Bernal (ABA) and rhombohedral (ABC) - which differ for the vertical stacking of the individual carbon layers. Among the two allotropes, ABC-stacked trilayer graphene is surely the most appealing for electronic applications as it possesses a tunable band-gap. However, the alluring rhombohedral phase is quite rare in nature as the energetically favored Bernal stacking makes up for more than 80% of the existing graphite. Clearly, in order to open a route towards the fabrication of gap-tunable trilayer devices, a way to synthesize large areas of ABC-stacked graphene need to be found.
To date, despite the large amount of interest for trilayer graphene, a direct experimental visualization of its electronic band structure has not yet been reported. In this work, we present angle resolved photoemission spectroscopy (ARPES) data that show with high resolution the band structure of ABA and ABC-stacked trilayer graphene obtained on silicon carbide (SiC) via hydrogen intercalation. We demonstrate that trilayer domains on SiC extend over areas of tens of square micrometers, suggesting the feasibility of exploiting this material in electronic and photonic devices. Notably our results indicate that on SiC substrates the occurrence of ABC-stacked trilayer is significantly higher than in natural bulk graphite. For ABC stacks and in the presence of an electrostatic asymmetry, we detect the existence of a band-gap of about 120 meV. Hence, growing trilayer graphene on SiC might be the answer to the challenge of controllably synthesizing ABC-stacked trilayer - an ideal material for the fabrication of a new class of gap-tunable devices.
C. Coletti et al., Phys. Rev. B 88, 155439 (2013)

Graphene is currently one of the most promising nano- materials, thanks to the extraordinary physical, electronic and mechanical properties of its pristine form. Nevertheless, the full understanding and control of its properties, and the unlocking of its large potential for micro- and nano- devices, have been hindered so far by the lack of a reliable method to obtain structured graphene in a controlled and reproducible fashion. This would be best achieved at the wafer- level.
The only feasible wafer-level route to-date is based on the use of SiC wafers to obtain high-quality graphene from Si sublimation in the 1300-1600°C temperature range [1]. However, prohibitive costs associated to the use and processing of SiC wafers are a major limitation. Attempts to produce wafer-scale graphene through sublimation from the cheaper SiC epitaxial layers on Si wafers have been widely reported [2]. Invariably, the quality of such graphene has been significantly inferior to that obtained from SiC wafers.
We have explored the use of epitaxial SiC on silicon as substrate for wafer -level graphene through the use of metal catalysts. We report for the first time in literature the achievement of high- quality graphene around 1050°C with a controlled number of layers on epitaxial SiC on Si by adjusting the ratio of a Ni:Cu alloy catalyst film [3]. As the few-layers-graphene is obtained at the SiC/metal interface, the catalytic layer can be removed via wet etch, leaving behind the graphene on SiC ready to be used in a device with no need for manual transfer. The pre-patterning of SiC on Si allows for a self-aligned synthesis of the few-layers-graphene.
This finding opens, on the one hand, the first realistic avenue to a mass production of graphene devices and their integration with the mainstream electronic systems in CMOS technology. On the other hand, this capability opens the opportunity for very controlled and reproducible studies of the fundamental mechanical and electronic properties of few-layers-graphene through the realization of graphene/SiC structures, devices and tailored interfaces via conventional silicon fabrication technologies.
[1] W.De Heer, C.Berger, M.Ruan, M.Sprinkle, X.Li YH, B.Zhang, et al. Large area and structured epitaxial graphene produced by confinement controlled sublimation of silicon carbide. PNAS 2011;108.
[2] H.Fukidome, Y.Kawai, H.Handa, H.Hibino, H.Miyashita, M.Kotsugi, et al. Site-selective epitaxy of graphene on Si wafers. Proc of the IEEE 2013.
[3] F.Iacopi, B.V.Cunning, M.Ahmed, Sept 2013, patent pending.

Graphene-based gas sensors normally show ultra-high sensitivity to certain gas molecules while suffering from poor selectivity and slow response and recovery. Several approaches based on graphene functionalization have been demonstrated to improve these issues, but most such measures result in poor reproducibility.
Here we report on surface modifications of epitaxial graphene on SiC (EG) with metal and metal-oxide nanostructures, formed by highly reproducible thin film deposition techniques, and their effect on the electronic properties of the graphene and on gas interactions at the graphene surface. It is demonstrated that under the right metallization or decoration conditions the electronic properties of the surface remain those of graphene, while the surface chemistry can be modified to improve sensitivity, selectivity and speed of response toward e.g. nitrogen dioxide (NO2) or certain toxic volatile organic compounds (VOCs). These gases are important to monitor for indoor air quality control due to their high toxicity already at parts per billion (ppb) concentrations.
We have previously demonstrated that monolayer graphene is crucial for optimum gas sensitivity [1]. This is guaranteed by our optimized epitaxial growth process [2]. Surface potential mapping by scanning Kelvin probe microscopy showed a distribution of about 90% single and 10% bilayer graphene, where the contrast arises from their differing work functions [3]. After metallization the morphology showed the formation of metal grains. However, surface potential mapping demonstrated that the electronic properties of the surface remain those of graphene.
Chemiresistor sensor devices were manufactured on the EG by deposition of Ti/Pt electrodes and subsequent mounting onto a sensor header with integrated heater and temperature sensor. The sensor response to ppb amounts of NO2 was evaluated at room temperature and at 100°C for sensors with and without surface modification. Decoration with Au gave a significantly larger and faster response to ppb concentrations of NO2 compared to the as-grown graphene, with a detection limit below 1 ppb. In general, the sensitivity, selectivity and response time to NO2 are significantly affected upon modifying the graphene surface by the addition of thin, nanostructured Au or Pt, and the effect is strongly dependent on the choice, thickness and nanostructure of the metal [4]. It is expected that decoration with different metals or metal-oxide nanostructures will allow careful targeting of selectivity to specific molecules. Indeed, we will present preliminary results indicating that decoration with SnO2 quantum dots can be used in a similar way to selectively detect ppb concentrations of certain toxic VOCs.
[1] R. Pearce et al., ACS Nano 7 (5), pp 4647-4656 (2013)
[2] R. Yakimova et al., Mater. Sci. Forum 565-568, 645 (2010)
[3] J. Eriksson et al., Appl. Phys. Lett.100, 241607 (2012)
[4] J. Eriksson et al., Physica B (2013), accepted.

Graphene has unique properties and hence the potential to overcome Si limitations in the development of nanoscale electronic. Graphene obtained from thermal decomposition of 3C SiC/Si is more appealing in terms of cost effectiveness compared to the one obtained from bulk SiC. The considerable advantage of this method is that graphene can be grown directly on the Si substrate where the rest of the electronic circuitry can be developed. Additionally, thermal decomposition in ultra-high vacuum (UHV) gives origin to a contaminant free surface. The general phenomenon of high temperature annealing of SiC includes the diffusion and sublimation of Si atoms leading to different surface reconstructions depending on the temperature. It has been reported that the challenge in UHV annealing of SiC/Si is to control the Si diffusion. The rate of Si out-diffusion in UHV annealing is higher compared to furnace annealing under Ar at atmospheric pressure.
Graphene was grown by annealing 3C SiC/Si (111) and 3C SiC (100) substrates in UHV for 10 mins [2]. We investigated the diffusion of Si in SiC/Si during UHV annealing at temperatures ranging from 1125^oC to 1375^oC in order to produce epitaxial graphene. We have also studied the effect of the exposure to Si flux at 900^oC before the final annealing stage. In-situ chemical compositions and surface morphology characterisations were investigated by using XPS and STM. Ex-situ surface analysis was performed by Raman spectroscopy.
The number of graphene layers was calculated by using the intensity ratio of XPS graphitic and carbidic peak of SiC. The results show an exponential increase in the number of graphene layers with the increase of temperature, which was fitted to an Arrhenius law. This behaviour is discussed in terms of the Si atom diffusion mechanism through the atomic lattice. The diffusion rate of Si atoms was moderately minimised by depositing Si at 900^oC before the final annealing. The change in atomic structure between single and multi layer graphene was confirmed by STM images. Raman 2D band intensity behaviour confirmed the increase of the graphitic layers leading to a similar Arrhenius law [3].
Further studies are in progress.
[1] A K.Geim, Science 324, 1530 (2009)
[2] A.Ouerghi, et al. Applied Physics Letters, 96, (2010).
[3] A. Ferrari, et al. Physical review letters 97(18), 187401 (2006).

Epitaxial graphene on silicon carbide (SiC) is promising for graphene-based electronic devices. The standard procedure to obtain graphene is to heat a Si-face SiC(0001) surface to 1100-1300°C in ultrahigh vacuum (UHV), which results in the sublimation of Si. However, this simple process produces a SiC surface with a pitted morphology, which probably degrades the transport properties of graphene on it.
The pitted morphology originates from the rapid and random sublimation of Si from the terraces that are not covered by a carbon-rich 6radic;3×6radic;3 layer, i.e., a buffer layer. Thus, a strategy to avoid the pitted morphology is to form a homogeneous buffer layer on the entire SiC surface.
In this study, we propose the deposition of C atoms at the monolayer level on a Si-face SiC(0001) surface by plasma oxidation at room temperature followed by HF etching. When a SiC surface was exposed to atmospheric-pressure plasma (He+O₂) at room temperature, the surface layer was oxidized to SiO₂. It is presumed that most of the C atoms were emitted in the gas phase as CO or CO₂. However, after the surface oxide was stripped off by immersion into HF solution, C atoms at the monolayer level were observed to have accumulated at the SiO₂/SiC interface, as revealed by X-ray photoelectron spectroscopy (XPS). We expect that the kinetic energy of the remaining C species was too low for them to have been emitted in the gas phase, because the enriched C layer at the SiO₂/SiC interface was not observed in the case of conventional thermal oxidation at approximately 1000°C. This process is unique because neither UHV nor a high temperature is required to selectively remove the outermost Si atoms from the SiC surface.
We prepared two samples to investigate the impact of the C-rich layer on the quality of graphene. One was a C-rich SiC surface obtained by plasma oxidation followed by HF dipping. It was then subjected to prolonged annealing at 1100°C for 30 min in UHV to form graphene (Sample A). The other was an untreated SiC surface that was subsequently annealed at 1100°C for 30 min in UHV (Sample B). For both samples, we used an atomically flat 4H-SiC(0001) surface created by catalytic reactions in HF solution [1-2]. This enabled us to suppress the formation of bunched SiC steps higher than 1.0 nm. Atomic force microscopy images revealed that the graphene on Sample A had much fewer pits than that on Sample B. This is probably because the enriched C layer on the SiC surface promoted the formation of a homogeneous buffer layer, which protected the SiC terraces from the rapid sublimation of Si.
[1] K. Arima et al., Appl. Phys. Lett. 90, 202106 (2007).
[2] K. Arima et al., J. Phys.: Condens. Matter 23, 394202 (2011).

Carbon nanomaterials have been the focus of intense research over the past several decades which includes materials such as carbon nanotubes (CNTs), carbon nanofibers (CNFs), and more recently gra-phene. With state-of-the-art synthesis techniques coupled with their remarkable properties, such materials hold the promise for technologically advancing numerous fields. Vertically grown and aligned individual CNFs, and arrays of CNFs with controlled spacing and dimensions, offer a unique nanomaterials platform for designing and engineering new types of nanoelectromechanical systems (NEMS). Vertically oriented NEMS, particularly resonant NEMS in vertical CNFs arrays with designed densities, have potential implications for sensing and communication devices, especially for harsh environments (e.g., for some of NASA&’s extreme environment missions, including high radiation conditions). Almost all of today&’s NEMS devices and resonators have been based on patterned nanostructures yielded by lithographic planar processes, or chemically synthesized nanofibers (or nanotubes, nanowires) that are harvested after growth and then painstakingly assembled into planar processes on chip. In this work, we report on the experimental demonstration of new resonant NEMS based on sub-100nm thin CNFs that are synthesized by using a plasma-enhanced chemical vapor deposition (PECVD) process. Beyond careful and extensive materials characterization of the CNFs, we have prototyped few-mu;m-long, cantilever-like CNF mechanical resonators with measured flexural resonances in the range of ~3-15 MHz and with quality (Q) factors of ~200-800. Based on the measurement and analysis of electromechanical properties of the CNFs, we then devise innovative schemes to engineer the vertical CNFs and arrays into NEMS devices for both quasi-DC and resonant operations. These new vertical NEMS will pave the way for a range of systems and new applications where non-planar processes and three-dimensional integration are desired. In addition to these new devices from one-dimensional (1D) carbon nanostructures, we will also present NEMS resonators and switching devices based on two-dimensional (2D) carbon - graphene nanomembranes that operate at high frequencies. Toward the latter part of the talk, an overview of 2D layered materials will also be presented, which complement and extend graphene&’s remarkable properties.

Silicon carbide is well-known as a wide-band gap semiconductor for use in electronic and optoelectronic applications at high powers, temperatures and radiation environments due to its high breakdown field, wide band gap, radiation hardness and thermal conductivity. Furthermore, it offers a high quality, semi-insulating substrate for use in III-N growth for high frequency electronics due to its relatively low lattice mismatch with GaN and AlN and its high thermal conductivity. Over the past 20 years, dramatic progress in materials and device quality has been realized leading to extremely low-defect density substrates and epilayers. During this same period, significant effort has also been focused on the field of metal-based plasmonics and its applications in enhanced spectroscopy, light emitters, waveguides, and absorbers for photodetectors. However, while plasmonic systems have attracted attention for their ability to achieve extreme sub-diffraction limit confinement with large concentrations of electromagnetic fields at optical frequencies, applications are severely limited by the inherent optical losses caused by the high carrier densities within metals. It has been shown previously that an alternative to plasmonic metals in the mid-infrared-THz spectral ranges are polar dielectrics such as silicon carbide, whereby such large, sub-diffraction limited, localized electromagnetic fields can be sustained through the optical stimulation of plasmon-like surface phonon polaritons (SPhPs). Unlike plasmons, these SPhP modes do not require the presence of free carriers, and thus exhibit exceptionally low optical losses.
Initial investigations into SiC for SPhPs began in the early part of the last decade and proof-of-principle experiments demonstrated that both localized and propagating SPhP modes could be supported. Recently, our group has demonstrated the first nanofabricated localized SPhP resonators. These nanostructure arrays exhibited optical resonances in the 10.3-12.5 um spectral range. The structures used varied in heights from 150-1500 nm-tall nanopillars fabricated from semi-insulating 6H- and 4H-SiC and had diameters ranging from 150-1000 nm and interpillar separations between 20-10,000 nm. These structures have enabled the understanding of local electromagnetic field distributions and intensities as a function of nanostructure size and interpillar separation. The low optical losses resulted in exceptionally narrow resonance linewidths of 3-24 cm^-1, corresponding to quality factors in the 40-300 range. It is important to note that the theoretical limit for plasmonic systems is a quality factor of 40 for a silver sphere.

Crystalline silicon carbide is chemically inert and it has high electric breakdown strength, thermal conductivity and mechanical strength, which make it an excellent material for numerous high-temperature applications including high-voltage and high-current devices, and sensors for harsh environments. This paper presents a novel SiC optical detector that operates on the principle of semiconductor optics and produces optical signal in contrast to the electric signal generated by conventional electrical detectors. The optical detector is a remote sensor providing response to incident photons from a distant object. In this study the SiC detector is fabricated by doping an n-type 4H-SiC substrate with gallium using a laser doping technique. Since Ga creates an acceptor level corresponding to a quantum of wavelength 4.21 mu;m, which falls in the midwave infrared (MWIR) range, the device acts as a MWIR detector.
The incident MWIR photons modify the reflectivity of the doped SiC by altering the electron densities in the valence band and the acceptor energy levels. This change in the reflectivity represents the optical signal as the detector response, which is determined with a probe laser such as a He-Ne laser or a light-emitting diode. The device can be used as a chemical sensor since many chemicals emit photons in the MWIR range. It is readily amenable to chemical sensing in high-temperature or harsh environments due to the capability of remote read-out of the detector response with a probe laser. It can also be used as an uncooled detector for MWIR imaging applications with an appropriate focal plane array of the detectors, since it does not require any cooling to generate the signal. The effects of different dopants on the detector response have been studied and the dopant concentration has been found to affect the optical signal. These results indicate that a new class of SiC detectors, which operate based on optical signals, can be produced for a variety of wavelengths using different dopants for numerous applications.

One method of exploiting solar energy is to use photovoltaic cells which convert the energy conveyed by the incident radiation into a continuous electric current. This conversion is based on the photovoltaic effect created by the absorption of photons. A part of the absorbed photons generates electrons-holes pairs which are separated by an electric field created in the depletion region of the p-n junction. A way of amplifying this current is to reduce the thickness of the first exposed zone through which photons must travel to reach the p-n junction, which absorbs a part of the incident light. This approach is possible with a layer of wide band- gap silicon carbide which absorbs the most efficient part of the spectrum (UV). Indeed, silicon carbide is a strategic material to use in extreme environments such as high frequencies, high temperatures or with high power. It possesses great possibilities for applications in the field of optoelectronics.
Recently, heterojunction 3C-SiC/Si solar cells have been produced at the CRHEA (Research Center on Hetero-Epitaxy and its Applications) in Nice, France, which has at our knowledge never done before. This open the way for Silicon Carbide as Solar cell Material.
In this document, we firstly measure the optical characteristics of cubic silicon carbide (3C or β-SiC) layers with several doping level deposited on (100) oriented silicon wafers using CVD (Chemical Vapor Deposition). Ellipsometric Measurements are made in the ultraviolet range, the refractive indices values observed for various doping levels are close to the value given in the literature, which is 2.696 [1] .Secondly, we study the electrical properties of our solar cells for the same SiC doping levels. Current-Voltage Characteristics show a pronounced photovoltaic effect. Spectral sensitivity curves will be presented in the final paper.
[1] Refractiveindex.Info SiC (Silicon Carbide) Handbook of optics: β-SiC