Symposium Organizers
Soeren Steudel IMEC
Shelby F. Nelson Eastman Kodak Company
Veit Wagner Jacobs University Bremen
Heiko Thiem Evonik Degussa GmbH
F1: Organic Semiconductor Material
Session Chairs
Monday PM, November 29, 2010
Room 309 (Hynes)
10:00 AM - **F1.1
Designing Solution-processable Materials for Organic Thin-film Transistors.
John Anthony 1
1 , University of Kentucky, Lexington, Kentucky, United States
Show AbstractThe drive for low-temperature processing in organic electronics has hastened the development of new materials that are conveniently processed from solution. Because highly crystalline organic materials are required for high field-effect mobilities, semiconductors must be carefully designed to allow for rapid crystallization during solvent-casting. This talk will focus broadly on our functionalization strategy to yield soluble, highly crystalline material, with detailed case-studies on functionalization studies that improve intermolecular close-contacts, accelerate the rate of crystallization and improve stability of these otherwise reactive aromatic molecules. For instance, the symmetry of the solubilizing groups has a significant impact on lateral and longitudinal shift of the chromophores in the solid state, and this phenomenon can be used to fine-tune crystal packing to yield enhanced mobility. Other desymmetrization of the chromophore leads to severe degradation of the observed transistor performance. Using derivatives substituted on only one end with a variety of functional groups changes the packing dramatically, typically yielding the less-desirable 1-D pi-stacking motif. Desymmetrization by increasing chromophore length leads to reasonable short-range order but signifiant long-range disorder, due to a lack of preferred orientation between adjacent pi-stacked systems. Further increases in chromophore length that re-symmetrize the system restore the desired pi-stacking motifs. However, with such large linearly-fused chromophores, strategies must be developed to stabilize the semiconductor against the most common decomposition pathways.
10:30 AM - F1.2
High Mobility TIPS-Pentacene Field Effect Transistors (FETs) Fabricated Using Solution Shearing.
Gaurav Giri 1 , Eric Verploegen 1 2 , Hector Becerril 3 , Alberto Salleo 4 , Michael Toney 2 , John Anthony 5 , Zhenan Bao 1
1 Chemical Engineering, Stanford University, Stanford, California, United States, 2 Stanford Synchrotron Radiation Lightsource, Stanford University, Stanford, California, United States, 3 Chemistry, Brigham Young University, Rexburg, Idaho, United States, 4 Material Science and Engineering, Stanford University, Stanford, California, United States, 5 Chemistry, University of Kentucky, Lexington, Kentucky, United States
Show AbstractSolution deposition of organic semiconductors (OSC) is a leading contender for producing large-area, inexpensive, and flexible organic electronics. A recently developed solution shearing method (SS) has demonstrated better organic field effect transistor (OFET) performance compared to simple drop casting or spin casting methods. In this method, an organic semiconductor (OSC) solution is sandwiched between two substrates, a non wetting ‘shearing substrate’ and a wetting ‘device substrate’; the latter is heated to a controlled temperature. As the OSC solution is sheared by translating the upper shearing substrate, semiconductor crystallization occurs on the bottom device substrate. Using the well-studied small molecule OSC 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS-Pn), SS has achieved a wide range of reproducible morphologies, which results in differing FET performance. SS can be used to vary many deposition conditions, such as OSC concentration, deposition temperature, shearing speed, etc. Certain conditions have yielded remarkable FET performance. The best shearing conditions yield large area films (> 4 cm^2) on which FETs show an average charge carrier mobility of > 2 cm^2/Vs with transistors showing mobilities as high as 4.7 cm^2/Vs, a current On/Off ratio of > 10^6, low hysteresis and a threshold voltage of -10 V. This is the best performance in terms of mobility for TIPS-Pn that has been reported in literature. We quantitatively measure the molecular ordering resulting from SS and how this ordering impacts charge carrier performance, and we investigate the relationship between the morphological anisotropy and anisotropy in the charge carrier transport. Finally, this study also outlines whether SS can impart the same morphological characteristics and increased charge transport performance for other OSCs.
10:45 AM - F1.3
Polymer and Nanoparticle Mediated TIPS-Pentacene Crystallization: Towards Enhanced Performance Consistency in Small-molecule-based Solution Processible Organic Thin-film Transistors.
Zhengran He 1 , William Durant 1 , Kai Xiao 2 , John Anthony 3 , Jihua Chen 2 , Michael Kilbey 2 , Dawen Li 1
1 Electrical and Computer Engineering, The University of Alabama, Tuscaloosa, Alabama, United States, 2 Center for Nanophase Materials Sciences, Oak Ridge National Lab, Oak Ridge, Tennessee, United States, 3 Deparment of Chemistry, University of Kentucky, Lexington, Kentucky, United States
Show AbstractOrganic thin-film transistors (OTFTs) with 6,13-bis(triisopropyl-silylethynyl)-pentacene (TIPS-pentacene) active layers have attracted much attention due to their room-temperature, solution-based deposition process and impressively high mobility ( up to 1.8 cm2/V.s).[1] However, OTFTs based on TIPS-pentacene polycrystalline films severely suffer from crystal growth anisotropy, which results in poor performance consistency.[2] In this work, in order to mediate the crystallization of TIPS-pentacene, SiO2 nanoparticles (~20 nm) or polymers are mixed with TIPS-pentacene in solution, and subsequent drop-casting of the blend solutions yields uniform film morphology with enhanced average mobility and significantly reduced performance variation. With a top-contact configuration and without hexamethyldisilazane (HMDS) treatment on substrate, the field-effect mobility from pure TIPS-pentacene films varies dramatically from 0.5 to 5×10−3 cm2/V.s, while TIPS-pentacene blends with 2-10% silicon dioxide nanoparticles consistently demonstrate mobilities of 0.1-0.4 cm2/V.s. In addition, three polymers with different crystallinity and solubility parameters: poly(vinylidene fluoride-hexafluoropropylene) (PVDF-HFP, solubility parameter δPVH= ~23 [MPa]1/2), poly(α-methyl styrene) (PαMS, δPαMS= 18.8 [MPa]1/2) and polyisobutylene (PiB, δPiB= 15.6 [MPa]1/2) are blended with TIPS-pentacene (δTP= 18-19 [MPa]1/2)[3]. The polarity- and polymer crystallization-driven phase separation in these systems are systematically correlated with device performance, optical microscopy, and X-ray diffraction. Interestingly, PVDF-HFP introduces lateral phase separation in the blend films while the other two polymers resulted in vertical phase separation with TIPS pentacene domains. Unlike the situations in pure TIPS-pentacene transistors, HMDS treatments on gate dielectrics turn out to reduce the device performance in the polymer/TIPS-pentacene system, most likely caused by the modified film/substrate interfacial energies upon polymer addition. Average mobilities of up to 0.2 cm2/V.s are achieved in these polymer/small molecule blend systems with optimized substrate treatment, device configuration and drop-casting conditions.[1] Park, S.K., Jackson, T.N., Anthony, J.E., Mourey, D.A., Appl. Phys. Lett., 91, 063514 (2007)[2] Chen, J., Tee, C.K., Shtein M., Martin D.C., Anthony, J.E., Org. Electron., 10, 696 (2009)[3] Chen, J., Martin D.C., Anthony, J.E., J. Mater. Res., 122, 1701 (2007)
11:00 AM - F1:OMaterial
BREAK
11:30 AM - **F1.4
High-mobility Organic Thin-film Transistors with Improved Shelf-life Stability.
Hagen Klauk 1
1 , Max Planck Institute for Solid State Research, Stuttgart Germany
Show AbstractPentacene is one of the most popular small-molecule semiconductors for organic p-channel thin-film transistors (TFTs), because it provides relatively large field-effect mobilities of about 1 cm2/Vs [1]. However, pentacene is very susceptible to oxidation, so the carrier mobility of pentacene TFTs degrades rapidly when the devices are exposed in air [2]. Recently, a six-ring fused heteroarene, dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (DNTT), has been synthesized that has a crystal structure and a thin-film morphology very similar to those of pentacene, but which is much less susceptible to oxidation [3]. As a result, the field-effect mobility of DNTT TFTs is as large as that of pentacene TFTs, but the DNTT devices have much better shelf-life stability [3,4]. We have fabricated flexible low-voltage DNTT TFTs that have hole mobilities between 1 and 2 cm2/Vs and on/off current ratios between 107 and 108. Due to the better oxidation resistance, the mobility of the DNTT TFTs degrades much less rapidly compared with pentacene TFTs: While the mobility of the pentacene TFTs decreases by about an order of magnitude within just a few months, the mobility of the DNTT TFTs is still about 70% of its initial value after 8 months of continuous exposure to air. Using a low-temperature shadow-mask process we have also fabricated flexible unipolar ring oscillators based on DNTT TFTs and measured signal propagation delays as low as 11 µsec per stage, which is within a factor of 30 of the fastest organic ring oscillators reported to date [5], despite the more relaxed design rule (10 µm instead of 2 µm) and despite the smaller supply voltage (3 V instead of 10 V). [1] C. Rolin et al., Appl. Phys. Lett., vol. 89, p. 203502 (2006). [2] H. Klauk et al., Adv. Mater., vol. 19, p. 3882 (2007). [3] T. Yamamoto et al., J. Am. Chem. Soc., vol. 129, p. 2224 (2007). [4] U. Zschieschang et al., Adv. Mater., vol. 22, p. 982 (2010). [5] K. Myny et al., Org. Electronics, vol. 11, p. 1176 (2010).
12:00 PM - F1.5
A New Solution-process for High Mobility and Small Variation in Organic TFT Performance via Liquid Crystal Film.
Hiroaki Iino 1 2 , Jun-ichi Hanna 1 2
1 Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, Yokohama, Kanagawa, Japan, 2 , JST-CREST, Yokohama, Kanagawa, Japan
Show AbstractThe materials research for organic thin film transistors (OTFTs) has been extended to exploration of materials suitable for fabrication of crystalline thin films by solution processes. It is reported that solution processed OTFTs fabricated with polycrystalline thin films such as TIPS-pentacene and beozothienobenzothiophenes (BTBT) derivatives show high field effect transistor (FET) mobility over 1 cm2/Vs. Uniformity of the solution-processed films, however, is not so good as those of polymer and vacuum evaporated films because of recrystallization of materials during the solution processes: in fact, we often get a wide variation of FET performance in the solution processed OTFTs. In this paper, we propose a new solution-process using liquid crystalline films as a precursor for polycrystalline thin films for OTFTs. We selected two liquid crystalline materials as model compounds, i.e., dialkylated-terthiophene and BTBT derivatives, 8-TTP-8 and C10-BTBT, respectively. These materials are crystals at room temperature and exhibit liquid crystal phase in a certain elevated temperature range. We spin-coated solutions of these materials on thermal oxidized Si wafer at the liquid crystalline temperatures in an oven, and then cooled them to room temperature in order to make them crystallized. The spin-coating solutions of 8-TTP-8 and C10-BTBT in liquid crystal phases at 88 oC and 113 oC, respectively, gave quite uniform crystalline films: we could not see any structures on the surface of the crystalline films in hundreds micron scale by optical microscopy and laser microscopy; the films were molecularly flat and exhibited wide terrace structures over 10 μm from AFM images. FETs fabricated with 8-TTP-8 exhibited a small variation of FET mobility of 0.14 cm2/Vs, and TFTs fabricated with C10-BTBT exhibited FET mobility of 3 cm2/Vs, which is three times higher than those of crystalline film spin-coated at room temperature and successive post thermal annealing previous reported and as good as those of the films fabricated by vacuum evaporation. We discuss the origin of these good performances of TFTs fabricated via liquid crystalline phase, in addition to a new result on new OTFT materials with process-durability and high FET mobility over 1 cm2/Vs.
12:15 PM - F1.6
Solution Processed n-Channel Organic Field-effect Transistors with High Uniformity and Electrical Stability.
Shree Tiwari 1 , Keith Knauer 1 , William Potscavage 1 , Bernard Kippelen 1
1 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractWe report on high performance n-channel organic field-effect transistors (OFETs) based on solution-processed [6,6]-phenyl C61 butyric acid methyl ester ([60]PCBM) with very good uniformity, electrical stability, and reproducibility. In our previous studies, solution-processed n-channel OFETs with [60]PCBM have been shown to produce electron mobility values higher than 0.1 cm2/Vs on the inorganic gate dielectric layers of thermally grown SiO2 or HfO2 deposited by atomic layer deposition (ALD) passivated with a thin buffer layer of crosslinkable divinyltetramethyl-disiloxanebis(benzocyclobutene) (BCB) on top, resulting in 30 V or 3 V operation respectively [1, 2]. BCB was used to minimize electron trapping at the dielectric/semiconductor interface, which is the primary limiting factor for n-channel conduction [3]. Here, we demonstrate the very high uniformity and reproducibility in [60]PCBM OFETs on Al2O3 by ALD)/BCB dielectric layer by fabricating several devices on the same substrate. On a single substrate, 64 devices with channel width (W) of 1000 μm and 32 devices with W = 2000 μm were fabricated. To calculate the average performance parameters, 16 (W = 1000 μm) or 8 (W = 2000 μm) devices of identical geometry were taken into account for channel lengths (L) of 25, 50, 100 and 200 μm. The 16 devices with W/L of 1000 μm/100 μm operated at 10 V exhibit excellent n-channel performances with an average electron mobility value of 0.11 ± 0.01 cm2/Vs and an average threshold voltage (VTH) of 1.6 V. The same number of devices with W/L of 1000 μm/50 μm exhibited similar average electron mobility value of 0.11 ± 0.01 cm2/Vs with average VTH of 2.0 V. All the devices exhibited high current on/off ratios (105-106) and sub-threshold slopes of about 0.4 V/decade. Transfer characteristics scanned for 3000 times at a time interval of 1 second between scans showed very good reproducibility of electrical characteristics in N2 atmosphere without any significant change in the performance parameters. After a continuous DC bias stress (VGS = VDS = 10 V) for 12 hours, the devices showed a decay of ~ 20% in drain current. Our results show that [60]PCBM can produce highly uniform and electrically stable n-channel OFETs on inorganic dielectrics with a BCB buffer layer on top.
[1] S.P. Tiwari, X.-H. Zhang, W.J. Postcavage, Jr., and B. Kippelen, J. Appl. Phys. 106, 054504 (2009).
[2] S.P. Tiwari, X.-H. Zhang, W.J. Postcavage, Jr., and B. Kippelen, J. Appl. Phys. 95, 223303 (2009).
[3] L.-L. Chua, J. Zaumseil, J.-F. Chang, E.C.W. Ou, P.K.H. Ho, H. Sirringhaus, and R.H. Friend, Nat. 434, 194 (2005).
F2: Dielectrics for TFTs
Session Chairs
Monday PM, November 29, 2010
Room 309 (Hynes)
2:30 PM - **F2.1
Fabrication and Stability of Low-temperature Solution-processed Organic Transistors.
Alberto Salleo 1 , Youngmin Park 1 , Leslie Jimison 1 , Jonathan Rivnay 1 , Tobin Marks 2 , Antonio Facchetti 3 2
1 , Stanford University, Stanford, California, United States, 2 Chemistry , Northwestern University, Evanston, Illinois, United States, 3 , Polyera Corp., Skokie, Illinois, United States
Show AbstractThere is great interest in being able to fabricate transistors from liquid precursors at temperatures lower than ~120°C, which makes them compatible with low-cost flexible substrates. We describe the fabrication of a hybrid organic/inorganic TFT from solution using a high capacitance sol-gel ZrOx dielectric cured at room temperature and an unannealed semiconducting polymer. The TFT swings from completely off to completely on within 3V on the gate, has an on/off ratio of the order of 105 and exhibits a mobility of approximately 0.2 cm2/V.s.While favorable static device characteristics are necessary conditions to make a dielectric/semiconductor pair technologically interesting, they are not sufficient. Gate bias stress for example has been studied in order to determine whether electrical device stability is satisfactory. In this regard, an “accelerated testing” procedure will be proposed to quickly determine the stabilized threshold voltage of organic transistors. From the materials standpoint, recently bias stress has been associated to water at the semiconductor/dielectric interface. By using directionally crystallized films of an n-type semiconductor (PDI8-CN2) processed at low temperature from solution, we will show that bias stress also depends on intrinsic properties of the semiconductor layer, such as its microstructure.
3:00 PM - F2.2
Low Cost Solution-processed High-k Gate Dielectric Materials for Large Area Circuit Applications.
Wan-Yu Lin 1 2 , Robert Mueller 1 , Kris Myny 1 , Soeren Steudel 1 , Jan Genoe 1 , Paul Heremans 1 3
1 , imec, Leuven Belgium, 2 Metallurgy and Materials Engineering(MTM), Katholieke Universiteit Leuven , Leuven Belgium, 3 Department of Electrical Engineering(ESAT), Katholieke Universiteit Leuven , Leuven Belgium
Show AbstractOne of the key challenges to manufacture low cost circuits (e.g. RFID tags, row driver) and backplanes on flexible substrates lie in the realization of reliable gate-dielectric with a high specific capacitance required for low voltage, high current drive. Flexible substrates necessitate deposition techniques with process temperatures lower than 150°C, making the production of high quality gate dielectric materials more difficult. Here we show a promising integration scheme for thin film circuits using anodization. Aluminium oxide can be fabricated easily and inexpensively by anodization of aluminium at room temperature, giving rise to an ultra-thin, smooth, and dense gate dielectric. Up to now, however, only single OTFTs have been shown with an anodized gate-dielectric. The reason is the difficulty of realizing two independent patterned metallization layers for source/drain and gate, which is required for circuits and AM-OLED backplanes. We show that only a uniform film of Al gives rise to a controlled and uniform oxide over large area. A novel method is also demonstrated to pattern the gate (aluminium) and overlying gate oxide (aluminium oxide) into individual islands, and to process source-drain contacts without side leakage between source and gate at the edge of these islands. Furthermore, we have fully characterized the properties of our anodized aluminium oxide, by demonstrating OTFT’s and unipolar circuits (inverter, 19-stage ring oscillator) with channel-length down to 3um at supply voltages as low as 2V.
3:15 PM - F2.3
High-k Gate Insulators for Thin Film Transistors Grown by Remote Plasma Atomic Layer Deposition.
Fu Tang 1 , Chiyu Zhu 1 , Robert Nemanich 1
1 Department of Physics, Arizona State University, Tempe, Arizona, United States
Show AbstractHigh-k oxides have been widely employed in the Si based nanoscale transistors in order to reduce the gate tunneling current and energy consumption. Recently, the application of high k dielectrics is also emerging in other semiconductor areas including as thin film transistors (TFTs) for flexible electronics. A high-k gate dielectric layer can significantly reduce the threshold voltage, increase the on/off current ratio and enhance the mobility of TFTs. One of the limiting factors in implementing high-k materials for flexible electronics is the development of a low temperature deposition process. In this work, we investigated the growth of Hf oxide, La oxide, and a Hf-oxide/La-oxide layered structure using remote plasma atomic layer deposition (ALD) at temperatures ranging from ~80°C to ~250 °C. The atomic bonding structure of the film was determined by in situ XPS. In a remote plasma process, the activated oxygen species enables a reduced temperature for ALD growth and ion induced damage to the film can be minimized. The XPS results indicated that for low temperature growth of pure Hf oxide, a significant amount of weakly bonded molecular oxygen was absorbed in the film deposited. This oxygen could lead to instabilities and adversely affect the function of TFTs. We established that increased the plasma power, resulted in a decrease of the amount of the absorbed oxygen. A post treatment of He or Ar plasma was also effective for removing the weakly bounded oxygen. We argue that the molecular oxygen is adsorbed at defect sites, and that the higher plasma power reduces the absorbed oxygen content either by diminishing the defected density and/or through photo-induced desorption. In addition, the pure Hf oxide films show a grained morphology which apparently reflects the polycrystalline nature of the Hf oxide. In order to suppress the crystallization of the oxide and to obtain a smooth morphology, we deposited 1-3 cycles of La-oxide between two adjacent Hf-oxide cycles. The multilayered films showed a significant improvement of the morphology compared with the roughness of the pure Hf oxide film. Process parameters were also identified that resulted in a relatively low concentration of carbon residue. *Work by US Army Cooperative Agreement W911NF-04-2-0005 (FDC-10-4.6)
3:30 PM - F2.4
UV Assisted Solution-based Zirconium Oxide Gate Dielectric for Low-voltage Operation of Organic Field Effect Transistors.
Young Min Park 1 , Alberto Salleo 1 , Juergen Daniel 2
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 , Palo Alto Research Center, Palo Alto, California, United States
Show AbstractOrganic field effect transistors (OFETs) have been attractive for low-cost and low-temperature processing of electronic devices such as RFID tags, sensors and electronic paper. For practical applications of OFETs, there is a need to develop nanometer-scale gate dielectric with high capacitance and low gate leakage current to achieve low-voltage operation. In this regard, inorganic high-κ metal oxide dielectrics have been investigated due to their high dielectric constant as well as the ability to functionalize their surface with self-assembled monolayers(SAM). Inorganic metal oxide, however, have required either vacuum processing or relatively high-temperature anneals, making them incompatible with low-cost solution processing on flexible substrates. Here, we demonstrate low-voltage polymeric OFETs operated below a gate voltage of -3V, fabricated with solution-processed zirconium oxide (ZrOx) at room temperature. ZrOx was deposited via a sol-gel process and cured by UV irradiation under ambient conditions, eliminating the need for a high-temperature anneal. UV irradiation decomposed the zirconium based sol-gel films into thin films composed of only Zr and O on a heavily doped Si substrate, as confirmed by X-ray photoelectron spectroscopy. The areal capacitance of UV cured dielectrics ranged from 470 to 522nF/cm2, and showed a dependence on UV irradiation time. Introduction of an Octadecyl-phosphonic acid (ODPA) SAM on the surface of ZrOx reduced the leakage current from the order of 10-4 A/cm2 to 10-7 A/cm2 at an applied voltage of -3V while making the dielectric more compatible with organic semiconductors. We demonstrate polymer OFET devices using poly(2,5-bis(3-dodecylthiophen-2yl(thieno[3,2-b]thiophene) (PBTTT C-14) on the solution-processed, UV cured ZrOx dielectric operating at low-voltage (|VGS|<3V) with high field effect mobility (µ~0.2 cm2/V.s) and high on-off current ratio (105~106).
3:45 PM - F2.5
Pressure Dependence on the Physical Properties of SiO2 Gate Oxide Formed by Inductive Coupled Plasma Oxidation.
Beomjong Kim 1 , Dongchan Kim 1 , Yoonjae Kim 1 , Hanjin Lim 1 , Jueun Kim 1 , Wookyeol Yi 1 , Daehyun Kim 1 , Bonghyun Kim 1 , Youngwan Kim 1 , Sungho Kang 1 , Youngseok Kim 1 , Woojun Lee 1 , Seokwoo Nam 1
1 , Samsung Electronics Co. Ltd., Hwasung Korea (the Republic of)
Show AbstractRecent semiconductor devices need low thermal budget process to scale down. The plasma oxidation is one of the most promising candidates. In this work, we investigated the pressure effect on the physical properties of the oxide grown by inductive coupled plasma oxidation. The activation energy (Ea) and electron temperature (Te) were calculated. The Te decreases as the pressure increases but the Ea increases with pressure. It is supposed that the pressure dependence on the Ea is related to the energy of oxygen ions participating in oxidation. In the low pressure region, ions are the major oxidants and they are accelerated by the plasma sheath potential. Because the potential is linearly proportional to the Te, the ions have more kinetic energy at the higher Te. These highly kinetic ions can easily break the Si-Si bonding and lower the energy barrier of oxidation. It reduces the Ea at low pressure below 100mTorr. In this case, the strong collisions can make the interfacial defect sites by damaging the initial silicon surface. The interfacial trap density estimated by charge pumping method shows the inverse proportionality with the pressure. At the higher pressure region, (> 100mTorr) the major oxidants are the oxygen radicals and the mean free path of these radicals decreases with pressure, the chance to reach at the silicon surface decrease. Thus, the Ea increases with pressure, although the Te is constant at over 100mTorr. The normalized field effective mobility is compared between samples of different pressures and the peak increases as the process pressure increases. For getting better interface, it is the key to lower the Te. From this point of view, the pressure is a very effective process parameter and it could come with an improved mobility and interface properties.
4:30 PM - F2.6
Precursor Design and Engineering for Low-temperature Deposition of Gate Dielectrics for Thin Film Transistors.
Anupama Mallikarjunan 1 , Laura Matz 1 , Andrew Johnson 1 , Raymond Vrtis 1 , Manchao Xiao 2 , Mark O'Neill 2 , Bing Han 1
1 , Air Products and Chemicals, Inc., Allentown, Pennsylvania, United States, 2 , Air Products and Chemicals, Inc., Carlsbad, California, United States
Show AbstractThe electrical and physical quality of gate and passivation dielectrics significantly impacts the device performance of thin film transistors (TFTs). As low temperature TFT processing becomes a requirement for novel applications and plastic substrates, there is a need for materials innovation that provides gate dielectrics having good density and dielectric constant (k), low leakage, low charge density (measured by flatband voltage or Vfb), low wet etch rate (WER), and high breakdown voltage (Vbd). The passivation dielectric also needs to act as a barrier to protect the TFT device. In this context, this paper discusses structure-property relationships and strategies for precursor development in silicon nitride, silicon oxycarbide (SiOC) and silicon oxide films; and demonstrates the value of precursor engineering for low temperature plasma enhanced chemical vapor deposition (PECVD) of SiO2 gate dielectrics (that are used with polysilicon TFTs for example). For SiO2 deposition, organosilicon precursors containing different types and amounts of Si, C, O and H bonding were experimentally compared to the industry standard TEOS (tetraethoxysilane) at different process conditions and temperatures. In general, carbon incorporation into these low temperature oxide (LTO) films was not detected by XPS or FTIR; and the O/Si ratio was between 2.1-2.2. However, major differences were identified in film quality especially WER (correlating to film density) and k values (correlating to moisture absorption). The paper will discuss a systematic methodology for optimization of the functionality of the precursors to enable superior performance over TEOS. It is advantageous to have precursors that are more plasma-driven and show less uncontrolled deposition as temperature is lowered. This is illustrated by the electrical performance with an optimized material, AP-LTO® 770. For example, under identical deposition conditions at 200°C, a TEOS SiO2 had a 6:1 BOE (Buffered Oxide Etch) WER of 538 nm/min vs 275 nm/min for AP-LTO® 770 film. This improvement comes due to higher density (measured by X –ray reflectivity) and lower moisture content (seen by FTIR) in the AP-LTO® 770 SiO2 films. Correspondingly, leakage current, k, Vbd, Vfb all show performance improvements over TEOS films. Additionally, the precursor has a lower B.P. than TEOS (B.P=169°C), simplifying current delivery and uniformity issues seen for large substrates. The design and development of such novel precursors is a key factor to successfully enable manufacturing of advanced low temperature processed devices.
4:45 PM - F2.7
Low-damage Preparation of SiO2 Dielectric Thin Film by the Photo-assisted Oxidation Processing.
Takehito Kodzasa 1 , Sei Uemura 1 , Kouji Suemori 1 , Manabu Yoshida 1 , Satoshi Hoshino 1 , Noriyuki Takada 1 , Toshihide Kamata 1
1 , National Institute of Advanced Industrial Science and Technology, Tsukuba Japan
Show AbstractWe have already reported that low-temperature (about 170C) preparation technique of SiO2 dielectric thin film that has high resistivity and extremely smooth surface by the photo oxidation processing. However convenient plastic films such as polyethylene terephthalate (PET), polystyrene (PS) and Poly(methyl methacrylate) (PMMA) are easily damaged by heating over 150C or light irradiation. Now, in this paper, we report that SiO2 thin film with high insulation performance can be obtained with no damage against light irradiation. And we show that the SiO2 dielectric thin film having high insulating property is prepared by the low-temperature processing below 100C by improving the pre- and post- processing of the photo oxidation of thin film.
5:00 PM - F2.8
Effect of Hydrogen on Electrical Performance of Charge-trapping Device Structure of SiAlON/Si3N4/SiO2/ Stacks.
Nam Nguyen 1 , Ziyuan Lu 2 , Markus Wilde 3 , Toyohiro Chikyow 1
1 Advanced Electronic Materials Center, National Institute for Materials Science, Tsukuba Japan, 2 Test and Analysis Division, NEC Electronic Corporation, Kawasaki Japan, 3 Institute of Industrial Science, University of Tokyo, Tokyo Japan
Show AbstractSilicon Aluminum Oxide Nitride (SiAlON) thin films are investigated as a new class of hydrogen diffusion barrier materials to replace the top silicon oxide layer in Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) charge-trapping flash memories devices. SiAlON thin films were deposited at temperature of 300 °C and oxygen partial pressure of 10-5 torr by pulsed laser deposition (PLD). The interfacial structure, chemistry along with the chemical composition, thickness, roughness of individual layer and H profile of MONOS stacks were analyzed using X-ray reflectivity (XRR), x-ray photoelectron spectroscopy (XPS), and nuclear reaction analysis (NRA). The changes observed in the interfacial structure, chemistry and H concentration of the MONOS device structures were correlated with their electrical performance. The results demonstrated that by using SiAlON to replace the top silicon oxide layer yields 1) reduced H concentration at the SiO2/Si interface and 2) enhanced electrical performance of MONOS memories devices. These findings suggest that SiAlON layer can effectively store hydrogen and it is a more effective diffusion barrier than the structurally open SiO2.
5:15 PM - F2.9
Small Molecule-polymer Blend Organic Field Effect Transistors with Long-term Environmental and Operational Stability Using Fluoropolymer/Oxide Bi-layer Top Gate Dielectric.
Do Kyung Hwang 1 , Canek Fuentes-Hernandez 1 , Jungbae Kim 1 , William Potscavage 1 , Sung-Jin Kim 1 , Bernard Kippelen 1
1 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractOver the last several years, organic field-effect transistors (OFETs) have made great progress. However, long-term environmental and operational stabilities are still two major issues for commercialization of OFETs. Recently, much effort has been devoted to improve environmental and operational stabilities of OFETs. In most studies, OFETs with a bottom-gate geometry have been used. OFETs with a top-gate geometry are relatively rare because the choice of gate dielectric materials is limited since its deposition can potentially damage the organic semiconductor layer. An amorphous fluoropolymer, CYTOP, has been shown to be a promising candidate for the realization of top-gate geometries because it dissolves in fluorinated solvents that are orthogonal to most organic semiconductor materials. The CYTOP has an excellent chemical stability and is highly hydrophobic, which leads to OFETs with good operational stability. Instead of using a single layer of CYTOP, CYTOP/high-
k oxide bi-layer as top-gate dielectric combines the excellent chemical properties of CYTOP with the high film quality and large capacitance density of high-
k oxides. In addition, this bi-layer top gate dielectric can be an encapsulation layer against environmental exposure.
Here, we report on the improved stability and performance of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene)-poly(triarylamine) (PTAA) blend OFETs with a top gate geometry using a CYTOP/Al2O3 bi-layer. OFETs fabricated with a single Al2O3 layer operate below 8 V due to a high capacitance density of 78.6 nF/cm2, but show a large hysteresis and low average mobility value of 5.5(±1.9)×10-3 cm2/Vs. On the other hand, the devices with a single CYTOP layer show an average mobility value of 0.39±0.16 cm2/Vs without hysteresis. However, they operate at high voltages, up to 50 V, due to a low high capacitance density of 2.3 nF/cm2. In contrast, OFETs using the CYTOP/Al2O3 bi-layer show no hysteresis and an average mobility value of 0.46±0.08 cm2/Vs below 8 V, due to a relatively high capacitance density of 34.8 nF/cm2. After 20,000 multiple scans or under 24 h constant dc bias stress in an inert atmosphere, OFETs with the CYTOP/Al2O3 bi-layer show no degradation of mobility or threshold voltage. Upon air exposure, and after an initial variation, negligible changes in mobility and threshold voltage were measured in OFETs with the CYTOP/Al2O3 bi-layer after being stored in air for over five months.
5:30 PM - F2.10
Biocompatible and Biodegradable Materials for Organic Field Effect Transistors.
Mihai Irimia-Vladu 1 4 , Pavel Troshin 2 , Melanie Reisinger 1 , Guenther Schwabegger 3 , Reinhard Schwoediauer 1 , Vladimir Razumov 2 , Helmut Sitter 3 , Siegfried Bauer 1 , Niyazi Sariciftci 4
1 Soft Matter Physics , Johannes Kepler University, Linz Austria, 4 Linz Institute for Organic Solar Cells (LIOS), Johannes Kepler University, Linz Austria, 2 Institute of Problems of Chemical Physics, Russian Academy of Sciences, Chernogolovka Russian Federation, 3 Institute of Semiconductor and Solid State Physics, Johannes Kepler University, Linz Austria
Show AbstractOrganic electronics has the potential to develop electronic products that are biocompatible, bioresorbable, biodegradable or even capable to bio-metabolize. An ideal solution for the production of such devices involves the fabrication of the electronics either from natural materials, or from materials that have been proved to be at least biocompatible. Here we report the combination of biocompatible and biodegradable substrates based on hard gelatine capsule or commercially available plastic foil based on starch, corn and polylactic acid (Ecoflex®, BASF) with fully natural or materials found in common commodity products, as gate dielectrics and organic semiconductors in low operating voltage organic field effect transistors (OFETs). In a first example, low operating voltage OFETs are built on commercially available biodegradable plastic foil (Ecoflex®, BASF), comprising naturally occurring dielectrics: adenine, guanine, cytosine, thymine and widely accepted perylene diimide-a simple red dye used extensively in cosmetic industry. In a second example, complete bio-materials based OFETs are introduced based on glucose, lactose, sucrose, for the gate dielectrics with vacuum processed indigo or solution processed beta-carotene as organic semiconductors respectively. In a third example, fully degradable devices are produced on hard gelatine capsule substrates substrate comprising layers of adenine and guanine for organic dielectrics and indanthrene yellow G and indanthrene brilliant orange RF (two vat dyes used extensively in textile industry) for the organic semiconductor. Tremendous improvement of the OFETs characteristics are feasible simply by employing aurin, a naturally occurring red-orange pigment as a smoothening layer for Ecoflex and hard gelatine capsule substrates or by employing the anodization of the aluminium gate electrodes in combination with organic dielectric layers for the samples built on glass substrates. Such transistors may be seen at the heart of organic electronic circuits, to be used in low-cost, large volume disposable or throwaway applications, such as food packaging, plastic bags, disposable dishware etc. There is also significant potential to use such electronic items in biomedical implants.The work was financially funded by Austrian Science Foundation “FWF” within the National Research Network NFN on Organic Devices (P20772-N20, S09712-N08, S09706-N08 and S9711-N08) as well as by Russian Foundation for Basic Research (07-04-01742) and Russian Ministry of Science and Education (02-513-11-3382).
F3: Poster Session: Organic and CNT TFT
Session Chairs
Tuesday AM, November 30, 2010
Exhibition Hall D (Hynes)
9:00 PM - F3.2
Adjustable Memory Effect in Organic Thin Film Transistors via Embedded Nanoparticles in Pentacene Layer.
Sumei Wang 1 2 , Paddy, K. L. Chan 1 , Dennis,C. W. Leung 2
1 Department of Mechanical Engineering, the Hongkong Polytechnic University, Hongkong China, 2 Department of Applied Physics, the Hongkong Polytechnic University, Hongkong China
Show AbstractOrganic devices have attracted considerable attentions due to the simplicity of fabrication process, flexible property and low manufacturing cost. Here we demonstrate organic nonvolatile transistor memory devices based on silver nanoparticles embedded in pentacene thin films layer. The transistor transfer characteristics exhibit large hysteresis (memory window) when the gate bias sweeps from positive value to negative and then back to positive. The memory window can be adjusted by varying the Ag nanoparticle location within the pentacene layer. A memory window as large as 90V was achieved in the pentacene (15 nm)/Ag nanoparticle (5nm)/pentacene (25 nm) device, which is three times larger than that of the conventional structure where the Ag NPs are directly deposited on the silicon dioxide dielectric layer. The influence of silver nanoparticle size on the performance of memory device was also studied. When the nanoparticle size was 1nm, the memory device showed a long retention time of more than 5×104 seconds with a distinct on/off current ratio of 10. The memory effect was explained by a model based on Ag nanoparticle-induced traps. This work demonstrates a simple route of tuning the memory behavior in organic thin film transistors, which has potential for memory applications in flexible electronic circuits.
9:00 PM - F3.3
A Detailed Experimental Study of the Short Channel Effect in PPV Based Organic Field Effect Transistors.
Ali Veysel Tunc 1 , Elizabeth von Hauff 1 , Juergen Parisi 1
1 Department of Physics, EHF Laboratory, University of Oldenburg, Oldenburg Germany
Show AbstractThe origin of the short channel effect in polymer-based field effect transistors (FETs) was investigated. Here, we employed poly [2-methoxy,5-(3',7'-dimethyl-octyloxy)]-p-phenylene vinylene (MDMO-PPV) in blends with different ratios of 1-(3-methoxycarbonyl) propyl-1-phenyl[6,6]C61 (PCBM). Bottom contact and bottom gate with interdigitated structure on SiO2 insulating substrates with channel lengths of 20, 10, 5 and 2.5 µm were used for these studies. In this work we demonstrate that the short channel effect is not only influenced by the device geometry but there is also a correlation between the hole current and field effect mobility, contact resistance and short channel behavior in PPV FETs. We observed that increasing the PCBM content in the blend leads to an increase in the hole current and field effect mobility, a decrease in the contact resistance, as well as a deviation from the saturation behavior of the output characteristics of the FET. This effect is attributed to a change in the polymer chain ordering in the source channel which in turn influences the charge transport properties in the polymer film. We show that using a self assembled monolayer on the SiO2 gate dielectric, known to affect polymer chain ordering, also influences the transistor parameters.
9:00 PM - F3.5
High Mobility, Low Voltage Operating C60 Based N-type Organic Field Effect Transistors.
Mujeeb Ullah 1 , Mihai Irimia-Vladu 2 , Melanie Reisinger 2 , Yasin Kanbur 3 , Guenther Schwabegger 1 , Reinhard Schwoediauer 2 , Siegfried Bauer 2 , Niyazi Sariciftci 4 , Helmut Sitter 1
1 Institute of Semiconductor and Solid State Physics, Johannes Kepler University Linz, Linz Austria, 2 Institute of Soft Matter Physics (SOMAP), Johannes Kepler University Linz, Linz Austria, 3 Department of Polymer Science and Technology, Middle East Technical University, Balgat, Ankara Turkey, 4 Linz Institute of Organic Solar Cells (LIOS), Johannes Kepler University Linz, Linz Austria
Show AbstractWe report the state-of-the-art of C60 based bottom gate-top contact transistors fabricated by using different organic materials (BCB, Polyethylene and Adenine) / metal-oxide (AlOx) bilayer as gate dielectric. The engineering of the metal-oxide and the organic material passivation bilayer combines the advantages of having a high dielectric metal oxide and a thin passivation layer of polymer or small molecule capped on AlOx layer. The passivation layer helps both smoothing the dielectric surface and suppressing the leakage current while providing good interface properties with the semiconductor layers. This results in OFETs that operate at voltages less than 500 mV. The AlOx layers are readily processable from solution and cured at low temperature, instead of traditionally sputtering or high temperature processing, thus this process is suitable for low-cost organic field effect transistors (OFETs) manufacture. The output characteristics of the OFETs show well saturation behavior while the transfer characteristic display an on/off ratio in excess of 103. The OFET devices have a high field effect mobility, which ranges from 2 - 5 cm2/V s for different passivation layers, with low threshold voltages in the range of 20 mV to 5o mV.
9:00 PM - F3.6
Capacitance-Voltage Measurement of an Ambipolar Pentacene Field Effect Transistor in Operation by Using Displacement Current Measurement.
Yuya Tanaka 1 , Yutaka Noguchi 1 2 , Hisao Ishii 1 2
1 Graduate School of Advanced Integration Science, Chiba University, Chiba Japan, 2 Center for Frontier Science, Chiba University, Chiba Japan
Show AbstractRecently, organic field effect transistors (OFETs) have been extensively studied because of their low cost, light weight, flexibility and so on. However the operation mechanism is not yet well understood and OFET has not been put to practical use. Since typical organic semiconductors have an extremely small number of thermal carriers due to their large energy gap and are mostly used without any intentional dopants unlike inorganic FETs, OFETs seem to be driven by the injected carriers from the source electrode. Therefore it is quite important to understand the mechanism of channel formation due to carrier injection in OFET. Capacitance-voltage measurement is crucial to understand the carrier injection and accumulation in OFETs, and has been applied to various OFETs. We also have investigated OFETs by using one of C-V methods, displacement current measurement (DCM)[1]. In this technique, a current through a device is measured under a ramp voltage, and the observed current is proportional to the effective capacitance of the device. C-V measurement including DCM is two-terminal measurement, but transistors are three terminal devices. Thus, the observed carrier behaviors by conventional C-V methods are not the same in operating transistors. In order to understand the channel formation process in OFETs, we need to measure C-V in an operation transistor. In literature [2], an attempt to measure C-V of operating transistor have been reported by measuring both source-gate and drain-gate displacement currents simultaneously. But in the method, the measurement accuracy was limited due to the coexistence of displacement and actual currents in the observed current: the measurement condition was restricted to separate both the components. So, the quality of the obtained C-V curve was not enough to discuss the mechanism of the formation and annihilation process of channel. In this study, we have proposed another method to measure C-V of an operating transistor and succeeded to observe a subtle change of the capacitance during the channel formation. By applying a voltage between a source and drain electrodes with an isolated battery, only displacement current between a gate and the battery was measured. Since it is not necessary to separate displacement and actual currents, high accuracy is achieved. From the observed results of an ambipolar pentacene FET with a tetratetracontance (C44H90) buffer layer on SiO2 insulating layer, we could clearly observe the channel formation and annihilation processes in operating transistor and determine the pinch-off voltage. These results demonstrate that DCM is the powerful tool to investigate the channel formation process of OFET in detail. [1] S. Ogawa et al., Jpn. J. Appl. Phys. 42, L1275 (2003). [2] Y. Majima et al., Jpn. J. Appl. Phys. 46, 1 (2007).
9:00 PM - F3.7
Tetracene Thin Films on Organic Dielectrics: Growth, Structure, and Functional Properties.
Clara Santato 1 , Julia Wuensche 1 , Simone Bertolazzi 1
1 , École Polytechnique Montréal, Montréal, Quebec, Canada
Show AbstractTetracene vacuum-sublimed films exhibit interesting charge carrier transport and electroluminescence properties.These films have been used to demonstrate the first Organic Light Emitting Field Effect Transistors (OLEFET), one of the most promising classes of devices in the field of plastic optoelectronics. Investigating the role played by the morphology and surface chemistry of the dielectric substrate as well as establishing sound structure-property relationships in organic semiconductor films are among the keys to understand and improve OLEFET performance.Here we present our results on the growth, morphology, structure, and functional properties of vacuum-sublimed tetracene films deposited on different organic dielectric substrates, namely HMDS- and OTS-treated SiO2, polystyrene, parylene, polymethylmethacrylate. All the results have been compared with those obtained on SiO2 dielectric substrate, employed as reference.In terms of field effect transistor (FET) performance, the most interesting results were observed for tetracene FET based on polystirene and parylene gate dielectrics.A careful atomic force microscopy (AFM) study performed since the early stages of the growth (i.e. on films whose nominal thickness was 3, 5, 10, 17, 25 and 35 nm) revealed the good substrate surface coverage, large particles' size (expressed in terms of correlation length), and low particles' density obtained for tetracene films deposited on parylene and polystirene dielectric substrates. These results are able to explain the tetracene FET performance.The AFM observations were compared with the results collected during a synchrotron grazing incidence x-ray diffraction study carried out on these same tetracene films. Information concerning the film crystalline structure, the particles' size, but also the molecular arrangement in the cell were useful to get a deeper insight on the FET performance.The complexity and richness of the results we collected indicate the number of semiconductor- and dielectric-related features to be considered to rationally design the new generation of plastic optoelectronic devices.
9:00 PM - F3.8
Polymer Source-Gated Transistors.
S. Georgakopoulos 1 , D. Sparrowe 2 , F. Meyer 2 , Maxim Shkunov 1
1 Advanced Technology Institute, University of Surrey, Surrey United Kingdom, 2 Chilworth Technical Centre, Merck Chemicals Ltd., Southampton United Kingdom
Show AbstractThe reliability and stability of organic transistors has been steadily improving. Recently, amorphous conjugated co-polymer Field-Effect Transistors (FETs) have exhibited outstanding stability in air [1] and narrow mobility spread across large numbers of transistors and several different processing methods [2]. However, significant challenges remain until practical large-scale production of sufficiently high-performance devices can be realized. Two of these challenges are the high operating voltage of organic FETs and short-channel effects requiring downscaling of the dielectric layer. We demonstrate organic transistors capable of overcoming these two limitations.In Field-Effect Transistors (FETs) the gate modulates the conductance of a channel with ohmic source/drain contacts, and the current saturates when the drain end is depleted of carriers. In a novel type of thin film transistor, namely Source-Gated Transistor (SGT), a Schottky barrier at the source modulates the current through the device, and the depletion region causes pinch-off of the conductive channel at much lower voltages than for FETs. SGTs retain strong saturation even for short channel lengths and thick dielectric layers.In this work we have fabricated SGTs with an amorphous π-conjugated polymer semiconductor that demonstrate source-gating in organics for the first time. The properties of our polymer SGTs generally follow the predictions developed for inorganic SGTs [3], including low-voltage saturation and good operation in short channels. The low-voltage saturation of organic SGTs provides an opportunity for the realization of solution- processable transistors with low power consumption. Also, the dielectric layer is not required to be downscaled, allowing for simpler fabrication, including low-temperature printing processes. References[1] W. Zhang, et al. J. Am. Chem. Soc. 131, 10814 (2009)[2] J.M. Verilhac, Org. Electron., 11, 456 (2010)[3] J.M. Shannon, E.G. Gerstner. IEEE Electr. Device Lett., 24, 405 (2003); J.M. Shannon, F. Balon. Solid State Electron., 52, 449 (2008); T. Lindner, G. Paasch, S. Scheinert. IEEE T. Electron. Dev., 52, 47 (2005)
Symposium Organizers
Soeren Steudel IMEC
Shelby F. Nelson Eastman Kodak Company
Veit Wagner Jacobs University Bremen
Heiko Thiem Evonik Degussa GmbH
F4/MM4: Joint Session: Vacuum Deposited Metaloxide TFT
Session Chairs
Shelby Nelson
Erin Ratcliff
Tuesday AM, November 30, 2010
Constitution B (Sheraton)
9:30 AM - **F4.1/MM4.1
Fully Transparent n and p-type Oxide TFTs.
Elvira Fortunato 1
1 Materials Science, FCT-UNL, Caparica Portugal
Show AbstractTransparent electronics is growing so fast and is today one of the most advanced topics for a wide range of device applications, where the key component are wide band gap semiconductors, and oxides of different origin play an important role, not only as passive component but also as an active component similar to what we observe in conventional semiconductors. In this paper we will review the main achievements related to fully transparent n-type oxide based TFTs as well as to p-type oxide based TFTs produced at CENIMAT/I3N.
10:00 AM - F4.2/MM4.2
P-Type Tin Monoxide Semiconductor Fabricated by Sputtering.
Po-Ching Hsu 1 , Wei-Chung Chen 1 , Tzu-Ming Wang 1 , Chung-Chih Wu 1 , Hsing-Hung Hsieh 2 , Ching-Sang Chuang 2 , Yusin Lin 2
1 Graduate Institute of Electronics Engineering, National Taiwan University, Taipei Taiwan, 2 , AU Optronics Corporation, Hsinchu Taiwan
Show Abstractp-type tin monoxide (SnO) is one of the most promising p-type oxide TFT material [1]. Here, we report the fabrication of SnO p-type oxide semiconductor on glass substrates by the TFT-industry compatible sputtering technique, which is different from the previous reports (e.g. epitaxy on crystalline substrates by pulsed laser deposition etc. [1, 2]). By using targets of appropriate compositions, SnO films on glass substrates were successfully obtained by deposition at room temperature, followed by post annealing. The as-deposited film showed an amorphous phase, while polycrystalline tin monoxide phase was obtained after thermal annealing. By judiciously controlling the working gas during the sputtering, we can not only modulate the Sn/O ratio in SnO films, but also improve the orientations/crystallinity of the SnO phase. We also observed that appropriate combinations of working gases can significantly decrease the post-annealing temperature required for the formation of the SnO phase, making the whole process temperature compatible with the glass substrates. With a <450°C process, the p-type Hall mobility of 0.1-1 cm2V-1s-1 and p-type carrier concentration down to the order of 1017 cm-3 were successfully achieved in the SnO films, which meet the requirements for active layers of thin-film transistors. The realization of p-type SnO films by room-temperature sputtering and low-temperature post annealing demonstrates the possibility of large-area and low-cost p-type oxide TFT fabrication. [1] Y. Ogo, H. Hiramatsu, K. Nomura, H. Yanagi, T. Kamiya, M. Hirano, and H. Hosono, Appl. Phys. Lett. 93, 032113 (2008). [2] Ho-Nyeon Lee, Hyung-Jung Kim, and Chang-Kyo Kim, Jpn. J. Appl. Phys. 49, 020202 (2010).
10:15 AM - **F4.3/MM4.3
The Improvement of Photo-induced Bias Stability of the Oxide TFT.
Chang Jung Kim 1 , Sun Il Kim 1 , Jae Chul Park 1 , Sang Wook Kim 1 , Ihun Song 1 , U-In Chung 1
1 , Samsung Advanced Institute of Technology (SAIT), Yongin-si Gyeonggi-do Korea (the Republic of)
Show AbstractWe successfully fabricated the high stable amorphous hafnium-indium-zinc-oxide (HIZO) thin film transistors (TFTs) with SiOF gate insulator layer and SiOx/SiON passivation layer by systematically investigating the role of various gate insulator layers and passivation layers under negative-bias-temperature illumination-stress (NBTIS) condition. For example, the instability of the TFTs with SiOx passivation layer (threshold voltage shift (ΔVth)~ -6.5V) is less than that of the TFTs with SiONx passivation layer (ΔVth ~ -8.5V). Also, we could get better photo-induced bias stability after back channel treatments. Finally, using the SiOF gate insulator, the back channel treatments, and the SiOx (inner)/SiONx (outer) passivation layers, the instability of the amorphous HIZO TFTs were drastically improved by the suppression of the positive charge trapping sites under the NBTIS conditions. These are very promising results for applications in large area AMLCD and AMOLED display with high intensity light source.
10:45 AM - F4/MM4:Vacuum
BREAK
11:15 AM - **F4.4/MM4.4
Improvement of Performances and Stability of a-In-Ga-Zn-O TFT by Low-temperature Annealing.
Kenji Nomura 2 , Hideo Hosono 1 2 , Toshio Kamiya 1
2 Frontier Research Center, Tokyo Institute of Technology, Yokohama Japan, 1 Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama Japan
Show AbstractTransparent amorphous oxide semiconductor represented by a-In-Ga-Zn-O (a-IGZO) is widely accepted as a channel material of driving /switching thin-film transistors (TFTs) for next-generation flat-panel displays such as high-resolution active-matrix (AM) organic light-emitting displays and large-size / high fram rate AM –liquid-crystal displays (LCD) because they have better performances such as large mobilities of ~10 cm2(Vs)-1 and substhreshold slope swing (S) values than a-Si:H TFTs even when they are fabricated at room temperature. To date, many efforts have been devoted to improve TFT characteristics including stability against electrical stress for practical-use. It is known well that post thermal annealing over 300 oC is effective to improve TFT characteristics due to the reduction of subgap defect states in a-IGZO channels. However, it is indispensible to reduce annealing temperature for developing stable and high-performance flexible electronic devices. In this paper, we report improvement of performances and stability of a-IGZO TFTs by low-temperature annealing. Bottom-gate and top-contact a-IGZO TFTs were fabricated on thermally-oxidized SiO2/ c-Si. The a-IGZO channel layers were deposited at room temperature (RT) and subjected subsequently to annealing at 100-400oC in dry O2, wet O2, or ozone atmospheres. Electron-beam evaporated Ti / Au electrodes were used as source / drain contacts. Constant current stress and light illuminated negative bias stress tests were examined to evaluate TFT stability. We found that strong power oxidation atmospheres such as wet O2 are effective to reduce subgap defects state for high-temperature annealing over 300oC. The 400oC-wet annealed TFTs exhibited best performances such as saturated mobility (μsat) ~ 12.4 cm2(Vs)-1 and S ~ 112 mV/dec. However, both the dry and wetO2 annealing caused large negative threshold voltage shifts originating from increase of donor density in the channel for low-temperature annealing at < 200oC. It was found that ozone thermal annealing can improve TFT characteristics even at 150oC, and the 150oC-ozone annealed TFTs exhibited reasonably good performances such as μsat ~ 11.9 cm2(Vs)-1 and S ~ 260 mV/dec. The TFT stability under constant current bias and light illuminated negative bias for TFTs with a wider range of channel quality will also be presented.
11:45 AM - F4.5/MM4.5
High Mobility Amorphous Metal Oxynitride Thin Film Semiconductors.
Yan Ye 1 , Rodney Lim 1 , Anshu Gaur 1 , John White 1
1 AKT, Applied Materials, Inc, Santa Clara, California, United States
Show AbstractAmorphous thin film semiconductors are preferred over polycrystalline films for large-area electronics manufacturing because of better local uniformity and consistency of structure through the thickness of the deposited film. Linked to their bond ionicities, single-metal oxides, such as In2O3, Ga2O3, ZnO and SnO2, tend to form films that are highly crystalline in structure. Combining several of these metal oxides by simultaneous deposition to form a single film such as InGaZnO, creates competition amongst the various oxides and frustrates the formation of any long-range crystalline structures; thereby producing a substantially amorphous structure.A different approach to produce amorphous semiconductor materials has been explored, using a single-metal system. The amorphous phase is achieved by promoting competition between reactions responsible for the growth of compounds from the same metal but different crystalline structures. We used zinc as the metal and both oxygen and nitrogen as reactants in a reactive sputtering process. By adjusting the ratio of the reactants, we are able to make the reaction dominated by either oxygen or nitrogen, or balanced with equivalent reaction rates. As the result, we are able to produce films of crystalline zinc oxide ZnO, nitrogen doped crystalline zinc oxide ZnO:N, amorphous or highly disordered nanocrystalline zinc oxynitride ZnON, or crystalline zinc nitride Zn3N2. Each film has its own chemical and physical properties. We observed that the highest mobility is attained from amorphous zinc oxynitrides. Even though the films produced from the multi-reactant process have a highly disordered structure, they exhibit a higher Hall mobility than the crystalline films produced from preferential growth under the dominance of a single reaction. Moreover, the mobility of the ZnON films deposited at low temperature is higher than that of InGaZnO. Furthermore, the mobility increases as electron carrier concentration decreases over a wide range of the carrier concentration. This characteristic is opposite from the behavior of InGaZnO and indicates that carrier transport in the new semiconductor is dominated by a different mechanism, likely due to different constitutions of conduction band bottom, as will be discussed. Stability of the films and devices made with the new semicoductor has been tested under various stress conditions. Shelf life of an as-deposited film deposited at 50C was about 30 days when it was exposed to room air without any passivation or other protection. Failure is due to the adsorption of moisture and pollutants in the air. An annealed film has been exposed to room air without any protection for more than 600 days without degradation. Thin film transistors (TFTs), active matrix-TFT arrays, and e-ink displays have all been made successfully with the new semiconductor material. Tests of the TFTs under high-temperature and bias-temperature stress have been performed and results will be presented.
12:00 PM - F4.6/MM4.6
High Performance Amorphous-oxide-semiconductor with Indium Tin Zinc Oxide (ITZO) for Thin Film Transistor.
Masashi Kasami 1 , Mami Nishimura 1 , Masayuki Itose 1 , Masahide Matsuura 1 , Shigeo Matsuzaki 1 , Hirokazu Kawashima 1 , Futoshi Utsuno 1 , Koki Yano 1
1 Advanced Research Laboratories, Idemitsu Kosan Co., Ltd., Chiba Japan
Show AbstractTransparent amorphous oxide semiconductors (TAOS) are of growing interest in the context of thin film transistor (TFT) channel layers for transparent electronics and various electronics applications because of their high mobility and large area uniformity. In particular, the most popular TAOS is indium gallium zinc oxide (IGZO), and there have been many studies on practical applications as the backplane of AM-OLED and 2k×4k display panels. Although IGZO was mobility of the order of ~10 cm2/Vs, higher mobility has been needed to fabricate next generation applications such as a super high-vision panel and to integrate driver circuit. Moreover, an etching stopper layer was necessary for using in the conventional pattering process because IGZO was acid soluble. Therefore, the TAOS with insolubility in various acids was needed to be adopted the conventional TFT process. We developed new oxide semiconductor of indium tin zinc oxide (ITZO) with high electrical performances and processability. Since our developed ITZO target has low resistivity, it was possible to be deposited by direct current (DC) sputtering. The obtained film was amorphous and PAN (phosphoric, acetic and nitric acid) insoluble. In this work, we studied electrical and practical properties of ITZO films deposited under various deposition conditions at room temperature.In the as-deposited ITZO films, the carrier density and Hall mobility decreased with increasing oxygen partial pressure. In the post annealed films, however, their carrier density and Hall mobility maintained almost constant values independent of oxygen partial pressure. Hall mobility and carrier density of their post annealed films, which were annealed at 300 °C for 1 hour, were 30 cm2/Vs and ~1018 cm-3, respectively. ITZO film was soluble in oxalic acid, as same as transparent electrodes such as amorphous ITO and IZO films. However it was insoluble in PAN which was used in conventional pattering process of source and drain electrode. Also the etching rate of ITZO film for oxalic acid was about 2~5 nm/sec at 40 °C as same as that of IZO. We fabricated the ITZO channel TFT using photolithography technique. The channel length and width were 20 μm and 10 μm, respectively. The field-effect mobility was 20 cm2/Vs, it was higher than that of IGZO TFT. It was noted that its threshold voltage, S-factor, and On/Off ratio were -5 V, 0.4 V/dec., and 108, respectively.
12:15 PM - F4.7/MM4.7
Transparent MgZnO-based Metal-semiconductor Field Effect Transistors and Devices.
Alexander Lajn 1 , Heiko Frenzel 1 , Tobias Diez 1 , Fabian Kluepfel 1 , Friedrich Schein 1 , Holger von Wenckstern 1 , Marius Grundmann 1
1 Semiconductor physics group, University of Leipzig, Leipzig , Saxony, Germany
Show AbstractTransparent electronics combined with transparent light emitters permit the fabrication of fully transparent displays. New designs, which involve higher information content, better ergonomics, augmented reality applications, lower power consumption and new aesthetic aspects, are feasible; e.g. in car wind shields, windows, sun glasses, monitors or cell phones.
The authors report on the fabrication of transparent rectifying contacts (TRC) on MgZnO thin films and their application in field-effect transistors and inverters. The TRC are fabricated by reactive sputtering of an about 5 nm thick silver oxide or platinum oxide layer and a subsequently deposited metallic conducting capping layer of about 5 nm thickness. An average transmission of 70 % (60%) in the visible spectral range was achieved for the AgxO (PtOy)-based TRC. Using standard photo-lithographic techniques, transparent metal-semiconductor field-effect transistors (TMESFET) utilizing TRC as gate electrodes and ZnO:Al for the source and drain contacts were processed.
These devices reach a channel mobility of 12 cm2/Vs and on/off-ratios of 106 1. These performance values are only slightly lower compared with those of opaque MESFETs2. With that, the devices meet the requirements for the use in transparent displays formulated by Wager3. Furthermore the TMESFETs operate at low voltages; a voltage sweep of only about ΔV = 2.5 V is required to switch between on- and off-state. In addition, with 120 mV/dec, the sub-threshold slope of the TMESFETs is only a factor of two higher than the thermodynamic limit of 60 mV/dec.
The advantages of MESFETs (compared to state of the art transparent MISFETs) were successfully transferred to inverter circuits, yielding a maximum gain of 200 at a supply voltage of only 4 V and a low uncertainty range of 0.3 V. The effect of irradiating the inverter circuits with visible light was studied and no significant influence of red and green light was observed. When irradiated with blue light, a 15% decrease of the gain was observed. Furthermore, the stability of the inverter circuits at temperatures between room temperature and 150°C was investigated. Thermal degradation of the AgxO-gate electrodes started at temperatures of about 90°C4, nevertheless the inverters remained fully operational up to 150°C.
In summary, the authors present a promising approach to transparent electronics based on TRC including fully transparent MESFETs and inverter circuits.
1. Frenzel
et al. , J. Appl. Phys.,
107, 114515 (2010)
2. Frenzel
et al. , Appl. Phys. Lett.
92, 192108 (2008)
3) J. F. Wager, Science,
300, 1245 (2003)
4) Frenzel
et al. , Thin Solid Films,
518, 1119 (2009).
12:30 PM - F4.8/MM4.8
Low-temperature Processing of Metal-semiconductor Field-effect Transistors Based on Amorphous Gallium-indium-zinc-oxide and Indium-zinc-oxide Thin Films.
Michael Lorenz 1 , Alexander Lajn 1 , Heiko Frenzel 1 , Holger von Wenckstern 1 , Marius Grundmann 1 , Pedro Barquinha 2 , Elvira Fortunato 2 , Rodrigo Martins 2
1 , Universität Leipzig - Institut für Experimentelle Physik II, Leipzig Germany, 2 CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa and CEMOP-UNINOVA, Caparica Portugal
Show AbstractThe physics and application of amorphous oxide semiconductors (AOS) are an emerging field of interest. Compared to covalent semiconductors like a-Si:H the influence of the disorder on the mobility of the charged carriers is negligible and not limited to values below 1cm
2/Vs[1]. Besides, AOS can be deposited at room temperature and thus electronics on flexible substrates are possible.
The authors demonstrate metal-semiconductor field-effect transistors (MESFET), which exhibit excellent electrical characteristics, e.g. channel mobilities up to 15cm2/Vs and a subthreshold swing of S=69mV/decade. The IZO or GIZO channel material and the AgxO-Schottky gate electrodes were all deposited at room-temperature. The influence of a low temperature annealing step (T=150°C) after device production is furthermore investigated.
IZO and GIZO thin films were grown by radio frequency magnetron sputtering at room temperature on Corning 1737 glass substrates. The composition of In and Ga controls the net doping concentration, which determines the extension of the space charge region below the Schottky contact. Accordingly, the IZO and GIZO thin films were grown with thicknesses of 16nm and 160nm, respectivelly. Subsequent annealing at 150°C has strong effects on the electrical properties of the thin films (e.g. Hall-effect mobility) as well as on the device characteristics, e.g. higher field-effect mobilities and lower values for the minimum subthreshold swing S=∂VG/∂log(ISD). The MESFET were fabricated by standard photolithography using lift-off technique. The ohmic source-drain electrodes were sputtered using an Au target in an argon atmosphere. The Schottky gate contacts were dc-sputtered by means of an Ag target in a mixed argon/oxygen atmosphere, which yields a partial oxidization of Ag and hence to higher effective barrier heights for the Schottky contact.
The effective barrier heights of the Schottky contacts (SC) on IZO and GIZO channel material are 0.85eV and 0.96eV, respectively. The ideality factor n of contacts on GIZO were determined for the annealed thin films to be n=1.5 and for the as-grown thin film n=1.8 while the values for n on IZO thin films are approx. 1.7 .
For MESFET on annealed GIZO channel material the source-drain current can be controlled over 8 orders of magnitude with a gate sweep voltage of ΔVG=2.5V. Transistors on the sample chip have the highest field-effect mobility of 15 cm2/Vs and best reproducibility. For annealed IZO channel material the minimum substhreshold swing is S=69mV/decade, which is near the theoretical minimum of 60mV/decade at room temperature and one of the best values reported so far even if compared with the extensive literature on oxide TFTs[2].
[1] R. Martins, P. Barquinha, I. Fereira, Goncalves, and E. Fortunato, J. Appl. Phys. 101, 044505 (2007)
[2] M. Grundmann, H. Frenzel, A. Lajn, M. Lorenz, F. Schein, and H. v. Wenckstern, Phys. Status Solidi A, 207 (2010)
12:45 PM - F4.9/MM4.9
Thermal Annealing and Time Dependent Electric Field Gating Studies of Conductivity Stability in Amorphous Indium Zinc Oxide Thin-film Transistors.
Charles Sievers 1 2 , Thomas Gennett 2 , Joseph Berry 2 , David Ginley 2 , John Perkins 2 , Charles Rogers 1
1 Department of Physics, University of Colorado, Boulder, Boulder, Colorado, United States, 2 , National Renewable Energy Laboratory, Golden, Colorado, United States
Show AbstractThe high electron mobility (10 – 50 cm2/V-s) of low carrier concentration semiconducting amorphous indium zinc oxide (a-IZO) makes a-IZO an attractive channel layer material for transparent thin film transistors (TTFTs). However, even modest thermal processing, such as is required for lithographic processing, can lead to large increases in carrier density in a-IZO. Here, we are studying the temperature dependence and the electric field gating of a-IZO conductivity in thin-film transistors in an effort to understand and control these carrier density changes. For as-grown films, we find that the electric field gated a-IZO conductivity has a two-stage time dependent response. First, the electric field produces a prompt change in conductivity, consistent with electron depletion physics. This quick response is then followed by a slow relaxation process with a time sale of order 10 minutes, strongly suggesting the presence of positive mobile ions in the as-grown films. Sequences of short thermal anneals at temperatures ranging from 100 to 300 °C yield an initial increase the conductivity from 1e-4 to 1e2 S/cm and then a subsequent decrease to a more stable conductivity of 1-10 S/cm. Furthermore, these anneals reduce the magnitude of the long time scale conductivity changes in the gating. Comparative studies of exposed and SiO encapsulated a-IZO channel layers over a range of environments from vacuum to pure oxygen suggest that the thermal and slow electric field response both trace to mobile positive ions, which can be driven from the films by suitable baking during device fabrication.
F5/MM5: Joint Session: Solution Processed Metaloxide Semiconductor
Session Chairs
Erin Ratcliff
Heiko Thiem
Tuesday PM, November 30, 2010
Constitution B (Sheraton)
2:30 PM - **F5.1/MM5.1
Low Temperature Processed Amorphous Oxide Semiconductor Thin-film Transistors.
John Wager 1 , Ken Hoshino 1 , Layannah Feller 1 , Rick Presley 1
1 School of EECS, Oregon State University, Corvallis, Oregon, United States
Show AbstractAmorphous oxide semiconductor (AOS) thin-film transistors (TFTs) appear to be well positioned for near-term commercial entry into the flat-panel display market as a replacement for hydrogenated amorphous silicon TFTs. This application mandates a maximum process temperature of approximately 300-350 °C. Process constraints for future flexible display and flexible electronics products promise to be even more challenging, requiring a maximum temperature of ~150 °C, or even lower. The purpose of this presentation is to review our work on reduced temperature processing of AOS TFTs.
3:00 PM - F5.2/MM5.2
Solution-processed Aluminum Indium Oxide Thin-film Transistor with Low Temperature Annealing.
Young Hwan Hwang 1 , Seok-Jun Seo 1 , Jun-Hyuck Jeon 1 , Byeong-Soo Bae 1
1 Lab. Optical Materials & Coating (LOMC), Dept. of Materials Science & Engineering, KAIST, Daejeon Korea (the Republic of)
Show AbstractOxide semiconductor has plenty of advantages such as transparency due to their large bandgap, high electron conduction property, high uniformity in large-scale fabrication applications, and environmental stability. Thus, it is expected that oxide semiconductor do a significant role in many applications such as, flat-panel displays, flexible displays, radiofrequency identification tags, and smart windows. Typically, oxide TFTs have been fabricated using vacuum-process which enables low temperature process. Recently, solution-processed oxide TFTs get intensive attraction since they can be prepared by simple and low cost methods. However, its high annealing temperature restricts the use of the solution-processed oxide TFTs as an active layer in TFT applications. Previously we have reported the aluminum indium oxide (AIO) TFTs which can be prepared with relatively low temperature process. (i.e. 350 °C) [1] In this study, we have applied additional annealing for the purpose of decreasing the annealing temperature. The vacuum annealing, which is understood as an effective tool to remove the remaining organics inside the film and increase the carrier concentration, was adopted to increase the conductivity of the film. After the vacuum annealing, the film was annealed under oxygen surrounding to optimize the carrier concentration in the film and decrease the surface oxygen deficiency which is related to off current of the TFT for better TFT performance. All the annealing process was performed at the 200 °C and 250 °C, individually. The resultant AIO TFT annealed at 250 °C exhibits a channel mobility of 3.5 cm^2/Vs, a subthreshold slope of 0.6 V/dec, and an on-to-off current ratio of ~10^6. In addition, based on the results of low temperature annealing, solution-processed AIO TFT fabricated on the flexible substrate will be demonstrated.[1] Y.H. Hwang, J.H. Jeon, S. Seo, and B. Bae, “Solution-processed, high performance aluminum indium oxide thin-film transistors fabricated at low temperature”, Electrochem. Solid-State Lett. 12, H336 (2009).
3:15 PM - F5.3/MM5.3
ZnBeMgO Nanostructured Based UV Detectors by Spin Coating.
Neeraj Panwar 1 , Jose Liriano 1 , Ram Katiyar 1
1 Department of Physics, University of Puerto Rico, San Juan United States
Show AbstractThe detection of ultraviolet radiation is of prime importance in the field of space, environment and biological applications etc. ZnO is a direct band semiconductor having wurtzite hexagonal structure with a band gap Eg ~ 3.37 eV which can be easily tuned by alloying it with MgO (Eg= 7.5 eV) and BeO (Eg= 10.8 eV). By this approach, one can cover the deep UV range avoiding interference from the visible spectrum and these detectors can work in the harsh enviornment. Zn1-x-yBexMgyO films were prepared on sapphire (Al2O3) and Si substrates by novel spin coating method. Starting materials were dissolved in 2-methoxyethanol and monoethanolamine (MEA) used as solvent and stabilizer respectively. The molar concentration of the solutions was 0.5M. The solutions were coated on the substrates rotated with 3000rpm for 30s. The films were then dried at 300°C for 10 min for evaporating the solvents and removal of organic residuals. The effect of deposition steps, annealing temperature variation and variation in Be and Mg concentration at Zn-site have been carried out. It was identified that with 15 deposition steps and 15 and 20 at% of Be and Mg concentration and 450°C annealing temperature produce film with best properties. XRD patterns of the films revealed that the pristine film has a wurtzite type structure. However, the doped films exhibited the preferential c-axis orientation along (002) indicating that the c-axis of the grains becomes uniformly perpendicular to the substrate surface. No extra peaks corresponding to BeO or MgO could be noticed in the XRD patterns of the films. From the optical measurements it was observed that for the pristine ZnO film, the cutoff wavelength was 364nm which decreased to 320nm for Zn0.65Be0.15Mg0.20O film which lies in UV-B region. The dark current, photoresponsivity and other optical measurements have been carried out on the films with inter-digitated electrodes and the results will be presented in the meeting.
3:30 PM - F5.4/MM5.4
Synthesis of Morphologically Controlled ZnO Nanostructures and Spray Deposition of Hybrid ZnO/Ag Nanostructured Films for Transparent Conductor Applications.
Saahil Mehra 1 , Rodrigo Noriega 5 , Mark Christoforo 3 , Sujay Phadke 4 , Dietmar Knipp 2 , Alberto Salleo 1
1 Materials Science & Engineering, Stanford University, Stanford, California, United States, 5 Applied Physics, Stanford University, Stanford, California, United States, 3 Electrical Engineering, Stanford University, Stanford, California, United States, 4 Mechanical Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Jacobs University, Bremen Germany
Show AbstractThe development of efficient back reflector light- trapping methods for long wavelength photons (λ > 850 nm) in thin film photovoltaic devices remains a major obstacle to making these technologies cost-competitive. Solution processed film deposition techniques are strong candidates for novel transparent conducting films, owing to their minimal fabrication costs and roll-to-roll processing compatibility. Here we explore the light-diffusing and electronic properties of solution processed nanostructured zinc oxide films fabricated on glass substrates using a scalable pneumatic spray coating process. Synthesis of hexagonal-base zinc oxide nanopyramids with controlled size distributions in the range of 100 and 500 nm diameters is achieved using low-temperature, solution-based decomposition of zinc acetate in organic solvents. The effects of Ga-dopant incorporation on ZnO nanopyramid morphology and electrical properties were characterized using Photothermal Deflection Spectroscopy (PDS). We further demonstrate a systematic optimization of spray-coating process variables for nanostructure film deposition, exhibiting control over film uniformity, thickness, and the resulting optical and electronic properties. Finally, the benefits of solution processed hybrid films using metallic (Ag) nanowires and highly scattering ZnO nanopyramids were explored as transparent conductive films. The effects of nanopyramid size, ZnO:Ag ratios, and post-processing steps on the light scattering and electrical properties of sprayed films were quantified using haze factor measurements, SEM, and electrical measurements. The fabrication requirements for thin film photovoltaics using spray-coating as a high-throughput deposition mechanism are estimated, and we show that solution-processed nanostructured films are promising materials for transparent top contacts or textured back electrodes for such thin film devices.
3:45 PM - F5.5/MM5.5
Sensor Devices Based on Ink-jet Printed ZnO Nanoparticle Thin Films.
Sonja Hartner 1 , Moazzam Ali 2 , Ahmed Khalil 2 , Markus Winterer 2 , Hartmut Wiggers 1
1 , Institute of Combustion and Gasdynamics and CeNIDE, Duisburg Germany, 2 , Nanoparticle Process Technology and CeNIDE, Duisburg Germany
Show AbstractFor device fabrication such as transparent conductive layer and sensor devices based on cost-efficient printing technologies, stable dispersions of smallsized (semi)-conducting particles in the nanometer scale are highly desirable. ZnO nanoparticles (NPs) are a very promising material due to the electrical and optical properties of zinc oxide, but due to its amphoteric behavior ZnO is not very stable in suitable dispersing solvents as the pH of the dispersion changes. By using chemical vapor synthesis, highly crystalline, less aggregated and narrow-sized ZnO nanoparticles can be obtained. Stable aqueous dispersions of these ZnO NPs have been successfully prepared after the addition of a polymeric stabilizer. The dispersions are stable for at least 2 months without any observable sedimentation. Interdigitating structures consisting of two opposite gold pads with gold fingers arranged in between were prepared by e-beam lithography and. Stable dispersions as mentioned above have been used to print ZnO NP films with a Dimatix 2800 ink-jet printer on the pre-structured substrates by ink-jet printing. The resulting films have a thickness between 100 and 250 nm, low porosity and could be fabricated on different substrates. The electrical and sensing properties of the as-prepared ZnO thin films are measured without any annealing steps in between from room temperature up to 473K in ambient conditions and in reducing atmosphere using impedance spectroscopy. Compared to the measurements in air, the resistance in hydrogen decreases by a factor of five even at room temperature. As a result we find that our nanosized ZnO ink enables for the formation of sensor devices without any annealing or post-processing. Substituting the interdigital structures prepared from e-beam lithograpy by printed structures (e.g. with silver ink) will lead to fully printed sensor devices even on temperature sensitive substrates.
4:00 PM - F5/MM5:Solution
BREAK
4:30 PM - F5.6/MM5.6
Solvothermal Synthesis of Uniform ITO Nanoparticles and Their TCO Properties.
Kiyoshi Kanie 1 , Takafumi Sasaki 1 , Atsushi Muramatsu 1
1 IMRAM, Tohoku University, Sendai, Miyagi, Japan
Show AbstractHighly crystalline cubic indium tin oxide (ITO) nanoparticles with narrow size distribution were successfully prepared directly in one step from the mixed solution of indium and tin salts by the solvothermal method with lean ethylene glycol as a solvent. The addition of water must inhibit the formation of ITO crystals, but can strongly promote the formation of In(OH)3 and InOOH, including tin hydroxide. Since In(OH)3 and InOOH was not found in water-free EG system, the transformation of In(OH)3 and InOOH into In2O3 phase must be remarkably slow so that once formed indium hydroxides become final product in water-containing system. The as-prepared particles in BuOH as a solvent consist of irregular shaped nanoparticles of ITO and InOOH. In the solvothermal system with glycol as solvents, direct formation of ITO solid particles was observed starting from amorphous indium hydroxides, In(OH)3 and InOOH phases are not detected as intermediates. In addition, their size with the range from 15 to 40 nm was easily operated with changing conditions, such as aging period and sodium hydroxide concentration. X-ray diffraction measurement and high resolution transmission electron microscopic observation revealed that basically single-crystalline ITO nanoparticles were successfully obtained, and doped tin atoms were uniformly distributed in the nanoparticles.
4:45 PM - F5.7/MM5.7
Zinc Oxide Organic Composites for Thin Film Transistor Applications.
Simon Bubel 1 , Claudia Busch 1 , Andreas Ringk 2 , Ralf Theissmann 1 , Peter Strohriegl 2 , Roland Schmechel 1
1 Faculty of Engineering and CeNIDE, University of Duisburg-Essen, Duisburg Germany, 2 Macromolecular Chemistry I, University of Bayreuth, Bayreuth Germany
Show AbstractMetal oxide semiconductors are considered as candidates to substitute silicon in large area and low-cost electronics. Therefore, when compared to silicon, it is essential that similar or simpler ways to control their charge carrier transport properties are available. This is especially important for such applications as field effect transistor devices. Since many metal oxides exhibit a highly reactive surface, one approach to alter their electronic properties could be the use of organic adsorbates. For the case of ZnO, we present two examples in which surface engineering dominates the macroscopic electrical properties of thin film transistors. In one experiment we introduce a novel facile low temperature (T~125°C) ZnO precursor process which allows the formation of ZnO layers with a thickness of approximately 7 nm and a field effect mobility exceeding 1 cm^2/Vs. Because of the low thickness, these films facilitate the investigation of surface induced changes on their electronic properties such as thermal charge carrier concentration and atmospheric stability. The layers were modified using pyrrolidone and phosphonic acid linkers attached to different moieties. In another experiment we use ZnO nanoparticles functionalized with the same adsorbates as described for the first experiment. Here these moieties act as dispersing agents or electrically active spacers between the ZnO particles. It can be shown that this approach allows for a macroscopic doping of the nanoparticles, in addition to the low temperature processability of these nanoparticles from an ink like dispersion.
5:00 PM - F5.8/MM5.8
Spray Deposited Lithium-doped Zinc Oxide Thin-film Transistors with Electron Mobility Exceeding 50 cm2/Vs.
George Adamopoulos 1 , Donal D Bradley 1 , Thomas Anthopoulos 1
1 Physics, Imperial College, London United Kingdom
Show AbstractThe high optical transparency and excellent charge transport characteristics combined with their excellent chemical stability and mechanical tolerance make oxide semiconductors attractive for applications in large area opto-/electronics and particularly thin-film transistors (TFTs). However, the vast majority of high performance oxide-based transistors reported to date are fabricated using sophisticated deposition methods that are usually incompatible with large area processing and hence potentially expensive. Here, we show an alternative processing method based on spray pyrolysis and soluble precursor molecules for the deposition of high-performance doped oxide semiconductors onto large area substrates under atmospheric conditions. Using this simple technique we are able to realise lithium-doped zinc oxide n-channel TFTs that are characterised by field-effect mobilities of >50 cm2/Vs, channel current on/off modulation ratio >10^6 and almost hysteresis-free operation. The physical properties of Li-ZnO films were investigated using a range of characterisation techniques namely AFM, XRD, Raman and Photoluminescence spectroscopy, spectroscopic ellipsometry and FTIR. Structural studies show that Li doping can lead to either interstitial or substitutional doping depending on the doping level. Interstitial doping was observed for Li concentration <1% and found to yield TFTs of high mobility. The latter was attributed to an increase in the average crystal size of Li-ZnO films. For Li doping concentration >1% (stoichiometry of precursor solution) it was shown that substitutional doping of Zn by Li occurs resulting to a drastic reduction in the average crystal size and interplanar spacing accompanied by a significant reduction in the electron field-effect mobility. The present results demonstrate that spray pyrolysis is a versatile tool for the deposition of oxide semiconductors onto large area substrates and provides a new route for the rapid development of materials far beyond those accessible by traditional deposition methods.
5:15 PM - F5.9/MM5.9
Ink-jet Printing of In2O3-ZnO 2D-structures from Solution.
Jenny Tellier 1 , Marija Kosec 1 , Barbara Malic 1 , Danjela Kuscer 1
1 , Jozef Stefan Institute, Ljubljana Slovenia
Show AbstractOxide semiconductors in the In2O3-ZnO system are highly transparent in the visible range and their electrical conductivity can be tuned by varying the ratio of constituents, making them good candidates for transparent electronic devices. We have studied the processing of solutions that enable the in-situ shaping of the structures with the thickness of a few nanometers and the lateral resolution of about 40 μm for the design of thin-film-transistors (TFTs) by piezoelectric ink-jet printing.The printing ink was based on the precursor solution consisting of In-isopropoxide and Zn-acetate in 2-methoxyethanol which was originally designed for Chemical Solution Deposition (CSD) of thin films on glass and silicon substrates. The thin films were organics-free and amorphous upon heating at as low as 150°C and crystallised upon heating at 450°C as determined by FTIR and XRD analyses, respectively.The viscosity and the surface tension of the ink needed to be adapted to reach the target values of the Dimatix printer: 10-12 mPas and 28-32 mN/m, respectively. The viscosity of the original CSD-solution was 3.4 mPas and by admixing a highly viscous solvent 1,3-propanediol (41 mPas) in a 55/45 volume ratio it reached 9.6 mPas. The surface tension of the ink was 34 mN/m. Further, the printing parameters: the cartridge and substrate temperature, and the drop spacing were adjusted to allow patterning with a good resolution on selected substrates.Precise and reproducible structures were obtained by ink-jet printing According to microstructural, chemical and XRD analyses, the structures heated at 150°C in air were amorphous, contained no organics, and crystallized upon heating at 450°C. The thickness of one printed layer was about 35 nm. Functional properties of films will be reported as well.
5:30 PM - F5.10/MM5.10
A Low-temperature Solution Precursor for In2O3-based Transparent Conductors.
Robert Pasquarelli 1 , Maikel van Hest 2 , Alexander Miedaner 2 , Calvin Curtis 2 , John Perkins 2 , Ryan O'Hayre 1 , David Ginley 2
1 Metallurgical and Materials Engineering, Colorado School of Mines, Golden, Colorado, United States, 2 , National Renewable Energy Laboratory, Golden, Colorado, United States
Show AbstractTransparent conducting oxide (TCO) thin-films play a critical role in many current and emerging opto-electronic devices due to their combination of high transparency in the visible region of the spectrum and tunable electronic conductivity. Atmospheric-pressure solution deposition is an attractive alternative to conventional vacuum-based TCO deposition techniques due to its ease and potential to lower device manufacturing costs. Solution precursors for In2O3 are of particular interest for material systems such as indium-tin-oxide (ITO) and more recently amorphous indium-zinc-oxide (a-IZO). We have reported on IZO thin-films prepared by ultrasonic spray deposition from an indium-zinc formate precursor at 300-400°C with good optical transmittance (>80%) and conductivities of ~50 S/cm [1]. However, the processing temperatures required for this and other traditional precursors are too high for many applications, such as thin-film photovoltaics and processing on flexible plastic substrates, which generally require temperatures < ~200°C. Here, we report on the exploration of the pentanuclear oxo-alkoxide cluster of In5O(isopropoxide)13 as a new low-temperature precursor for In2O3 thin-film deposition. The initial decomposition of this precursor occurs at temperatures as low as 150-170°C. The decomposition process and phases formed under various atmospheres were investigated as a function of temperature using thermogravimetry, differential scanning calorimetry, mass spectrometry, and X-ray diffraction. Characterization of the decomposition of the precursor, as well as initial results on the structural, optical, and electronic properties of the alkoxide deposited films, will be presented.[1] Pasquarelli et al., Inorg. Chem. 49, 5424 (2010).
Symposium Organizers
Soeren Steudel IMEC
Shelby F. Nelson Eastman Kodak Company
Veit Wagner Jacobs University Bremen
Heiko Thiem Evonik Degussa GmbH
F6/D3/G7: Joint Session: Novel Manufacturing Strategies for Electronic Devices
Session Chairs
Jurgen Daniel
Soeren Steudel
Wednesday AM, December 01, 2010
Room 311 (Hynes)
9:30 AM - F6.1/D3.1/G7.1
Chemically Modified Ink-jet Printed Electrodes for Organic Field-effect Transistors.
Gregory Whiting 1 , Tse Nga Ng 1 , Natasha Yamamoto 1 , Ana Arias 1
1 , Palo Alto Research Center (PARC), Palo Alto, California, United States
Show AbstractInk-jet printing is a desirable manufacturing technique for electronic devices as this mask-less, additive method should allow for integration of different electronic components over large substrate areas at low cost. In order to realize entirely jet-printed devices, appropriate printed electrodes for organic semiconductor-based field effect transistors (FETs) must be chosen. Generally, gold is used as the source and drain contacts in these devices. While gold creates good contact with many organic semiconductors, its high price makes it non-ideal for large-scale manufacture. There is therefore a desire to investigate other conductors for printed devices, and typically printable conductive inks are silver based, which is lower cost and allows for low-temperature processing, but can lead to poor energy level matching with the organic semiconductor. This report will study the use of both a nanoparticle silver ink as well as a soluble silver precursor ink and will show that by modifying the surface chemistry of the printed silver contacts through solution-based self-assembly of the organic electron acceptor 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), the electronic and wetting characteristics of the electrodes can be tailored. Combining these modified electrodes with p-type organic semiconductors such as 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS-pentacene), and polymer/small molecule (acene-type) blend semiconductors results in a significant improvement in device performance over the untreated electrodes, yielding high-quality devices with field-effect mobilities > 1 cm2 V-1 s-1. The effect of this treatment on field-effect transistors incorporating n-type small molecule organic semiconductors will also be discussed.
9:45 AM - F6.2/D3.2/G7.2
Subfemtoliter Inkjet for 3-V Operation, High Mobility Organic Transistors.
Tomoyuki Yokota 1 , Tsuyoshi Sekitani 1 , Yoshiaki Noguchi 1 , Kenjiro Fukuda 1 , Ute Zschieschang 2 , Hagen Klauk 2 , Tatsuya Yamamoto 3 , Kazuo Takimiya 3 , Masaaki Ikeda 4 , Hirokazu Kuwabara 4 , Takao Someya 1 5
1 , University of Tokyo, Tokyo Japan, 2 , Max Planck Institute for Solid State Research, Stuttgart Germany, 3 , Hiroshima University, Higashi-Hiroshima Japan, 4 , Nippon Kayaku Co., Ltd., Tokyo Japan, 5 , Institute for Nano Quantum Information Electronics, Tokyo Japan
Show AbstractWe have fabricated top-contact p-channel organic transistors with very high transconductance by inkjet technology with subfemtoliter accuracy. A gate dielectric is formed using single-molecule-thick self-assembled monolayer (SAM). Very fine source/drain electrodes with 2-μm-linewidth are printed using subfemtoliter inkjet directly on high mobility organic semiconductors, dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (DNTT) [1], and channel length is systematically changed with ranging from 2.5 μm to 98 μm. The TFT with channel length of 98 μm exhibited a high mobility of 1.2 cm2/Vs within 3-V operation. Furthermore, the TFT with channel length of 2.5 μm exhibited a high transconductance of 254 μS/mm, which is the highest value among organic transistors fabricated by using direct printing methods.These transistors are fabricated by vacuum evaporation, solution, and inkjet printing process. First, 30-nm-thick Al layer is thermally evaporated through a shadow mask as gate electrode. Second, we form a gate dielectric layer, which comprisies thin layers of 4-nm-thick aluminum oxide and 2-nm-thick molecular SAMs (n-octadecylphosphonic acid) [2]. A thin aluminum oxide layer with a large density of hydroxyl groups for molecular adsorption is formed by oxygen-plasma treatment (300W 30 min) and a SAM layers are prepared from a 2-propanolsolution at room temperature. On the dielectrics, 30-nm-thick p-type organic semiconductor DNTT [1] is patterned by thermal evaporation through a shadow mask. Finally, on the organic semiconductor films, we printed silver lines by inkjet printing systems with subfemtoliter accuracy and sintered at 90 °C for 5 hours in nitrogen environment to form source and drain electrodes.We thank Harima Chemicals for providing high-quality Ag nanoparticles, and SIJ Technology for technical support in the inkjet process. This work is partially supported by Special Coordination Funds for Promoting, JST/CREST and KAKENHI (Wakate S). One of the authors (T.Y.) is grateful to the research fellowships for young scientists of JSPS. This study was partially supported by JST/CREST and NEDO.[1] T. Yamamoto and K. Takimiya, J. Am. Chem. Soc. 129, 2224 (2007).[2] H. Klauk, U. Zschieschang, J. Pflaum and M. Halik, Nature 445, 745 (2007).
10:00 AM - F6.3/D3.3/G7.3
Structure and Properties of Gravure Printed Organic Diodes.
Kaisa Lilja 1 , Timo Joutsenoja 1 , Donald Lupo 1
1 Department of Electronics, Tampere University of Technology, Tampere Finland
Show AbstractThe development of organic electronic components, such as diodes and transistors, offers the possibility to manufacture flexible and lightweight electronics using cost-effective processes. We report characteristics and properties of gravure printed organic diodes that are fabricated using a process that is scalable to high-volume production. The diodes consist of a layer of poly(triarylamine) (PTAA) sandwiched between copper and silver electrodes. A wet etching process where the etch resist was printed by rotary screen printing was used to pattern the copper cathode. The PTAA and silver layers were printed using a laboratory scale automatic gravure printing press. The diode fabrication and characterization was performed in ambient laboratory conditions. The diode characteristics showed no significant degradation after months of storage.Previously, we have demonstrated printed organic diodes as RFID rectifiers and as the active components in a display driving circuitry. [1,2] In these applications, a sufficient rectification ratio is needed. The used diode structure has a significant effect on the performance of the diodes. Here, we report a thin interfacial layer that reduces the reverse current of the printed diodes without having a notable effect on the forward characteristics above 1 V. This enables the diodes to be used for applications that require low reverse currents and/or high rectification ratios.References:[1] K. E. Lilja, T. G. Bäcklund, D. Lupo, T. Hassinen, T. Joutsenoja, Org. Electr. 10 (2009) 1011.[2] K.E. Lilja, T.G. Bäcklund, D. Lupo, J. Virtanen, E. Hämäläinen, T. Joutsenoja, Thin Solid Films. 518 (2010) 4385.
10:15 AM - **F6.4/D3.4/G7.4
Low-temperature, Solution-processing of Organic and Metal Oxide Field-effect Transistors.
Henning Sirringhaus 1
1 Cavendish Laboratory , University of Cambridge, Cambridge United Kingdom
Show AbstractOrganic semiconductors have been considered for some time as an attractive class of materials for realising electronics on plastic substrates by low-temperature solution processing and direct-write printing. However, there are also certain inorganic semiconductors which are amenable to solution processing, in particular metal oxide semiconductors. We have worked on both classes of materials and in this presentation we will present the status of device performance achievable with both approaches and discuss specific aspects of the device and materials physics of organic semiconductor as well as metal oxide field-effect transistors.
10:45 AM - F6/D3/G7
BREAK
11:15 AM - **F6.5/D3.5/G7.5
Enabling Roll-to-roll Manufacturing of Flexible Electronics: Advances in Vacuum Deposition, Photolithography and Wet Processing of Thin Film Multilayers on Flexible Polymeric Substrates.
Mark Poliks 1 2 , James Switzer 2 , Paul Wickboldt 2 , Bruce White 2 , Bahgat Sammakia 2
1 Research and Development, Endicott Interconnect Technologies, Inc., Endicott, New York, United States, 2 Center for Advanced Microelectronics Manufacturing (CAMM), State University of New York at Binghamton, Binghamton, New York, United States
Show AbstractThe Center for Advanced Microelectronics Manufacturing (CAMM) is an academic-industry- government research and development center established by an award from the Flex Tech Alliance (formerly called the United States Display Consortium) to Binghamton University, Endicott Interconnect Technologies and Cornell University. The CAMM was established to demonstrate the feasibility of roll-to-roll (R2R) electronics manufacturing by acquiring first generation tools and establishing processes capable of producing low volume prototypes. The CAMM addresses R2R fundamental enabling science, technologies, and system design (integration, performance, yield and manufacturing feasibility) issues. This revolutionary approach will enable both ubiquitous and disposable electronic devices.Recent R2R research activities include: single micron photolithography and interlayer registration on unsupported flexible PET and PEN, as well as vacuum deposition of Al, Si, their oxides and ITO. The CAMM has produced a number of products and technologies including: flexible sensors, intravascular ultrasound devices, flexible polymer optical waveguides and structured surfaces for tailored wetting. Having established this suite of film deposition, lithography and etch capabilities, our next goal is demonstration of thin film transistor fabrication. A process flow based on zinc oxide and gallium indium zinc oxide TFTs is being developed. Sputtered SiO2, PECVD Si3N4 , and sputtered HfO2 are be explored for use as gate dielectrics. The demonstration of these high performance, low cost thin TFTs is a critical first step in generating the process, device, and desgn infrastructure required to realize the revolutionary products enabled by R2R manufacturing.
11:45 AM - F6.6/D3.6/G7.6
Mass-printed Integrated Circuits with Enhanced Performance Using Novel Materials and Concepts.
Heiko Kempa 1 , Mike Hambsch 1 , Kay Reuter 1 , Georg Schmidt 1 , Michael Stanel 1 , Maxi Bellmann 1 , Arved Huebler 1
1 Institute of Print and Media Technology, TU Chemnitz, Chemnitz Germany
Show AbstractLab-scale experiments, which were demonstrating the basic suitability for printing of electronic devices and circuits of so-called mass-printing techniques, which are based on patterned ink transfer from rotating cylindrical printing forms to flexible substrates moving with a speed of several m/s and which therefore exhibit an unrivalled productivity for large numbers of copies, resulted in transistor circuits with performances not sufficient for targeted application scenarios. [1] Further developments aiming at enhanced circuit performance while avoiding decline in productivity have three basic options: i) reduction of critical structure dimensions, ii) enhancement of charge carrier mobility and iii) novel concepts of circuitry.i) Optimization of conventional printing techniques and application of innovative modifications has led to transistor channel lengths below 20 µm, resulting in stage delay times as low as 7 ms. [2] However, further reduction of these values will be connected with superlinear increase of efforts in terms of investment costs and manpower. In addition, parasitic effects are limiting the reduction of switching times at small transistor dimensions, which require further technological challenges to be overcome.ii) Progress in synthesis and production of soluble organic semiconductor materials has led to impressive progress in this respect. Especially the commercial availability of relevant amounts of printable formulations of small molecules, namely TIPS-Pentacene, with charge carrier mobilities of the order of 1 cm2/Vs has facilitated printing of high-mobility transistors and circuits thereof. [3]iii) Undoubtedly, the introduction of complementary circuitry in printed electronics will lead to an immediate enhancement of circuit performance. Due to the recent availability of stable and printable n-type semiconductors with decent mobility, this process is currently on the way. [4] However, control of threshold voltage of printed transistors by means of a permanently stored charge in the gate dielectric allows for an alternative quasi-complementary approach using enhancement and depletion transistors that might turn out to be as effective as the usage of different (n- and p-type) semiconductors. [5]We report on progress in terms of performance of mass-printed integrated circuit which goes beyond reduction of critical structure dimensions. In particular, we focus on printing of highly performing p- and n-type semiconductors and on printed quasi-complementary circuits using charged gate dielectrics.[1] A. Hübler et al., Org. Electr. 8 (2007) 480.[2] G. Schmidt et al., subm. to Org. Electr. (2010).[3] S.K. Park et al., IEDM Tech. Digest (2005) 105.[4] H. Yan et al., Adv. Mater. 20 (2008) 3393.[5] K. Reuter et al., Org. Electr. 11 (2010) 95.
12:00 PM - **F6.7/D3.7/G7.7
Towards Roll-to-roll Fabricated Organic Devices.
Paul Blom 1 , Ton van Mol 1 , Ronn Andriessen 1 , Andreas Dietzel 1 , Erwin Meinders 1 , Gerwin Gelinck 1 , Herman Schoo 1
1 , TNO/Holst Centre, Eindhoven Netherlands
Show AbstractOrganic light-emitting diodes (OLEDs) and organic photovoltaic devices (OPV) have the potential to revolutionize the lighting and energy harvesting market. For lighting applications OLEDs made on flexible foils have a number of beneficial properties, such as free form factor, tunable color, being difficult to break compared to glass, having a large area emitting surface, and being potentially very efficient and low cost. For OLED lighting and signage, the layer quality requirements can be harsher as compared to OPV. One of the reasons is that for OLED devices, any (major) layer in-homogeneity causing an electric trouble will result ultimately in a visual defect. For OPV this will “only” affect efficiency. Another difference is that organic light emitting diodes (OLED) are more very sensitive to moisture and oxygen. The cathode, typically BaAl, easily oxidizes and this oxidation leads to formation of black spots. Also the organic emitter can degrade under the influence of oxygen. Both effects are undesired and necessitate the need for good encapsulation of the OLED. Today, OLED’s (on glass) are encapsulated with either a metal or glass lid with a cavity. Despite its effectiveness in terms of encapsulation, glass or metal lid packaging is expensive and prevents the possibility to fabricate thin, flexible devices. At the Holst Centre flexible OLED lighting and OPV architectures are being developed including thin film barriers which can be processed with roll-to-roll (R2R) compatible technology with high yield.
12:30 PM - F6.8/D3.8/G7.8
Self-aligned Fabrication of Flexible Organic Thin Film Transistors by Means of R2R-compatible Nanoimprint Lithography.
Barbara Stadlober 1 , Andreas Petritz 1 , Ursula Palfinger 1 , Thomas Rothlaender 1 , Frank Reil 1 , Herbert Gold 1
1 Institute of Nanostructured Materials and Photonics, Joanneum Research, Weiz Austria
Show AbstractOrganic thin film transistors (OTFTs) need to fulfil several performance requirements in order to be applicable in e.g. active matrix display backplanes. On the one hand high on/off ratios are required in the drain current to achieve a better contrast ratio, on the other hand the area consumption should be as small as possible. Both demands can be met by scaling down the dimensions of the transistors, as smaller channel length values result in higher currents. We’ve realized the miniaturization of flexible OTFTs by use of self-aligned nanoimprint lithography (NIL) for the definition of the source and drain electrodes in the submicron range. PET as well as polycarbonate films were used as the substrate. It is shown that this approach is compatible with different organic dielectric materials, as for example a BCB derivative and an Ormocer™ material. The devices show satisfactory saturation in the output characteristics even for channel length values in the submicron regime as long as proper scaling of the dielectric layer thickness is maintained. The nanoimprinting was either based on hot embossing or on UV-nanoimprint lithography. Self-alignment, which is very important for large-area NIL techniques, was achieved by either utilizing a back-substrate exposure technique or by direct imprinting. In the former approach the nanoimprinted gate layer defines the pattern of the source-drain layer thus resulting in perfect alignment and minimized gate-to-source and gate-to-drain overlaps. In the direct imprint approach a metal layer is applied first on the imprint resist coated flexible substrate followed by the coating of an ultrathin dielectric layer. Then imprinting was performed defining both the gate as well the channel electrodes in one step. The device is finalized by the application of the organic semiconductor. The self-aligned submicron devices are either of n- or p-type and show proper device characteristics with a very large bandwidth as is expected for transistors with minimized electrode overlaps and therefore decreased parasitic gate capacitance.
12:45 PM - F6.9/D3.9/G7.9
Concepts of Metal-organic Decomposition (MOD) Silver Inks for Structured Metallization by Inkjet Printing.
Claudia Schoner 1 , Stephan Jahn 1 , Thomas Blaudeck 1 , Alexander Jakob 2 , Heinrich Lang 2 , Reinhard Baumann 1
1 Digital Printing and Imaging, Chemnitz University of Technology, Chemnitz Germany, 2 Inorganic Chemistry, Chemnitz University of Technology, Chemnitz Germany
Show AbstractInkjet printing has gained growing interest in the field of electronics for the manufacture of many devices of printed electronics such as OLEDs or solar cells. Moreover, patterned metallization at ambient conditions is a key issue for a cost-effective manufacturing of passive wiring components. Recently, Jahn et al. introduced the silver(I)-2-[2-(2-methoxyethoxy)-ethoxy]acetat as an aqueous metal-organic decomposition (MOD) ink without additional stabilizing ligands. Based on a silver salt concentration of 23 wt%, conductivities of printed structures of above 10^7 Sm^(-1) were obtained applying thermal or photo-thermal annealing techniques [1, 2]. In this contribution, we report about the further optimization of the MOD ink by varying the solvent base and increasing the silver salt concentration. Five different ink concepts were compared with respect to their key physical parameters relevant for inkjet printing and the final performance, including viscosity, surface tension, and density. The concepts include the usage of N-methyl-2-pyrrolidone as a humectant with low vapor pressure, addition of sodium lauryl sulfate as optional stabilizing ligand or addition of co-solvents such as diethylene glycole or acetonitrile. Following this route, printability could be achieved for inks with silver salt concentrations up to 45 wt% at maintained conductivity. References[1] S. F. Jahn, T. Blaudeck, R. R. Baumann, A. Jakob, P. Ecorchard, T. Rüffer, H. Lang, P. Schmidt, Chemistry of Materials 22 (10), 3067-3071 (2010). [2] S. F. Jahn, A. Jakob, T. Blaudeck, P. Schmidt, H. Lang, R. R. Baumann, Thin Solid Films 518 (12), 3218-3222 (2010).
F7: Material and Device Characterization I
Session Chairs
Wednesday PM, December 01, 2010
Room 309 (Hynes)
2:30 PM - **F7.1
Growth of High Density, Semiconducting Carbon Nanotube Arrays and Their Use in Thin Film Transistors.
John Rogers 1
1 , University of Illinois, Urbana, Illinois, United States
Show AbstractSingle walled carbon nanotubes configured as random networks or horizontally aligned arrays represent thin film type semiconductors that can be used in transistors and other devices. Techniques for solution deposition or dry transfer can integrate these materials onto low temperature substrates, such as thin sheets of plastic. The arrays offer the highest effective mobilities in such applications. This talk summarizes some recent advances in the growth of these arrays, with focus on achieving high densities and without metallic tubes.
3:00 PM - **F7.2
Organic Thin-film Transistors Based on Graphene Electrodes.
Paul Woebkenberg 1 , Goki Eda 3 , Dong-Seok Leem 2 , John de Mello 2 , Donal D. Bradley 1 , Manish Chhowalla 3 , Thomas Anthopoulos 1
1 Department of Physics and Centre for Plastic Electronics, Imperial College London, London United Kingdom, 3 Department of Materials Science, Imperial College London, London United Kingdom, 2 Department of Chemistry and Centre for Plastic Electronics , Imperial College London, London United Kingdom
Show AbstractTransparent conducting materials that are environmentally stable and capable of injecting and collecting both types of charges along with being solution processable are high desirable for a range of electronic applications. Here we demonstrate the use of solution-processed transparent and conducting chemically derived graphene (CDG) as air-stable ambipolar injecting electrodes in organic thin-film transistors and circuits. The CDG electrodes are patterned using a novel simplified photolithographic method, which effectively allows building complex high performance device architectures by means of fast and cost effective sheet-to-sheet solution processing. We demonstrate the versatility of these patterned CDG electrodes in three organic electronics applications: (i) hole, electron and ambipolar transporting organic transistors, (ii) complementary voltage inverters, and (iii) discrete low-voltage organic transistors based on a novel device architecture comprising a self-assembled monolayer nanodielectric. The present methodology paves the way to widespread utilization of CDG in state-of-the-art large area electronics.
3:30 PM - F7.3
Print Fabrication and Characterization of CNT Transistors on Plastic Films.
Hiroyuki Endoh 1 , Fumiyuki Nihey 2 , Hideaki Numata 2 , Kazuki Ihara 2 , Tsuyoshi Sekitani 3 , Takao Someya 3
1 Green Innovation Research Laboratories, NEC Corporation, Tsukuba, Ibaraki Japan, 2 , AIST Nanotube Research Center, Tsukuba, Ibaraki Japan, 3 , The Univ.Tokyo, Bunkyo-ku, Tokyo Japan
Show AbstractPrinting technology to fabricate carbon nano-tube thin film transistors (CNT-TFT) at low temperature on plastic films is developed. A simple ink-jet printing system was used for drawing the device patterns. The maximum temperature was 200 degrees during nano-silver electrode fabrication. The temperature of CNT-channel patterning is under 50 degrees. The widths of the source and drain electrodes were about 1 mm and the channel length were about 150 um. The thickness of the gate insulator was about 650 nm. The CNT-TFTs had p-type characteristics, and an on/off ratio of about 1000 was obtained. There is, however, a tradeoff between the on/off ratio and the drain current. We think it is due to the metallic CNTs. As the CNT density gets higher, the drain current increases. Simultaneously, the metallic CNT get connecting each other and the on/off ratio deceases. We expect the trade-off should be improved by decreasing metallic CNT concentration. We estimated mobilities from the TFT characteristics using device geometry. The estimated mobilities using over 95% purified semiconductive-CNT were ~5.1 cm2/Vs for the TFTs whose on/off ratio were more than 5,000. We also observed the CNT channel by conductive AFM, and it was shown that the active area was very small. Therefore, we expect the intrinsic carrier mobility based on the CNT networks should be much more value than estimated values. We fabricated CNT-TFT with an on/off ratio of 10,000 by printing methods on plastic films. It is expected mobility will be much increased by increasing CNT density. These results are promising to realize the low cost printable electronics using CNT-TFTs.
3:45 PM - F7.4
Stretchable Nanowire/Nanotube Electronic Devices.
Gunchul Shin 1 , Jaehyun Park 1 , Junghwan Huh 2 , Gyu Tae Kim 2 , Jeong Sook Ha 1
1 Chemical and biological engineering, Korea University, Seoul Korea (the Republic of), 2 School of electrical engineering, Korea University, Seoul Korea (the Republic of)
Show AbstractRecently, various kinds of future devices including micro-electronics and bio-implantable devices have been reported as curvilinear layouts on curved or stretchable surfaces of skin or organs. Silicon and polymer-based organics have been mostly used not only for commercial flat/rigid electronics but also for curvilinear flexible/stretchable electronics [1, 2]. However, 1-D materials such as nanowires and nanotubes are expected to be advantageous in future stretchable electronics with high performance and better integration due to their superior electronic properties and structurally high aspect ratios. In this paper, we report on the fabrication of stretchable nanowire/nanotube devices. Similar to the previous report [3], we have used two mechanical strategies, neutral mechanical plane and arc shaped interconnection. While the flexible polymer substrates were compressed or stretched, polymer/metal interconnections made arc shape to accommodate the strain without affecting the main device channel areas. Moreover, the whole device and interconnections were covered with flexible polymer to place the actual device onto the mechanically neutral plane. For the fabrication of stretchable nanowire/nanotube devices including transistors and inverters, we adopted the various patterning strategies of channel materials: Metal oxide nanowires (SnO2 and ZnO) grown by chemical vapor deposition (CVD) technique were transferred onto the stretchable polymer substrate via a sliding transfer method and the CVD grown single walled carbon nanotubes were transferred by using thermal tapes. Then electrical properties of the devices were measured while they were compressed or stretched, showing the high potential in application to wearable or bio-implantable device systems. [1] Viventi et al. “Conformal, Bio-Interfaced Class of Silicon Electronics for Mapping Cardiac Electrophysiology”, Science Translational Medicine 2:24ra22 (2010).[2] Ko et al. “Curvilinear Electronics Formed Using Silicon Membrane Circuits and Elastomeric Transfer Elements”, Small 5(23), 2703~2709 (2009).[3] Kim et al. “Stretchable and Foldable Silicon Integrated Circuits”, Science 320, 507-511 (2008).
4:00 PM - F7:Charac
BREAK
4:30 PM - F7.5
Anisotropic Properties of Strain Aligned Regioregular Poly(3-hexylthiophene).
Brendan O'Connor 1 , R. Kline 1 , Brad Conrad 2 , David Gundlach 2 , Lee Richter 3 , Dean DeLongchamp 1
1 Polymers Division, National Institute of Standards and Technology, Gaithersburg, Maryland, United States, 2 Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, Maryland, United States, 3 Surface and Microanalysis Division, National Institute of Standards and Technology, Gaithersburg, Maryland, United States
Show AbstractSemicrystalline polymer semiconductors are becoming a viable technology for large area and low-cost electronic applications. Charge transport in these materials is a complex combination of transport through and between anisotropic crystalline and amorphous regions of the polymer. As this technology matures a fundamental understanding of charge transport is concomitantly developing with device performance, however there remain many unresolved questions. Here, we employ a novel method to align the semicrystalline polymer poly(3-hexylthiophene) (P3HT) to gain insight into charge transport in this material system.The strain alignment process begins by casting the polymer on an octyltrichlorosilane (OTS) treated substrate then transferring the film to polydimethylsiloxane (PDMS). The P3HT-PDMS composite is strained to varying extents and held in place. The P3HT is then transferred from the strained PDMS to a range of secondary substrates for detailed morphological and electronic characterization. We apply a range of spectroscopic tools including UV-visible spectroscopy, atomic force microscopy, and x-ray diffraction to provide a detailed view of film morphology along with a range of organic thin film transistor (OTFT) measurements to probe the electronic properties. The P3HT film can be strained by over 150 % with the polymer backbone aligning in the stretch direction resulting in a dichroic ratio of over 7. The ability to initially cast P3HT on OTS provides OTFTs with high charge mobility while stretching the P3HT film can lead to mobility anisotropies of over 10. We show that mobility increases in the direction of polymer backbone alignment, and with increasing strain the mobility perpendicular to the alignment direction reduces at a faster rate than the mobility increases parallel to alignment. Additionally, we demonstrate the ability to apply a mobility tensor to the aligned polymer semiconductor data.The strain alignment approach provides a simple and effective method to align polymer films to investigate fundamental transport in semicrystalline polymer semiconductors. The ability to develop a high level of morphological and electronic anisotropy assists in illuminating features of charge transport that are difficult to distinguish in isotropic semicrytalline polymers.
4:45 PM - F7.6
Correlations of Energetic and Structural Order in P3HT Films – Key Parameters for High OFET Mobility.
Benedikt Gburek 1 , Richa Sharma 1 , Torsten Balster 1 , Veit Wagner 1
1 School of Engineering and Science, Jacobs University Bremen, Bremen Germany
Show AbstractAmong the top candidates for materials in low-temperature processed electronics, polymeric organic semiconductors play a prominent role. Most of them are soluble at room temperature and can therefore be processed under ambient conditions. In this study, organic field-effect transistors (OFETs) with the organic semiconductor P3HT are analyzed with respect to structural and energetic ordering, which are crucial parameters for high OFET performance. The active layer and the gate insulator are deposited wet-chemically by spin-coating under atmospheric conditions on polyethylene-terephtalate (PET) foils.Active P3HT layers with different degrees of structural ordering can be produced by varying the layer thickness. Phase contrast AFM images are used to determine the microscopic order and the domain size. The domain size increases systematically with layer thickness. Typical domain sizes are 50 nm in 2 nm thin films and more than 500 nm in thicker films. In order to analyze the correlation with the energetic disorder of the system, the curvature of transfer characteristics is taken into account. A suitable model for charge transport in disordered systems is the Vissenberg-Matters model. The model results in a gate-voltage dependent charge carrier mobility μ = μ0((VGS – Vth)/1 V)γ, where the exponent γ gives direct access to the energetic disorder of the system. The analysis reveals that the disorder parameter γ is high (3.1) in very thin P3HT films of just a few nanometers but gradually decreases to 1.0 when increasing the active layer thickness to 220 nm. The result shows the high energetic disorder in interface dominated thin films and increasing energetic order in thicker films. This energetic order is correlated with the structural properties of the film obtained by AFM.[1]The importance of this energetic and structural order for charge transport is reflected by the observed strong variation of charge carrier mobility. The mobility varies by more than two orders of magnitude in dependence of the film structure. Furthermore, increasing the film structural ordering by spin-coating from higher boiling-point solvents shows larger domain sizes in the P3HT layer. This results in improved energetic ordering with a low disorder parameter γ ranging from 1.7 to 0.8 and mobility increase by one order of magnitude.The analysis of energetic disorder proves to be highly advantageous in comparison to the commonly used method employing linear fits at a limited gate-voltage range, as our fits reproduce the whole transfer curve and offer more physical insight for material analysis. To ensure reliability of the results more than 10 transistors were measured and analyzed statistically for each examined layer thickness. Our study demonstrates the crucial role of active layer thickness and solvent selection for improved film structure in order to achieve the optimum material performance.[1] B. Gburek, V. Wagner, Organic Electronics 11 (2010), 814-819
5:00 PM - F7.7
Air-stable C60 Organic Transistors Assisted by Electric Dipoles in the Gate Dielectric.
Yoonyoung Chung 1 , Eric Verploegen 2 , Yoshio Nishi 1 , Boris Murmann 1 , Zhenan Bao 2
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 Chemical Engineering, Stanford University, Stanford, California, United States
Show AbstractWe present a novel method to enable air-stable operation of C60 organic field-effect transistors (OFETs).The performance and stability of electron-conducting (n-channel) OFETs have been worse than those of hole-conducting (p-channel) transistors in air due to the presence of electron-trapping species, such as water and oxygen. Although several organic semiconductors have been used to make n-channel OFETs with mobility values larger than 1 cm2/Vs, these transistors have only operated in an inert atmosphere. Thus, it is desirable to develop n-channel OFETs having similar performance and stability to their p-channel counterparts in order to maximize the benefits of complementary circuits.In this study, we utilized self-assembled monolayers to generate electric dipoles and built-in potentials. We found that it is possible to manipulate the electron energy levels in the channel region using these dipoles and that air-stable operation of C60 OFETs is achievable by choosing proper dipole moments. Our C60 OFETs exhibited an average mobility of 1.65 (±0.11) cm2/Vs after a 24-hour exposure to air, and they still operated with an average mobility of 0.73 (±0.06) cm2/Vs even after one week in air.
5:15 PM - F7.8
Probing the Solid-Liquid Interface During Deposition of Molecular and Polymer Semiconductors.
Ruipeng Li 1 , Lisong Xu 1 , Kui Zhao 1 , Mingjie Zhang 1 , Debora Marques 1 , Detlef-M. Smilgies 3 , John Anthony 2 , Aram Amassian 1
1 Materials Science and Engineering, Division of Physical Science and Engineering, KAUST, Thuwal Saudi Arabia, 3 , Cornell High Energy Synchrotron Source, Ithaca, New York, United States, 2 Chemistry, University of kentucky, Lexington, Kentucky, United States
Show AbstractLow-cost solution processes are deemed to be crucial to the future commercial success of organic electronics. As such, solution processing of small-molecules and polymers deserves special attention and in-depth investigation. As the liquid environment does not lend itself well to in situ probing via traditional surface science tools, we have developed alternative strategies to investigate solution processes (drop- and spin-casting) by simultaneously monitoring the formation of the thin film (i.e., heterogenous nucleation, deposition rate, solvation, crystallization, mosaicity, texture and phase separation) and the state of the solution (i.e., evaporation rate, concentration, aggregation/nucleation) in relation to processing conditions. We have done so by combining powerful techniques such as fast, in situ optical reflectometry, with quartz crystal microbalance, and/or grazing incidence X-ray scattering, thus gaining unprecedented insight into mechanisms and kinetics of self-assembly, crystallization, and thin film formation. Our results provide new insight into the formation of model solution-cast thin film systems of relevance to organic thin film transistors (e.g., TIPS-pentacene, TES-F-ADT, P3HT) prepared via drop- and spin-casting. Importantly, we demonstrate important differences between the growth behavior of polymers and small-molecules, which we use to relate carrier transport in OTFTs to growth behavior.
5:30 PM - F7.9
Mechanism of Memory Effect of an Organic Field Effect Transistor with Poly(α-methylstyrene) Insulating Layer Studied by Displacement Current Measurement and Photoelectron Yield Spectroscopy.
Gongweik Li 1 , Yasuo Nakayama 2 , Yutaka Noguchi 1 2 , Hisao Ishii 1 2
1 Graduate School of Advanced Integration Science, Chiba University, Chiba-shi Japan, 2 Center for Frontier Science, Chiba University, Chiba-shi Japan
Show AbstractRecently memory effect of an organic field effect transistor including poly(α-methylstyrene) (PαMS) as an insulating layer has been reported[1,2]. The state of the transistor is switched between ON and OFF states by applying a bias voltage. The formation of electret due to carrier injection to the PαMS layer during the biasing process has been proposed as the possible mechanism of the memory effect. But, the carrier injection was not directly observed, and the mechanism of possible trapping of the injected carriers for the electret formation is also not clarified. In order to understand the mechanism of the electret formation, we have investigated carrier behavior in a pentacene MIS device and transistor with PαMS layer by using displacement current measurement (DCM). In this technique, a current through a device is measured under a ramp voltage scan, giving useful information about carrier injection and accumulation. The increase of displacement current was clearly observed during the biasing process, demonstrating that holes are injected into the PαMS layer and trapped. By integrating the current, the total amount of the trapped charges was also determined. In the case of the reversed biasing process, the other change of displacement current due to detrapping was observed. These results clearly indicate the validity of electret model for the memory effect. To understand the observed trapping and detrapping processes, the electronic structure of PαMS was also investigated by using photoelectron yield spectroscopy (PYS). From the PYS, the ionization energy of PαMS was determined to be 6.7 eV. The detailed analysis of the PYS revealed that additional weak density of states locates within the gap region. Such gap state is expected to be the origin of the trapping. More detailed study by ultraviolet photoemission spectroscopy will be also reported.[1] K. J. Baegetal et al., Adv. Mater. 18, 3179 (2006). [2] M. Debucquoy et al., Org. Electonics. 10, 1252 (2009).
5:45 PM - F7.10
Gate-voltage-independent Contact Resistance in Pentacene Organic Field-effect Transistors.
Shree Tiwari 1 , William Potscavage 1 , Tissa Sajoto 2 , Stephen Barlow 2 , Seth Marder 2 , Bernard Kippelen 1
1 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States, 2 School of Chemistry and Biochemistry, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractVarious dopants for organic semiconductors are being developed to improve the carrier injection from the source electrode to the semiconductor in organic field-effect transistors (OFETs). Improvement in the carrier injection results in the reduction of the contact resistance [1], which is a crucial parameter for designing high-performance OFETs with short channel lengths. The contact resistance is highly dependent on applied gate voltage (VGS) and decreases significantly on increasing the |VGS|. Here we report a 0.5 kΩ-cm contact resistance in pentacene organic field-effect transistors, which is almost independent of VGS. This is achieved by selectively p-doping the semiconductor region beneath the source/drain electrodes with molybdenum tris[1,2-bis(trifluoromethyl) ethane-1,2-dithiolene] (Mo(tfd)3) [2]. Top-contact OFET device structures with Au source/drain electrodes and channel lengths varying from 25 μm to 200 μm were used for calculation of contact resistance. A 10 nm co-evaporated (1:1 ratio) layer of Mo(tfd)3 and pentacene was deposited under the metal electrodes and above the 50 nm pentacene layer for selective doping of the electrode-pentacene contacts of the OFETs. This selective doping results in improved mobility and threshold voltage values. A significant reduction in the width-normalized contact resistance (RCW) is observed (from 3.4 kΩ-cm to 0.5 kΩ-cm at VGS = -30 V) and the value of RCW is almost independent of applied VGS in the studied range of -15 to -30 V. The doping does not significantly affect the electrical stability of the devices [3].
[1] C. Vanoni, S. Tsujino, T.A. Jung, Appl. Phys. Lett. 90 193119 (2007).
[2] Y.B. Qi, T. Sajoto, S. Barlow, E.G. Kim, J.L. Brédas, S.R. Marder, A. Kahn, J. Am. Chem. Soc. 131, 12530 (2009).
[3] S.P. Tiwari, W.J. Postcavage, Jr., T. Sajoto, S. Barlow, S.R. Marder and B. Kippelen, Org. Elect. 11, 860 (2010).
F8: Poster Session: Inorganic TFT
Session Chairs
Thursday AM, December 02, 2010
Exhibition Hall D (Hynes)
9:00 PM - F8.1
Deep Level Transient Spectroscopy Studies of Indium Gallium Zinc Oxide Thin Film Transistors.
Yutaka Tokuda 1 , Tatsunari Shibata 1 , Toshiya Matsumura 1
1 Department of Electrical and Electronics Engineering, Aichi Institute of Technology, Toyota Japan
Show AbstractWe have characterized indium gallium zinc oxide (IGZO) thin film transistors (TFTs) by measuring the transfer and output characteristics and using current deep level transient spectroscopy (DLTS) in the temperature range from 80 to 300 K. The bottom gate structure IGZO TFTs on glass substrates were used with a Mo gate electrode under a SiO2 layer as a gate insulator. Al was used as source and drain electrodes. The drain current decreased with decreasing temperature, corresponding to the decrease of the mobility. The threshold voltage shifted to the more positive values with decreasing temperature, probably due to filling of traps with shallower energy levels. DLTS measurements were carried out by applying the gate bias pulses for IGZO TFTs with the source electrode shorted to the drain electrode. This MOS capacitor was biased into accumulation to fill traps with electrons. Subsequently, it was biased into depletion to emit electrons from filled traps. This caused current transients for the MOS capacitor which were processed into DLTS signals. DLTS signals with the DLTS time constant of 1.82 ms exhibited the broader spectrum with a peak at about 135 K, which reveals the continuous energy distribution of defect states. The trap densities were in the range 8.2x1013 cm-2eV-1 at Ec-0.12 eV to 2.0x1013 cm-2eV-1 at Ec-0.50 eV with the maximum of 1.8x1014 cm-2eV-1 at Ec-0.18 eV assuming the capture cross section of 10-15 cm2. Both interface states and bulk states are considered to be responsible for the trap densities obtained from DLTS measurements of the MOS capacitor.
9:00 PM - F8.10
Spin-on Glass As Low Temperature Gate Insulator.
Miguel Dominguez 1 , Pedro Rosales Quintero 1 , Alfonso Torres Jacome 1 , Joel Molina Reyes 1 , Mario Moreno Moreno 1 , Francisco De la Hidalga Wade 1 , Carlos Zuniga Islas 1 , Wilfrido Calleja Arriaga 1
1 Electronics Department, National Institute for Astrophysics, Optics and Electronics (INAOE), Tonantzintla, Puebla, Mexico
Show AbstractAt present, Thin-Film Transistors (TFTs) research field is of high interest because of development of low cost products, such as sensors and LCDs. Low temperature deposition processes are required in order to use flexible substrates. Nevertheless, the performance of the gate insulators at temperatures below 300 °C is not as good as in CMOS technology [1]. Thus, physical and electrical properties of semiconductor and insulator materials deposited at these low temperatures must be improved. In this work, we report the characterization of Spin-On Glass (SOG) as low temperature gate insulator. There have been attempts to use SOG as gate insulator for TFTs, but it was only reported at 425 °C [2]. Our SOG film was deposited at a temperature of 200°C, which is compatible to use on flexible substrates. The optical and electrical characterization showed that the refractive index and dielectric constant are very close to those of thermally grown SiO2. Also, analysis of surface roughness by AFM is presented. We demonstrated the use of SOG as gate insulator, fabricating and characterizing inverted staggered a-SiGe:H TFTs. The observed results are promising and suggest that SOG films deposited at 200°C in the Laboratory of Microelectronics of INAOE could be an alternative to improve electrical characteristics of TFTs on low temperature flexible substrates. [1] P. C. Joshi, A. T. Voutsas, and J. W. Hartzell “high performance gate dielectric for low temperature TFTs” electrochemical society Abs. 776, 215th meeting, 2009.[2] J. H. Cheon, J. H. Bae, and J. Jang “Inverted staggered Poly-Si Thin film transistor with planarized SOG gate insulator” IEEE Electron Device Lett., vol. 29, no. 3, pp. 235-237, March 2008.
9:00 PM - F8.11
Ohmic Contacts to InZnO on Paper Substrates.
Erica Douglas 1 , Rohit Khanna 1 , David Norton 1 , Fan Ren 2 , Steve Pearton 1
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States, 2 Chemical Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractTransparent and flexible electronics are becoming ever increasingly attractive for use in low cost, wearable applications. In order to achieve higher performing flexible electronics, in particular on paper based substrates, processing temperatures must be below 200°C. Therefore it is imperative to achieve low resistance Ohmic contacts with little or no annealing. The study of Ti/Au Ohmic contacts on n-type amorphous Indium Zinc Oxide deposited on cellulose paper is reported. To use paper substrates, it is crucial to reduce the substrate degradation due to absorption of water and other solvents typically encountered during device fabrication. A barrier layer was utilized to coat the paper substrate on both sides to help prevent solvent absorption and reduce starting surface roughness. Sheet resistance was found to vary from 24 Ω/square to 17 Ω/square and transfer resistance was ~ .045 Ω .mm for the as-deposited and low temperature annealed samples. The contact resistance was independent of measurement temperature, indicating that field emission plays a dominant role in the current transport.
9:00 PM - F8.12
Electrical Characterization of Close-packed ZnSe Nanoparticle Films.
Jaewon Jang 1 , Rungrot Kitsomboonloha 1 , Lakshmi Jagannathan 1 , Hongki Kang 1 , Vivek Subramanian 1
1 EECS, UC Berkeley, Berkeley, California, United States
Show AbstractZnSe has received attention in recent years as a potential candidate semiconductor for a range of electronic applications. In particular, ZnSe nanoparticles are potentially a promising route for the realization of solution-processed semiconductor thin films for use in such applications as transistors, sensors, and photovoltaic devices. Here, we study the properties of close-packed films of ZnSe nanoparticles. ZnSe nanoparticles were synthesized by a wet chemical method in an aqueous solution at room temperature. The synthesized ZnSe nanoparticles were spherical in shape with a diameter of about 25 nm, as confirmed by X-ray diffraction and transmittance electron microscopy. Using spin-coating of a redistributed aqueous ZnSe nanoparticle solution to cause rapid solvent evolution, close-packed ZnSe nanoparticles films were deposited onto SiO2 substrates. The packing and surface roughness of the films was measured by atomic force microscopy. To determine electrical properties of the resulting films as a function of thermal annealing, the conductivity of the films was investigated and related to film sintering temperature. Films sintered at 500°C in vacuum for 30 minutes showed a dramatic increase in conductivity of as much as three orders of magnitude. Measurements of conductivity were correlated to Hall Effect measurements to understand the semiconducting nature of the films as a function of sintering conditions.
9:00 PM - F8.14
High Performance Low Temperature Poly-Si Thin-film Transistor.
Min-Sun Kim 1 , Young Seok Kim 1 , Hyun Min Cho 1 , Bongkwan Shin 1 , Min Gi Kwak 1
1 Display components and materials research center, Korea Electronics Technology Institute, Gyunggi Korea (the Republic of)
Show AbstractThe characteristics of a flat panel display device, such as brightness, resolution, and image transport speed are very much dependent on the carrier mobility of thin-films transistors (TFTs). Especially, 3D display panels need faster response speed than 2D display panels because human-eyes fatigue. Therefore, much attention has focused on crystallization techniques and low temperature polycrystalline silicon (LTPS) TFTs, because of the several hundred times higher carrier mobility than that of amorphous Si (a-Si) TFTs and promising applications of LTPS TFTs in 3D flat panel displays. As a crystallization technique, excimer laser scanning (ELS), and metal-induced lateral crystallization (MILC) are representative methods. However, these crystallization techniques have some problems. ELS is the sole technology for LTPS crystallization method, it suffers from two major problems such as non-uniform crystal quality and high production cost. On the other hand, MILC has many advantages such as low temperature processes, smoother surface, higher degree of crystal uniformity, and etc. However, the carrier mobility of MILC poly-Si is lower than that of excimer laser crystallization. Generally, the MILC poly-Si grains have many different orientations, so it has many grain boundary defects. The presence of poly-Si grain boundary defects in the channel region of TFTs affects the electrical performance. Therefore, control of the orientation of Si crystal grains enables us to control the alignment of grain boundaries thus electrical performance can be improved because of reducing randomly oriented grain boundaries and grain boundary defects from device area. Previous research on the orientation of MILC poly-Si has been reported.In this work, a series of TFTs having crystal filtered (CF) poly-Si grains (here-in-after CF-TFTs) with various crystal filter widths were fabricated to study the relationship between the crystal filtering and the field-effect mobility. A conventional MILC-TFT (channel regions are crystallized by MILC, so TFTs have randomly oriented poly-Si grains; here-in-after MILC-TFTs) was also fabricated for comparison. In addition, we made multi-channel paths for carrier mobility so carrier mobility faster than one-channel path mobility. This TFT structure is able to design driving circuit and device.
9:00 PM - F8.16
Amorphous IGZO TFTs and Circuits on Highly Flexible and Dimensionally Stable Kovar (Ni-Fe alloy) Metal Foils.
Shahrukh Khan 1 , Xiaoxiao Ma 1 , Miltiadis Hatalis 1
1 Electrical Engineering, Lehigh University, Bethlehem, Pennsylvania, United States
Show AbstractElectronics on flexible substrates is highly desirable for display-based applications and for integration of large area systems in general. Inexpensive and light-weight flexible electronics would be more rugged and portable than the ones on rigid substrates. Although plastic substrates are considered these days, they still pose significant engineering challenges due to their chemical and mechanical instability. Thin metal foils on the other hand offer greater dimensional stability and allow for implementation of circuit designs with small feature sizes and is compatible with existing TFT processes. Kovar 42 (Ni-Fe alloy) is such a metal foil with low and nominally constant coefficient of thermal expansion over a wide range of temperature and excellent mechanical and chemical robustness.In this work, we stabilize cold-rolled Kovar 42 sheets and limit the thermal run-out on them by a pre-anneal process at 800oC. Detailed metallographic analysis combined with traditional thermal run-out examination is done to ensure that the pre-anneal process limits the thermal run-out to within 100ppm. After substrate annealing, Kovar 42 alloy retains high yield strength and good flexibility with the re-crystallized structure containing large isotropic grain between 20-50μm. Once the metal foils are stabilized, IGZO TFTs and circuits are fabricated on 100μm thick, 6 inch Kovar 42 foils. The Kovar 42 foils are coated with 1 μm thick PECVD SiO2 layer on both sides to electrically isolate the substrate as well as to prevent thermal expansion mismatch. The IGZO TFT devices have a staggered, bottom-gate architecture. RF sputtered Mo, lithographically patterned and wet etched, forms the gate layer. A 100 nm thick SiO2 is then deposited by PECVD at 300oC. Then, 50 nm of IGZO thin film is deposited by RF sputtering from a 6-inch diameter commercially available IGZO target (1:1:1 molar ratio of In2O3:Ga2O3:ZnO. The optimized IGZO active layer is patterned by wet etching in dilute HCl. Contact openings to the gate pads are accomplished by lithography and selective etching of the oxide layer. Finally, Mo source and drain metallization is done by RF sputtering and subsequent lift-off. Non-flexed TFTs have field effect mobility of 14 cm2/V.s, threshold voltage around 3 V and sub-threshold swing of 0.6 V/decade and on/off current ratio exceeding 107. TFT characteristics were also evaluated when flexed at different radii corresponding to uniaxial tensile strain applied parallel to source-drain current path and will be reported. To demonstrate the viability of oxide-based device integration, simple circuits such as inverters and pseudo-logic circuits are designed, fabricated and tested. This is the first successful integration of IGZO TFTs and circuits on Kovar 42 alloys and the results suggest that device integration on such a highly flexible substrate has the potential to be a very robust process easily transferable to industrial applications.
9:00 PM - F8.17
Tin Oxide Thin-film Transistors by Using Plasma Enhanced Atomic Layer Deposition.
Byung Kook Lee 1 2 , Seok Hwan Kim 1 , Jae Ki Min 1 , Sun Suk Lee 1 , Taek-Mo Chung 1 , Chang Gyoun Kim 1 , Jinha Hwang 2 , Ki-Seok An 1
1 Device Materials Research Center, Korea Research Institute of Chemical Technology, Taejion Korea (the Republic of), 2 Material Science and Engineering, Hongik Univ., Seoul Korea (the Republic of)
Show AbstractRecently, transparent metal oxide semiconductors, such as ZnO, In2O3-ZnO, ZnO-SnO2, and In2O3-Ga2O3-ZnO, have been intensively investigated for optoelectronic applications such as light emitting diodes and display technologies, e.g., thin-film transistors (TFTs). Among the various kinds of transparent oxide semiconductor, tin oxide has been widely studied as the channel material of TFTs due to its wide band gap of 3-4 eV, high optical transparency in the visible light range, and good chemical stability.In this study, TTFTs are fabricated with a tin oxide film as the channel layer by using plasma enhanced atomic layer deposition (PE-ALD) and then rapid thermal annealed in O2 at 200 °C. The field-effect mobility of 7.63 cm2/V s and the threshold voltage of 2.5 V are obtained for annealed samples. Ion/off ratio and subthreshold swing are 8.2 x 103 and 6.5 V/dec, respectively.
9:00 PM - F8.2
Development of ZnO/Ta2O5 Heterojunction Using Low-temperature Technological Processes.
Roberto Baca 1 , Jose Alberto Andraca 1 , Miguel Galvan 1 , Gabriel Paredes 1 , Ramon Pena 1
1 Electrical Engineering, CINVESTAV IPN, Mexico D.F., D.F., Mexico
Show AbstractTa2O5 has been deposited on ZnO from vacuum evaporation of tantalum powder (Ta) and annealing at low temperature (320C). ZnO was deposited on glass substrate by direct current sputtering process from zinc (Zn) target at room temperature and oxidation at 320C in air atmosphere. Structural and optical properties of ZnO are investigated by X-ray diffraction (XRD) and photoluminescence (PL) spectra at room temperature. Also we explain the defects formation by photoluminescence (PL) spectra studies. Raman spectra, shows the existence of Ta2O5 as insulator film. Mechanism of carrier transport and in ZnO/Ta2O5 heterojunction was obtained from current-voltage characteristics, with direct and reverse bias voltage of 5V at room temperature also transient response under a rectangle-pulse voltage source has been obtained. Defects formation in ZnO, electrical properties and transient response suggest that the ZnO/Ta2O5 heterojunction can be an alternative for development of thin film electroluminescent (TFEL) device applications.
9:00 PM - F8.3
IGZO Based TFTs with Room Temperature Deposited Mg2Hf5O12 Gate Insulator Using Composite MgO-HfO2 Target.
Dong Hun Kim 1 , Hyungtak Seo 2 , Kwun-Bum Chung 3 , Nam Gyu Cho 4 , Ho-Gi Kim 4 , Il-Doo Kim 5
1 Materials Science and Engineering, MIT, Cambridge, Massachusetts, United States, 2 Materials Sciences Division, Lawrence Berkeley National Laboratory and Departme, Berkeley CA , California, United States, 3 Department of Physics, Dankook University, Cheonan Korea (the Republic of), 4 Department of Materials Science and Engineering, KAIST, Daejeon Korea (the Republic of), 5 Center for Energy Materials Research, KIST, Seoul Korea (the Republic of)
Show AbstractThis study reports the dielectric and leakage current properties Mg2Hf5O12 thin films deposited at room temperature by RF magnetron sputtering. Polycrystalline Mg2Hf5O12 thin films showed reasonably high dielectric constant (εr=22) and greatly enhanced leakage current characteristics (<2 × 10-7 A/cm2) compared to the leakage current (~2 × 10-5 A/cm2) of HfO2 thin films at 0.4 MV/cm. A band edge spectroscopic analysis revealed lower conduction band edge defect states and a greater p-type-like Fermi energy level of Mg2Hf5O12 compared to the HfO2 thin films. The suitability of Mg2Hf5O12 films as gate insulators for low-voltage operating InGaZnO4 thin film transistors (TFTs) was investigated. All room-temperature processed InGaZnO4-TFTs on plastic substrates exhibited a high field effect mobility of 27.32 cm2/Vs and a current on/off ratio of 4.01 × 106. The threshold voltage and subthreshold swing were 2 V and 440 mV/dec, respectively. The fabrication and compositional manipulation method of Mg2Hf5O12 films described in this work is simple and versatile, providing fascinating opportunities for new high-K gate dielectrics.
9:00 PM - F8.4
Improved Electrical Stability by Al Dopants in the Thin-film-transistors with Al Doped ZnO Channels Grown by Atomic Layer Deposition.
Cheol Hyoun Ahn 1 , Dong Kyu Seo 1 , Ho Seong Lee 2 , Hyung Koun Cho 1
1 School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon Korea (the Republic of), 2 School of Materials Science and Engineering, Kyungpook National University, Daegu Korea (the Republic of)
Show AbstractMuch effort has been devoted to the development of reliable channel layers based on oxide thin films in thin-film-transistors (TFTs) for applications in organic light emitting diodes and transparent displays, because of their excellent electrical and optical properties even at low deposition temperatures [1,2]. The main deposition methods for oxide thin films are based on physical vapor deposition (PVD)such as sputtering. As a representative PVD technique available commercially for display applications, magnetron sputtering has some problems that must be solved. They include non reproducibility and non uniformity for film composition in the growth of multicomponent oxide films, which obstruct the mass production of the TFTs based on multicomponent oxides.On the other hand, the atomic layer deposition (ALD) of films at the atomic level provides extremely high uniformity, as well as thickness and composition control for the deposition of various oxides, nitrides, and sulfides. In particular, ALD is considered as a powerful deposition method, due to its being a surface-controlled and chemically stable process, resulting in thin films with high electrical and optical quality. The deposition of high-quality gate dielectrics and transparent conductive oxides based on the ALD process has already become a mature technology. Therefore, the material development for channel layers using the ALD process is a very important research field for the fabrication of TFTs based on all ALD processes. Nevertheless, the deposition of channel layers using ALD has been focused on only ZnO layers and they showed electrically unstable TFT performance. Recently, Cho et al.[3] reported that Al doped zinc tin oxide exhibited good TFT performance without post annealing, but the effect of Al addition is not clear. However, the application of the doped ZnO channels deposited by ALD in the TFTs has rarely been investigated to date. Herein, we report on the fabrication of oxide TFTs with Al doped ZnO channels grown by ALD at relatively low temperatures and the correlation between their electrical stability and microstructural properties.The AZO layers with ~17 nm thickness were grown on SiO2/Si substrate by ALD at 110 oC with various Al contents. The source and drain electrodes of Ti/Au bilayers were deposited by E-beam evaporation, and the fabricated TFTs were characterized by an HP4145B semiconductor parameter analyzer. The carrier density and resistivity of the oxide films were measured by Hall effect configuration. Microstructural analysis of the channel layer was investigated by transmission electron microscopy and the results were correlated with device performance.References[1]K. Nomura et al., Nature (London) 432, 488 (2004)[2]J. S. Park et al., Appl. Phys. Lett. 95, 013503 (2009)[3]D. H. Cho et al., Appl. Phys. Lett. 93, 142111 (2008)
9:00 PM - F8.5
Effects of Oxygen and Forming Gas Annealing on ZnO-TFTs.
Jiaye Huang 1 , Ujwal Radhakrishna 1 , Martin Lemberger 1 , Michael Jank 1 , Sebastian Polster 2 , Heiner Ryssel 1 2 , Lothar Frey 1 2
1 Technology, Fraunhofer Institute for Integrated Systems and Device Technology (IISB), Erlangen Germany, 2 Chair of Electron Devices, University of Erlangen-Nuremberg , Erlangen Germany
Show AbstractIn the past few years, there has been intensive research interest in ZnO for utilization in electronic, optoelectronic, and spintronic devices. ZnO has gained particular interest because of its applicability in printed electronics as well as in transparent devices. This presentation reports on the impact of thermal annealing in oxygen and forming gas on the electrical properties of ZnO-based thin film transistors (TFTs) that have been fabricated by sputtering on 200 nm SiO2 on p+-Si substrates. Sputtered ZnO thin films were chosen as a reference system to printed layers. The TFTs have a bottom-gate structure with a thickness of the ZnO active layer in the range of 30 to 60 nm and Al source and drain contacts. Post deposition annealing was carried out in oxygen and forming gas in the temperature range of 400 to 500°C for 60 min. All samples fabricated showed n-type transistor characteristics. When oxygen annealing was carried out, threshold voltage and saturation mobility improved as the temperature was increased. When annealed at 400°C , TFTs exhibited a threshold voltage of 27 V and saturation mobility of 0.07 cm2/Vs while TFTs annealed at 500°C exhibited a much lower threshold voltage of 11 V and an increased saturation mobility of 0.5 cm2/Vs. A lower threshold voltage is desirable for ease of device turn-on. Effects of forming gas annealing at 450°C were also compared to oxygen annealing at the same temperature and it was observed that threshold voltage was further reduced to 3.8 V and the saturation mobility increased to 0.7 cm2/Vs under forming gas annealing. For different annealing temperatures, Ion/Ioff ratio remained at a level of 104. The electrical performance of the devices also improved with reduction of the ZnO layer thickness. It is concluded that the improved electrical properties at higher oxygen annealing temperatures result from reduction of oxygen vacancies which act as deep donors trapping electrons from the accumulation channel. An improvement of electrical properties with forming gas annealing is due to the incorporation of hydrogen in the active ZnO layer. Hydrogen at oxygen vacancy sites bonds to four Zn atoms (i.e., H forms a multicenter bond) and acts as a shallow donor in ZnO contributing electrons to the conduction band.
9:00 PM - F8.6
Electrical Stability of Low Temperature Microcrystalline Silicon Thin Film Transistors.
Anita Risteska 1 , Kah-Yoong Chan 2 3 , Elias Hashem 1 , Aad Gordijn 2 , Helmut Stiebig 2 4 , Dietmar Knipp 1
1 School of Engineering and Science, Jacobs University Bremen, Bremen Germany, 2 Institute of Photovoltaics, Research Center Juelich, Juelich Germany, 3 Faculty of Engineering, Multimedia University, Cyberjaya Malaysia, 4 , Malibu Solar, Bielefeld Germany
Show AbstractThe electrical stability of microcrystalline silicon thin film transistors (µc-Si TFTs) under prolonged bias stress was studied. The microcrystalline silicon TFTs were prepared by plasma-enhanced chemical vapor deposition at temperatures compatible with flexible plastic substrates. The realized microcrystalline silicon transistors exhibit high electron ranging from 30 to 70 cm2/Vs. Prolonged operation of the transistors leads to a small shift of the threshold voltage towards positive and negative gate voltages depending on gate biasing conditions (positive or negative gate voltage). The shift of the threshold voltage increases with increasing positive and negative gate bias stress. The behavior is fundamentally different from the behavior of amorphous silicon thin film transistors, which exhibit only a shift of the threshold voltage towards positive gate voltages irrespective of the polarity of the gate bias stress. The threshold voltage shift of the microcrystalline silicon TFT saturates after a few minutes to a few hours depending on the gate voltage. We attribute the threshold voltage shift to charge trapping in the low temperature silicon oxide gate dielectric. After prolonged bias stress a recovery of the initial threshold voltage is observed without any thermal annealing or biasing of the transistors, which is not the case for amorphous silicon TFTs. The bias stress behavior of amorphous and microcrystalline silicon thin film transistors will be compared.
9:00 PM - F8.7
Investigation of the P-type ZnO:N Thin Film Fabricated by Atomic Layer Deposition.
Wen-Chih Chang 1 , Jyun-Yi Wu 1 , Tai-Bor Wu 1
1 , National Tsing Hua University-MSE, Hsinchu Taiwan
Show Abstract Zinc oxide (ZnO) is considered as an attractive material for optoeletronic applications which has good electrical and optical properties due to its wide band gap of 3.37 eV and large exciton binding energy of 60 meV at room temperature (RT). Because of the self-compensation effect from the native defects such as oxygen vacancies and zinc interstitials on doping, the fabrication of p-type ZnO is quite difficult. In this study, we successfully fabricated the p-type ZnO by ALD. We fabricated the nitrogen-doped ZnO (ZnO:N) thin films with diethylzinc(DEZn), water and NH3 precursors and are especially focused on NH3 plasma.The electrical properties of ALD ZnO:N thin films were investigated as a function of incorporated nitrogen concentration. The nitrogen concentrations in the films were controlled by using different percentage of NH3 plasma , which was used as a single source for the reactant and nitrogen doping for ALD ZnO:N. Finally, the p-type characteristics, such as mobility, concentration, resistivity were measured by Hall effect measurement. The p-type ZnO:N with resistivity of 10−2 ~105 Ω.cm, carrier concentration of 1014~1017 cm−3, and mobility of 1~10 cm/V s was obtained by in-situ NH3 plasma treatment in the ALD process. The x-ray photoelectron spectroscopy (XPS) shows the direct evidence that oxygen atom sites was occupied by nitrogen atom in relation to the p-type characteristics.
9:00 PM - F8.8
New Approach to Fabricate Metal Sulfide Thin Films by Chemical Bath Deposition Method Based on Thermal Decomposition Mechanism of Single Molecule Precursors.
Yun Ku Jung 1 , Jin-Kyu Lee 1
1 Chemistry, Seoul National University, Seoul Korea (the Republic of)
Show AbstractThe semiconductor thin films fabricated by chemical bath deposition method are attracting considerable attention as it is relatively inexpensive, simple and convenient for large area deposition. We have prepared various metal sulfide thin films by a new approach of using chemical solution method, based on the mechanistic understanding of the formation of metal sulfide nanoparticles from single molecule precursors in the presence of alkylamine; nucleophilic attack of the metal-coordinated alkylamine on the most electron-deficient thiocarbonyl carbon of the alkyldithiocarbamate ligands at a low temperature initiated the decomposition to generate solid metal sulfide nanoparticles. The metal sulfide thin films have been successfully realized on the glass substrate modified with mercarptoprophyltrimethoxysilane by immersing the modified glass substrate into the chemical bath of singe molecule precursor (metal dialkyldithiocarbamate, M(DATC)2) and heating the solution in the presence of alkylamine at low temperature (< 150°C). The annealing effects on structural, morphological and optical properties of fabricated metal sulfide thin films were studied using XRD, SEM, and UV-Vis spectroscopy etc.
9:00 PM - F8.9
Initial Reaction Mechanism of Zn Precursors for ZnO Thin-film Growth on Si (001) Surface: A First Principles Study.
Dae-Hee Kim 1 , Seung-Bin Baek 1 , Ga-Won Lee 2 , Yeong-Cheol Kim 1
1 Department of Materials Engineering, Korea University of Technology and Education, Cheonan, Chungnam, Korea (the Republic of), 2 Department of Electronics Engineering, Chungnam National University, Daejeon, Chungnam, Korea (the Republic of)
Show AbstractWe studied the initial reaction mechanism of Zn precursors for ZnO thin-film growth on a Si (001) surface using density functional theory (DFT). Di-methylzinc (Zn(CH3)2, DMZ) and di-ethylzinc (Zn(C2H5)2, DEZ) are Zn precursors for ZnO thin-film growth via the atomic layer deposition (ALD) technique. We employed the climbing nudged elastic band (CNEB) tool implemented in Vienna ab-initio simulation package (VASP) code to calculate the reaction and migration energy barriers for the DMZ and DEZ on a fully OH-terminated Si (001) surface. The Zn atom of DMZ or DEZ was adsorbed on an O atom of a –OH with adsorption energy of 0.09 or 0.22 eV, respectively, due to the lone pair electrons of the O atom on the surface. There were three different sites such as the inter-dimer, intra-dimer, and inter-row sites for the adsorbed DMZ and DEZ migration. They were easily migrated and rotated with the low energy barriers that were in the range of 0.02-0.13 eV. However, the adsorbed DMZ was migrated to the inter-dimer site with the largest energy decrease. In the case of the adsorbed DEZ, it was migrated to the intra-dimer site with the largest energy decrease. The migrated DMZ reacted with a –OH to produce a uni-methylzinc (–ZnCH3, UMZ) group and methane (CH4) at the inter-dimer site with a high energy barrier of 0.65 eV. However, in the case of the migrated DEZ at the intra-dimer site, an energy barrier of 0.35 eV was needed for its reaction to produce a uni-ethylzinc (–ZnC2H5, UEZ) group and ethane (C2H6). In addition, the produced C2H6, as a by-product, was adsorbed on an H atom of a –OH near the UEZ group. It could be easily removed from the surface to the vacuum region through the purge process of the ALD technique. We believe that DEZ is an excellent precursor for ZnO thin-film growth at low temperatures, because its energy barrier for reaction with the Si surface is low, while that of DMZ is high.
Symposium Organizers
Soeren Steudel IMEC
Shelby F. Nelson Eastman Kodak Company
Veit Wagner Jacobs University Bremen
Heiko Thiem Evonik Degussa GmbH
F9: Integration of TFT
Session Chairs
Thursday AM, December 02, 2010
Room 309 (Hynes)
9:30 AM - **F9.1
Transparent Amorphous Oxide Semiconductor TFT for Electronic Paper.
Manabu Ito 1 , Chihiro Miyazaki 1 , Noriaki Ikeda 1 , Kodai Murata 1 , Yukari Harada 1 , Mamoru Ishizaki 1
1 Technical Research Institute, Toppan Printing Co., Ltd., Sugito, Saitama, Japan
Show AbstractWe review the application of transparent amorphous oxide semiconductor (TAOS) TFT to electronic paper. Since the first report of a-InGaZnO TFT by Nomura et.al., [1], TAOS has emerged as one of the most promising candidates for next-generation channel materials for TFT. Compared with other types of semiconductor materials, TAOS is characterized as the following features: processability for large area, high mobility, low process temperature, high stability, transparency, and processability for printing process. No other semiconductors can meet above mentioned features simultaneously. In this article, we focus our attention on the low process temperature and processability for printing process of TAOS and demonstrate the feasibility of combining microencapsulated electrophoretic frontplane, which is called Vizplex Imaging Film, and TAOS TFT backplane. Low process temperature of TAOS is suitable for fabricating flexible electronic devices on conventional plastic substrate. Taking advantage of low process temperature, we demonstrate a-InGaZnO (a-IGZO) TFT array onto poly-ethylene-naphthalate (PEN) below 150 degree-C. We employ bottom gate, top contact with etch stopper structure. Low process temperature deposited a-IGZO TFT showed mobility of 5.3 cm2/Vs and on/off ratio of more than 9th order of magnitude. Flexible 5.35 inch VGA electronic paper was successfully driven by a-IGZO TFT array. The image of the electronic paper was not affected by bending.Recently, solution processed TAOS attracts a lot of attention due to its low cost fabrication process and high material usage. One of the issues in solution processed TAOS, however, is its high process temperature. Typically, more than 400 degree-C annealing process is necessary to obtain satisfactory performance, which is not compatible with plastic substrates. We aim at lowering process temperature below 300 degree-C. The material, which is supplied by Evonik GmbH, was applied by spin coating in a vacuum-free solution-based process, while other layers were made using a standard vacuum deposition process. Solution-processed TAOS was annealed at 270 degree-C for 5minutes which is lower process temperature and shorter annealing time than the typical reported values. Field effect mobility of solution processed TAOS TFT showed 5.7cm2/Vs and on/off ratio of more than 10^6. Moreover, 2 inch VGA electronic paper with 400 ppi-resolution was successfully driven by solution processed TAOS TFT array. Further lowering process temperature is desired, however, we see a big potential to realize low cost flexible display.[1] Nomura et al. Nature 432, 488 (2004)
10:00 AM - F9.2
Low Temperature Amorphous Indium Zinc Oxide Backplane Technology Development for Flexible OLED Displays in a Manufacturing Pilot Line Environment.
Michael Marrs 1 , Sameer Venugopal 1 , Curtis Moyer 1 , Edward Bawolek 1 , Dirk Bottesch 1 , Barry O'Brien 1 , Rita Cordova 1 , Jovan Trujillo 1 , Douglas Loy 1 , Gregory Raupp 1 , David Allee 1
1 , Flexible Display Center at Arizona State University, Tempe, Arizona, United States
Show AbstractA low temperature amorphous indium zinc oxide (IZO) thin film transistor (TFT) backplane technology for high information content flexible organic light emitting diode (OLED) displays has been developed. Mixed oxides, such as IZO, have been extensively researched due to their improved stability under electrical bias stress and higher mobility compared to amorphous silicon. We have fabricated OLED backplanes up to four inches along the diagonal on a six inch wafer scale pilot line using IZO as the active layer and plasma enhanced chemical vapor deposition (PECVD) silicon oxide as the gate dielectric and passivation. The IZO based TFTs exhibited an effective saturation mobility of 11.7 cm2/V-s and a threshold voltage shift of less than 1 Volt under positive gate bias DC stress for 10000 seconds. We report on the critical steps in the evolution of the backplane process from qualification of the low temperature (180°C) IZO process, the transfer of the process to flexible plastic substrates, the stability of the devices under forward bias stress, and finally a discussion on the scale-up to a Gen II (370 x 470 mm) display scale pilot line.
10:15 AM - F9.3
Amorphous Gallium-indium-zinc Oxide Based Thin Film Transistors and Circuits on Foil.
Ashutosh Tripathi 1 , Manoj Nag 2 , Kris Myny 2 , Bas Putten 1 , Martin Neer 1 , Jan Genoe 2 , Soeren Steudel 2 , Paul Hermans 2 , Gerwin Gelinck 1
1 , TNO-Holst Centre, Eindhoven, Noord Brabant, Netherlands, 2 , imec, Leuven Belgium
Show AbstractAmorphous oxide semiconductor (AOS) based thin film transistor (TFT) technology has gained considerable attention in the last years. In particular, amorphous gallium-indium-zinc oxide (a-GIZO) based TFTs with mobilities as high as 100 cm2/Vs have been reported. AOS have several advantages, e.g. they can be fabricated at low temperature, exhibit, large electron mobilities, and they are expected to show lower parameter spread due to their amorphous nature. a-GIZO TFTs can be fabricated by RF or DC sputtering, even at the room temperature. However, generally, a-GIZO TFTs needs to be annealed to higher temperatures (> 250 °C) in order to achieve required performance and therefore are incompatible with low cost, flexible plastic substrates.In addition, TFT performance depends strongly on the substrates, deposition conditions, target composition, gate-dielectrics and the contact metals. With a suitable choice of above parameters, the annealing temperatures for a-GIZO devices can be lowered significantly. We investigated the effect of various parameters, e.g. deposition conditions, different dielectrics and contact metals. a-GIZO TFTs were fabricated on top of the photo-lithographically defined metal-insulator-metal stacks on PEN-foil(Polyethylene naphthalate) at temperatures below 150 °C. TFTs show electron mobilities larger than 10 cm2/Vs and threshold voltages close to 0V. We also report a-GIZO based circuits, e.g. a 19 stage ring oscillators operating at frequencies larger than 100 kHz.
10:30 AM - F9.4
Fabrication of Organic P(VDF-TrFE) Film on PEN Substrate or Flexible IGZO-channel Ferroelectric-gate TFTs.
Gwang-Geun Lee 1 , Sung-Min Yoon 2 , Yoshihisa Fujisaki 4 , Hiroshi Ishiwara 3 , Eisuke Tokumitsu 1
1 Precision and Intelligence Lab., Tokyo Institute of Technology, Yokohama Japan, 2 , Electronics And Telecommunications Res. Inst., Deajeon Korea (the Republic of), 4 Central Research Laboratory, Hitachi Ltd,, Tokyo Japan, 3 Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama Japan
Show AbstractThin film transistors (TFTs) using oxide semiconductors as a channel material have been extensively studied for flat panel displays, flexible displays. In particular, for system-on-panel applications, it is interesting to integrate nonvolatile memory elements using the TFT structure. We previously reported indium-tin-oxide (ITO) channel ferroelectric-gate thin film transistors using ferroelectric (Bi,La)4Ti3O12 (BLT) gate insulator. However, BLT film annealed at 750oC before the channel formation to obtain good ferroelectric properties and conventional other inorganic ferroelectric materials such as Pb(Zr,Ti)O3(PZT) and SrBi2Ta2O9 (SBT) also need high crystallization temperature. In this work, we utilize organic P(VDF-TrFE) film as a ferroelectric gate insulator with combination of amorphous InGaZnO (IGZO) channel since the organic P(VDF-TrFE) film can be crystallized as low as 150oC. We first fabricated ferroelectric P(VDF-TrFE) films on plastic polyethylenenaphthalate (PEN) substrate with an Al bottom electrode. Square-shaped polarization – electric field (P-E) hysteresis loop was obtained for the P(VDF-TrFE) film which was crystallized at 140oC. A remanent polarization (Pr) and coercive field (Ec) were 7.0 µC/cm2 and 0.6 MV/cm, respectively. Similar remanent polarization was observed under the bending condition with a strain of 1.1%, whereas the coercive field was increased by the strain to 0.7MV/cm. Next we fabricated top-gate structure ferroelectric-gate TFTs on PEN substrate. First, Al source and drain electrodes were vacuum evaporated and then the 40-nm-thick IGZO channel layer was deposited by RF sputtering at room temperature in an argon atmosphere. This deposition condition produced IGZO films with carrier concentration of approximately 10^15-10^16 cm^-3 and Hall mobility of 7-10 cm2/Vs. Next, 120-nm-thick P(VDF-TrFE) film was spin-coated and annealed on a hot plate at 140 oC for 1 h. After contact holes for the source and drain regions were opened, Al gate electrode was evaporated and patterned. The channel length and width of the fabricated device were 10 and 100 µm, respectively. Note that the TFTs were fabricated under 140oC. We confirmed nonvolatile memory effect in drain current - gate voltage (ID-VG) characteristics with a memory window of 5 V for the gate voltage sweep of +-10V. On/off drain current ratio is as large as 10^6 and the subthreshold voltage swing is 200 mV/decade. This work was supported by Grants-in-Aid for Scientific Research (A) from the Ministry of Education, Culture, Sports, Science and Technology, Japan.
10:45 AM - F9.5
Vertical Stacked Complementary Inverters Using Pentacene and Amorphous InGaZnO Thin-film Transistors.
Jungbae Kim 1 , Canek Fuentes-Hernandez 1 , William Potscavage 1 , Do Kyung Hwang 1 , Hyeunseok Cheun 1 , Bernard Kippelen 1
1 , Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractSilicon based digital technology is based on complementary metal oxide semiconductor circuits that use n- and p- channel transistors to operate with low static power consumption and at high-speeds. Recently, organic or oxide-based thin-film transistors (TFTs) have attracted considerable attention for flexible, printed, large-area electronic circuit applications because they show larger mobility values than those from amorphous silicon TFTs and allow low temperature processing. Conventional all-organic or hybrid organic-inorganic TFT-based complementary inverters have been demonstrated using horizontally distributed n- and p-channel semiconductor layers. Here, we report on a novel vertically stacked complementary inverter implemented with one p-channel transistor fabricated on the top of another n-channel transistor using pentacene and amorphous InGaZnO as p- and n-channel layers, respectively. A 65 nm-thick Al2O3 grown by atomic layer deposition was used as bottom and top gate dielectric layers, with a high capacitance density value of 123 nF/cm2. With a shared common gate electrode positioned between two dielectric layers, top contact n- and p-channel TFTs showed saturation mobility values of 1.84 and 0.38 cm2/Vs and threshold voltages of 1.6 and -3.8 V, respectively. To compensate the on-current mismatch between the n- and p-channel TFTs, arising from variations of mobility and threshold voltage, the width of p-channel TFT is sized to be 10 times larger than that of n-channel. The inverter yielded a high gain of > 100 V/V with a switching threshold voltage of 3.8 V at a supply voltage of 10 V. The use of vertically stacked p- and n-channel TFTs in complementary circuits is a promising way to realize high-packing density with low power and high drivability by the reduction of the interconnection lengths and parasitic resistances. Our results provide a versatile new approach for achieving high performance complementary electronic components that can be easily adapted to any material platforms and processing methods. Further optimizaion methods and the tradeoffs of following a complementary circuit approach will be discussed.
11:30 AM - **F9.6
Integration of 145 Thin Film Transistors on Plastic Foil Using All Low-temperature-wet Processes.
Gyoujin Cho 1 , Jinsoo Noh 1 2 , Minhun Jung 1 2 , Joonseok Kim 1 2 , Hwiwon Kang 2 , Soyeon Lim 2 , Gwangyong Lee 1 2 , Kyunghwan Jung 1 2 , Dongsun Yeom 2 , Yongsu Park 1 , Minjin Lee 1
1 , Sunchon University, Suncheon Korea (the Republic of), 2 , Paru Co. Ltd., Suncheon Korea (the Republic of)
Show AbstractThere has been no report to successfully integrate more than 30 transistors on plastic foils using all low-temperature-wet processes to generate multi bit digital codes under low DC voltage (> 20 V). The major reasons in delaying the practical success in all low-temperature-wet processed multi bit digital circuits on plastic foils are originated from the lack of understanding on interface phenomena between the low-temperature-wet process, substrates and materials for fabricating electrodes, dielectrics and active layers on plastic foils to integrate thin film transistors (TFTs). Unlike the well known photolithographic process, the macroscopic view (~ 100 µm) of patterns should be workable in all low-temperature-wet processed-TFTs on plastic foils. In fact, less than 100 nm of unevenness in patterns from the photolithographic process are generating unacceptable TFTs in the integrated circuits, but even a couple of micrometer-sized unevenness in patterns of TFTs should be tolerable in the integrated circuits. In this presentation, the successful way of integration of 145 TFTs on plastic foils using all low-temperature-wet processes will be discussed as demonstrating stable 16 bit digital codes under DC 20 V.
12:00 PM - F9.7
Demonstration of Fully Patterned Hybrid CdS/Pentacene CMOS Circuits.
Jesus Mejia 1 , Ana Salas-Villasenor 1 , Julius Horvath 1 , Adrian Avendano 1 , Harvey Stiegler 1 , Bruce Gnade 1 , Manuel Quevedo-Lopez 1
1 Materials Science and Engineering, University of Texas at Dallas, Richardson, Texas, United States
Show AbstractIn recent years, fabrication of inexpensive and flexible electronics has become an increasing research area where both organic and inorganic materials are developed for simple and low-cost deposition techniques as well as processes that allow full circuit integration at low temperatures. Here, we demonstrate a fully integrated approach to fabricate Cadmium Sulfide (CdS)-Pentacene CMOS transistors. CdS is chemically bath deposited at 75° C and is used as n-type semiconductor, showing thin film transistor (TFT) mobility values of 10 cm2/V-s and threshold voltages around 5 V for fully integrated devices. This value is higher in comparison to n-type organic molecules and even higher than hydrogenated amorphous silicon (a-Si:H). Furthermore, this TFT are stable when exposed to air. P-type TFTs were fabricated using thermally evaporated pentacene as semiconductor with mobility and threshold voltage in the range of 3x10-2 cm2/V-s and -3 V, respectively. The CMOS integration approach includes six mask levels with a maximum processing temperature of 100° C, well suitable for low temperature and inexpensive applications. NAND, NOR and Inverter gates are demonstrated, as well as isolated transistors. We also discuss dielectric, contacts and semiconductor impact on devices performance.
12:15 PM - F9.8
4-V Operational Braille Display Using Low Operational Organic TFTs and Carbon Nanotube Based Actuator.
Kenjiro Fukuda 1 , Kazunori Kuribara 1 , Tomoyuki Yokota 1 , Tsuyoshi Sekitani 2 , Ute Zschieschang 3 , Hagen Klauk 3 , Takushi Sugino 4 , Kinji Asaka 4 , Masaaki Ikeda 5 , Hirokazu Kuwabara 5 , Tatsuya Yamamoto 6 , Kazuo Takimiya 6 , Takanori Fukushima 7 , Takuzo Aida 8 , Takao Someya 1 2 9
1 Department of Applied Physics, The University of Tokyo, Tokyo Japan, 2 Department of Electrical and Electronic Engineering, The University of Tokyo, Tokyo Japan, 3 , Max Planck Institute for solid state research, Stuttgart Germany, 4 , AIST, Osaka Japan, 5 , Nippon Kayaku, Co. Ltd., Tokyo Japan, 6 Department of Applied Chemistry, Hiroshima University, Hiroshima Japan, 7 , RIKEN, Saitama Japan, 8 Department of Chemistry and Biotechnology, The University of Tokyo, Tokyo Japan, 9 INQIE, The University of Tokyo, Tokyo Japan
Show AbstractWe have fabricated the 4-V operational sheet type Braille displays using low voltage operational organic thin-film transistors and carbon nanotube (CNT) based actuators. The TFTs on film shows high mobility of more than 1.0 cm2/Vs and large on current of more than 3 mA. For integrating the TFTs and CNT based actuators, the displacement of 300 μm was achieved at operational voltage of 3 V. The time required to operate the individual actuator was 1.8 seconds at 4 V. High-performance organic TFTs with low operating voltage and high performance were achieved with novel p-type semiconductors of Dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) and self-assembled monolayer (SAM) gate dielectrics whose thickness were only a few nm [1-4]. Organic TFTs with SAM gate dielectrics were manufactured by vacuum evaporation and low temperature solution processes. A 25 nm thick aluminum layer was deposited as the gate electrodes through a shadow mask in a vacuum evaporator on a plastic film. A thin aluminum oxide film with a large density of hydroxyl groups for molecular adsorption was formed by oxygen-plasma treatment (100 W, 10 min), and a SAM of n-tetradecylphosphonic acid was prepared from a 2-propanol solution at room temperature. DNTT was deposited to form 30 nm thick channel layers on the AlOx/SAM gate dielectric. Finally, a 50 nm thick Au layer was evaporated through a shadow mask to form the source/drain contacts. The Channel width and the channel length of the fabricated TFTs were 100000 μm and 20 μm, respectively. The CNT based actuators composes three layers: the sandwich structure of the electrolyte between CNT electrodes. The technical details of the CNT based actuators were already reported [5].The fabricated TFTs showed large on current of more than 3 mA at 3 V. The mobility at saturation regime exceeds than 1.0 cm2/Vs, and ON/OFF ratio exceeds than 106. When the TFTs integrated to the CNT based actuators whose size was 1 by 4 mm, the displacement of 300 μm which was sufficient value for recognizing whether the individual dots were up or down state was achieved under the voltage conditions of –3 V. The time required for achieving displacements more than 300 μm was 1.8 sec at –4 V, which was sufficient for applying the technology to the Braille displays. [1] H. Klauk et al., Nature, 445, 745 (2007). [2] K. Fukuda et al., Appl. Phys. Lett.95, 203301 (2009). [3] U. Zschieschang et al., Advanced Materials, 22, 982 (2010). [4] T. Yamamoto and K. Takimiya, J. Am. Chem. Soc. 129, 2224 (2007). [5] K. Mukai et al., Advanced Materials 21, 1582 (2009).
12:30 PM - F9.9
Characteristics of OTFTs Using Olefin-polymer Gate Insulator and Their Application to a 5-in. OTFT-driven Flexible AMOLED Display.
Yoshiki Nakajima 1 , Yoshihide Fujisaki 1 , Tatsuya Takei 1 , Hiroto Sato 1 , Mitsuru Nakata 1 , Mitsunori Suzuki 1 , Hirohiko Fukagawa 1 , Genichi Motomura 1 , Takahisa Shimizu 1 , Koichi Sugitani 2 , Yukie Isogai 2 , Takeyoshi Katoh 2 , Toshihiro Yamamoto 1 , Hideo Fujikake 1 , Shizuo Tokito 1
1 Science and Technology Research Laboratories, Japan Broadcasting Corporation (NHK), Tokyo Japan, 2 R & D Center, ZEON Corporation, Tokyo Japan
Show AbstractOrganic thin-film transistors (OTFTs), which can be fabricated on plastic films at low temperature, have attracted considerable attention for their application to low-cost large-area electronic devices. In this work, we report a fabrication and characteristics of OTFTs using cross-linked olefin type polymer (olefin-polymer) as a gate insulator, and demonstrate their application to a 5 inches flexible AMOLED display.Olefin-polymer layer was formed by spin-coating and annealing at low temperature below 150°C. Pentacene was used as an organic semiconductor layer. We employed the bottom gate and bottom contact structure of the OTFTs on a glass or plastic substrate. The fabricated OTFTs with a short channel length of 5 μm showed a mobility of 0.1-0.2 cm2/Vs, a current ON/OFF ratio of 107, and a threshold voltage of 1-2 V. The OTFTs also exhibited high stable performance in air ambient. These electronic characteristics indicate that olefin-polymer is suitable for a gate insulator of OTFTs on a plastic substrate because of its low process temperature.Based on these results, we developed an OTFT-driven flexible AMOLED display. Pixel number was 320(RGB) × 240 (QVGA) and pixel size was 318 μm × 318 μm. A standard pixel circuit consisted of 2 transistors and 1 capacitor was employed. Polyethylene naphthalate (PEN) film was used as a flexible substrate. The gate insulator, some metal wirings and electrodes on an OTFT backplane were patterned by photolithography. The pentacene was patterned by a polymer separator like a partition wall structure. After fabrication of the OTFT backplane, OLED layers were formed by vacuum deposition through shadow-masks. A barrier film was laminated as an encapsulation onto the fabricated panel. The maximum temperature for fabricating the panel was 130°C. The panel was connected to a driving circuit system. Clear color moving images were observed on the flexible display at the frame frequency of 60 Hz. Stable moving images were also shown on the fabricated display even when it was bent. These results indicate that the OTFT-driven flexible AMOLED display has promising potential for ultra-thin, lightweight and large-screen displays.
12:45 PM - F9.10
Organic/Inorganic Hybrid-type Nonvolatile Memory Thin-film Transistor on Plastic Substrate Below 150°C.
Sung-Min Yoon 1 , Shinhyuk Yang 1 , Soon-Won Jung 1 , Sang-Hee Ko Park 1 , Chun-Won Byun 1 , Min-Ki Ryu 1 , Him-Chan Oh 1 , Kyounghwan Kim 1 , Chi-Sun Hwang 1 , Kyoung-Ik Cho 1 , Byoung-Gon Yu 1
1 , ETRI, Daejeon Korea (the Republic of)
Show AbstractNonvolatile memory thin-film transistors (M-TFT) embeddable into the flexible large-area electronic systems can provide us very interesting and highly-functional applications. The employment of suitable memory device can also effectively reduce the power consumption of the system. These M-TFTs are required to have a mechanical flexibility with high performances and to be fabricated at low temperature of around 150°C. In this work, the flexible M-TFT with an organic/inorganic hybrid-type gate stack was proposed and fabricated on a plastic poly(ethylene naphthalate) (PEN) substrate. Fabrication procedures were so optimized as to obtain excellent device characteristics even at a low process temperature. ZnO and a poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] were employed as a semiconducting active channel and a polymeric ferroelectric gate insulator (GI), respectively. The use of oxide semiconductor (ZnO in this work) can be expected to provide a transparency in the visible range, superior performances compared to the organic semiconductor, and low-temperature compatibility. Firstly, Ti/Au/Ti film was patterned into the source/drain electrodes on the 200-μm-thick PEN (Teijin DuPont). 10-nm-thick ZnO film and 6-nm-thick Al2O3 interface controlling layers were successively deposited by atomic-layer deposition methods. After the patterning of channel areas, thermal treatment was performed at 150°C to enhance the ZnO channel properties. 100 nm-thick P(VDF-TrFE) (70/30 mol%) film was formed by spin-coating method and crystallized at 140°C for 1 h. Via-holes were formed by O2 plasma etching of the given areas of P(VDF-TrFE) layer. Finally, Au film was deposited and patterned as gate electrode and pads.The basic ferroelectric behaviors were well confirmed for the P(VDF-TrFE) capacitors fabricated on the same substrate. Then, M-TFTs were also electrically characterized. Transfer characteristics (ID-VG) of the M-TFT showed that the memory window (MW) originating from the ferroelectric field-effect was clearly obtained, in which the width of MW was measured to be 3.4 V at VG sweep from -10 to 8 V. TFT characteristics of the field-effect mobility, subthreshold swing, and on/off ratio were typically found to be approximately 36 cm2/Vs, 0.3 V/dec, and 3.2×108, respectively. These characteristics did not experience so marked variations when the substrate was under bending situations with a given curvature radius. We can conclude that the proposed flexible M-TFT having organic GI/inorganic oxide channel gate structure is one of the most promising devices to realize the low-cost flexible memory with excellent performances even at lower process temperature.
F10: Material and Device Characterization II
Session Chairs
Thursday PM, December 02, 2010
Room 309 (Hynes)
2:30 PM - **F10.1
High-definition Screen Printing of Organic Transistor Active Matrices for Large-area Electronics.
Tsuyoshi Sekitani 1 , Takao Someya 1
1 , The University of Tokyo, Tokyo Japan
Show AbstractEmploying high-definition screen-printing technology with an accuracy of 20 μm, we successfully fabricated organic transistor active matrices (diagonal: 150 mm) on polyethylene naphthalate (PEN) films for application to large-area sensors and actuators. The minimum linewidth and channel length are both 20 μm, while the total number of transistors is 14,400 (120 ×120 cells) and the periodicity is 1 mm. The printed transistors exhibit a mobility of 0.8 cm^2/Vs and on/off ratio of >10^6. The maximum process temperatures are as high as 150 °C; thus, the fabrication of the matrices is realized using a low-temperature, flexible-substrate-compatible, cost-effective, large-area, and easy fabrication approach.The screen-printing system utilizes high-resolution screen masks for fine patterning of electrical pastes. First, a low-resistive silver paste was patterned on a PEN film and sintered at 150 °C for 1 h to form 5-μm-thick gate electrodes and word lines. A parylene was formed at room temperature for 400-nm-thick gate dielectric layers. Source and drain electrodes with thicknesses of 5 μm were formed along with bit lines by using screen-printed silver pastes. The entire film except for the channel parts was coated with epoxy resin for encapsulation purposes. Finally, a 50-nm-thick pentacene layer was deposited by thermal evaporation. The channel length and width of the organic transistors were 20 μm and 300 μm, respectively. The matrices fabricated using the present printing process exhibit sufficiently good electronic performance and yield for application to large-area sensors and actuators.
3:00 PM - F10.2
Field Effect Transistors from Colloidal Silicon and Germanium Nanocrystals.
Zachary Holman 1 , Chin-Yi Liu 1 , Uwe Kortshagen 1
1 Mechanical Engineering, University of Minnesota, Minneapolis, Minnesota, United States
Show AbstractColloidal semiconductor nanocrystals (NCs) show significant promise for cheap solution processed electronic devices. Solution processed films of semiconductor nanocrystals can have a band structure tunable through the nanocrystal size, can be processed with inexpensive printing or coating techniques, and have in some cases shown electrical conductivities and mobilities that can compete with some organic semiconductors. We here report thin film transistor results based on plasma-synthesized germanium (Ge) and silicon (Si) NCs.Germanium tetrachloride or silane is dissociated in the presence of hydrogen in a nonthermal plasma to nucleate Ge or Si NCs. Transmission electron microscopy and X-ray diffraction indicate that the particles are nearly monodisperse (standard deviations of 10-15% the mean particle diameter) and the mean diameter can be tuned from 4-15 nm by changing the residence time of the NCs in the plasma. Ge and Si NC colloids are formed by dispersing the NCs in 1,2-dicholorobenzene (DCB) without further surface modification. In contrast to many other solvents, in which “bare” NCs quickly agglomerate and flocculate, NCs remain stable in DCB. We believe that this occurs because DCB has a similar dielectric constant to Ge, significantly reducing the effective Hamaker constant of the van der Waals attraction. Films are formed by spinning the NC colloids onto substrates. Bottom-gate FETs were fabricated by spinning Ge and Si NC suspensions onto Au/Si2+/SiO2 substrates in a glovebox. Source and drain contacts were then evaporated on top to complete the devices. Geermanium NC FETs exhibit promising performance with electron and hole mobilities on the order of 10-2 cm2/V-s and on-to-off ratios better than 103. Annealing induced removal of H and Cl surface species is required to activate the devices, and the annealing temperature determines whether n-type, ambipolar, or p-type behavior is observed. Si NC FET performance is hindered by nonuniformfilm morphology, but the devices show gating without any post-deposition treatment. We have verified by X-ray diffraction that this performance is not due to sintering of the NCs but merely due to changes of the NC surface conditions. This work was supported by NSF under grant CBET-0756326, and by the DOE Center of Advanced Solar Photophysics. Support was also provided by the UMN Center for Nanostructure Applications.
3:15 PM - F10.3
Solution Processable Nanowire Field-effect Transistors.
Charles Opoku 1 , Marcus Newton 1 , Maxim Shkunov 1
1 Advanced Technology Institute, University of Surrey, Surrey United Kingdom
Show AbstractSolution processable nanomaterials such as inorganic semiconducting nanowires are offering high charge carrier mobilities and are fully compatible with low-temperature device deposition steps on a variety of substrates, including plastics. Moreover, organic-inorganic hybrid structures with advanced properties can be obtained by solvent-based methods, where working devices are passivated/coated with organic dielectric layers. In this work we demonstrate low temperature solution-processed transistors using hybrid approach where the active channel is composed of inorganic semiconducting nanowires and other parts of the device are very similar to typical polymer electronics devices. We discuss the challenges in device engineering and materials-related issues for transistor applications on both rigid and flexible substrates.We also show a new type of nanowire FETs, where the source barrier is controlled by the gate field, resulting in early current saturation. Considering printing approaches for high performance FETs, this novel nanowire transistor design allows to overcome issues of thick dielectric layers and variation of channel lengths during the printing process.Typical top-gate devices based on ZnO nanowire channel and polymer dielectric (1 micron thick) show excellent current saturation at source-drain bias of ~ 1V and charge carrier mobility of ~100cm2/Vs.
3:30 PM - F10.4
Trap-related Behavior of Charge Carrier Transport in Transparent Conductive Oxides.
Marlis Ortel 1 , Veit Wagner 1
1 , Jacobs University Bremen, Bremen Germany
Show AbstractRecently significant progress was made in the field of wet-chemically processed metal oxide semiconductors. Due to the unique properties of these inorganic materials they are of great interest for basic research as well as for large area electronic applications.Even though these materials are amorphous they show high mobility values of up to 100 cm2/Vs. Furthermore metal oxide semiconductors are transparent due to their large band gap. Especially the combination of both properties makes these inorganic semiconductors important for applications such as active matrix displays or transparent electronics. In addition the TCOs (transparent conducting oxides) have good light and gas sensing properties which makes them suitable for smart sensors. A further crucial advantage is their solubility in nontoxic solvents which eases large scale applications based on wet-chemical production technologies like printing.However TCO-based devices often show hysteresis and stress-related threshold voltage shift, which is not acceptable in many applicationsIn this work the charge carrier transport in TCO-based transistors is analyzed. The active layer for ZnO films is wet-chemically deposited from a zinc acetate precursor solution and thermally converted into ZnO. The hysteresis and bias stress in these layers are attributed to trapping of charges. Here deep traps are responsible for the observed threshold voltage shifts, which are strongly affected by charge carrier density, electric field strength, temperatures and ambient gases. These dependences are systematically investigated. To gain deeper insight detailed information about the potential drop in the channel and the local threshold voltage shift within the channel is obtained via 4-probe setup. This setup includes two electrodes in the conducting channel. These additional electrodes enable the determination of the potential in the channel while stressing the device and thus yield valuable information if charge density or electric field strength is more important.The analysis yields, among others, especially a strong influence of the electric field strength on the observed bias stress.
3:45 PM - F10.5
High Performance and Stability of Amorphous Hf-In-Zn-O Thin Film Transistors under Visible Light Illumination.
Hyun-Suk Kim 1 , Kyung-Bae Park 1 , Kyoung Seok Son 1 , Joon Seok Park 1 , Wan-Joo Maeng 1 , Tae Sang Kim 1 , Kwang-Hee Lee 1 , Eok Su Kim 1 , Jong-Baek Seon 1 , Myung Kwan Ryu 1 , Sangyun Lee 1
1 Display Lab., Samsung Advanced Institute of Technology, Yongin-si, Gyeonggi-do, Korea (the Republic of)
Show AbstractRecently, thin film transistors (TFTs) that incorporate oxide semiconductors such as ZnO, GaInZnO or HfInZnO (HIZO) are subject of intensive investigation due to their high potential for applications in flat panel displays. Because of their relatively high field effect mobility values above 5 cm2/Vs compared to their amorphous Si counterparts (~0.5 cm2/Vs), oxide-based TFTs are promising switching/driving elements, especially for large-area, high-resolution active-matrix liquid crystal display (AMLCD) and active-matrix organic light-emitting diode (AMOLED) products. Desired properties of TFTs for display application include high field effect mobility, steep subthreshold swing, and high on/off current ratio. However, because the TFTs are exposed to visible light originating from the underlying backlight unit in a working AMLCD panel or the self-emitting radiation in AMOLED products, the susceptibility of oxide TFTs with respect to illumination should also be minimized in order to successfully implement them into real operating displays. A typical undesired phenomenon that occurs upon light exposure is the occurrence of non-zero subthreshold currents in the normally ‘off’ region of the transfer curve, which is well known to be induced by the excess photo-generated carriers within the semiconductor layer. Under such adverse conditions the pixels would not turn off when they should, and hence blurred images will be shown on the display.In the present work, the device properties of TFTs employing HIZO as the active semiconductor are studied, and their sensitivity to visible light radiation is examined in particular with respect to the HIZO deposition conditions. Because real switching devices spend most of their lifetime experiencing a negative gate bias, the device reliability under simultaneous application of negative gate bias stress and illumination is also investigated. Our results suggest that by properly optimizing the deposition condition of the oxide channel layers (i.e., higher sputtering power and higher O2/Ar gas flow ratio), we can effectively lessen the sensitivity of oxide semiconductor TFTs to visible light, and as a result, the operating lifetime of the display switching/driving elements can be significantly extended, which will allow the realization of large-size and high-resolution AMLCD and AMOLED products.
4:00 PM - F10.6
P-type Oxide Based Thin Film Transistors.
Joseph Saji 1 , Raquel Barros 1 , Pedro Barquinha 1 , Rodrigo Martins 1 , Elvira Fortunato 1
1 Materials Science, FCT-UNL, Caparica Portugal
Show AbstractAlthough the performance achieved with oxide transistors processed at low temperatures exceed far beyond the ones obtained with amorphous silicon and organic semiconductors, the oxides reported in the literature are mostly limited to n-type device applications, since there is a lack of p-type oxide semiconductors, mainly regarding the ones processed at low substrate temperatures. This confines the field of application of oxide semiconductors solely to unipolar (n-type) devices, inhibiting the fabrication of complementary MOS (CMOS) structures where both n- and p-type transistors are needed, as demanded for the next generation of flexible and disposable low cost electronic systems, away from the traditional silicon technology. In this work we report p-type oxide TFTs based on transparent SnOx and Cu2O semiconductors deposited by reactive rf sputtering at room temperature, with the final devices requiring annealing temperatures of only 200 °C to exhibit improved electrical properties over similar devices reported in literature, produced at considerably higher temperatures. The good performance achieved precludes a promising future integration of these devices with the already well-established n-type oxide TFTs in flexible, low-cost and transparent CMOS structures. Furthermore, the sputtering technique presents a great advantage regarding the industrial migration of these devices, as it has been widely used by industry due to the easy control of the deposition parameters and to the possibility of obtaining uniform films over large surfaces.
4:15 PM - F10.7
High Breakdown Voltage FETs Utilizing Oxide-based Materials.
Ikuo Soga 1 , Taisuke Iwai 1
1 Nanoelectronics Resarch Center, Fujitsu laboratories, Atsugi Japan
Show AbstractRecently, there are great interests in the development of oxide-based transistors. Zinc oxide (ZnO) and indium-gallium-zinc oxide (IGZO) are pointed out as the example of oxide-based materials frequently. These oxide-based semiconductors show the transparent property for visible wavelength, high electron mobility and low deposition temperature. It enables us to realize several applications, such as thin film transistors (TFTs) for display panel, flexible devices for wearable computer and optical devices. One of the most important applications is the high power transistor for power supply because we can expect the high breakdown field resulting from wide bandgap property. The oxide-based transistors have an advantage on the cost compared with other wide bandgap semiconductors such as GaN and SiC.We demonstrated the oxide-based transistors with bottom-gate structure and gate field plate. The channels consist of IGZO deposited by RF sputtering at room temperature on the copper substrate. Source and drain electrodes were formed with Ti:Au. Gate metal made of Ti:Pt was insulated from channel by alumina. The drain electrode was separated from gate electrode by 10 μm. The fabricated transistors were operated at drain voltage of 100 V. This transistor shows the drain current of about 0.55 mA/mm and the on-off current ratio of 2.6E+2. This is first step for the oxide-based transistors with high breakdown voltage. We can expect to increase the drain current by the optimization of channel material, ohmic contact metals and device structure.
4:30 PM - F10.8
The Effect of HfO2 Buffer Layer on Al2O3-passivated IGZO TFTs.
Soyeon Park 1 , Seokhwan Bang 1 , Seungjun Lee 1 , Joohyun Park 1 , Youngbin Ko 1 , Hyeongtag Jeon 1
1 Division of Materials Science and Engineering, Hanyang Univ., Seoul Korea (the Republic of)
Show AbstractRecently, the transparent electronics have a considerable attention for the next generation display industry. To realize the transparent electronics, the reliable characteristics of thin film transistor (TFT), used as a fundamental operation unit, are indispensable. Therefore, the oxide based-TFTs have been extensively investigated as the solution of transparent TFTs due to their excellent electrical and optical characteristics. In particular, amorphous indium–gallium–zinc oxide (a-IGZO) TFTs have shown excellent electrical properties such as high mobility and excellent on/off ratio, which make these transistors promising alternatives to amorphous silicon (a-Si) TFTs, especially in a backplane application of active-matrix organic light emitting diode displays. However, there is the problem regarding electrical instability of IGZO TFT although a-IGZO TFTs have the potential advantages. In order to improve the stability and the electrical properties, the passivation process has been widely used. Especially, the passivation process for the bottom gate-type TFTs is important for the environmental and electrical stability in order to prevent the active layer from being exposed. Recently, aluminum oxide (Al2O3) has been mostly used as a surface passivation material. However, during the deposition of the Al2O3 passivation layer, the active layer, a-IGZO, could react with Al2O3, leading to the change in characteristics of a-IGZO TFTs. To solve this problem, HfO2 has been used as a buffer layer because it is less reactive with IGZO compared to Al2O3. In this study, we used ALD process to ensure thin and uniform film as a buffer layer and passivation layer. We compared the effect on the electrical characteristics and stabilities of non-passivated TFT, Al2O3 passivated TFT and Al2O3 passivated TFT with HfO2 buffer layer.
4:45 PM - F10.9
Fabrication of Low-temperature Amorphous In-Ga-Zn-O Thin-film Transistor Using UV Annealing and Carrier-suppressing Layer.
Hsiao-Wen Zan 1 , Wei-Tsung Chen 1 , Hsiu-Wen Hsueh 1 , Chuan-Cheng Yeh 1 , Chuang-Chuang Tsai 1 , Jian-Hong Lin 2 , Chun-Hsiang Fang 2 , Chung-Chun Lee 2
1 , National Chiao Tung University, Institute of Electro-Optical Engineering, HsinChu Taiwan, 2 , AU Optronics Corporation, Hsinchu Taiwan
Show AbstractIn this study, a low-temperature amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is fabricated by using UV annealing and a carrier-suppressing layer. The as-fabricated a-IGZO TFT with room-temperature-deposited IGZO active layer faces a serious instability problem of a fluctuating threshold voltage during device operation. In this study, an a-IGZO TFT with an active layer deposited by RF sputtering is investigated. The threshold voltage shifts more than 9 V during the sequent transfer curve measurements. Post-annealing is generally required to stabilize the threshold voltage. However, conventional annealing that is based on furnace heating always requires a high temperature of more than 300°C; therefore, this process cannot be used for fabricating the desired low-temperature metal-oxide devices. Therefore, we develop a low-temperature post-annealing technique by using a mild UV lamp with a low power density of 50 mW/cm2 (λ = 172 nm). The UV illumination employed as the annealing treatment could stabilize the threshold voltage of an a-IGZO TFT by prolonging the irradiation duration. However, another side effect, the increase in the carrier concentration in the IGZO film with an increase in the irradiation time, occurs. A considerably high carrier concentration in the active layer will narrow the depletion width in the off state. The incompletely depleted active layer results in a serious leakage current in the body of the IGZO TFT. According to our previous study, the UV illumination time must be carefully controlled in order to avoid the formation of an over-conductive active layer, which limits the feasibility of UV annealing, in the a-IGZO TFT.In order to widen the process window of low-temperature UV annealing, we develop another carrier-suppressing approach to extract the excess carriers caused by UV annealing. A Au capping layer is deposited on the active layer of the bottom-gate top-contact a-IGZO TFT to draw the electrons in the IGZO film. This mechanism is based on the fermi-level difference in vacuum. The work functions of IGZO and Au are approximately 4 eV and 5.1 eV, respectively. During the IGZO/Au junction formation, the electrons with a high energy in the IGZO layer follow into the Au layer. After UV annealing, the length of the a-IGZO TFT becomes considerably conductive and results in a low on/off ratio of 20. Then, the annealed a-IGZO TFT is capped by a 50-nm-thick Au layer located between the source and the drain electrodes. The fabricated low-temperature device has an improved on/off ratio of 5 × 106 and a stable threshold voltage in sequent transfer curve measurements. The extracted threshold voltage, mobility, and sub-threshold swing from the transfer characteristics are 1.1 V, 14.8 cm2/Vs and 0.72 dec./V, respectively. A stable low-temperature a-IGZO TFT is fabricated by using UV annealing and a carrier-suppressing layer in this study.
5:00 PM - F10.10
Flash Lamp Annealing: High Temperature Surface Treatment of Heat Sensitive Substrates.
Thoralf Gebel 1 , Joerg Weber 1 , Harald Liepack 1 , Wolfgang Skorupa 2
1 , DTF Technology GmbH, Dresden, Saxony, Germany, 2 Inst. of Ion Beam Physics & Mat. Research, FZD Dresden-Rossendorf, Dresden, Saxony, Germany
Show AbstractNovel thin-film technologies like spraying or printing of semiconductor or metallic materials on innovative substrates (e.g. PET, polymer foils, glass or paper) require new annealing technologies for surface modification. Optical, electric and mechanical properties of such layers deposited at low temperatures need to be improved by subsequent annealing steps, e.g. in order to achieve crystallization, drying or simply to evaporate solvents. The annealing of such layers on heat sensitive substrates is a real challenge. Conventional annealing methods like oven, RTP or spike anneal typically last more than one second - and that is why they may cause irreversible damage, since the whole substrate is heated. Therefore, novel annealing techniques in the millisecond of microsecond range like the flash lamp annealing (FLA) are of great interest, since they allow heat management for thin layers at the surface. Results of optical and electrical parameters after FLA treatment of TCO layers and semiconductor materials are presented in the talk. The influence of flash duration, energy density and multi-flash operation are discussed.
5:15 PM - F10.11
Effects of Excimer Laser Annealing of Transparent Oxide Semiconductor Films.
Mami Fujii 1 , Ryoichi Ishihara 2 , Tao Chen 2 , Johan van der Cingel 2 , Mohammad R. T. Mofrad 2 , Masashi Kasami 3 , Koki Yano 3 , Yasuaki Ishikawa 1 , Yukiharu Uraoka 1 4
1 Graduate School of Materials Science, Information device science laboratry, Nara Institute of Science and Technology, Nara Japan, 2 , Delft University of Technology, Delft Netherlands, 3 , Idemitsu Kosan Co., Ltd.,, Chiba Japan, 4 , CREST, Japan Science and Technology Agency, Saitama Japan
Show AbstractOxide semiconductor films deposited by sputtering have recently attracted considerable attention in fields of transparent and flexible electronics for the next generation displays in comparison with conventional semiconductors. In general, the annealing process with about 300°C or more is effective to obtain the good characteristics when the oxide semiconductor films are applied to electronic devices such as thin film transistors (TFTs). In this case, the high temperature in the post-annealing is a serious problem in fabrication of TFTs on the plastic substrates. Excimer laser annealing (ELA) process with short pulses can achieve the annealing and crystallization without thermal damage against the substrate. In this study, we investigated effects of the ELA of Indium-Oxide (In2O3), Indium-Zinc-Oxide (IZO) and Indium-Gallium-Zinc-Oxide (IGZO) thin films with various thickness and oxygen contents on their optical and electrical properties.The three kinds of oxide semiconductor films with a thickness of 50 nm were deposited by RF magnetron sputtering on oxidized silicon wafers with a gas mixture of argon and oxygen at room temperature. Oxygen partial pressure ratio P was varied from 0 to 10 percemt to change the oxygen contents in the films. One shot of XeCl excimer laser with a wavelength of 308 nm and a pulse duration of 25 ns at FWHM irradiated the surface. Before the laser crystallization, absorption coefficient α at 308nm of the IZO with the P value of 0 percent and with a thickness of 50 nm was measured to be 2.7×105 cm-1. With increasing the P value to 3 percent, the α is reduced by 40 percent, due to reduction of oxygen vacancy resulting in widening the bandgap. Further increasing P does not increase the α value. Similar α values and the trends were obtained for the other two oxide semiconductors as well. This corresponds to the reduction of the carrier density of IZO from 3.5×1019 cm-3 to 1.5×1019 cm-3, estimated from the conductivity, with increasing the P value from 0 to 3 percent. With irradiation of excimer-laser with an energy density of 65 mJ/cm2 to the IZO with the P value of 0 percent, the α was decreased by 20 percent. This could be attributed to the fact that the annealing with the laser reduced the oxygen vacancy by crystallization. This corresponds to decrease in the conductivity of IZO from 379.27 Ω-1cm-1 to 170.79 Ω-1cm-1 by the laser annealing. With increasing the energy density at 165 mJ/cm2, the film ablation was observed on the IZO with P value of 0 percent. With transient heat diffusion simulation, maximum temperature of the IZO film was estimated to reach as high as 2100 K, at which vaporization of the oxygen may occur. The ablation energy density increases with increasing the P value to 3 percent due to the less absorption. Further increase in the P value does not change the ablation energy density. In2O3 and IGZO films showed the similar tendencies of conductivity and ablation energy.
5:30 PM - F10.12
Microcrystalline Silicon Thin-film Transistors Operating at Very High Frequencies.
Elias Hashem 1 , Marko Marinkovic 1 , Kah-Yoong Chan 1 2 3 , Aad Gordijn 2 , Helmut Stiebig 2 4 , Dietmar Knipp 1
1 School of Engineering and Science, Jacobs University Bremen, Bremen Germany, 2 IEF5-Photovoltaics, Research Center Jülich, Jülich Germany, 3 Faculty of Engineering, Multimedia University, Cyberjaya, Selangor, Malaysia, 4 , Malibu GmbH & Co. KG, Bielefeld Germany
Show AbstractThe switching behavior of hydrogenated microcrystalline silicon (µc-Si:H) thin-film transistors (TFTs) was examined and switching frequencies exceeding 20 MHz were measured for short channel devices. The microcrystalline silicon TFTs were prepared by plasma-enhanced chemical vapor deposition at temperatures below 200 °C. The realized microcrystalline silicon transistors exhibit high electron and hole charge carrier mobilities of 30-50 cm2/Vs and 10-15 cm2/Vs, respectively. The switching behavior was measured for different device geometries. The switching frequency is limited by the drain and source contact resistance and the overlap capacitance between the gate and the drain/source electrodes. We have developed a simple electrical model of the microcrystalline thin film transistor that allows for describing the switching frequency as a function of the device geometry. The model takes the influence of the contact resistance and the parasitic capacitance into account. Switching frequencies of more than 20 MHz were measured for transistors with a channel length of 5 μm. The high switching frequencies facilitates the realization of radio frequency identification tags (RFID tags) operating at 13.56 MHz.
5:45 PM - F10.13
Three-terminal Photo Detector Based on Electronically Active Oxide Semiconductor for Remote Touch Screen Applications.
Sungho Park 1 , Sanghun Jeon 1 , Ihun Song 1 , Seungeon Ahn 1 , Sangwook Kim 1 , Sun Il Kim 1 , Jaechul Park 1 , Changjung Kim 1 , Uin Chung 1
1 Semiconductor Device Lab, Samsung Advanced Institute of Technology, Yongin-Si, Gyeonggi-Do, Korea (the Republic of)
Show Abstract Transparent zinc oxide based thin film transistors (TFTs) have attracted considerable interest because of optical transparency, high mobility property and room temperature process capability. Therefore, an amorphous indium zinc oxide (a-IZO, gallium indium zinc oxide (GIZO), and hafnium indium zinc oxide (HIZO)have been extensively investigated for use as switch elements in display technology. A zinc oxide based semiconductor has a wide band-gap of about 3.5-3.8eV depending on the composition of semiconductor. However, it has high sensitivity for visible light illumination due to sub-gap states in the bad-gap of semiconductor. In this article, we propose a novel sensor architecture utilizing different oxide semiconductor transistors as both a switching element and a photo sensor. In addition, our study presents the optimum active structure for three-terminal photo-sensor and the operation principle of our proposed photo device architecture which overcomes intrinsically slow response issue of two-terminal oxide-based photo detector. The photosensitivity of optimun active TFTs also extends its application for light sensors in flat panel displays.