Symposium Organizers
Robert Geer State University of New York-Albany
James D. Meindl Georgia Institute of Technology
Rajashree (Raji) Baskaran Intel Corporation
Pulickel M. Ajayan Rice University
Ehrenfried Zschech AMD Saxony LLC & Co. KG
M2: Optical Interconnect Systems and Advanced Interconnects
Session Chairs
Wednesday AM, November 28, 2007
Hampton (Sheraton)
9:30 AM - **M2.1
Germanium on Silicon Modulators and Nanometallic-Enhanced Detectors for Optical Interconnects.
David Miller 1
1 Electrical Engineering, Stanford University, Stanford, California, United States
Show AbstractOptical interconnects to the silicon chip itself are very attractive from the perspective of their basic physics [1], potentially solving scaling and signal integrity problems of electrical wiring, and allowing precise timing injection [2-3]. To have sufficient low power dissipation, the optoelectronic devices need to be well integrated with the silicon integrated circuits. For photodetectors, low capacitance is very important for reducing system power [1]. The optoelectronic output devices that convert that information from electrical to optical form, also need good integration for high performance, and integration is generally essential for reducing manufacturing costs.Especially if we want a technology that can also be compatible with longer distance optical communications near 1.5 microns wavelength, silicon itself is not a particularly good optoelectronic material. It does not detect light at those long wavelengths, it is not a good light emitter at any wavelength, and it has only weak mechanisms for modulating light. Germanium can be a good photodetector at such long wavelengths, and can be integrated with silicon. Recently, germanium quantum wells grown on silicon were demonstrated to have a very strong electroabsorption mechanism [4] that should allow high-performance modulators, with the first such device recently demonstrated [5].The talk will summarize our recent work on the integration of germanium on silicon for optical modulators and detectors, including also nanometallic enhancement of photodetection [6,7].[1] D. A. B. Miller, Int’l J. Optoelectronics 11 (3), 155 168 (1997); Proc. IEEE 88, 728-749 (2000)[2] C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, and D. A. B. Miller, IEEE J. Sel. Top. Quantum Electron. 9, 400-409 (2003)[3] R. Urata, L. Y. Nathawad, R. Takahashi, K. Ma, D. A. B. Miller, B. A. Wooley, and J. S. Harris, J. Lightwave Technol. 21, 3104-3115 (2003)[4] Y.-H. Kuo, Y. K. Lee, Y. Ge, S. Ren, J. E. Roth, T. I. Kamins, D. A. B. Miller, and J. S. Harris Jr., Nature 437, 1334-1336 (2005); IEEE J. Sel. Top. Quantum Electron. 12, 1503-1513 (2006)[5] J. E. Roth, O. Fidaner, R. K. Schaevitz, Y. -H. Kuo, T. I. Kamins, J. S. Harris, and D. A. B. Miller, Opt. Express 15, 5851-5859 (2007)[6] L. Tang, D. A. B. Miller, A. K. Okyay, J. A. Matteo, Y. Yuen, K. C. Saraswat, and L. Hesselink, Opt. Lett. 31, 1519-1521 (2006)[7] L. Tang, E. Kocabas, S. Latif, A. K. Okyay, D. Ly-Gagnon, K. C. Saraswat, D. A. B. Miller, OSA Integrated Photonics and Nanophotonics Research and Applications Topical Meeting, July 10, 2007, Paper ITuD3
10:00 AM - **M2.2
Novel Concepts of Fast Optical Sources for off-Chip Interconnect Applications.
Serge Oktyabrsky 1 , Vadim Tokranov 1 , Jobert van Eisden 1 , Michael Yakimov 1 , Manasa Varanasi 1 , Rama Kambhampati 1
1 CNSE, University at Albany, Albany, New York, United States
Show AbstractChallenging target performance parameters of future chip-level off-chip optical interconnects (OI) require novel materials and integration concepts of optical sources. We discuss the physical reasons for limitations of bandwidth of the optical sources such as vertical cavity surface emitting lasers (VCSEL) and laser-modulators. Three novel concepts and the recent results from the present authors are summarized with the emphasis on OI specific solutions. These results include: (1) the development of tunnel-coupled pairs consisting of InGaAs quantum wells grown on top of self-assembled InAs quantum dots as gain medium in VCSELs. All-epitaxial VCSELs with triple-pair tunnel QW-on-QDs demonstrated continuous wave mode lasing with record characteristics: DC power up to 2.45 mW, threshold current down to 0.76 mA at emission wavelength 1135 nm, thermal stability >100 C, 3db bandwidth of 9 GHz, and estimated dumping-limited cut-off frequency of 34 GHz. (2) the development of thin QD gain layer transfer technology using hydrophilic bonding and novel oxidation lift-off technology for SOI-based waveguide laser. A pseudo-epitaxial interface allowed for efficient optical coupling of III-V nanostructures with SOI waveguide. (3) Optical decoupling approach based on duo-cavity monolithic VCSEL-modulator. Bandwidth over 20 GHz with feedback-free operation is demonstrated.
10:30 AM - **M2.3
Plasmonics - The Next Wave of Chipscale Technologies!
Mark Brongersma 1
1 , Geballe Laboratory for Advanced Materials, Stanford, California, United States
Show AbstractThe development of advanced optical structures has enabled tremendous control over the propagation and manipulation of light waves. At the forefront of these advances is the development of nanoscale plasmonic devices with dimensions smaller than the wavelength of light (~ 0.1 μm). The unique properties of such structures can be exploited to gain an even higher degree of control over light-matter interactions and opens the door to the development of a myriad of new device architectures for generating, routing, modulating, and detecting light. Moreover, their small size directly results in higher operating speeds and facilitates an improved synergy with electronic components. The field of plasmonics is rapidly growing and provides a whole range of seemingly exciting research and development opportunities. In this presentation we will provide a critical assessment of the field and indicate the truly exciting opportunities for use of plasmonics on a Si chip.
11:30 AM - **M2.4
Cellular Automata-based Electronic Architecture: An Alternative Approach to Meet the Materials and Processing Challenges for the Next Generation Interconnect Technology.
Shashi Karna 1 , James Lyke 2
1 Weapons & Materials Research Directorate, US Army Research Laboratory, Aberdeen Proving Ground, Maryland, United States, 2 Space Vehicles Directorate, AFRL/VSSE, US Air Force Research Laboratory, Kirtland Air Force Base, New Mexico, United States
Show AbstractRecent advances in controlled growth and manipulation of materials at nanometer-scale have opened new avenues for current and future electronics technologies. It is anticipated that with the controlled growth and assembly of materials such as quantum dots, nanowires, and nanotubes, electronics technology, which has witnessed unprecedented increase in active device density, processing power, and communication speed in the past three decades will further undergo revolutionary changes. However, with the decreasing feature-size and ultra-high density of the integrated circuits, that could be possible through nanotechnologies, interconnects appear to present a major challenge – both from the materials as well as processing points of view. Materials, such as carbon nanotubes (CNTs), which have excellent conductivity and are ideally suited for interconnects between nanometer-scale devices, are presenting major challenges in processing and controlled assembly in large-scale fabrication. Efforts are underway in several laboratories to surmount the issues associated with the processing and integration of CNTs and metal nanowires in silicon technology. Simultaneously, efforts are also underway in various laboratories to incorporate new architectural paradigm in very large scale integrated circuits (VLSI) that take advantage of the concepts of cellular automata (CA). While CA implementation does not fully reduce the materials challenges, it helps reduce the number of nodes the length of interconnects in VLSI. This talk will provide an overview of the materials and architectural challenges in giga-scale electronics and potential application of CA concepts to address some of the interconnect issues.
12:00 PM - M2.5
Effects of Nanometer-Scale Surface Roughness and Applied Load on the Contact Resistance of Cu-Cu Bonded 3D ICs.
Hoi Liong Leong 2 1 , Chee Lip Gan 1 2 , Carl Thompson 5 2 , Kin Leong Pey 3 2 , Hongyu Li 4
2 Advanced Materials for Micro- and Nano-Systems, Singapore-MIT Alliance, Singapore Singapore, 1 School of Materials Science and Engineering, Nanyang Technological University, Singapore Singapore, 5 Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 3 School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore Singapore, 4 , Institute of Microelectronics, Singapore Singapore
Show AbstractA 3D four-point probe contact resistance measurement structure was designed to characterize the effects of total surface roughness of Cu bond pads and the applied load during bonding on the contact resistance of the bonded interface. The 3D structure was fabricated by thermo-compression bonding of two wafers, each with a bond pad that was interconnected with two probe pads that were fabricated with a Cu damascene process. The total surface roughness is defined as the sum of the pre-bond surface roughness of the two bonding pads. Cu interconnects with different surface roughnesses were bonded, creating Cu bonded interfaces with different total surface roughness. The wafers were also bonded under different applied loads.Contact resistance measurements were performed on these Cu bonded interfaces. It was found that the average contact resistance increased as the total surface roughness of the bonded interface increased, as well as when the applied load decreased. The increase in resistance is related to the smaller true contact area, which can be calculated using a model based on contact mechanics theory, which has been previously described. We have now also developed a contact resistance model that can be used to estimate the contact resistance of bonded interfaces based on their true contact area.Within each set of measurements, we observed a significant spread about the average value of contact resistance, suggesting issues of contact and bonding non-uniformity of the wafers. However, the values given by the model are in good agreement with the minimum values observed in experiments, which may represent the ideal cases of bonding of rough surfaces. Our results show that the impact of surface roughness and applied load on the contact resistance of Cu-Cu thermo-compression bonds can be quantified experimentally, and understood in the context of established theory for contact mechanics.
12:15 PM - M2.6
Low Temperature, Metal(Ni)-induced Lateral Crystallization(MILC) of amorphous(α)-Germanium(Ge) for 3-Dimensional Integrated Circuits(3D ICs).
Jin-Hong Park 1 , Pawan Kapur 1 , Hailin Peng 2 , Krishna Saraswat 1 2
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 Material&Science Engineering, Stanford University, Stanford, California, United States
Show Abstract12:30 PM - M2.7
Performance of Random-metal Dielectric Film for Signal Transmission.
Mitsuo Fukuda 1 , Atsushi Utsumi 1 , Yusuke Yamasaki 1 , Hiroya Funato 1 , Naohiro Takemoto 1 , Norihiro Oota 1
1 Electrical & Electronics Engineering Department, Toyohashi University of Technology, Toyohashi, Aichi, Japan
Show AbstractA novel optical near-field generator and detector have been developed and their performances were confirmed [1-3]. The generator was fabricated by forming a random metal-dielectric film on the light emitting area of laser diode, and lasing propagating light was converted to optical near field through surface plasmon propagation. The random metal-dielectric film was composed of silver paste and submicron-sized spherical fused silica. In the film, silica balls were randomly embedded in silver and nano-scaled optical apertures were formed at the surface illuminated with light. The detector (Schottky-type diode) was fabricated by forming the film on Si or compound semiconductors such as InGaAs and InP and monitored well the optical near-field generated just beneath the film. In this paper, we propose the random metal-dielectric film as a passive waveguide of surface plasmon for optical signal transmission. The performances of the film are summarized in the items (1), (2), and (3).(1) The metal-dielectric film transmitted surface plasmon converted from propagating light, and information of optical intensity was linearly transmitted. This linearity was confirmed by using the optical near-field generators and detectors. The intensity of optical near-field, which was monitored by using an optical fiber probe, is proportional to the optical output power emitted from the opposite facet without the random metal-dielectric film. The photoresponse of the detector is also proportional to the input optical power. (2) The linearity of lasing longitudinal modes (wavelength) and modulated optical signal were maintained within the film. (3) Input propagating light incident upon the film was converted to optical near field in the film, and the intensity ratio of the propagating light to the optical near field was sufficiently reduced at the output surface of the film. This suppression of the propagating light is important to eliminate noise and crosstalk under signal transmission.From these results, the random metal-dielectric film has been confirmed to be a practical passive waveguide of surface plasmon. The polarization property of light in the film will be also discussed in the presentation. This study was partially supported by the Ministry of Education, Science, Sports and Culture, Grant-in-Aid for Scientific Research (C)19560342.[1] A. Utsumi, et al, An optical near-field generator fabricated on laser diodes, IU-MRS Inter. Conf. in Asia 2006 (IU-MRS-ICA2006), Abstract 3-P-78, Korea, Sept. 2006.[2] M. Fukuda, et al., The performance of an optical near-field generator and detector fabricated with spherical fused silica and siliver paste, 19th annual meeting of IEEE LEOS, Paper MD5, Montreal, Canada, Oct.-Nov., 2006.[3] M. Fukuda, et al., Optical near-field generation and detection by using a metal-dielectric film fabricated from silver paste and spherical fused silica, IEEE Photon. Technol. Lett., (accepted).
12:45 PM - M2.8
All Copper Chip-to-Substrate Interconnects.
Paul Kohl 1 , Tyler Osborn 1
1 Chemical and Biomolecular Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractA novel fabrication process has been developed to create all-copper connections from the chip to substrate. Elimination of solder from the flip-chip process would (i) remove the brittle copper-tin intermetallics for the connections, (ii) facilitate the fabrication of higher chip-to-substrate off-set distances, (iii) improve the electromigration resistance, (iv) improve the yield strength of the connection, and (v) possibly remove the need for underfill. In this work, an all-copper chip-to-substrate connection process has been developed and modeled. The process is tolerant to z-axis (through-plane) and x,y-axis (in-plane) alignment mismatch. Electroless copper plating is used to form the initial metal connection followed by low temperature annealing to create an all-copper (pillar-based) bond between two components. Bond strengths up to 165 MPa have been realized using processing temperatures of 180oC. The pillar technology has been analyzed for the geometric requirements to achieve compliant all-copper, chip-to-substrate connections. The design space (pitch, diameter, height) to achieve pillars which are mechanically and electrically acceptable for high performance packages will be presented.
M3: Growth and Characterization of Interconnect Materials
Session Chairs
Wednesday PM, November 28, 2007
Hampton (Sheraton)
2:30 PM - M3.1
Low Temperature Silicon Nitride Films Deposited on 3D Topography by Hot Wire Chemical Vapor Deposition (HWCVD).
Stephan Warnat 1 , Markus Hoefer 2 , Lothar Schaefer 2 , Helmut Foll 3 , Peter Lange 1
1 , Fraunhofer Institute for Silicon Technology, Itzehoe Germany, 2 , Fraunhofer Institute for Surface Engineering and Thin Films, Braunschweig Germany, 3 Technical Faculty, University of Kiel, Kiel Germany
Show AbstractWhile electronic systems are becoming increasingly complex their size must either decrease or stay the same as compared to the previous generation. A lateral integration of sensing elements and their required electronic devices inside one package is often not possible due to geometrical limitations. Vertical interconnects, also called “through silicon vias” (TSV), running through the entire wafer is the more favorable approach in order to reduce the package size by stacking different devices on each other. TSV’s are basically made by holes etched from the backside and covered by an isolation and a metallization layer. The isolation layer is required to avoid leakage current and cross talking of different signals in electronic devices and they are commonly deposited by low pressure (LPCVD) or plasma enhanced CVD (PECVD) processes at temperatures above 300°C. This is critical for optical sensors like cameras, because organic micro lenses or color filters atop of photo diodes degrade during these LP- or PECVD processes. The HWCVD technique enables the deposition of silicon nitride films (SiN) at temperatures below 200°C. This paper shows for the first time the integration and the characterization of SiN films in a TSV deposited by the HWCVD technique. Breakdown Voltage (Vbd) measurements of insulators in a TSV, which reveal significant surface roughness, are difficult to perform. Therefore planar Metal-Insulator-Semiconductor (MIS) structures were used to measure the Vbd of the films. To imitate the surface roughness the SiN films were deposited on the non-polished side of highly n-doped wafers. The calculated dielectric breakdown fields Ebd are in the range of 4…6 MV/cm, which is lower as comparable Ebd from LP- or PECVD SiN films, but sufficiently high for the planned application. An index of reflection of 1.96…2.02 was measured for different SiN thicknesses, which indicates a stoichiometric Si3N4 film and agrees well with those of LP- and PECVD SiN films. The characterization of nitrides with respect to structural arrangements, i.e. the degree of disorder and the content of impurities was done by IR spectroscopy. In comparison to nitrides deposited in LP- and PECVD processes we found that the respective networks display very similar variations of the tetrahedral (N-Si-N) and dihedral (Si-N-Si) angles. 3D depositions of the HWCVD films into TSV’s are in progress. The first results showed that close to the bottom of a 300 µm deep hole 100 µm in diameter the thickness of the SiN layer was reduced to about 20% of the value on the plain wafer. Even for hole diameters of 50 µm the reduction of film thickness at the bottom was about 8%. No pinholes were observed inside the TSV after a KOH pinhole test, in spite of the thickness gradient. In summary, these first measurements have shown that the deposited HWCVD a-SixNy:H layers are suitable candidates for isolation layers in through silicon vias deposited at low temperature.
2:45 PM - M3.2
Dielectric Constant Measurement of Pure-Silica-Zeolite Low-k Powder Materials by Time Domain Reflectometry (TDR).
Minwei Sun 1 , Wolfgang Maichen 2 , Ramdas Pophale 3 , Christopher Lew 1 , Yan Liu 1 , Heather Hunter 4 , Michael Deem 3 , Mark Davis 4 , Yushan Yan 1
1 CEE, University of California, Riverside, Riverside, California, United States, 2 , Teradyne Inc., Agoura Hills, California, United States, 3 Department of Bioengineering, Physics and Astronomy, Rice University, Houston, Texas, United States, 4 Chemical Engineering, California Institute of Technology, Pasadena, California, United States
Show AbstractLow dielectric constant (low-k) insulators are essential for the development of future generation computer microprocessors with lowering both crosstalk noises and power consumption. The dielectric insulator of choice since the inception of the semiconductor industry has been dense silica that has a k value of approximately 4. One approach to reduce k value is to incorporate porosity into silica. We have been investigating pure-silica-zeolites (PSZs) as possible low-k materials, which have advantages of uniform micro-porosity, high heat conductivity, superior mechanical strength as well as high hydrophobicity over other porous silica based low-k materials. One of the important directions of PSZ low-k research is to explore the zeolites with lower framework density (FD) that what have been explored (e.g., MFI and MEL). There are many PSZs available to be examined for their k value, but the progress has been slow because the measurements of k value thus far required the preparation of a high quality thin film, which could take years of efforts. Since powder samples are more accessible than thin films, it is very useful to develop measurement methods of powder samples, which can help to speed up the screening process and also facilitate studies of many factors of PSZs on their dielectric constants, e.g., the existence of organic structure directing agent, chemical composition, crystal size, etc. In this presentation, we will discuss the setup and k (capacitance) measurements by Time Domain Reflectometry (TDR). The TDR measurement procedure consists of sending a fast step signal into the line under test and recording the reflected signal versus time. The size of a capacitance connected to the open end of the path can be determined by comparing it to a reference measurement without the capacitance. This setup requires only a small amount of sample and the measurements are fast. The k value from theoretical calculation with using the GULP simulation package will also be presented.
3:00 PM - M3.3
Plasma Enhanced Atomic Layer Chemical Vapor Deposition of TaNX Diffusion Barrier on Plasma-modified Ultralow-k Mesoporous Silica Dielectric Thin Films.
Chih-Chieh Chang 1 , Fu-Ming Pan 1 , Ching-Wen Chen 1
1 Materials Science and Engineering, National Chiao-Tung University, Hsinchu Taiwan
Show AbstractPorous materials are a potential candidate as ultralow-k dielectrics for nanoelectronic interconnect technology. However, because of its porous nature, which results in many integration hurdles, the porous dielectric materials require surface modification before being integrated with subsequent process steps. In the study, we have prepared surfactant templated mesoporous silica thin films as the ultralow-k dielectrics and a TaNX thin film deposited by plasma enhanced atomic layer chemical vapor deposition (PE-ALCVD) using TaCl5 as the gas precursor was used as the diffusion barrier. Without any surface treatment for the dielectric layer, Ta atoms could easily diffuse into the mesoporous layer seriously degrading dielectric properties. Various plasma gas sources, such as O2, N2 and Ar, have been used to modify the surface layer of the mesoporous dielectric in a high density plasma chemical vapor deposition (HDP-CVD) system, and all the treatments produced a dense oxide layer a few nanometer thick. According to transmission electron microscopy (TEM), the pore sealing treatment could effectively prevent Ta atoms from diffusing into the mesoporous dielectric during the PE-ALCVD process. After the deposition of the PE-ALCVD TaNX barrier layer on an O2-plasma-treated mesoporous silica film, the surface of the TaNX barrier was further modified in the PE-ALCVD system by hydrogen or NH3 plasma treatment to improve the wetting of Cu on the barrier. We found that the H2-plasma-treated barrier surface had a better wetting effect for sputter-deposited Cu thin film. We ascribe the improved wetting effect to that a graded Ta atomic concentration distribution developed after the hydrogen plasma treatment producing a Ta-rich surface, which adhered better to the Cu top layer than that without the treatment.
3:15 PM - M3.4
Diffusion Barrier Property of Mo/Ti Bi-layer Films for Cu-metallization.
Prodyut Majumder 1 , Christos Takoudis 2
1 Department of Chemical Engineering, University of Illinois at Chicago, Chicago, Illinois, United States, 2 Departments Chemical Engineering and Bioengineering, University of Illinois at Chicago, Chicago, Illinois, United States
Show AbstractCopper (Cu) has drawn much attention as a new interconnect material for deep submicron ultra-large scale integrated circuits because of its lower bulk resistivity (1.7 μΩ.cm) and superior electromigration resistance as compared to Al. However, Cu reacts with Si at relatively low temperatures (~200 °C) to form Cu-silicides, which can deteriorate device operation. Therefore, it is necessary to use a diffusion barrier between Cu and Si in order to suppress Cu diffusion and the subsequent reaction with Si. Sputter-deposited refractory metals, like W, Ta, Mo, and Ti along with their nitrides have been recognized as diffusion barriers due to their high thermal stability, low resistivity and excellent capability of suppressing reactions between Cu and Si. However most of these barrier layers are thermally stable until 600 °C. The failure of these diffusion barriers are due to the diffusion of Cu atoms through their grain boundaries resulting in the formation of Cu3Si. Studies show that bi-layer barrier structures are more stable compare to the single-layer structure due to the mismatch of their grain boundaries. In this study, we investigated the performance of Mo/Ti bi-layer barrier structure between Cu and Si. The barrier films were deposited using r.f. magnetron sputtering at 4 mTorr sputtering pressure. The flow rate of Ar was kept constant at 40 sccm. The Cu/Mo (5 nm) /Ti (5 nm)/ structures were fabricated and annealed at wide range of temperatures in the presence of N2 in RTP furnace. The thermal stability of Mo/Ti barrier layers were evaluated after annealing using four probe measurements for sheet resistance, X-ray diffraction (XRD) analysis for phase identification and scanning electron microscopy (SEM)/Energy dispersive spectroscopy (EDS) for surface morphology and elemental mapping. The formation of Cu3Si takes place only after annealing at 775 °C as indicated by the drastic increase in sheet resistance value. At that temperature, the surface morphology of Cu was highly detoriated and the formation of Cu3Si was evident from XRD and SEM/EDS results. Thus the Mo/Ti bi-layer barrier structure could effectively block the diffusion of Cu up to 750 °C.
3:30 PM - M3.5
Influence of Trench Width on the Microstructural Evolution of Copper Electroplated in Narrow Features.
Ruud van den Boom 1 , Eric Lifshin 1 , Kathleen Dunn 1
1 College of Nanoscale Science & Engineering, University at Albany - SUNY, Albany, New York, United States
Show AbstractAs interconnect dimensions continue to decrease, microstructural inhomogeneities such as grain boundaries and impurities incorporated within the conductor have increasing impact on back-end performance metrics such as electromigration resistance and resistivity. To study the progress of recrystallization from the overburden into narrow features, oxide trenches (down to 80 nm) were filled with ALD TaN/Ta liners, I-PVD Cu seed layers and electroplated copper with ~800 nm of overburden. Wafer coupons were stored cryogenically after plating and after annealing to prevent inadvertent additional recrystallization, and transmission electron microscopy specimens were prepared as needed. Grain size and orientation were found to depend not only on annealing time and temperature but on the width and/or aspect ratio of the feature, with only modest increases in grain size even in the most aggressive annealing condition. Overall, the largest grains were observed in the sample annealed at 150°C, but small grains near the liner did not grow even under those accelerated conditions, remaining ~40nm on average, with grains as small as 10nm observed. With increasing time and temperature, the copper develops an <011> texture along the trench, although consistent surface normal (i.e., normal to the liner surface) is observed only in the narrowest trenches. To explore this trend in further detail, structures down to 20nm wide defined by e-beam lithography are being prepared for comparison. Finally, because initial SIMS work with blanket samples suggest that impurity distribution may not be homogeneous within the plated metal, higher resolution impurity mapping studies are underway to examine the role of additives incorporated from the plating bath on recrystallization within the trenches as well.
3:45 PM - M3.6
Microstructure Optimization and Texture Manipulation of Al and Cu Films via SLS.
Min Hwan Choi 1 , Jae Beom Choi 2 , Ui-Jin Chung 1 , Paul Van Der Wilt 1 , Alexander Limanov 1 , James Im 1
1 Applied Physics and Applied Mathematics, Columbia University, New York, New York, United States, 2 , Samsung Electronics Co., Ltd., Yongin Korea (the Republic of)
Show AbstractIn general, it is considered to be the case that the microstructure and texture of Al and Cu films can affect their interconnect-application-relevant properties. As the metallization-related challenges and demands continue to rise with increasing levels of integration, it is becoming commensurately imperative to improve such properties of the materials (e.g., conductivity, resistance to electromigration, etc.) by optimally engineering the microstructure and texture of the films. Previously, we have shown that pulsed-laser-based lateral-solidification schemes that were originally developed for manipulating the microstructure of Si films can be readily applied to deal with Al and Cu films; In this work, we focus on applying the most flexible and effective method referred to as sequential lateral solidification (SLS), and show that it is not difficult to generate large-grained and grain-boundary-location controlled Al and Cu films that can, furthermore, be crystallographically textured. Samples consisted of Al films that were deposited on oxidized Si wafers and Cu films that were deposited on oxidized Si wafers (with or without a tantalum interlayer). The samples were SLS processed using an excimer-laser-based irradiation system with projection optics, and were subsequently analyzed using TEM, SEM, EBSD, and AFM techniques. The results show that, depending on the details of the process (e.g., beamlet pattern and microtranslation scheme), it is possible to generate a variety of low-defect-density/large-grained Al and Cu films including (1) grain-boundary-location engineered polycrystalline Al and Cu films, (2) polycrystalline films with a directionally solidified microstructure, and (3) location-controlled single-crystal regions. Additionally, we show that it is possible produce strongly textured Al and Cu films either by utilizing a textured precursor film (which can be obtained via a number of different approaches), or by inducing the texture development during directional SLS. In particular, we will present (111) surface-textured Al films with the perfectly periodic bamboo microstructure and (100) textured (in all three crystallographic directions) Cu films that are obtained via directional SLS of the as-deposited films. We will discuss various solidification-related phenomena and physical factors that are relevant in generating these microstructure and texture controlled Al and Cu films, and provide preliminary experimental results that indicate how the process can be further extended to deal with other metallic and non-metallic films.
4:30 PM - M3.7
A Specimen Preparation Technique for 3D Characterization of Nano Materials at Specific-site using FIB-STEM/TEM System.
Toshie Yaguchi 1 , Mitsuru Konno 1 , Takeo Kamino 1 , Kuniyasu Nakamura 1 , Junzo Azuma 1 , Takashi Kita 2 , Tomoya Inoue 2
1 , Hitahi High-Technologies Corporation, Hitachinaka-shi Japan, 2 , Kobe University, Kobe Japan
Show AbstractIn the field of nano technology, demands for three dimensional (3D) structural and elemental analyses of a specific site are increasing rapidly. For 3D characterization at specific-site, we have developeda new specimen preparation technique which achieves a sampling positional accuracy of better than 100nm [1]. The instruments used in the method are a FB-2100 focused ion beam (FIB) system, a HD-2700 spherical aberration corrected scanning transmission electron microscope (STEM) and a H-9500 300kV analytical electron microscope (AEM). A low energy Ar ion milling system (GENTLE-MILL HI) was used after FIB system so that the final thinning of a specimen at the acceptable positional accuracy and removal of FIB damage layer was carried out successfully.In this method, a FIB-(S)TEM compatible specimen rotation holder was used throughout specimenpreparation, observation and analyses. The specimen holder allows 360 degrees rotation and ±20 degrees tilting of a specimen even in a narrow-gapped high resolution pole-piece [2]. Since the specimen is mounted on the tip of a needle stub using the FIB micro-sampling technique, the specimen is in full view of the incident electron beam, detectors and spectrometers over the rotation and tilt angles. A STEM observation and an additional FIB milling are carried out sequentially until the specimen becomes suitable shape and size for the characterization. The technique was applied to a InAs quantum dot (QD) embedded in a GaAs matrix [3]. The single QD was extracted from a desired portion using the FIB micro-sampling technique [4] and shaped into a pillar using a FIB. The final milling of the specimen was performed using a 500eV Ar ion milling. Then the dark field(DF)-STEM images were recorded every 2 degrees from 0 to 178 degrees. The 3D image of indium distribution was reconstructed from the series of these images. By 3D reconstruction, it is revealed that the shape of QD three dimensionally. References[1] T. Yaguchi et al.,Proc. Microsc. Microanal. 12 (Suppl .2) (2006) 528-529.[2] T.Kamino et.al., J.Electron Microsc.,53 (2004) 583-588. [3] T.Kita,et.al.,Applied Phisics Letters 90, (2007) 041911[4] Ohnishi, T., et al, Proc.25thInt.Symp. for Testing and Failure Analysis, Santa Clara, CA, Nov. (1999) 449-501.
4:45 PM - M3.8
Dielectrophoretic Aligned Ni Silicide Nanowire Connections and Electrical Properties.
Joondong Kim 1 , Yun Chang Park 2 , Dong Hun Shin 1 , Eung-Sug Lee 1 , Chang-Soo Han 1
1 Nano-Mechanical Systems Research Center, Korea Institute of Machinery and Materials, Daejeon Korea (the Republic of), 2 Measurement and Analysis Division, National Nanofab Center, Daejeon Korea (the Republic of)
Show AbstractSilicides have been utilized to crystallize a silicon (Si) layer or grow a Si film by the compatibility to Si technology, which also attributes to reduce a processing temperature. Recently, the silicide material uses have been evolved to as a nanoscale functional unit due to its excellent electrical property having a potential to be a nanoscale interconnection, an emitter, or a nanoscale probe. Ni silicide nanowires were grown by PECVD at 350 oC. TEM analysis showed that the Ni silicide nanowire has a single crystalline Ni3Si2 structure. The nanowire alignment was controlled by dielectrophoretic method and two nanowires were placed onto Pt electrodes under an ac biasing of 10 Vp-p at 100 kHz. The electric characteristics of the nanowire were obtained from double connections and a single connection to be 5.07 kΩ and 10.44 kΩ, respectively. The resistivity values were obtained as to be 183 μΩcm and 208 μΩcm showing a uniform performance of the connection. We present the single crystalline grown Ni silicide nanowires and a reliable scheme of positioning nanowires by dielectrophoretic method. [1] J. Kim, D. Shin, E.-S. Lee, and C.-S. Han Appl. Phys. Lett. 90, 253103 (2007). [2] J. Kim and W. A. Anderson, Nano Lett. 6, 1356 (2006). [3] J. Kim and W. A. Anderson, Appl. Phys. Lett. 86, 253101 (2005).
5:00 PM - M3.9
Carbon Nanotube Growth on Conductive Substrates for Interconnect Applications.
Gilbert Nessim 1 , Donatello Acquaviva 2 , Harvey Tang 1 , Matteo Seita 1 , Nicola Abate 1 , Carl Thompson 1
1 Department of Materials Science and Engineering, MIT, Cambridge, Massachusetts, United States, 2 Laboratory of Micro and Nanoelectronics Devices (LEG2), Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne Switzerland
Show AbstractAs integrated circuit technology is developed at dimensions below 32nm, carbon Nanotubes (CNTs) represent an ideal replacement for copper interconnects as they can carry higher current densities, don’t need liners, and don’t suffer from electromigration. However, fabrication issues such as growing the desired type of CNTs in a selected position, and making electrical contacts and interconnections remain major technical challenges. One approach to integration of CNTs into interconnect structures is to growth them directly on metals, to achieve good multi-wall electrical contacts. While there are many reports of successful CNT growth on insulating substrates, there are few for growth on conductive substrates. We have successfully grown CNTs on a variety of metallic underlayers, by controlling the thermal history of the substrate. Mats of CNTs, ranging in thickness between a few microns to over a centimeter, have been grown on Pd underlayers using Ni catalysts and ethylene as the feed gas. The thickest mats were obtained at growth temperatures at or below 500°C, which is significantly lower than the growth temperatures typically used for growth of CNTs on insulating substrates. Thicker mats were also produced when the substrate was rapidly heated before growth. Similar results were also obtained when using Fe or Co catalysts on Pd. In all three cases, we found that the catalysts preferential formed at Pd grain boundaries, so that the CNT density was limited by the Pd grain size. Using W underalyer, we were able to obtain denser carpets of vertically aligned CNTs. This may be due, in part, to the fact that the smaller grains in W do not coarsen at the CNT growth temperature.
5:15 PM - M3.10
Strained Zigzag Single Walled Carbon Nanotubes (SWNTs) for Interconnects.
Subbulakshmi Sreekala 1 2 , Xi-Hong Penx 1 , Ajayan Pulickel 2 , Saroj Nayak 1
1 Department of Physics, Applied Physics and Astronomy, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Department of Materials Science and Enggineering, Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractWe have studied the behavior of the band gap of single walled carbon nanotubes under uniaxial stress for its use as interconnects. This is done using the first principles density-functional calculations for the helical repeat units of carbon and periodic boundary conditions. All zigzag SWNTs showed semiconductor-metal transitions upon straining. Using the band structure, the effective mass of both the electrons and holes were also calculated both under relaxed and strained conditions and it was found that neither compression nor tension favored the currentcarriers thus can be used as both p and n type semiconductor when doped with appropriate dopants. The response of the changes of the band gap and effective mass to the uniaxial strain could be grouped into three categories, depending on their chirality. This study gives a basis for the interconnects how their conductivity can be tailored based on the mechanical strain.
5:30 PM - M3.11
Very High Density Three Dimensional Single-Walled Carbon Nanotube Based Interconnects.
Mehmet Dokmeci 1 , Chia-Ling Chen 1 , Selvapraba Selvarasah 1 , Shih-Hsien Chao 1 , Prashanth Makaram 2 , Ahmed Busnaina 2
1 Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts, United States, 2 Department of Mechanical and Industrial Engineering, Northeastern University, Boston, Massachusetts, United States
Show AbstractHigher density integration by utilizing the third dimension onto the substrate has been a major goal in the semiconductor industry and has been pursued aggressively both in academia and industrial research laboratories for various decades. With the proliferation of high aspect ratio nanoscale materials specifically carbon nanotubes, it is possible to make ultra small high density interconnects and active elements with properties matching the needs of the semiconductor industry. In this work, by utilizing a microfabricated platform and dielectrophoretic assembly, we present three dimensional vertically integrated carbon nanotube based interconnects. The assembly combines the attractive properties of top down microfabrication (fabrication of the microplatform) and the bottom up processes (dielectrophoretic assembly). The assembly process is achieved at room temperature and is amenable for CMOS fabrication. The two terminal resistance of the assembled SWNT bridge is about 545 Ohms. Encapsulation of the 3D structure with a thin layer of parylene-C protects it from the environment and keeps it intact. This directed assembly procedure is versatile, inexpensive, and achieved at room temperature. By utilizing a self-aligned three mask process, we demonstrate a 3D assembly/encapsulation method utilizing conductive SWNTs as the metallization material, parylene-C as the inter-level dielectric and the encapsulation layer. This technology is also applicable for vertical assembly of other conductive nanostructures and will enable 3D research in nanotechnology.
M4: Poster Session
Session Chairs
Pulickel M. Ajayan
Raji Baskaran
Thursday AM, November 29, 2007
Exhibition Hall D (Hynes)
9:00 PM - M4.1
Photonic Crystal Light Emitting Devices on Silicon on Insulator.
Nicolas Pauc 1 2 , Vincent Aimez 2 , Emmanuel Hadji 1 , Dominique Drouin 2
1 DRFMC/SP2M, CEA Grenoble, Grenoble France, 2 CRN2, Universite de Sherbrooke, Sherbrooke, Quebec, Canada
Show AbstractSilicon (Si) photonics has been appearing for many years as a promising route towards a greater degree of performance in logic circuits. Despite the numerous progresses accomplished recently in the fields of guiding and filtering of light on silicon, efficient generation of light by silicon in the chip itself still remains a challenging task. Many Si based light sources have been reported so far that make benefit of either quantum confinement or erbium incorporation to achieve efficient internal quantum efficiency or infra red emission respectively. Here, we explore another path for light generation in Si which is compatible with microelectronics requirements. We used an approach which combines surface patterning of matter into photonic crystals (PCs) and electrical carrier injection inside the nanostructure itself. We have fabricated PCs made on Silicon On Insulator (SOI) as a light generation medium that efficiently extracts the band gap emission of silicon at room temperature and we simultaneously developed a fabrication process of a lattice matched electrode network to insure carrier injection and recombination in the PC itself. We will present the first results obtained on these structures by optical and electrical excitation. In particular, we simultaneously achieved good photon extraction and fine tuning of the slow group velocity mode to free space wavelength coupling as a function of the PC geometric factors. We also studied the effect of the lattice matched electrode network on the PC emission properties and examined its influence on the device performance.
9:00 PM - M4.10
Evaluation of the Kinetics of Sn Nucleation in Near Eutectic SnAgCu and Examination of Corresponding Solder Joint Microstructures.
Babak Arfaei 1 , Eric Cotts 1
1 Physics and Materials Science, Binghamton University, Binghamton, New York, United States
Show AbstractDespite the widespread implementation of Pb free solders such as SnAgCu, the thermomechanical properties of such Pb free solder joints are not well understood. Particular aspects of joint microstructure have a strong influence on properties; the size and orientation of Sn grains, the morphology and chemistry of precipitates and of the intermetallic compounds, all may affect the response of a solder joint to stress. These microstructural features are profoundly influenced by the time above liquidus during the manufacture (reflow) of a solder joint, and the final solidification temperature. Thus, large variations in the degree of undercooling of Sn are important; as they may result in large variations in Pb free solder joint thermomechanical response. We studied nucleation and solidification in SnAgCu solder joints. Previous work showed that the nucleation kinetics of Sn in commercial flip chips change dramatically with the time above liquidus, although this effect was not explained. This research was conducted to understand the correlation between the microstructural changes during reflow and their effect on the nucleation kinetics of Sn in near-eutectic SnAgCu solder joints. Differential Scanning Calorimetry (DSC) was used to investigate the solidification behavior of flip chip samples at various temperatures and times during isothermal annealing. Results were analyzed with classical nucleation theory. Optical microscopy, Scanning Electron Microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDS) were used to characterize the resulting microstructure of the solder balls. Correlations of microstructure and nucleation behavior (including solidification temperatures) were examined. Examinations of correlations between such microstructures and mechanical properties are underway.
9:00 PM - M4.11
Mesoporous Silica Films with Enhanced Stability by Passivation with Multifunctional Organosilanes.
Binay Singh 1 , Darshan Gandhi 1 , Amit Singh 1 , G. Ramanath 1
1 , Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractMesoporous silica (MPS) thin films are attractive candidates for electrically isolating adjacent layers in device wiring. While the porosity decreases the signal propagation delays due to resistance-capacitance coupling, the entailing high surface area makes MPS susceptible to moisture uptake and metal diffusion. Prior recent work has shown that functionalizing MPS with trimethyl-terminated organosilanes is a solution to protect against these instabilities. Here, we show that using molecular nanolayers (MNLs) with more than one type of terminal moiety provides several-fold greater chemical stability against water uptake and copper diffusion. In particular, electrical tests on Cu/MNL/MPS structures with bipodal organosilane MNL with a tetrasulfide (TS) group at the center results in about a factor-of-70 increase in failure times due to strong immobilization of copper by the TS group. However, the leakage currents induced by water uptake is about two orders of magnitude higher than that seen in structures with MPS films functionalized with trimethoxy-terminated organosilanes. By functionalizing MPS with a combination of trimethoxy and TS organosilanes, we curtail both copper diffusion as well as water uptake, and increase the time to dielectric breakdown by an additional factor of 4. That is, MPS films functionalized with TS- as well as trimethoxy-terminated organosilanes show 2-3 orders of magnitude lower leakage currents and exhibit no electrical breakdown even after 3000 minutes. X-ray photoelectron and infrared spectroscopy, and depth profiling measurements, of the functionalized MPS films indicate that the long failure time is due to the combined effect of Cu immobilization by multiple sulfur atoms in the TS-MNL and moisture reduction in the pores by the trimethyl MNLs. The hydrophobic trimethyl termini are effective at inhibiting moisture uptake while the TS moiety is efficient in decreasing copper-induced leakage currents. We will present a phenomenological description of the immobilization mechanisms. Our findings provide a viable strategy for realizing high-stability low-dielectric constant materials for use in nanodevice wiring architectures.
9:00 PM - M4.12
Influence of Plating Parameters on the Voiding Propensity at Electroplated Copper-Solder Interface.
Y. Liu 1 , J. Wang 1 , L. Yin 4 , P. Kondos 4 , P. Borgesen 4 , D. Henderson 5 , C. Parks 5 , N. Dimitrov 1 3 , E. Cotts 1 2
1 Material Science and Engineering program, Binghamton University, Binghamton, New York, United States, 4 Area Array Consortium , Unovis Solutions, Binghamton, New York, United States, 5 , IBM, Endicott, New York, United States, 3 Department of Chemistry, Binghamton University, Binghamton, New York, United States, 2 Department of Physics, Binghamton University, Binghamton, New York, United States
Show Abstract9:00 PM - M4.13
Energy Gaps in Zero-dimensional Graphene Nanoribbons.
Philip Shemella 1 , Yiming Zhang 1 , Li Chen 1 , Mitch Mailman 1 , Pulickel Ajayan 2 , Saroj Nayak 1
1 Department of Physics, Applied Physics, and Astronomy, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Department of Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractWe have studied finite size effect on the electronic structures of graphene ribbons using first principles density functional electronic structure techniques. In particular, we have computed the energy gap (difference between highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO)) dependence on the width and length for both armchair and zigzag ribbons and compared to their one-dimensional (infinite length) cases. Our results suggest, in addition to quantum confinement along the width of the ribbon, an additional finite size effect emerges along the length of ribbons only for armchair ribbons with width N ≠ 3M-1, where M is an integer. The origin of additional quantum confinement in these structures are analyzed based on the energy states near the Fermi energy: both HOMO and LUMO energy levels for armchair ribbons which satisfy the N = 3M-1 rule are delocalized entirely on the ribbons while for ribbons with N ≠ 3M-1 these states are localized at the edges only. Our results are discussed in light of effect of passivation on the electronic properties of graphenes and their impact on nanoelectronics devices based on graphenes.
9:00 PM - M4.14
Thermal Diffusivity Measurement of Thin Films on Silicon Substrate by Telecom Wavelength Picosecond Laser Thermoreflectance.
Shakhawat Firoz 1 , Takashi Yagi 1 , Naoyuki Taketoshi 1 , Tetsuya Baba 1
1 Material Properties and Metrological Statistics Division, National Metrology Institute of Japan, AIST, Tsukuba, Ibaraki, Japan
Show AbstractA telecom wavelength picosecond thermoreflectance system has been adopted in National Metrological Institute of Japan (NMIJ) of AIST. This is the first time; the thermal diffusivity of thin films on silicon substrate has been demonstrated by a rear heating-front detection type picosecond thermoreflectance system. Considering the transparency of Si substrate, a picosecond laser having wavelength of 1550 nm has been used as a pump laser to irradiate the films on substrate side and the heat diffuses perpendicular to opposite side of the film has been determined by another pulse laser of wavelength 785 nm. The temperature history has been determined by measuring the signal amplitude caused by the reflectivity change on the film due to pulse heating. The signal was analyzed based on one dimensional heat flow across the film. Molybdenum (Mo) film having thickness of 400 and 600 nm have been employed as samples sputtered on silicon 100 and 111 planes as well as on quartz substrate. There is no marked difference between the thermoreflectance signal profiles (heat diffusion) of films on different planes of silicon (100 and 111) and so the thermal diffusivity values, which is determined as 3×105 m2s-1.
9:00 PM - M4.15
Quantum Resistance of Copper Nanowire and its Comparison with Carbon Nanotube for Interconnect Applications from First Principles Calculations.
Yu Zhou 1 , Yiming Zhang 1 , Subbalakshmi Sreekala 1 , Pulickel Ajayan 1 , Saroj Nayak 1
1 Physics, RPI, Troy, New York, United States
Show AbstractWe have studied electronic properties and band structure of copper nanowires of different diameters using first principle density functional method and super cell approach. The quantum resistances of copper wires are computed based on Landauer formalism and compared with empirical approach. The fundamental resistances of small copper nanowires (~ 60 nm diameter) are found to be larger than that predicted by Ohm's law. In parallel, we have computed fundamental resistance of bundles of single walled carbon nanotubes and compared them with that of a single copper wire of similar dimensions. We find that the resistance of carbon nanotube bundles is smaller compared to that of copper wires for dimensions below 60 nm. Our results are discussed in the light of recent experiments.
9:00 PM - M4.16
Ferromagnetic Metal Impregnated Multi-wall Nanotubes for Spin-sensitive Interconnects.
Swastik Kar 1 , Caterina Soldano 2 , Saroj Nayak 2 , Saikat Talapatra 3 , Pulickel Ajayan 1
1 Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Deparment of Physics, Applied Physics and Astronomy, Rensselaer Polytechnic Institute, Troy, New York, United States, 3 Department of Physics, Southern Illinois University at Carbondale, Carbondale, Illinois, United States
Show AbstractThe possibility of using carbon nanotubes for future electrical interconnects in the gigascale integration regime is a highly popular idea. It has been established that the large current density possible in nanotubes is chiefly due to long-range charge transport without significant scattering processes. Recent works have shown that the absence of scattering can also maintain spin information of a spin-polarized current over long ranges, giving rise to the possibility of low-power, spin-current sensitive interconnects. A key feature in building spin-sensitive interconnects is to controllably position ferromagnetic “polarizers” and “analyzers” for spin-generation and detection. Traditional polarizers and analyzers are fabricated by lithographically placing ferromagnetic contacts to the nanotubes, with different switching fields. These suffer from high-contact resistance deficiencies, which give rise to inefficient spin-detection. We present the fabrication and characterization of ferromagnetic metal nanoclusters impregnated multi walled carbon nanotubes using a simple electrochemical method. Devices fabricated from the metal-impregnated nanotubes can then be separately contacted using low contact-resistance metals, while the nanoclusters residing within the tube itself can work as polarizers and analyzers. We present preliminary electrical measurement of these systems at room and low-temperatures, and in the presence of magnetic fields, and discuss the results in the framework of transport mechanisms of low-dimensional systems.
9:00 PM - M4.17
A Unique Method of Forming either Pseudomorphic or Relaxed GexSi1-x Thin-Films on Insulator.
Khalid Hossain 1 , Jerome Duggan 1 , Floyd McDaniel 1 , Orin Holland 1 2
1 Department of Physics, University of North Texas, Denton, Texas, United States, 2 , Amethyst Research Inc., Ardmore, Oklahoma, United States
Show AbstractA unique process of fabricating a strained layer GexSi1-x on insulator is demonstrated. Such strained heterostructures are useful in the fabrication of high-mobility transistors. This technique incorporates well-established silicon processing technology e.g., ion implantation and thermal oxidation. A dilute GeSi layer is initially formed by implanting Ge+ into a silicon-on-insulator (SOI) substrate. Thermal oxidation segregates the Ge at the growing oxide interface to form a distinct GexSi1-x thin-film with a composition that can be tailored by controlling the oxidation parameters (e.g. temperature and oxidation ambient). In addition, the film thickness can be controlled by implantation fluence, which is important since the film forms pseudomophically below 2E16 Ge/cm2. Continued oxidation consumes the underlying Si leaving the strained GeSi film encapsulated by the two oxide layers, i.e. the top thermal oxide and the buried oxide. Removal of the thermal oxide by a dilute HF etch completes the process. Strain relaxation can be achieved by either of two methods. One involves vacancy injection by ion implantation to introduce sufficient open-volume within the film to compensate for the compressive strain. The other depends upon the formation of GeO2. If Ge is oxidized in the absence of Si, it evaporates as GeO(g) resulting in spontaneous relaxation within the strained film. Conditions under which this occurs will be discussed.
9:00 PM - M4.18
ALD Precursors Based on Formamidinates for High-k Application.
Deodatta Shenai 1 , Huazhi Li 1 , Ralph Pugh 1
1 Metalorganics, Rohm and Haas Company, North Andover, Massachusetts, United States
Show Abstract9:00 PM - M4.19
Oxygen Effect on the Pulsed Laser Deposition and Post-deposition Heat Treatment for Yttrium Iron Garnet Thin Films.
Michael Zaezjev 1 , M. Sekhar 1 , M. Ferrera 1 , L. Razzari 1 , G. Ross 1 , B. Holmes 2 , M. Sorel 2 , D. Hutchings 2 , S. Roorda 3 , R. Morandotti 1
1 , INRS-EMT, Varennes, Quebec, Canada, 2 Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow United Kingdom, 3 Physics Department, University of Montreal, Montreal, Quebec, Canada
Show AbstractIt has been shown that oxygen is a major player in the fabrication of high quality yttrium-iron garnet (YIG) thin films deposited by pulsed laser deposition (PLD). This is likely true for other fabrication techniques such as sputtering. Nevertheless, only a very general understanding of its role during the deposition process has been obtained to date. In general, it is commonly accepted that oxygen must be present in the deposition ambient atmosphere, even though no optimization has been carried out in order to find the optimal values (substrate temperature, oxygen pressure, etc.) for an efficient PLD process. In the published literature oxygen pressure was studied in a rather wide range from 0 to 1000 mTorr, and different values have been reported as optimal. It has, therefore, remained unclear which oxygen pressure is the most favourable, and why. In this paper, we report the growth of polycrystalline yttrium iron garnet Y3Fe5O12 (YIG) thin films on single crystalline MgO substrates by PLD. The films were deposited in vacuum and at various oxygen and argon pressures. The substrate temperature was chosen in the range 600°C - 800°C (high temperature), and compared with a deposition carried out at 150°C (low temperature). As-deposited films grown in an oxygen atmosphere were mostly amorphous, while films deposited in vacuum and in an argon atmosphere were polycrystalline, with some yttrium and iron oxides phases. To study the effect of ambient gas and temperature on the YIG phase crystallization, subsequent annealing in different conditions was performed: temperature as high as 800°C and 1000°C were chosen, while the ambient gas was chosen to be either air, argon or oxygen. Good quality polycrystalline structures were found in the films annealed at 800°C under an air or an oxygen atmosphere. On the other hand, if Argon was used, post-deposition annealing could not promote the formation of a (high quality) crystalline YIG phase even at temperature as high as 1000°C. We have found that the oxygen partial pressure in the annealing atmosphere is of lower importance in the studied range: indeed results were similar for samples annealed in air or in pure oxygen. Finally, no effects associated to a increase in the anneal temperature were observed: similar polycrystalline structures were found for both samples annealed at 800°C or at 1000°C. In general, good quality polycrystalline YIG films were obtained only when as-deposited films were amorphous and annealing was done in an air or in an oxygen atmosphere. When as-deposited films were polycrystalline, only monophase orthorhombic FeYO3 was found. Therefore, we may assume that certain parasitic crystalline phases (Y2O3 and Fe2O3) may preclude the crystallization of a YIG phase. In particular we observed that when those phases were present, no further heat treatment could promote their re-crystallization into a YIG cubic phase. In order to suppress the crystallization of those phases during the deposition process, we tried and reduced the substrate temperature. We found that thin films deposited at 150°C and annealed in air or oxygen exhibited a good polycrystalline YIG phase even when they were deposited in vacuum, a very important fact that has never been observed to date.
9:00 PM - M4.2
Contrast Enhancement Layers as Extensions of 193 nm Lithography: Materials and Viability Evaluation.
Libor Vyklicky 1 , Gregory McIntyre 2 , David Medeiros 1
1 , IBM T.J.Watson Res. Center, Yorktown Heights, New York, United States, 2 , IBM Corp., Hopewell Junction, New York, United States
Show AbstractMetal interconnect layers are among the most challenging to lithographically print as they are usually at the tightest pitch. With the technical challenges that continue to delay the introduction of extreme ultraviolet (EUV) lithography solutions, and with no other viable next generation lithographic options available, the semiconductor industry is searching for any means necessary, including the use of multiple exposures, to extend the utility of optical lithography, namely immersion 193 nm, for the 32 nm half pitch node and potentially beyond. Considerable attention is being paid to role of innovative material approaches to afford this extendibility. The concept of a photobleachable, contrast enhancement layer (CEL) has been shown in the past at longer wavelengths (365 nm and 436 nm) to improve the aerial image, and therefore the resolution, of a pattern printed into the resist during the exposure. However, little effort has been invested in developing materials compatible with today’s state-of-the-art exposure tools. We will discuss our efforts in design and synthesis of photobleachable materials tailored for 193 nm lithography as well as associated design challenges. We will present structures of materials synthesized and methods and data pertaining to their photobleaching performance. In addition, we will also present computational simulations that assess the benefits of such materials when used in either irreversibly (traditional) or reversibly bleachable CELs especially with focus on double exposure schemes.
9:00 PM - M4.4
Interfacial Microstructure of SIMOX Materials for Photonic Application.
Dongwoo Suh 1 , Junghyung Pyo 1 , O-Kyun Kwon 1 , Gyungock Kim 1
1 , ETRI, Daejeon Korea (the Republic of)
Show Abstract9:00 PM - M4.5
Fracture Pathways in Molecularly-passivated Mesoporous Silica Films Interfaced with Copper Wiring in Nanodevices.
Darshan Gandhi 1 , Amit Singh 1 , Binay Singh 1 , Richard Moore 2 , Eva Simonyi 3 , Michael Lane 3 , Ganapathiraman Ramanath 1
1 Materials Science and Engg., Rensselaer Polytechnic Institute, Troy, New York, United States, 2 College of Nanoscale Science & Engineering, State University of New York, Albany, New York, United States, 3 Microelectronics, T. J. Watson Research Center, IBM, Yorktown Heights, New York, United States
Show AbstractIntroducing porosity into dielectric materials is an effective strategy to obtain low relative permittivity (κ) layers for isolation in nanodevice wiring. However, porosity also facilitates water uptake and metal penetration during or after device fabrication, degrading chemical stability and electrical properties.1,2 Sealing the pores or altering their chemistry using molecular surfactants with appropriate termini is an attractive strategy to counteract such instabilities.3 Here, we describe the effect of molecular passivation on the fracture behavior of mesoporous silica (MPS) films and Cu/MPS/Si stacks. We show that while molecular passivation can lower the fracture energy and modulus of MPS, it provides a means to alter the fracture pathway—an attribute that could be advantageous for tailoring device reliability. Nanoindentation, thin film stress and infrared spectroscopy measurements reveal that silylation relaxes the stress and lowers the modulus of the MPS films due to disruption of the siloxane network. Four-point bend mechanical tests on Cu/MPS/Si stacks show that structures with silylated MPS films show a ~50% lower fracture energy than the 3 Jm-2 for unsilylated MPS. X-ray photoelectron spectroscopy (XPS) analyses of fracture surfaces reveal cohesive fracture in the MPS, close to the Cu overlayer. Variable take-off angle XPS and secondary ion mass spectrometry shows that the fracture location bears a close correlation with the depth of Cu penetration into the MPS layer. In particular, we show that silylation decreases Cu penetration and results in fracture closer to the Cu/silylated-MPS interface. Our results show that molecular passivation of porous films not only inhibit metal penetration and water uptake, but also allow the engineering of different mechanical properties of porous materials.1 J. A. Lee, J. T. Wetzel, C. Merrill, and P. S. Ho, Mat. Res. Soc. Symp. Proc., 716 B12.12.1-B12.12.6 (2002).2 A. P. Singh, P. Victor, P. G. Ganesan, O. Nalamasu, and G. Ramanath, Appl. Phys. Letters 87 253506 (2005).3 C. Jezewski, W.A. Lanford, C. J. Wiegand, Jay J. Senkevich, and T.-M. Lu, Semi. Intl, 27(5), 56-59 (2004).
9:00 PM - M4.6
High-Yield Approach of Pure-Silica-Zeolite MFI Nanocrystals and Applications in Ultra-Low-k Films
Minwei Sun 1 , Christopher Lew 1 , Yan Liu 1 , Yushan Yan 1
1 CEE, University of California, Riverside, Riverside, California, United States
Show AbstractAs the feature size of microprocessors decreases, ultra low dielectric constant (ultra-low-k) insulators are highly desired. Pure silica zeolites (PSZs) are promising candidates because of their uniform micro-porosity, high heat conductivity, superior mechanical strength as well as high hydrophobicity. Two film deposition processes have been developed by us — in-situ crystallization and spin-on of zeolite nanoparticle suspension. For spin-on process, the crystallinity and crystal size are both critical parameters to control the film properties. Once the crystal size is reduced while keeping high yield, the inter-particle mesopores will become smaller and more uniform, which will result in higher modulus and heat conductivity as well as smoother film. In this research, a new high yield approach of zeolite nanocrystal synthesis is reported. Two-stage method was used in the first batch to synthesize PSZ MFI nanocrystals. After the reaction, nanocrystals were removed by centrifugation and the rest of reaction gel was recycled. For the latter batches, the reaction time was much shorter than the first batch because of the presence of precursors in the synthesis solutions. Based on this method, PSZ MFI nanocrystal size was controlled at 30~35nm, 40~50nm, 53~58nm with the accumulative yields of 23%, 48% and 62% respectively. Moreover, ultra-low-k films were prepared from different size nanocrystal suspensions. The mechanical and dielectric properties of the films were measured.
9:00 PM - M4.7
Understanding the Effects of Surfactant in Post-CMP Cleaning.
Dedy Ng 1 , Hong Liang 1
1 Mechanical Engineering, Texas A&M University, College Station, Texas, United States
Show AbstractSurface cleaning is an important step in fabricating semiconductor devices. In chemical-mechanical planarization (CMP) of integrated circuits (IC), the usage of slurry abrasives and debris from the film being polished can introduce a complex contamination on the substrate. Other factors promoting surface contamination during CMP are zeta-potential and pH of the slurry. In this research, post-CMP cleaning was conducted using single surfactant and mixed surfactant systems. The cleaning method used in this work employs a single-sided brush made from polyvinyl acetal (PVA) sweeping across a substrate. In order to compare the effectiveness of selected surfactant systems, the adhesion forces were directly measured using an Atomic Force Microscope (AFM). Further surfactant characterization was carried out using a Small Angle X-ray Spectroscope (SAXS). It was found that a bilayer formation can be achieved at an optimum surfactant concentration. This layer dominates the dispersion of mechanical energy through friction that directly affects the cleaning effectiveness. New understanding in post-CMP cleaning is proposed.
9:00 PM - M4.8
Thermal Stability of Sputtered Mo-WNx Thin Films for Cu Diffusion Barrier Applications.
Prodyut Majumder 1 , Christos Takoudis 2
1 Department of Chemical Engineering, University of Illinois at Chicago, Chicago, Illinois, United States, 2 Departments of Chemical Engineering and Bioengineering, University of Illinois at Chicago, Chiacgo, Illinois, United States
Show AbstractCopper is used as interconnect in advanced ultra large scale integration microelectronic devices due to its low electrical resistivity and superior resistance to electromigration compare to Al. However, Cu diffuses easily into Si and SiO2, and forms copper silicide compounds at temperatures as low as 200 °C, resulting in degradation of Si devices at low temperature.Ta-based diffusion barriers (Ta and TaN) have been extensively used in Cu interconnection systems due to their low electrical resistivity and moderate thermal stability. But sputtered Ta/TaN barrier layer exhibits columnar structure that has grain boundaries extended throughout the film. These grain boundaries are the effective pathways for diffusion of Cu and/or substrate atoms leading to the failure of diffusion barriers. Furthermore, the breakdown of single layer diffusion barrier takes place due to the presence bulk defects or loss of barrier integrity. Thus it is necessary to use multilayer structures as diffusion barrier in order to restrict the diffusion through the grain boundaries. Also multilayer barrier structures have higher thermal stability as compared with single layer structures. In this study, we evaluate the performance of Mo-WNx as barrier layer for Cu metallization. Mo and WNx films are sputtered deposited using Ar and Ar/N2 mixture, respectively, under a 4.0 mtorr total sputtering pressure. Cu is deposited over Mo-WNx using e-beam evaporation operated at a base pressure of ~10-7 torr. The thermal stability of Cu/Mo-WNx/Si structure is evaluated after annealing at wide range of temperatures in the presence of N2 using four probe measurements for sheet resistance, X-ray diffraction analysis for phase identification and scanning electron microscopy for surface morphology. The interaction of different layers due to high temperature annealing is evaluated by depth profiling using X-ray photoelectron spectroscopy.
9:00 PM - M4.9
Laterally Grown CNT Arrays for Lateral Interconnection.
Xiaofeng Wang 1 , SeongHo Moon 1 , Subramanya Mayya 1 , Sunwoo Lee 1 , DongWoo Kim 1 , KyungRae Byun 1 , Hongsik Yoon 1 , In-Seok Yeo 1 , Sung-Tae Kim 1 , Woosung Han 1
1 , Samsung Electronics, San#24 Nongseo-Ri,Giheung-Eup,Yongin-City,Gyeonggi-Do Korea (the Republic of)
Show AbstractUsing CNT for interconnect has attracted lots of interest recently. However, until now, most research on using CNT for interconnect are concentrated on vertical interconnects. Previous reports on lateral growth of CNT included directed growth using electrical field, gas flow, etc. These methods were either not friendly with semiconductor process or involved complex patterning procedures. In this abstract, we demonstrate a simple lateral CNT growth process that is compatible with semiconductor process whilst allowing good control of growth direction. Our method involves conventional photolithography steps to realize model island structures with metal catalysts deposited onto the sidewalls of the island patterns. The selective deposition of catalysts to the sidewalls was sensitively dependent on the etch process. This etch time had a direct impact on the density and diameter of the nanotubes grown. The selective placement of catalyst to the sidewall enabled by photolithography allowed successful growth of direction controlled lateral CNT arrays. The above standardized process can be easily transferred to other complex patterns thus enabling successful integration of CNT for lateral interconnect applications. Thus grown CNT were characterized using electron microscopy (SEM&TEM), Raman spectroscopy etc.
Symposium Organizers
Robert Geer State University of New York-Albany
James D. Meindl Georgia Institute of Technology
Rajashree (Raji) Baskaran Intel Corporation
Pulickel M. Ajayan Rice University
Ehrenfried Zschech AMD Saxony LLC & Co. KG
M5: Nanoscale Interconnects
Session Chairs
Thursday AM, November 29, 2007
Hampton (Sheraton)
9:00 AM - **M5.1
First Principles Study of Charge and Spin Transport in Carbon Nanotubes and Graphenes for Interconnect Applications: From Electrons to Interconnects.
Yu Zhou 1 , Subbalakshmi Sreekala 2 , Philip Shemella 1 , Yiming Zhang 1 , Li Chen 1 , Catarina Soldano 1 2 , Swastik Kar 2 , Pulickel Ajayan 2 , Saroj Nayak 1
1 Physics Department, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractWe will present our recent study of charge and spin transport in single walled carbon nanotubes and in their bundles for interconnect applications. Our results are based on first principles density functional theory and Landauer formalism. The computed electrical properties of carbon nanotube based materials are compared with that of copper nanowires of similar dimensions particularly below 60 nm. Our quantum calculations are compared with semi-classical model which are typically used for circuit simulations. We will also present our results on metal doped carbon nanotubes that is emerging a new way to reduce resistance for interconnect applications. In parallel, we will discuss our results on graphene nanoribbons and the effect of functionalization on the electronic properties of these new classes of materials. Finally, we will present our negative magneto-resistance result obtained in carbon nanotubes and compare with recent experiments.
9:30 AM - **M5.2
Electromigration Reliability in Nanoscale Cu Interconnects.
Chao-Kun Hu 1 , L. Gignac 1 , B. Baker-O'Neal 1 , G. Bonilla 2 , E. Liniger 1 , P. Flaitz 2
1 , IBM, Yorktown Heights, New York, United States, 2 , IBM, Hopewell Junction, New York, United States
Show AbstractElectromigration is a phenomenon of atom diffusion under electric potential gradient. Electromigration mass flow is generated by a dc current and can result in integrated circuit chip failure. The electromigration induced mass flow is determined by the effective Cu diffusivity and electromigration driving force. The effective Cu diffusivity in a Cu line is very sensitive to the Cu microstructure and is dependent on fabrication conditions. A typical Cu damascene interconnect has a top surface covered with a thin dielectric diffusion barrier layer and the bottom Cu surface and the two sidewalls covered with a metal liner. Electromigration data have indicated that Cu lifetime in damascene structures scales by 0.5 for every generation, even at the same current density. The dominant diffusion path in Cu interconnections was found to be mostly along the Cu/dielectric cap interface for interconnects prior to the 65 nm node technology. The bamboo-like Cu grain structure observed in above 65 nm node interconnects did not always exist for < 65 nm node interconnects and a polycrystalline grain structure or mixture of bamboo-polycrystalline grain structures have often been observed. Characterization of the mass flow along interfaces and grain boundaries in Cu nanowires becomes important for predicting Cu reliability. The activation energy for grain boundary diffusion was found to be lower than that of interface diffusion. Thus, electromigration-induced mass flow should be increased by the addition of Cu grain boundary diffusion, especial for nanowires. Furthermore, the smaller volume and grain size in Cu nanowire will further shorten the chip lifetime because there is a larger fraction of atoms along these fast paths in conjunction with a smaller void needed to cause the wire failure. These results suggest that improvement in electromigration reliability for the 32 nm technology node and beyond will be a great challenge. In this talk, we will present the electromigration Cu damascene nanowire lifetime scaling rule, methods for measuring various mass flow contributions, and the techniques for reducing Cu mass flow, such as Cu alloy, Cu surface plasma pre-clean techniques or CoWP metal cap before the dielectric deposition, etc.. In addition the Cu line size effect on the Cu conductivity will also be presented.
10:00 AM - **M5.3
Mechanical Properties of Interconnects at the Nanoscale: Where is the Limit?
Ralph Spolenak 1
1 Department of Materials, ETH Zurich, Zurich Switzerland
Show AbstractThe yield stress of thin metal films or metal interconnects increases with decreasing feature size. This leads to higher mechanical stresses with every new microprocessor as the applied strains, as determined by the thermal budget, stay the same. High stresses in turn constitute a reliability challenge.In this paper, yield stress and fracture toughness of gold interconnects as narrow as 20 nm are presented. The interconnects exhibit unexpectedly low yield stresses and modest fracture strains. Thus their applicability to “wearable” electronics needs to be addressed with caution.Results are compared to classical Cu/Ta systems and the mechanisms of deformation are analyzed. Scaling laws are used to determine limits in mechanical properties.
10:30 AM - M5.4
Colossal Interfacial Toughening of Copper-silica Interfaces using a Molecular Nanolayer for Nanodevice Wiring.
Darshan Gandhi 1 , Yu Zhou 2 , Saroj Nayak 2 , Michael Lane 3 , Ganapathiraman Ramanath 1
1 Materials Science and Engg., Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Physics, Rensselaer Polytechnic Institute, Troy, New York, United States, 3 Microelectronics, T. J. Watson Research Center, IBM, Yorktown Heights, New York, United States
Show AbstractTailoring the chemical, mechanical and thermal stability of copper-dielectric interfaces is critical for the sustenance, and realization of the full potential, of copper wiring technology for nanodevice applications. Recent works have shown that near-zero-thickness self-assembled molecular nanolayers (MNLs) provide an attractive alternative to conventional metal-based interfacial layers used to inhibit copper diffusion and promote adhesion of copper-dielectric interfaces. However, the low stability of MNLs above 300 °C due to molecular desorption is a major concern that could limit the use of MNLs for device fabrication processes involving steps in the vicinity of such temperatures. Here, we demonstrate an entirely new use of a sub-nanometer-thick mercaptan-terminated organosilane MNL to obtain remarkable mechanical toughening of copper-silica thin film interfaces at temperatures higher than the MNL desorption temperature. Annealing Cu/MNL/SiO2 structures at 400 °C ≤ Tanneal ≤ 700 °C results in interfaces that are five-fold tougher than pristine Cu/SiO2 structures, yielding values exceeding ~20 Jm-2. Although similarly high toughness values can be obtained using micrometer-thick interfacial layers, toughening by annealing an interfacial molecular nanolayer at high temperatures is entirely new 1. Electron spectroscopy of fracture surfaces, and density functional theory modeling of molecular stretching and fracture, show that toughening arises from thermally-activated interfacial siloxane bridging that enables the MNL to be strongly linked to both the adjacent layers at the interface. The incorporation of the MNL at the interface suppresses desorption, and allows thermally activated bond formation that enhances adhesion. We show that the copper-MNL interface bonding is strong and temperature insensitive, while the silica-MNL bonding is sensitive to the annealing temperature. The latter attribute can be used to tune the stability of interfaces and design processes that will allow the integration MNLs with standard device fabrication steps. Our findings open up completely new opportunities for molecular-level tailoring of a variety of interface properties, at temperatures higher than previously envisaged, for nanodevice applications where microlayers are not a viable option, and for devising new types of thermally resistant molecular-inorganic hybrid devices.1 D.D. Gandhi et al, Nature 447, 299 (2007).
10:45 AM - M5.5
Effect of Grain Orientation on Stress-Induced Void Formation in Nanoscale Copper Interconnects.
Jin Ho An 1 , Paulo J. Ferreira 1
1 , University of Texas at Austin, Austin, Texas, United States
Show AbstractAs the linewidth of Cu interconnects continues to be downscaled below 50 nm, reliability issues are still a major concern. Changes in grain structure, stress state, and the use of novel low-k materials, all can affect reliability behavior. In this regard, novel experimental methods capable of enhancing our understanding of nanoscale Cu interconnects must be developed in order to predict/control interconnect failure mechanisms. One key problem in understanding the failure behavior of nanoscale copper interconnects lies in the fact that it is difficult to measure local crystal orientation in nano size grains. In this context, we have developed a technique for measuring a large number of individual crystal orientations of grains as small as 20 nm, using an automated crystallography software for diffraction pattern indexing in a transmission electron microscope (TEM). We were able to obtained local crystallographic data of over 80 individual grains in 180 nm Cu interconnects. The grain orientation information was used to calculate local stresses using a Finite Element Method, based on previously experimentally reported normal stress values. At 230 C, where void formation has been observed, local hydrostatic stress values ranging from 270 MPa to over 430 MPa were calculated depending on the local crystal orientation. In-situ heating in a TEM showed that high local stresses at Cu triple junctions (Cu grain boundary and Ta diffusion barrier) directly affected the void formation behavior under thermal stress conditions. These experimental results were subsequently used to model void formation, thus enhancing our understanding of failure mechanisms. Such techniques can be directly applied to the next generation Cu interconnects with linewidths below 50 nm, particularly in monitoring how changes in interconnect linewidth can affect the failure behavior. Basic understanding of such behavior is crucial for both controlling electromigration (EM) and stress-induced-voiding (SIV) mechanisms in future nanoscale interconnects.
11:30 AM - **M5.6
DNA-Directed Assembly of Nanocomponents: A Versatile Approach to Nano-Materials, Nano-Components and Nano-Integration.
Richard Kiehl 1
1 Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, Minnesota, United States
Show AbstractProgress in electronics thus far has relied on the scaling of transistors and an increasingly complex maze of interconnecting wires. The charging and discharging of these interconnects, which dominates power dissipation, has produced a bottleneck to continued improvement by scaling. Continued advances in information processing will therefore require a major paradigm shift involving radically different fabrication technologies, device principles, and circuit architectures. Constraints on layout and power dissipation at high integration levels will mandate the use of simple, ultrasmall devices arranged in highly regular arrays and interconnected locally – all done with nanometer-scale precision. Arrays of inorganic nanoclusters or organic molecules could provide a means for processing information with local connections (Kiehl, J. Nanopart. Res. 2,331, 2000). One possible scheme for computing in locally connected arrays is an approach known as tunneling phase logic, in which Coulomb blockade effects in nanoparticles, or analogous “integrate-and-fire” mechanisms in molecular systems, are used to represent logic states by the electrical phase of a dynamic process (Ohshima & Kiehl, J. Appl. Phys. 80, 912, 1996). Studies show that this scheme can potentially realize high-level information processing through nonlinear dynamics similar to those used in the brain (T. Yang, R. A. Kiehl, L. O. Chua, Intl, J. Bifur. Chaos 11, 2895, 2001). The use of DNA as a programmable scaffolding upon which nanoparticles, nanotubes, and molecules can precisely assemble offers a method for the fabrication of such nano-electronic circuitry. This approach is also well suited to the fabrication of nanoscale optical interconnects, such as nanoparticle plasmonic waveguides. The ultrasmall size and programmability of the nucleotide subunits in DNA provide a versatile basis for precise, tailorable self-assembly. In this talk, I will discuss our work toward nanocomponent assembly by 2D DNA scaffolding, including 1) in situ assembly of 5-nm metallic nanoparticle arrays with precisely controlled dimensions (Le et al, Nano Lett. 4, 2343, 2004), 2) sequence-encoded assembly of different sized nanocomponents in a common scaffolding (Pinto et al, Nano Lett. 4, 2399, 2005), and 3) hierarchical assembly of metallic nanowire superstructures from a nanoparticle array (Le et al, FNANO06, 2006).
12:00 PM - **M5.7
Electromigration Phenomena in Single-Crystalline Ag Nanowires.
B. Stahlmecke 1 , K. Roos 2 1 , K. Roos 3 1 , G. Dumpich 1 , Frank Meyer zu Heringdorf 1
1 Dept. of Physics and Center for Nanointegration Duisberg-Essen , University of Duisburg-Essen, Duisburg Germany, 2 , Bradley University, Peoria, Illinois, United States, 3 , Caterpillar Inc., Peoria, Illinois, United States
Show AbstractElectromigration effects in poly-crystalline metallization layers strongly limit the performance in todays semiconducting circuits. With smaller active areas in such devices, interconnects are shrinking as well, changing the surface-to-volume ratio so that surface transport becomes increasingly important. Similarly, with smaller interconnects, the influence of single grains on the electromigration becomes an important issue, as ultimately, the wires will only be one grain wide (with grain boundaries only perpendicular to the current direction). We have studied electromigration in single-crystalline silver nanowires, to investigate on the interplay of surface material transport, crystallinity of the nanowires, and the resulting electromigration behavior. The wires were formed in-situ via a self-assembly process during deposition of Ag at 650°C on a stepped 4° vicinal Si(001) template inside a photoemission electron microscope (PEEM). This preparation yields wires with a triangular cross-section and a length of several tens of micrometers. The wires were transported through air, contacted by e-beam lithography, and electrically stressed during in-situ scanning electron microscopy (SEM). The surprising finding of reversed electromigration behavior, compared to poly-crystalline Ag nanowires, is indicative of a dominating contribution of the direct (field) force for electromigration. Accordingly, voids are formed at the anode side of the wire, and material is transported nearly the entire length of the wire to the cathode contact pad, where hillocks are formed. The high structural quality of the Ag nanowires even provides for reversible electromigration. When the polarity of the current is reversed, the hillocks vanish and the previously formed voids are refilled. In contrast, in poly-crystalline Ag wires, the wind force dominates the electromigration behavior. Here, electromigration starts at grain boundaries, the material flows from the cathode to the anode side, and reversible electromigration is strongly hindered.
12:30 PM - **M5.8
Nanostructured Thermal Materials.
Kenneth Goodson 1
1 Mechanical Engineering, Stanford University, Stanford, California, United States
Show AbstractHyper-integration and advanced interconnect technologies pose major challenges to IC thermal management. Increasing numbers of metal layers, separated by dielectric materials with lower thermal conductivity, are elevating the temperature rise in metallization [1]. Hyperintegration, including 3D circuits, leads to larger power densities and much larger off-chip temperature rises [2]. This talk summarizes recent progress on thermal management involving nanostructured materials, which provide unique combinations of thermal, mechanical, and electrical properties. Metal-coated and patterned CNT films provide high through-plane thermal conductance and mechanical compliance appropriate for application as thermal interface materials [3]. Laser-reflectance data resolve the spatially-distributed resistances and dictate the engineering of tailored metal coatings for adhesion and low-temperature application. For package-level cooling, data are provided for nanostructured membranes for two-phase microfluidic cooling and nanofluids for enhanced single-phase microchannel convection.1. Im, S., Srivastava, N., Banerjee, K., and Goodson, K.E., 2005, “Scaling Analysis of Multilevel Interconnect Temperatures for High-Performance ICs,” IEEE Transactions on Electron Devices, Vol. 52, pp. 2710-2719.2. Koo, J.M., Im, S., Jiang, L., and Goodson, K.E., 2005, “Integrated Microchannel Cooling for Three-Dimensional Circuit Architectures,” ASME Journal of Heat Transfer, Vol. 127, pp. 49-58.3. Hu, X., Padilla, A.A., Xu, J., Fisher, T.A., and Goodson, K.E., 2006, “3-Omega Measurements of the Thermal Conductivity of Vertically Oriented Carbon Nanotubes on Silicon,” ASME Journal of Heat Transfer, Vol. 128, pp. 1109-1113.
M6: Carbon Nanotube Based Interconnects
Session Chairs
Thursday PM, November 29, 2007
Hampton (Sheraton)
2:30 PM - **M6.1
Novel LSI Interconnect Using Bundles of Carbon Nanotubes Synthesized at a Low Temperature.
Shintaro Sato 1 , Tatsuhiro Nozue 1 , Akio Kawabata 1 , Daiyu Kondo 1 , Miho Mishima 1 , Tomo Murakami 1 , Takashi Hyakushima 1 , Mizuhisa Nihei 1 , Yuji Awano 1
1 , MIRAI-SELETE, Atsugi Japan
Show AbstractCopper is currently used as an interconnect material for LSIs due to its low resistivity, but is believed to encounter serious problems in the near future. One of the most serious problems is that Cu cannot sustain a high current density required for LSIs in future generations, possibly in the hp32 technology node and beyond. Therefore, new interconnect materials that can replace Cu are now being sought. The carbon nanotube (CNT) is one of the most promising candidates due to its excellent properties. They include abilities to sustain a high current density (> 109 A/cm2) and to exhibit a ballistic transport along a tube. In fact, we have been working on developing vias (vertical wiring) using a bundle of multi-walled carbon nanotubes (MWNTs) for several years [1, 2].In this presentation, we explain our novel damascene process to fabricate CNT vias, which is compatible with the conventional LSI processes. The new process includes low-temperature (400-450 °C) CVD growth that does not damage LSIs by heat. We have also developed a chemical mechanical polishing process which can planarize a substrate with CNT vias. The diameters of fabricated CNT vias were as small as 160 nm.In the new process, a substrate with Cu interconnect covered by a dielectric layer (SiOC or SiO2) was first prepared. Via holes were made using conventional photolithography followed by dry etching. A TaN/Ta barrier layer and a TiN contact layer were deposited by physical vapor deposition (PVD). Size-controlled Co particles with a mean diameter of about 4 nm were then deposited using a nanoparticles deposition system [1]. Previously we grew CNTs selectively in via holes, but all over the substrate in our new damascene process. MWNTs were grown by thermal CVD with C2H2 diluted by argon as the source gas. The substrate temperature was 400 °C or 450 °C. The substrate with MWNTs were then coated with the spin-on glass (SOG) and planarized by CMP. The CMP condition was similar to the one used for polishing a silicon dioxide layer. Finally, a Ti top contact layer, a Ta barrier layer and Cu wire were connected to CNT vias by PVD.The quality of MWNTs was examined by transmission electron microscopy. It was found that high-quality MWNTs can be obtained at a growth temperature down to 400 °C by optimizing the growth condition. CNT vias as small as 160 nm in diameter were successfully fabricated by the new process. The resistivity of CNT vias with 2.8 μm in diameter (growth temperature: 450 °C) was 379 μΩcm. This value is of the same order as that of CVD-W plugs. The temperature dependence of the resistance suggests that carrier transport is ballistic. Electrical properties of 160-nm CNT vias fabricated at 400 °C and 450 °C were also measured. The details will be explained in the presentation.This work was completed as part of MIRAI Project supported by NEDO.[1] Sato. S. et al., Proc. IEEE IITC2006, 230 (2006)[2] Nihei. M. et al., Proc. IEEE IITC2007, 204 (2007)
3:00 PM - **M6.2
Theory and Measurements of the RF Impedance of Individual and Massively Parallel Single Walled Carbon Nanotubes.
Peter Burke 1 , Chris Rutherglen 1
1 , University of California at Irvine, Irvine, California, United States
Show AbstractThis talk will present an overview of the predicted RF performance of single walled carbon nanotubes, both as individual interconnects an their properties as massively parallel interconnects. We will present measurements supporting the notion of ballistic transport for interconnects shorter than one micron, and discuss in depth the effect of the contact resistance. Measurements and theory of the RF impedance of nanotube interconnects (both from our own research group as well as a review of the literature) will also be presented, in order to present an overview of the current state of the art of understanding of high speed signal propagation on nanotube interconnects.
3:30 PM - **M6.3
Carbon Nanotube Interconnects - A Data Perspective.
Kevin O'Brien 1
1 Components Research, Intel Corporation, Hillsboro, Oregon, United States
Show Abstract4:30 PM - **M6.4
Modeling of Carbon Nanotube-Based Interconnect for Future VLSI Applications.
Yehia Massoud 1
1 , Rice University, Houston, Texas, United States
Show AbstractProcess technology scaling coupled with increasing operating frequencies will exacerbate the delay, noise, and power problems that already plague interconnect in today's designs. Size-dependent factors, such as, electron-surface scattering, grain boundary scattering, and surface roughness-induced scattering, will dramatically increase the copper interconnect resistivity for technology nodes beyond 45nm. Due to the resistivity and electromigration problems that are impacting traditional copper wires as process technology scales downward, alternate technologies are required for the realization of reliable and high performance VLSI systems. Carbon nanotubes (CNTs) are promising replacements for on-chip copper interconnect due to their large conductivity and current carrying capabilities. While SWCNTs have desirable material properties, individual nanotubes suffer from large intrinsic and metal-nanotube contact resistances that are not dependent on the length of the nanotube. To alleviate the intrinsic resistance problem, bundles or ropes of SWCNTs in parallel, have been proposed and physically demonstrated as a possible interconnect medium. Multi-walled carbon nanotubes (MWCNT) are also a potential solution for on-chip interconnect applications. Recent experimental research has demonstrated that it is possible to contact the interior nanotubes in a MWCNT structure, which leads low resistance conductors. CNT-based interconnects can potentially solve the problem of heat dissipation in densely integrated circuits. In this talk, we plan to address the recent development of efficient modeling and design techniques for nanotube-based interconnect structures in future VLSI systems.
5:00 PM - M6.5
Metallization of Nanotubes for Interconnect Applications.
Caterina Soldano 1 , Fung Ou 2 , Mancheri Shaijumon 2 , Swastik Kar 2 , Saroj Nayak 1 , Pulickel Ajayan 2
1 Deparment of Physics, Applied Physics and Astronomy, Rensselaer Polytechnic Institute, Troy, New York, United States, 2 Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractWe describe detailed investigations of a post-fabrication CMOS compatible method for building high-conductance interconnects using carbon nanotubes. The process involves a systematic, repeatable and controllable enhancement of interconnect conductance using a rapid high-voltage cycling. The method works equally well for Ti-Au contacted single wall nanotubes as well as focused ion beam platinum-contacted multi walled nanotubes. The rapid high-bias cycling process, conducted in vacuum, leads to orders of magnitude drop in the two-terminal interconnect resistances. The end-product of this process is high-current density throughput in low-diameter interconnects. To understand the underlying mechanism, we describe investigations in multi walled nanotubes. These large diameter nanotubes were used for better visibility of the mechanism. Electron microscopy indicates that the high-bias cycling of nanotubes cause sufficient migration of platinum from the contact regions to decorate the outer surface of the nanotubes, giving rise to enhanced metallization. Selected results from a large number of multi walled nanotubes are presented, with pre-and post metallization characterization. We believe that the enhanced conductance may be due to a decrease in disorder inherently present in our nanotube interconnects, along with an increase in the number of available channels for conductance. This inference is based on detailed temperature dependence of the nanotube interconnect resistance, and fitting data to existing theoretical models.
5:15 PM - M6.6
Carbon Nanotubes as Interconnects in CMOS.
John Robertson 1
1 Engineering, Cambridge University, Cambridge United Kingdom
Show AbstractEvolutionary development of CMOS is the lower cost solution. For interconnects in CMOS, there is only one material with a significantly higher current carrying capacity than copper, carbon nanotubes (CNTs). In fact they have a 1000-fold higher capacity. This has led to a perception that interconnects might be the first adoption of CNTs in electronics rather than say as FET channels. However, carbon nanotubes are one-dimensional conductors. Their conductance is given by G0 per ‘conductance channel’, which limits their minimum resistivity as an apparent ‘contact resistance’. It is extremely difficult for short nanotube interconnects as in vias to have as low a resistance as Cu. The way round this is to have many nanotubes in parallel per interconnect or via. There are numerous problems to implementing this in practice which are not so discussed. For vias, this requires a nanotube density of near 10^14 cm^-2. This corresponds to a separation of below the nanotube diameter. The nanotubes will be grown by CVD. So far Awano et al [1] have reached ~10^-11. Second, the highest nanotube densities of ~10^13 cm^-2 are reached a specific case of a Fe catalyst on Al2O3 support, as in ‘Super growth’ [2,3]. However, we need a conductive substrate, not an insulator like Al2O3. Third, interconnects are a back end of line process, where the temperature is limited to 400C and highly etching conditions are not allowed. Our group has recently succeeded in growing SWNTs at 400C and below, in purely thermal CVD conditions [4]. However, work suggests that lowering growth temperatures in CVD favours more semiconducting SWNTs [5], whereas metallic SWNTs are desired. This overall combination of problems is discussed I this talk.1.Y Awano et al, Phys Stat Solidi A 203 3611 (20062.K Hata, D Futuba, S Iijima, Science 306 1362 (2004)3.M Cantoro, S Hofmann,... J Robertson, , Nanoletts 6 (2006) 11074.G Zhong, T Iwasaki, H Kawarada, Carbon 44 2009 (2006)5.S M Bachilo, L Balzano, D E Resasco, B Weismann, D Resasco, J Am Chem Soc 125 (2003) 11186
5:30 PM - **M6.7
Chip Cooling with Tailored Carbon Nanotube Architectures.
Robert Vajtai 1 , K. Kordas 2 , G. Toth 2 , X. An 3 , P. Ajayan 3
1 Rensselaer Nanotechnology Center, RPI, Troy, New York, United States, 2 Department of Electrical and Information Engineering, University of Oulu, Oulu Finland, 3 3Department of Materials Science & Engineering, RPI, Troy, New York, United States
Show AbstractHigh power consumption and the corresponding problem of heat dissipation is the biggest issue in high performance microprocessors. we show that efficient cooling can be achieved on silicon chips using micro-fins made of aligned multi-walled carbon nanotube arrays. The cooling elements fabricated and mounted on the backside of temperature measurement flip-chips enable significantly enhanced power dissipation from the heated chips; approximately the same amount of extra power can be extracted with nanotubes that a similar geometry copper cooler is able to achieve. In this talk we will describe the main thermal and mechanical advantages of the nanotube cooler, as well as the limiting factors of the system; namely we analyze the role of the interfaces (solid-solid and solid-gas).The cooling performance observed for nanotube structures - accompanied with excellent mechanical properties and light weight - make them strong candidates for on-chip thermal management applications, presently in the power density range of >100 W cm^{-2}. With tailoring the type and structure of nanotubes to obtain higher thermal conductivity, to improve the chip-nanotube and nanotube-air thermal interface, our goal is to reach higher power density removal values than the classical, macroscopic limit now. In the talk we will present our latest results into this direction, we will present our results on optimizing nanotube type, quality and geometry for achieving high power density heat removal both on the local (hot spot) and on the chip level.